Negative voltage charge pump circuit, switching power supply converter and electronic equipment

Abstract

The invention belongs to the technical field of electronic circuits, and provides a negative voltage charge pump circuit, a switching power supply converter and electronic equipment. A reference voltage generation module, a comparison module, a fourth driving module, a fifth power tube, a sixth power tube and a seventh power tube are additionally arranged on an existing charge pump. The reference voltage generation module is used for generating third reference voltage, namely threshold voltage when the negative-voltage charge pump circuit enters the light load, then the comparison module is used for comparing the third reference voltage with error voltage output by the error amplifier, and whether the negative-voltage charge pump circuit enters the light-load working condition or not is judged; when the negative-voltage charge pump circuit enters a light-load working condition, the large-size power tube and the driving module thereof are closed, and only the small-size power tube works, so that other performances of the negative-voltage charge pump circuit are ensured, the working current of the negative-voltage charge pump circuit in the light-load state is greatly reduced, and the working efficiency of the negative-voltage charge pump circuit is improved. Therefore, the conversion efficiency of the charge pump circuit in light load is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular relates to a negative voltage charge pump circuit, a switching power converter, and an electronic device. Background Art

[0002] Switching power converters are an integral component of electronic product power supply systems, converting voltages to different values ​​for various components while minimizing excess losses. Switched capacitor converters, also known as charge pumps, operate by storing energy in capacitors. Compared to inductor-based switching power converters, these converters offer advantages such as smaller size, lower quiescent current, lower noise, and reduced electromagnetic interference, making them widely used in low-load scenarios.

[0003] Conversion efficiency is a crucial metric for switching power converters. The higher the efficiency, the less power is lost during the conversion process. Charge pumps utilize switched capacitors as their primary structure, and the losses during the conversion process primarily include the on-resistance loss of the power switch tube, the current loss of the power tube driver circuit, and the current loss of other basic modules that provide voltage and current. To achieve higher output voltages and improve conversion efficiency, power tubes are typically larger. This reduces the on-resistance of the power tube and also requires the power tube driver circuit to possess stronger drive capability.

[0004] However, when the load current is very low, the charge pump's current is primarily consumed by driving the power transistors in each cycle, and the switching of the power transistors is necessary to maintain the output voltage. This results in the charge pump still drawing a high operating current when the load is light, especially at zero load, significantly reducing its conversion efficiency. In some systems, the charge pump's input voltage is provided by a boost converter. In this case, the charge pump's operating current increases further when it is applied to the boost converter's input. Summary of the Invention

[0005] The embodiments of the present application provide a negative voltage charge pump circuit, a switching power converter and an electronic device, which can solve the problem that the current charge pump still has a large operating current under light load, resulting in a significant decrease in its conversion efficiency.

[0006] In a first aspect, an embodiment of the present application provides a negative voltage charge pump circuit, including a first power tube, a second power tube, a third power tube, a fourth power tube, an output capacitor, an output resistor, a first resistor, a second resistor, a flying capacitor, a first switch, an error amplifier, a first drive module, a second drive module and a third drive module, wherein the source of the first power tube receives an input voltage, the gate of the first power tube is connected to the first end of the first switch, the second end of the first switch is connected to the output end of the error amplifier, the control end of the first switch receives a clock signal, and the drain of the first power tube is connected to the drain of the second power tube and the drain of the flying capacitor respectively. The first end of the output transistor is connected to the first drive module, the gate of the second power transistor is connected to the first drive module, the source of the second power transistor and the source of the third power transistor are both grounded, the gate of the third power transistor is connected to the second drive module, the drain of the third power transistor is respectively connected to the drain of the fourth power transistor and the second end of the flying capacitor, the gate of the fourth power transistor is connected to the third drive module, the source of the fourth power transistor is respectively connected to the first end of the output capacitor, the first end of the output resistor and the first end of the second resistor, and the second end of the second resistor is respectively connected to the first end of the first resistor and the first input end of the error amplifier , the second end of the first resistor receives a first reference voltage, and the second input end of the error amplifier receives a second reference voltage; the negative charge pump circuit further includes a reference voltage generation module, a comparison module, a fourth driving module, a fifth power tube, a sixth power tube and a seventh power tube, the size of the fifth power tube is smaller than the size of the second power tube and the two are of the same type, the size of the sixth power tube is smaller than the size of the third power tube and the two are of the same type, the size of the seventh power tube is smaller than the size of the fourth power tube and the two are of the same type; the comparison module is respectively connected to the reference voltage generation module, the output end of the error amplifier and the fourth driving module The fourth driving module is connected to the first driving module, the second driving module, the third driving module, the gate of the fifth power tube, the gate of the sixth power tube, and the gate of the seventh power tube respectively; the drain of the fifth power tube is connected to the drain of the second power tube, the source of the fifth power tube is connected to the source of the second power tube, the drain of the sixth power tube is connected to the source of the third power tube, the source of the sixth power tube is connected to the drain of the third power tube, the drain of the seventh power tube is connected to the drain of the fourth power tube, and the source of the seventh power tube is connected to the source of the fourth power tube; The reference voltage generating module is used to generate a third reference voltage based on a first current, where the first current is proportional to the current flowing through the first power tube; the comparing module is used to compare the error voltage output by the error amplifier with the third reference voltage, and output a first comparison signal when the error voltage is greater than the third reference voltage; the fourth driving module is used to receive a clock signal and output a first driving signal, a second driving signal, and a third driving signal according to the clock signal, which are respectively used to drive the fifth power tube, the sixth power tube, and the seventh power tube; and the fourth driving module is also used to output a first control signal, a second control signal, and a third control signal according to the clock signal and the first comparison signal, which are respectively used to shut down the first driving module, the second driving module, and the third driving module, thereby shutting down the second power tube, the third power tube, and the fourth power tube.

[0007] In a possible implementation of the first aspect, the comparison module is further used to output a second comparison signal when the error voltage is less than the third reference voltage; the fourth drive module is further used to output a fourth control signal, a fifth control signal, and a sixth control signal based on the second comparison signal and the clock signal, which are respectively used to control the first drive module to drive the second power tube, the second drive module to drive the third power tube, and the third drive module to drive the fourth power tube.

[0008] In a possible implementation of the first aspect, the reference voltage generation module includes an eighth power tube and a current source, the drain of the eighth power tube receives the input voltage, the gate of the eighth power tube is respectively connected to the source of the eighth power tube, the first end of the current source, and the comparison module, and the second end of the current source is grounded; wherein the eighth power tube and the first power tube are power tubes of the same type and have the same size.

[0009] In a possible implementation of the first aspect, the comparison module includes a comparator and an inverter, a first input end of the comparator is connected to the reference voltage generation module, a second input end of the comparator is connected to the output end of the error amplifier, the output end of the comparator is connected to the input end of the inverter, and the output end of the inverter is connected to the fourth driving module.

[0010] In a possible implementation of the first aspect, the fourth driving module includes a first driving unit, a second driving unit, and a third driving unit, the first driving unit being respectively connected to the comparison module, the second driving unit, the third driving unit, the first driving module, and a gate of the fifth power tube; the second driving unit being respectively connected to the second driving module and a gate of the sixth power tube; and the third driving unit being respectively connected to the third driving module and a gate of the seventh power tube. The first driving unit is configured to output a first driving signal according to the clock signal, for driving the fifth power tube; and also output a first control signal according to the clock signal and the first comparison signal, for turning off the first driving module, thereby turning off the second power tube; The second driving unit is configured to output a second driving signal according to the clock signal, so as to drive the sixth power tube; and also output a second control signal according to the clock signal and the first comparison signal, so as to turn off the second driving module and thereby turn off the third power tube; The third driving unit is used to output a third driving signal according to the clock signal to drive the seventh power tube; and also output a third control signal according to the clock signal and the first comparison signal to turn off the third driving module and thereby turn off the fourth power tube.

[0011] In a possible implementation of the first aspect, the first driving unit includes a first AND gate and a first driving sub-unit, the first input end of the first AND gate is respectively connected to the comparison module, the second driving unit and the third driving unit, the output end of the first AND gate is connected to the first driving module, the output end of the first driving sub-unit is connected to the gate of the fifth power tube, and the second input end of the first AND gate and the input end of the first driving sub-unit both receive the clock signal.

[0012] In a possible implementation of the first aspect, the second driving unit includes a second AND gate and a second driving sub-unit, the first input end of the second AND gate is respectively connected to the comparison module, the first driving unit and the third driving unit, the output end of the second AND gate is connected to the second driving module, the output end of the second driving sub-unit is connected to the gate of the sixth power tube, and the second input end of the second AND gate and the input end of the second driving sub-unit both receive the clock signal.

[0013] In a possible implementation of the first aspect, the third driving unit includes a third AND gate and a third driving sub-unit, the first input end of the third AND gate is respectively connected to the comparison module, the first driving unit and the second driving unit, the output end of the third AND gate is connected to the third driving module, the output end of the third driving sub-unit is connected to the gate of the seventh power tube, and the second input end of the third AND gate and the input end of the third driving sub-unit both receive the clock signal.

[0014] In a second aspect, an embodiment of the present application provides a switching power converter, comprising the negative voltage charge pump circuit described in any one of the first aspects.

[0015] In a third aspect, an embodiment of the present application provides an electronic device comprising the switching power converter described in any one of the second aspects.

[0016] Compared with the prior art, the embodiments of the present application have the following beneficial effects: An embodiment of the present application provides a negative voltage charge pump circuit, which adds a reference voltage generation module, a comparison module, a fourth drive module, a fifth power tube, a sixth power tube, and a seventh power tube to an existing charge pump. The size of the fifth power tube is smaller than that of the second power tube and the two power tubes are of the same type. The size of the sixth power tube is smaller than that of the third power tube and the two power tubes are of the same type. The size of the seventh power tube is smaller than that of the fourth power tube and the two power tubes are of the same type. The comparison module is respectively connected to the reference voltage generation module, the output end of the error amplifier, and the fourth drive module. The fourth drive module is respectively connected to the first drive module, the second drive module, the third drive module, the gate of the fifth power tube, the gate of the sixth power tube, and the gate of the seventh power tube. The drain of the fifth power tube is connected to the drain of the second power tube, the source of the fifth power tube is connected to the source of the second power tube, the drain of the sixth power tube is connected to the source of the third power tube, the source of the sixth power tube is connected to the drain of the third power tube, the drain of the seventh power tube is connected to the drain of the fourth power tube, and the source of the seventh power tube is connected to the source of the fourth power tube.

[0017] The reference voltage generation module is configured to generate a third reference voltage based on a first current. The first current is proportional to the current flowing through the first power transistor. The current flowing through the first power transistor represents the load current. Therefore, the first current represents the load current. The third reference voltage generated by the reference voltage generation module based on the first current can serve as a threshold voltage for the negative charge pump circuit to enter a light-load state. The comparison module is configured to compare the error voltage output by the error amplifier with the third reference voltage. When the error voltage is greater than the third reference voltage, the negative charge pump circuit enters a light-load state and outputs a first comparison signal. The fourth driver module receives a clock signal and, based on the clock signal, outputs first, second, and third driver signals for driving the fifth, sixth, and seventh power transistors, respectively. Furthermore, the fourth driver module outputs first, second, and third control signals based on the clock signal and the first comparison signal, for disabling the first, second, and third driver modules, respectively, thereby shutting down the second, third, and fourth power transistors. It can be seen from this that when the negative voltage charge pump circuit enters the light load condition, the large-size power tube and its driving module are turned off, and only the small-size power tube is operated to maintain the normal switching cycle of the negative voltage charge pump circuit and ensure the normal output voltage. While ensuring other performance of the negative voltage charge pump circuit, the operating current of the negative voltage charge pump circuit at light load is greatly reduced, thereby improving the conversion efficiency of the negative voltage charge pump circuit at light load.

[0018] In summary, the present application uses a reference voltage generation module to generate a third reference voltage, and then compares the third reference voltage with the error voltage output by the error amplifier through a comparison module to determine whether the negative voltage charge pump circuit enters a light load condition. When the negative voltage charge pump circuit enters a light load condition, the large-size power tube and its driving module are turned off, and only the small-size power tube is operated. While ensuring other performance of the negative voltage charge pump circuit, the operating current of the negative voltage charge pump circuit at light load is greatly reduced, thereby improving the conversion efficiency of the negative voltage charge pump circuit at light load.

[0019] It can be understood that the beneficial effects of the second to third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 1 is a circuit connection diagram of an existing charge pump; Figure 2 This is the working timing diagram of the existing charge pump; Figure 3 This is a principle block diagram of a negative pressure charge pump circuit provided in one embodiment of the present application; Figure 4 is a principle block diagram of a negative pressure charge pump circuit provided by another embodiment of the present application; Figure 5 1 is a circuit connection diagram of a negative pressure charge pump circuit provided in one embodiment of the present application; Figure 6 This is a working timing diagram of a negative pressure charge pump circuit provided in one embodiment of the present application.

[0022] In the figure: 10, reference voltage generating module; 20, comparison module; 30, fourth driving module; 31, first driving unit; 32, second driving unit; 33, third driving unit. DETAILED DESCRIPTION

[0023] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0024] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0025] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0026] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0027] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0028] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0029] Figure 1 A schematic diagram of a circuit connection of an existing charge pump is shown in FIG. Figure 1As shown, the existing charge pump includes a first power tube M1, a second power tube M2, a third power tube M3, a fourth power tube M4, an output capacitor Cout, an output resistor Rout, a first resistor R1, a second resistor R2, a flying capacitor Cfly, a first switch SW1, an error amplifier EA, a first driving module DRV1, a second driving module DRV2 and a third driving module DRV3. The source of the first power tube M1 receives the input voltage VIN, the gate of the first power tube M1 is connected to the first end of the first switch SW1, the second end of the first switch SW1 is connected to the output end of the error amplifier EA, the control end of the first switch SW1 receives the clock signal clk, the drain of the first power tube M1 is respectively connected to the drain of the second power tube M2 and the first end of the flying capacitor Cfly, the gate of the second power tube M2 is connected to the first driving module DRV1, the source of the second power tube M2 and the source of the third power tube M3 are both grounded, and the third power tube M3 The gate of the third power transistor M3 is connected to the second driver module DRV2, the drain of the third power transistor M3 is respectively connected to the drain of the fourth power transistor M4 and the second end of the flying capacitor Cfly, the gate of the fourth power transistor M4 is connected to the third driver module DRV3, the source of the fourth power transistor M4 is respectively connected to the first end of the output capacitor Cout, the first end of the output resistor Rout, and the first end of the second resistor R2, and the second end of the second resistor R2 is respectively connected to the first end of the first resistor R1 and the first input end of the error amplifier EA. In the present application, the first input end of the error amplifier EA is the inverting input end, the second end of the first resistor R1 receives the first reference voltage VREF1, and the second input end of the error amplifier EA receives the second reference voltage VREF2. In the present application, the second input end of the error amplifier EA is the non-inverting input end. The first driver module DRV1, the second driver module DRV2, and the third driver module DRV3 all receive the clock signal clk. Among them, the first power transistor M1 and the third power transistor M3 are both PMOS power transistors, and the second power transistor M2 and the fourth power transistor M4 are both NMOS power transistors.

[0030] The first, second, and third driver modules DRV1, DRV2, and DRV3 serve as driver modules for the second, third, and fourth power transistors M2, M3, and M4, respectively, and are configured to output drive signals VGMN1, VGMP2, and VGMN2. The first power transistor M1 is driven by an error amplifier EA and is connected between the error voltage VC and the signal VGMP1 by a first switch SW1 controlled by the clock signal clk. When the clock signal clk is low, the first switch SW1 is turned on, and the voltage of the signal VGMP1 equals the error voltage VC. When the clock signal clk is high, the first switch SW1 is turned off, and the signal VGMP1 is high. The first and second resistors R1 and R2 function as a voltage divider resistor string. The generated feedback voltage is compared with the second reference voltage VREF2 to adjust the error voltage VC, thereby adjusting the gate-source voltage VGS of the first power transistor M1. This changes the on-resistance of the first power transistor M1, which in turn causes a change in the output voltage VOUT. This constitutes a feedback system that allows the output voltage VOUT to be controlled.

[0031] When the clock signal clk is low, the first and third power transistors M1 and M3 are turned on, while the second and fourth power transistors M2 and M4 are turned off. The first end of the flying capacitor Cfly is connected to the input voltage VIN through the first power transistor M1, and the second end of the flying capacitor Cfly is connected to ground through the third power transistor M3. The input voltage VIN charges the flying capacitor Cfly, and the flying capacitor Cfly stores energy. When the clock signal clk is high, the second and fourth power transistors M2 and M4 are turned on, while the first and third power transistors M1 and M3 are turned off. The first end of the flying capacitor Cfly is connected to ground through the second power transistor M2, and the second end of the flying capacitor Cfly is connected to the output capacitor Cout through the fourth power transistor M4. The flying capacitor Cfly charges the output capacitor Cout, transferring energy to the output capacitor Cout. During discharge, the direction of the flying capacitor Cfly reverses, resulting in a negative output voltage VOUT. Ignoring the on-resistance of the power tube, the existing charge pump can generate a maximum output voltage VOUT of -VIN. The output voltage VOUT can also be set by the first reference voltages VREF1 and VREF2.

[0032] Figure 2The operating timing of a conventional charge pump is shown. As the load current Iload decreases, the ripple of the output voltage VOUT decreases with each clock cycle. If the first power transistor M1 maintains its previous conduction level, the charge replenished by the output voltage Cout during each clock cycle will exceed the charge consumed, causing the absolute value of the output voltage VOUT to increase. In practice, the first resistor R1 and the second resistor R2 act as a feedback unit. If the output voltage VOUT decreases, i.e., its absolute value increases, the feedback voltage is fed back to the inverting input of the error amplifier EA, increasing the error voltage VC generated by the error amplifier EA. When the clock signal clk is low, the conduction level of the first power transistor M1 decreases, increasing its on-resistance. This reduces the energy transferred to the flying capacitor Cfly during each clock cycle, as well as the energy transferred from the flying capacitor Cfly to the output capacitor Cout. This feedback mechanism causes the error voltage VC to increase as the load current Iload decreases. When the clock signal clk is low, the first switch SW1 is turned on, and the voltage of the signal VGMP1 equals the error voltage VC. Like the error voltage VC, the low level of the signal VGMP1 increases as the load current Iload decreases. Signals VGMP1, VGMN1, VGMP2, and VGMN2 are all in phase with the clock signal clk. Regardless of load variations, each clock cycle controls the on / off switching of the first power transistor M1, the second power transistor M2, the third power transistor M3, and the fourth power transistor M4. In actual designs, to reduce the voltage drop between the output voltage VOUT and the absolute value of the input voltage VIN, and to improve the charge pump's conversion efficiency under heavy loads, the power transistors are typically larger, considering their on-resistance is the primary factor. This reduces their on-resistance. However, under light loads, driving large power transistors consumes a significant amount of operating current, significantly reducing conversion efficiency.

[0033] In order to solve the above problems, the present invention provides a negative voltage charge pump circuit. Figure 3As shown, the negative voltage charge pump circuit adds a reference voltage generating module 10, a comparison module 20, a fourth driving module 30, a fifth power tube M5, a sixth power tube M6 and a seventh power tube M7 to the existing charge pump. The size of the fifth power tube M5 is smaller than that of the second power tube M2 and the two are of the same type. The size of the sixth power tube M6 is smaller than that of the third power tube M3 and the two are of the same type. The size of the seventh power tube M7 is smaller than that of the fourth power tube M4 and the two are of the same type. The comparison module 20 is respectively connected to the reference voltage generation module 10, the output end of the error amplifier EA and the fourth driving module 30. The fourth driving module 30 is respectively connected to the first driving module DRV1, the second driving module DRV2, the third driving module DRV3, the gate of the fifth power tube M5, the gate of the sixth power tube M6 and the gate of the seventh power tube M7. The drain of the fifth power tube M5 is connected to the drain of the second power tube M2, the source of the fifth power tube M5 is connected to the source of the second power tube M2, the drain of the sixth power tube M6 is connected to the source of the third power tube M3, the source of the sixth power tube M6 is connected to the drain of the third power tube M3, the drain of the seventh power tube M7 is connected to the drain of the fourth power tube M4, and the source of the seventh power tube M7 is connected to the source of the fourth power tube M4.

[0034] Specifically, the reference voltage generation module 10 is configured to generate a third reference voltage VREF3 based on a first current. The first current is proportional to the current flowing through the first power transistor M1. The current flowing through the first power transistor M1 represents the load current Iload. Therefore, the first current represents the load current Iload. Therefore, the third reference voltage VREF3 generated by the reference voltage generation module 10 based on the first current can serve as a threshold voltage for the negative voltage charge pump circuit when it enters a light-load state. The comparison module 20 is configured to compare the error voltage VC output by the error amplifier EA with the third reference voltage VREF3. When the error voltage VC is greater than the third reference voltage VREF3, it indicates that the negative voltage charge pump circuit has entered a light-load state, and a first comparison signal is output at this time. The fourth driver module 30 is configured to receive a clock signal clk and output a first drive signal VGMN1W, a second drive signal VGMP2W, and a third drive signal VGMN2W based on the clock signal clk, respectively driving the fifth power transistor M5, the sixth power transistor M6, and the seventh power transistor M7. Furthermore, the fourth driver module 30 outputs a first control signal, a second control signal, and a third control signal based on the clock signal clk and a first comparison signal, respectively shutting down the first driver module DRV1, the second driver module DRV2, and the third driver module DRV3, thereby shutting down the second power transistor M2, the third power transistor M3, and the fourth power transistor M4. Thus, when the negative charge pump circuit enters a light-load operating condition, the large-sized power transistors and their driver modules are shut down, leaving only the small-sized power transistors in operation to maintain a normal switching cycle of the negative charge pump circuit. This significantly reduces the operating current of the negative charge pump circuit under light load conditions while ensuring other performance characteristics of the negative charge pump circuit, thereby improving the conversion efficiency of the negative charge pump circuit under light load conditions.

[0035] In summary, the present application utilizes the reference voltage generation module 10 to generate a third reference voltage VREF3, and then compares the third reference voltage VREF3 with the error voltage VC output by the error amplifier through the comparison module 20 to determine whether the negative voltage charge pump circuit enters a light load condition. When the negative voltage charge pump circuit enters a light load condition, the large-size power tube and its driving module are turned off, and only the small-size power tube is operated. While ensuring other performances of the negative voltage charge pump circuit, the operating current of the negative voltage charge pump circuit at light load is greatly reduced, thereby improving the conversion efficiency of the negative voltage charge pump circuit at light load.

[0036] It should be noted that the driving power tube mentioned in this application means controlling the power tube to be turned on and off so that it is periodically turned on and off according to the clock cycle of the clock signal clk.

[0037] In some embodiments, the comparison module 20 is further configured to output a second comparison signal when the error voltage VC is less than the third reference voltage VREF3, indicating that the negative charge pump circuit has entered a heavy-load condition. When this occurs, the fourth driver module 30 is further configured to output a fourth control signal, a fifth control signal, and a sixth control signal based on the second comparison signal and the clock signal clk, respectively controlling the first driver module DRV1 to drive the second power transistor M2, the second driver module DRV2 to drive the third power transistor M3, and the third driver module DRV3 to drive the fourth power transistor M4. It should be noted that the fifth power transistor M5, the sixth power transistor M6, and the seventh power transistor M7 remain in operation, and their drive signals are not affected by the comparison signal. Thus, when the negative charge pump circuit enters a heavy-load condition, the large-sized power transistors and the small-sized power transistors operate together, and the large-sized power transistors can maintain the high conversion efficiency of the negative charge pump circuit under heavy load.

[0038] In some embodiments, as Figure 4 As shown, the fourth driving module 30 includes a first driving unit 31, a second driving unit 32 and a third driving unit 33. The first driving unit 31 is respectively connected to the comparison module 20, the second driving unit 32, the third driving unit 33, the first driving module DRV1 and the gate of the fifth power tube M5. The second driving unit 32 is respectively connected to the gate of the second driving module DRV2 and the sixth power tube M6. The third driving unit 33 is respectively connected to the gate of the third driving module DRV3 and the seventh power tube M7.

[0039] Specifically, the first driving unit 31 is used to output a first driving signal according to the clock signal clk to drive the fifth power tube M5; at the same time, it also outputs a first control signal according to the clock signal clk and the first comparison signal to turn off the first driving module DRV1 and then turn off the second power tube M2.

[0040] The second driving unit 32 is used to output a second driving signal according to the clock signal clk to drive the sixth power tube M6; and also output a second control signal according to the clock signal clk and the first comparison signal to turn off the second driving module DRV2 and further turn off the third power tube M3.

[0041] The third driving unit 33 is used to output a third driving signal according to the clock signal clk to drive the seventh power tube M7; and also output a third control signal according to the clock signal clk and the first comparison signal to turn off the third driving module DRV3 and further turn off the fourth power tube M4.

[0042] From the above, it can be seen that when the negative voltage charge pump circuit enters the light load condition, the large-size power tube and its driving module are turned off, and only the small-size power tube is operated. While ensuring other performances of the negative voltage charge pump circuit, the operating current of the negative voltage charge pump circuit under light load is greatly reduced, thereby improving the conversion efficiency of the negative voltage charge pump circuit under light load.

[0043] The first driver unit 31 is further configured to output a fourth control signal based on the clock signal clk and the second comparison signal, for controlling the first driver module DRV1 to drive the second power transistor M2. The second driver unit 32 is further configured to output a fifth control signal based on the clock signal clk and the second comparison signal, for controlling the second driver module DRV2 to drive the third power transistor M3. The third driver unit 33 is configured to output a sixth control signal based on the clock signal clk and the second comparison signal, for controlling the third driver module DRV3 to drive the fourth power transistor M4. At this time, the fifth power transistor M5, the sixth power transistor M6, and the seventh power transistor M7 are still in operation.

[0044] From the above, it can be seen that when the negative voltage charge pump circuit enters a heavy load condition, the large-size power tube and the small-size power tube work together, and the large-size power tube can maintain the high conversion efficiency of the negative voltage charge pump circuit under heavy load.

[0045] In some embodiments, as Figure 5 As shown, the reference voltage generating module 10 includes an eighth power tube M8 and a current source. The drain of the eighth power tube M8 receives the input voltage VIN, the gate of the eighth power tube M8 is connected to the source of the eighth power tube M8, the first end of the current source and the comparison module 20 respectively, and the second end of the current source is grounded. The eighth power tube M8 and the first power tube M1 are power tubes of the same type and have the same size.

[0046] Specifically, the first current IREF1 generated by the current source passes through the eighth power transistor M8 to generate a third reference voltage VREF3. Since the eighth power transistor M8 and the first power transistor M1 are of the same type and are matched, the first current IREF1 is proportional to the current flowing through the first power transistor M1. Since the current flowing through the first power transistor M1 represents the load current Iload, the first current IREF1 represents the load current Iload. Therefore, the third reference voltage VREF3 generated based on the first current IREF1 can serve as the threshold voltage for the negative voltage charge pump circuit to enter a light-load state. When the error voltage VC is greater than the third reference voltage VREF3, the negative voltage charge pump circuit enters a light-load state. When the error voltage VC is less than the third reference voltage VREF3, the negative voltage charge pump circuit enters a heavy-load state. It should be noted that since the eighth power transistor M8 and the first power transistor M1 are of the same type and are matched, the third reference voltage VREF3 can adapt to variations in process corners (i.e., production variations), thereby narrowing the range of variation in the load current threshold when switching power transistor sizes.

[0047] In some embodiments, as Figure 5 As shown, the comparison module 20 includes a comparator COMP and an inverter INV, a first input terminal of the comparator COMP is connected to the reference voltage generation module 10, a second input terminal of the comparator COMP is connected to the output terminal of the error amplifier EA, an output terminal of the comparator COMP is connected to the input terminal of the inverter INV, and an output terminal of the inverter INV is connected to the fourth driving module 30. In the present application, the first input terminal of the comparator COMP is the inverting input terminal, and the second input terminal of the comparator COMP is the non-inverting input terminal.

[0048] Specifically, the comparator COMP compares the error voltage VC output by the error amplifier EA with the third reference voltage VREF3. When the error voltage VC is greater than the third reference voltage VREF3, the output signal SAVE_POWER is flipped to a high level, and after being inverted by the inverter INV, the first comparison signal is output, and the first comparison signal is a low level.

[0049] When the error voltage VC is less than the third reference voltage VREF3, the output signal SAVE_POWER is flipped to a low level, and after being inverted by the inverter INV, a second comparison signal is output, and the second comparison signal is a high level.

[0050] In some embodiments, as Figure 5As shown, the first driving unit 31 includes a first AND gate AND1 and a first driving sub-unit DRV_MN1W. The first input end of the first AND gate AND1 is respectively connected to the comparison module 20, the second driving unit 32 and the third driving unit 33, the output end of the first AND gate AND1 is connected to the first driving module DRV1, the output end of the first driving sub-unit DRV_MN1W is connected to the gate of the fifth power tube M5, and the second input end of the first AND gate AND1 and the input end of the first driving sub-unit DRV_MN1W both receive the clock signal clk.

[0051] Specifically, when the error voltage VC is greater than the third reference voltage VREF3, the first comparison signal output by the comparison module 20 is low. Since the first comparison signal is low, the first control signal output by the first AND gate AND1 is also low, which is used to turn off the first driver module DRV1 and, in turn, the second power transistor M2.

[0052] When the error voltage VC is less than the third reference voltage VREF3, the second comparison signal output by the comparison module 20 is at a high level. Since the second comparison signal is at a high level, the fourth control signal output by the first AND gate AND1 is in phase with the clock signal clk and is used to control the first driver module DRV1 to drive the second power transistor M2.

[0053] The first driving subunit DRV_MN1W is only controlled by the clock signal clk. Therefore, no matter what working condition the negative voltage charge pump circuit is in, the first driving subunit DRV_MN1W always outputs the first driving signal according to the clock signal clk to drive the fifth power transistor M5.

[0054] In some embodiments, as Figure 5 As shown, the second driving unit 32 includes a second AND gate AND2 and a second driving sub-unit DRV_MP2W, the first input end of the second AND gate AND2 is respectively connected to the comparison module 20, the first driving unit 31 and the third driving unit 33, the output end of the second AND gate AND2 is connected to the second driving module DRV2, the output end of the second driving sub-unit DRV_MP2W is connected to the gate of the sixth power tube M6, and the second input end of the second AND gate AND2 and the input end of the second driving sub-unit DRV_MP2W both receive the clock signal clk.

[0055] Specifically, when the error voltage VC is greater than the third reference voltage VREF3, the first comparison signal output by the comparison module 20 is low. Since the first comparison signal is low, the second control signal output by the second AND gate AND2 is also low, which is used to turn off the second driver module DRV2 and, in turn, the third power transistor M3.

[0056] When the error voltage VC is less than the third reference voltage VREF3, the second comparison signal output by the comparison module 20 is at a high level. Since the second comparison signal is at a high level, the fifth control signal output by the second AND gate AND2 is in phase with the clock signal clk, and is used to control the second driver module DRV2 to drive the third power transistor M3.

[0057] The second driving subunit DRV_MP2W is only controlled by the clock signal clk. Therefore, no matter what working condition the negative voltage charge pump circuit is in, the second driving subunit DRV_MP2W always outputs the second driving signal according to the clock signal clk to drive the sixth power transistor M6.

[0058] In some embodiments, as Figure 5 As shown, the third driving unit 33 includes a third AND gate AND3 and a third driving sub-unit DRV_MN2W. The first input end of the third AND gate AND3 is respectively connected to the comparison module 20, the first driving unit 31 and the second driving unit 32, the output end of the third AND gate AND3 is connected to the third driving module DRV3, the output end of the third driving sub-unit DRV_MN2W is connected to the gate of the seventh power tube M7, and the second input end of the third AND gate AND3 and the input end of the third driving sub-unit DRV_MN2W both receive the clock signal clk.

[0059] Specifically, when the error voltage VC is greater than the third reference voltage VREF3, the first comparison signal output by the comparison module 20 is low. Since the first comparison signal is low, the third control signal output by the third AND gate AND3 is also low, which is used to disable the third driver module DRV3 and, in turn, turn off the fourth power transistor M4.

[0060] When the error voltage VC is less than the third reference voltage VREF3, the second comparison signal output by the comparison module 20 is at a high level. Since the second comparison signal is at a high level, the sixth control signal output by the third AND gate AND3 is in phase with the clock signal clk and is used to control the third driver module DRV3 to drive the fourth power transistor M4.

[0061] The third driving subunit DRV_MN2W is only controlled by the clock signal clk. Therefore, no matter what working condition the negative voltage charge pump circuit is in, the third driving subunit DRV_MN2W always outputs the third driving signal according to the clock signal clk to drive the seventh power transistor M7.

[0062] Combine Figure 5 and Figure 6 Explain how this application works.

[0063] like Figure 5As shown, the first current IREF1 passes through the eighth power transistor M8 to generate the third reference voltage VREF3. The eighth power transistor M8 and the first power transistor M1 are of the same type and are matched. The first current IREF1 is proportional to the current flowing through the first power transistor M1. The current flowing through the first power transistor M1 represents the load current Iload. Therefore, the first current IREF1 represents the load current Iload. The error voltage VC is compared with the third reference voltage VREF3. When the load current Iload decreases, the error voltage VC increases. When the error voltage VC reaches the third reference voltage VREF3, the output of the comparator COMP flips high, i.e., the signal SAVE_POWER flips high. After passing through the inverter INV, the first comparison signal is generated, which is at a low level. The first comparison signal is respectively transmitted through three AND gates to disable the three driver modules, thereby shutting down the large-size power transistors and only operating the small-size power transistors, maintaining the normal switching cycle of the negative charge pump circuit and ensuring a normal output voltage VOUT.

[0064] Taking the second power tube M2 and the fifth power tube M5 as an example, when the negative voltage charge pump circuit is heavily loaded, both power tubes operate together. The larger size of the second power tube M2 allows for high efficiency under heavy loads. Under light loads, only the fifth power tube M5 operates, shutting down the second power tube M2 and its first driver module DRV1. Therefore, neither the second power tube M2 nor its first driver module DRV1 generates current. Due to the smaller size of the fifth power tube M5, the drive current of the first driver subunit DRV_MN1W can be reduced to a relatively low level. The same applies to the third power tube M3, the sixth power tube M6, the fourth power tube M4, and the seventh power tube M7. Through the above control method, the operating current under light loads can be significantly reduced, improving the conversion efficiency of the negative voltage charge pump circuit while ensuring other circuit performance.

[0065] like Figure 6 As shown, after the output voltage VOUT of the negative charge pump circuit stabilizes, the load current Iload gradually decreases, the error voltage VC gradually increases, and the low potential of the signal VGMP1 also gradually increases. When the error voltage VC reaches the third reference voltage VREF3, the comparator COMP flips, the signal SAVE_POWER goes high, and the first drive signal VGMN1W, the second drive signal VGMP2W, and the third drive signal VGMN2W are not affected. The drive signal VGMN1S for the second power transistor M2 and the drive signal VGMN2S for the fourth power transistor M4 remain constant low, and the drive signal VGMP2S for the third power transistor M3 remains constant high, thereby shutting down the second power transistor M2, the third power transistor M3, and the fourth power transistor M4.

[0066] This application detects the load current Iload and utilizes the current IREF1 and the eighth power transistor M8 to generate a third reference voltage VREF3. This is then compared with the error voltage VC output by the error amplifier EA to determine whether the circuit is lightly loaded. Under light load conditions, the large power transistor and its driver module are turned off, leaving only the small power transistor operational. This significantly reduces the circuit's operating current while maintaining other circuit performance, thereby improving the circuit's conversion efficiency under light load conditions. Under heavy load conditions, both the large and small power transistors operate together to maintain high conversion efficiency.

[0067] The present invention also provides a switching power converter including the negative charge pump circuit described above. Because the switching power converter provided by the present invention includes the negative charge pump circuit described above, the switching power converter provided by the present invention has the advantage of high conversion efficiency under light load conditions.

[0068] The present application also provides an electronic device including the switching power converter described above. Since the electronic device provided in the present application utilizes all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be detailed here.

[0069] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0070] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A negative voltage charge pump circuit, comprising a first power tube, a second power tube, a third power tube, a fourth power tube, an output capacitor, an output resistor, a first resistor, a second resistor, a flying capacitor, a first switch, an error amplifier, a first driver module, a second driver module, and a third driver module, wherein the source of the first power tube receives an input voltage, the gate of the first power tube is connected to the first end of the first switch, the second end of the first switch is connected to the output end of the error amplifier, the control end of the first switch receives a clock signal, the drain of the first power tube is respectively connected to the drain of the second power tube and the first end of the flying capacitor, the gate of the second power tube is connected to the first driver module, and the The source of the second power tube and the source of the third power tube are both grounded, the gate of the third power tube is connected to the second driving module, the drain of the third power tube is respectively connected to the drain of the fourth power tube and the second end of the flying capacitor, the gate of the fourth power tube is connected to the third driving module, the source of the fourth power tube is respectively connected to the first end of the output capacitor, the first end of the output resistor, and the first end of the second resistor, the second end of the second resistor is respectively connected to the first end of the first resistor and the first input end of the error amplifier, the second end of the first resistor receives a first reference voltage, and the second input end of the error amplifier receives a second reference voltage; characterized in that: The negative voltage charge pump circuit further includes a reference voltage generating module, a comparison module, a fourth driving module, a fifth power tube, a sixth power tube, and a seventh power tube. The fifth power tube is smaller in size than the second power tube and of the same type. The sixth power tube is smaller in size than the third power tube and of the same type. The seventh power tube is smaller in size than the fourth power tube and of the same type. The comparison module is respectively connected to the reference voltage generating module, the output end of the error amplifier, and the fourth driving module. The fourth driving module is respectively connected to the first driving module, the second driving module, the third driving module, the gate of the fifth power tube, the gate of the sixth power tube, and the gate of the seventh power tube. The drain of the fifth power tube is connected to the drain of the second power tube, the source of the fifth power tube is connected to the source of the second power tube, the drain of the sixth power tube is connected to the source of the third power tube, the source of the sixth power tube is connected to the drain of the third power tube, the drain of the seventh power tube is connected to the drain of the fourth power tube, and the source of the seventh power tube is connected to the source of the fourth power tube. The reference voltage generating module is used to generate a third reference voltage according to the first current, where the first current is proportional to the current flowing through the first power tube; The comparison module is used to compare the error voltage output by the error amplifier with the third reference voltage, and output a first comparison signal when the error voltage is greater than the third reference voltage; The fourth driving module is used to receive a clock signal and output a first driving signal, a second driving signal and a third driving signal according to the clock signal, which are respectively used to drive the fifth power tube, the sixth power tube and the seventh power tube; and at the same time, it also outputs a first control signal, a second control signal and a third control signal according to the clock signal and the first comparison signal, which are respectively used to turn off the first driving module, the second driving module and the third driving module, and then turn off the second power tube, the third power tube and the fourth power tube.

2. The negative voltage charge pump circuit according to claim 1, wherein: The comparison module is further used to output a second comparison signal when the error voltage is less than the third reference voltage; the fourth driving module is further used to output a fourth control signal, a fifth control signal and a sixth control signal according to the second comparison signal and the clock signal, which are respectively used to control the first driving module to drive the second power tube, the second driving module to drive the third power tube and the third driving module to drive the fourth power tube.

3. The negative voltage charge pump circuit according to claim 1 or 2, characterized in that: The reference voltage generation module includes an eighth power tube and a current source, the drain of the eighth power tube receives the input voltage, the gate of the eighth power tube is respectively connected to the source of the eighth power tube, the first end of the current source and the comparison module, and the second end of the current source is grounded; wherein the eighth power tube and the first power tube are power tubes of the same type and have the same size.

4. The negative voltage charge pump circuit according to claim 1 or 2, characterized in that: The comparison module includes a comparator and an inverter, the first input end of the comparator is connected to the reference voltage generation module, the second input end of the comparator is connected to the output end of the error amplifier, the output end of the comparator is connected to the input end of the inverter, and the output end of the inverter is connected to the fourth driving module.

5. The negative voltage charge pump circuit according to claim 1 or 2, characterized in that: The fourth driving module includes a first driving unit, a second driving unit, and a third driving unit, wherein the first driving unit is respectively connected to the comparison module, the second driving unit, the third driving unit, the first driving module, and the gate of the fifth power tube; the second driving unit is respectively connected to the second driving module and the gate of the sixth power tube; and the third driving unit is respectively connected to the third driving module and the gate of the seventh power tube; The first driving unit is configured to output a first driving signal according to the clock signal, for driving the fifth power tube; and also output a first control signal according to the clock signal and the first comparison signal, for turning off the first driving module, thereby turning off the second power tube; The second driving unit is configured to output a second driving signal according to the clock signal, so as to drive the sixth power tube; and also output a second control signal according to the clock signal and the first comparison signal, so as to turn off the second driving module and thereby turn off the third power tube; The third driving unit is used to output a third driving signal according to the clock signal to drive the seventh power tube; and also output a third control signal according to the clock signal and the first comparison signal to turn off the third driving module and thereby turn off the fourth power tube.

6. The negative voltage charge pump circuit according to claim 5, characterized in that: The first driving unit includes a first AND gate and a first driving sub-unit, the first input end of the first AND gate is respectively connected to the comparison module, the second driving unit and the third driving unit, the output end of the first AND gate is connected to the first driving module, the output end of the first driving sub-unit is connected to the gate of the fifth power tube, and the second input end of the first AND gate and the input end of the first driving sub-unit both receive the clock signal.

7. The negative voltage charge pump circuit according to claim 5, wherein: The second driving unit includes a second AND gate and a second driving sub-unit, the first input end of the second AND gate is respectively connected to the comparison module, the first driving unit and the third driving unit, the output end of the second AND gate is connected to the second driving module, the output end of the second driving sub-unit is connected to the gate of the sixth power tube, and the second input end of the second AND gate and the input end of the second driving sub-unit both receive the clock signal.

8. The negative voltage charge pump circuit according to claim 5, wherein: The third driving unit includes a third AND gate and a third driving sub-unit, the first input end of the third AND gate is respectively connected to the comparison module, the first driving unit and the second driving unit, the output end of the third AND gate is connected to the third driving module, the output end of the third driving sub-unit is connected to the gate of the seventh power tube, and the second input end of the third AND gate and the input end of the third driving sub-unit both receive the clock signal.

9. A switching power converter, characterized in that: The negative voltage charge pump circuit comprises the negative voltage charge pump circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: Including the switching power converter according to claim 9.

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