Hardware protection circuit with self-locking and delayed resetting functions

Abstract

The invention discloses a hardware protection circuit with a self-locking function and a delayed reset function, and relates to the technical field of circuits, the hardware circuit comprises a trigger module, a first protection module, a second protection module and a third protection module, the circuit implementation cost is low, and functions can be achieved only through five signal MOS tubes, a comparator and a plurality of resistors and capacitors. The trigger module is used for triggering the first protection module at a low level under the condition that the hardware to be protected has a circuit fault, and the first protection module is used for outputting a fault signal of the hardware to be protected and performing self-locking on the fault signal, so that the functions of fault latching and delayed resetting can be independently realized by completely separating from software; the second protection module is used for recovering circuit faults of the hardware to be protected and determining the reset delay time of the first protection module, the fault reset delay time can be adjusted, the first protection module is controlled to reset through the third protection module under the condition that the reset delay time is overtime, and the circuit trigger response speed is high.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technology, and in particular to a hardware protection circuit with self-locking and delayed reset capabilities. Background Art

[0002] In some simpler devices, microcontrollers or programmable devices are not used to save costs, so the devices do not have software protection functions. Even if they have software protection functions, they cannot achieve a fast response by relying solely on software protection functions. Therefore, hardware protection circuits with certain functions are required.

[0003] Existing hardware protection circuits mainly shut down the output by directly connecting the fault signal to the enable pin of the functional chip and turning off the enable of the functional chip.

[0004] However, the hardware protection circuit of the connected functional chip does not have the self-locking capability. When the fault signal time is too short, the hardware protection circuit will not trigger the protection. Most functional chips do not have the fault recovery function, which will cause the circuit to be unable to complete the fault reset. Summary of the Invention

[0005] In view of this, the present disclosure provides a hardware protection circuit with self-locking and delayed reset, which can solve the technical problems that the existing hardware protection circuit does not have self-locking capability, the hardware protection circuit will not trigger protection when the fault signal time is too short, and most functional chips do not have fault recovery function, which will cause the circuit to be unable to complete fault reset.

[0006] To achieve the above-mentioned object, a first embodiment of the present disclosure provides a hardware protection circuit with self-locking and delayed reset, the hardware protection circuit comprising: a trigger module, a first protection module, a second protection module and a third protection module;

[0007] The first end of the trigger module is externally connected to the protection hardware, the second end of the trigger module is connected to the first end of the first protection module and the first end of the second protection module, the second end of the trigger module is externally connected to a power supply, and the third end of the trigger module is connected to the second end of the first protection module and the first end of the third protection module;

[0008] The third end of the first protection module is connected to the second end of the second protection module, the third end of the first protection module is connected to an external output port, the fourth end of the first protection module is connected to the third end of the second protection module and the second end of the third protection module, the second end of the third protection module is grounded, and the fourth end of the second protection module is connected to the third end of the third protection module;

[0009] The trigger module is used to trigger the first protection module at a low level when a circuit fault occurs in the hardware to be protected. The first protection module is used to output a fault signal of the hardware to be protected and self-lock the fault signal;

[0010] The second protection module is used to recover circuit faults of the hardware to be protected, determine the reset delay time of the first protection module, and control the first protection module to reset through the third protection module when the reset delay time times out.

[0011] Optionally, the trigger module includes: a first trigger unit and a second trigger unit;

[0012] The first end of the first trigger unit is externally connected to the hardware to be protected, and the second end of the first trigger unit is connected to the first end of the second trigger unit;

[0013] The second end of the second trigger unit is connected to the first end of the first protection module and the first end of the second protection module, the second end of the second trigger unit is externally connected to a power supply, and the third end of the second trigger unit is connected to the second end of the first protection module and the first end of the third protection module.

[0014] The first trigger unit is used to trigger a low-level signal when a circuit fault occurs in the hardware to be protected, and the second trigger unit is used to trigger the first protection module to turn on when receiving the low-level signal.

[0015] Optionally, the first trigger unit includes: at least one parallel diode;

[0016] The cathode of the at least one parallel diode is externally connected to the hardware to be protected, and the anode of the at least one parallel diode is connected to the first end of the second trigger unit.

[0017] Optionally, the second trigger unit includes: a first switch tube and a first resistor;

[0018] The gate of the first switching tube is connected to the first end of the first resistor and the second end of the first trigger module, the source of the first switching tube is connected to the second end of the first resistor and the first end of the first protection module, the source of the first switching tube is connected to an external power supply, and the drain of the first switching tube is connected to the second end of the first protection module and the first end of the third protection module.

[0019] Optionally, the first protection module includes: a second switch tube, a third switch tube, a second resistor and a third resistor;

[0020] The source of the second switching tube is connected to the first end of the second resistor, the drain of the second switching tube is connected to the gate of the third switching tube, the third end of the trigger module, and the first end of the third protection module, the gate of the second switching tube is connected to the drain of the third switching tube, the first end of the third resistor, and the second end of the second protection module, and the gate of the second switching tube is connected to the external output port.

[0021] Optionally, the second end of the second resistor is connected to the second end of the third resistor, the second end of the trigger module, and the first end of the second protection module, and the source of the third switch tube is connected to the third end of the second protection module and the second end of the third protection module.

[0022] Optionally, the second protection module includes: a first protection unit and a second protection unit;

[0023] The first end of the first protection unit is connected to the first end of the first protection module and the first end of the second protection unit, the second end of the first protection unit is connected to the third end of the first protection module, the third end of the first protection unit is connected to the fourth end of the first protection module, the second end of the third protection module, and the second end of the second protection unit, and the fourth end of the first protection unit is connected to the third end of the second protection unit;

[0024] The fourth end of the second protection unit is connected to the third end of the third protection module;

[0025] The first protection unit is used to determine the reset delay time of the first protection module when the circuit fault of the hardware to be protected is restored. The second protection unit is used to determine that the reset delay time has expired and control the first protection module to reset through the third protection module.

[0026] Optionally, the first protection unit includes: a fourth switch tube, a capacitor and a fourth resistor;

[0027] The gate of the fourth switching tube is connected to the third end of the first protection module, the source of the fourth switching tube is connected to the fourth end of the first protection module, the second end of the third protection module, the second end of the second protection unit, and the first end of the capacitor, and the drain of the fourth switching tube is connected to the second end of the capacitor, the first end of the fourth resistor, and the third end of the second protection module;

[0028] The second end of the fourth resistor is connected to the first end of the second protection module.

[0029] Optionally, the second protection unit includes: a fifth resistor, a sixth resistor, a seventh resistor and a comparator;

[0030] The positive input terminal of the comparator is connected to the fourth terminal of the first protection unit, the negative input terminal of the comparator is connected to the first terminal of the fifth resistor and the first terminal of the sixth resistor, and the output terminal of the comparator is connected to the first terminal of the seventh resistor;

[0031] The second end of the fifth resistor is connected to the first end of the first protection unit, the second end of the sixth resistor is connected to the third end of the first protection unit and the second end of the third protection module, and the second end of the seventh resistor is connected to the third end of the third protection module.

[0032] Optionally, the third protection module includes: a fifth switch tube, an eighth resistor and a ninth resistor;

[0033] The gate of the fifth switching tube is connected to the fourth terminal of the second protection module, the source of the fifth switching tube is connected to the fourth terminal of the first protection module, the third terminal of the second protection module, and the first terminal of the eighth resistor, the source of the fifth switching tube is grounded, and the drain of the fifth switching tube is connected to the first terminal of the ninth resistor;

[0034] The second end of the eighth resistor is connected to the third end of the trigger module, the second end of the first protection module, and the second end of the ninth resistor.

[0035] The present disclosure provides a hardware protection circuit with self-locking and delayed reset, comprising a trigger module, a first protection module, a second protection module and a third protection module. The first end of the trigger module is externally connected to the protection hardware, the second end of the trigger module is connected to the first end of the first protection module and the first end of the second protection module, the second end of the trigger module is externally connected to a power supply, the third end of the trigger module is connected to the second end of the first protection module and the first end of the third protection module; the third end of the first protection module is connected to the second end of the second protection module, the third end of the first protection module is externally connected to an output port, and the fourth end of the first protection module is connected to the second protection module. The third end of the protection module and the second end of the third protection module are connected, the second end of the third protection module is grounded, and the fourth end of the second protection module is connected to the third end of the third protection module; the trigger module is used to trigger the first protection module at a low level when a circuit fault occurs in the hardware to be protected, and the first protection module is used to output a fault signal of the hardware to be protected and self-lock the fault signal; the second protection module is used to recover from the circuit fault of the hardware to be protected, determine the reset delay time of the first protection module, and control the first protection module to reset through the third protection module when the reset delay time expires. Compared with the current existing technology, the hardware protection circuit of the present application includes a trigger module, a first protection module, a second protection module and a third protection module. The circuit implementation cost is low, and only five signal MOS tubes, one comparator and several resistors and capacitors are required to realize the function. The trigger module is used to trigger the first protection module at a low level when a circuit fault occurs in the hardware to be protected. The first protection module is used to output the fault signal of the hardware to be protected and self-lock the fault signal, thereby being able to independently implement the fault latching and delayed reset functions completely without software; the second protection module is used to recover from the circuit fault of the hardware to be protected and determine the reset delay time of the first protection module. The fault reset delay time can be adjusted, and when the reset delay time times out, the first protection module is controlled to be reset through the third protection module. There is no complicated information response process, and the circuit trigger response speed is fast.

[0036] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0038] Figure 1 A schematic diagram of the circuit structure of a hardware protection circuit with self-locking and delayed reset provided by an embodiment of the present disclosure is shown;

[0039] In the picture:

[0040] 1-trigger module (not shown in the figure), 11-first trigger unit, 12-second trigger unit;

[0041] 2-first protection module;

[0042] 3-second protection module (not shown in the figure), 31-first protection unit, 32-second protection unit;

[0043] 4- The third protection module. DETAILED DESCRIPTION

[0044] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0046] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0047] The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

[0048] The following combination Figure 1 A hardware protection circuit according to some embodiments of the present disclosure is described.

[0049] The embodiment of the present disclosure provides a hardware protection circuit with self-locking and delayed reset, such as Figure 1 As shown, the hardware protection circuit includes: a trigger module 1, a first protection module 2, a second protection module 3 and a third protection module 4; the first end of the trigger module 1 is externally connected to the protection hardware, the second end of the trigger module 1 is connected to the first end of the first protection module 2 and the first end of the second protection module 3, the second end of the trigger module 1 is externally connected to a power supply, the third end of the trigger module 1 is connected to the second end of the first protection module 2 and the first end of the third protection module 4; the third end of the first protection module 2 is connected to the second end of the second protection module 3, the third end of the first protection module 2 is externally connected to an output port, and the fourth end of the first protection module 2 is connected to the second protection module The third end of the block 3 and the second end of the third protection module 4 are connected, the second end of the third protection module 4 is grounded, and the fourth end of the second protection module 3 is connected to the third end of the third protection module 4; the trigger module 1 is used to trigger the first protection module 2 at a low level when a circuit fault occurs in the hardware to be protected, and the first protection module 2 is used to output a fault signal of the hardware to be protected and self-lock the fault signal; the second protection module 3 is used to recover from the circuit fault of the hardware to be protected, determine the reset delay time of the first protection module 2, and control the first protection module to reset through the third protection module 4 when the reset delay time times out.

[0050] In some examples, the trigger module 1 includes: a first trigger unit 11 and a second trigger unit 12;

[0051] A first end of the first trigger unit 11 receives protection hardware externally, and a second end of the first trigger unit 11 is connected to a first end of the second trigger unit 12;

[0052] The second end of the second trigger unit 12 is connected to the first end of the first protection module 2 and the first end of the second protection module 3. The second end of the second trigger unit 12 is connected to an external power supply. The third end of the second trigger unit 12 is connected to the second end of the first protection module 2 and the first end of the third protection module 4.

[0053] The first trigger unit 11 is used to trigger a low-level signal when a circuit fault occurs in the hardware to be protected. The second trigger unit 12 is used to trigger the first protection module 2 to turn on when receiving the low-level signal.

[0054] Accordingly, in some examples, the first trigger unit includes: at least one parallel diode DI1, DI2, ..., DIn;

[0055] A cathode of at least one parallel diode DI1 , DI2 . . . DIn is externally connected to the protection hardware, and an anode of at least one parallel diode DI1 , DI2 . . . DIn is connected to the first end of the second trigger unit 12 .

[0056] In this embodiment, the first trigger unit has multiple trigger input terminals, and can simultaneously detect multiple circuit faults of the hardware to be protected by triggering with a low level or a low pulse, thus widening the protection range.

[0057] In some examples, as a preferred embodiment, the second trigger unit 12 includes: a first switch tube D1 and a first resistor R1;

[0058] The gate of the first switch tube D1 is connected to the first end of the first resistor R1 and the second end of the first trigger module 11. The source of the first switch tube D1 is connected to the second end of the first resistor R1 and the first end of the first protection module 2. The source of the first switch tube D1 is connected to an external power supply. The drain of the first switch tube D1 is connected to the second end of the first protection module 2 and the first end of the third protection module 4.

[0059] It should be noted that the first switch D1 can be a PMOS (positive channel Metal Oxide Semiconductor) or a triode. Metal oxide semiconductor field effect (MOS) transistors can be divided into two categories: N-channel and P-channel. A P-channel silicon MOS field effect transistor has two P+ regions on an N-type silicon substrate, called the source and drain. There is no conduction between the two electrodes. When a sufficiently negative voltage is applied to the gate (the source is grounded), the N-type silicon surface beneath the gate exhibits a P-type inversion layer, forming a channel connecting the source and drain. Changing the gate voltage can alter the electron density in the channel, thereby changing the channel resistance. This type of MOS field effect transistor is called a P-channel enhancement-mode field effect transistor. If a P-type inversion layer channel already exists on the surface of the N-type silicon substrate without applying a gate voltage, applying an appropriate bias voltage can increase or decrease the channel resistance. This type of MOS field effect transistor is called a P-channel depletion-mode field effect transistor. PMOS circuits are simple to manufacture and inexpensive.

[0060] In some examples, the first protection module 2 includes: a second switch tube D2, a third switch tube D4, a second resistor R4 and a third resistor R5;

[0061] The source of the second switch tube D2 is connected to the first end of the second resistor R2, the drain of the second switch tube D2 is connected to the gate of the third switch tube D4, the third end of the trigger module 1, and the first end of the third protection module 4, the gate of the second switch tube D2 is connected to the drain of the third switch tube D4, the first end of the third resistor R5, and the second end of the second protection module 3, and the gate of the second switch tube D2 is connected to the external output port.

[0062] It should be noted that the second switch tube D2 may be a PMOS tube or a triode, and correspondingly, the third switch tube D4 may be an NMOS tube or a triode.

[0063] Furthermore, the second end of the second resistor R4 is connected to the second end of the third resistor R5, the second end of the trigger module 1, and the first end of the second protection module 3, and the source of the third switch tube D4 is connected to the third end of the second protection module 3 and the second end of the third protection module 4.

[0064] Accordingly, in some examples, the second protection module 3 includes: a first protection unit 31 and a second protection unit 32;

[0065] The first end of the first protection unit 31 is connected to the first end of the first protection module 2 and the first end of the second protection unit 32. The second end of the first protection unit 31 is connected to the third end of the first protection module 2. The third end of the first protection unit 31 is connected to the fourth end of the first protection module 2, the second end of the third protection module 4, and the second end of the second protection unit 32. The fourth end of the first protection unit 31 is connected to the third end of the second protection unit 32.

[0066] The fourth end of the second protection unit 32 is connected to the third end of the third protection module 4;

[0067] The first protection unit 31 is used to determine the reset delay time of the first protection module 2 when the circuit fault of the hardware to be protected is restored. The second protection unit 32 is used to determine that the reset delay time has expired and control the first protection module 2 to reset through the third protection module 4.

[0068] In the embodiment of the present application, the first protection unit 31 includes: a fourth switch tube D5, a capacitor C1 and a fourth resistor R6;

[0069] The gate of the fourth switch tube D5 is connected to the third terminal of the first protection module 2. The source of the fourth switch tube D5 is connected to the fourth terminal of the first protection module 2, the second terminal of the third protection module 4, the second terminal of the second protection unit 32, and the first terminal of the capacitor C1. The drain of the fourth switch tube D5 is connected to the second terminal of the capacitor C1, the first terminal of the fourth resistor R6, and the third terminal of the second protection module 3.

[0070] The second end of the fourth resistor R6 is connected to the first end of the second protection module 3 .

[0071] It should be noted that the fourth switch tube D5 can be an NMOS tube or a transistor.

[0072] In some examples, the second protection unit 32 includes: a fifth resistor R8, a sixth resistor R7, a seventh resistor R9, and a comparator U1;

[0073] The positive terminal of the input end of comparator U1 is connected to the fourth terminal of the first protection unit 2. The negative terminal of the input end of comparator U1 is connected to the first terminal of the fifth resistor R8 and the first terminal of the sixth resistor R7. The output end of comparator U1 is connected to the first terminal of the seventh resistor R9;

[0074] The second terminal of the fifth resistor R8 is connected to the first terminal of the first protection unit 31. The second terminal of the sixth resistor R7 is connected to the third terminal of the first protection unit 31 and the second terminal of the third protection module 4. The second terminal of the seventh resistor R9 is connected to the third terminal of the third protection module 4.

[0075] In the embodiment of the present application, the fault reset delay time can be adjusted by adjusting C1, R6, R7, and R8, as shown in the following formula (1):

[0076]

[0077] For this embodiment, the third protection module 4 includes: the fifth switch tube D3, the eighth resistor R2, and the ninth resistor R3;

[0078] The gate of the fifth switch tube D3 is connected to the fourth terminal of the second protection module 3. The source of the fifth switch tube D3 is connected to the fourth terminal of the first protection module 2, the third terminal of the second protection module 3, and the first terminal of the eighth resistor R2. The source of the fifth switch tube D3 is grounded. The drain of the fifth switch tube D3 is connected to the first terminal of the ninth resistor R3;

[0079] The second terminal of the eighth resistor R2 is connected to the third terminal of the trigger module 1, the second terminal of the first protection module 2, and the second terminal of the ninth resistor R3.

[0080] It should be noted that the fifth switch tube D3 can be an NMOS tube or a triode, and it needs to meet the condition of R3 << R4 << R2 to work properly.

[0081] For example, when any trigger terminal is pulled low, the gate of the PMOS D1 transistor is pulled low, the D1 transistor is turned on, the gate of the NMOS D4 transistor is pulled high, the D4 transistor is turned on, and the output terminal is pulled low, thereby outputting the fault information. The gate of the PMOS D2 transistor is connected to the output terminal and is also pulled low, and the D2 transistor is turned on to maintain the gate of the D4 high, thereby achieving self-locking of the fault information. At the same time, the gate of the NMOS D5 transistor is also connected to the output terminal. After the output terminal is pulled low, D5 is cut off, and the capacitor C1 begins to charge through R6. When the voltage across the capacitor is higher than the voltage set by R7 and R8, the comparator U1 outputs a high level, the NMOS D3 transistor is turned on, pulling the gate of the D4 low, and the D4 cut-off output terminal is pulled high to return to normal, thereby resetting the fault. After the output terminal is pulled high, D5 resumes conduction, releasing the energy in C1, and the voltage across C1 is clamped to 0V, completing the reset of the delay circuit. However, if the low-level fault signal at the trigger terminal is not restored, D1 remains on, and D3 cannot pull the gate of D4 down. The circuit will continue to maintain the fault state and can only be reset when the trigger signal is restored. This circuit uses a signal MOSFET for faster response and lower power consumption. However, this function can also be achieved with a simple circuit modification using a triode.

[0082] Compared with the current existing technology, the hardware protection circuit of the embodiment of the present application includes a trigger module, a first protection module, a second protection module, and a third protection module. The circuit implementation cost is low, and only five signal MOS tubes, a comparator, and a number of resistors and capacitors are required to realize the function. The trigger module is used to trigger the first protection module at a low level when a circuit fault occurs in the hardware to be protected. The first protection module is used to output a fault signal of the hardware to be protected and self-lock the fault signal, thereby being able to independently realize the functions of fault latching and delayed reset completely without software; the second protection module is used to recover from the circuit fault of the hardware to be protected, determine the reset delay time of the first protection module, and the fault reset delay time can be adjusted. When the reset delay time expires, the first protection module is controlled to reset through the third protection module. There is no complicated information response process, and the circuit trigger response speed is fast.

[0083] It should be noted that the technical solution in the present disclosure is not limited to use in the control of low-side switching circuits, but can also be extended to related applications of the same type that require control, which should all fall within the scope of protection of the present disclosure. No specific limitations are made here for the related applications that require control.

[0084] All articles and references disclosed above, including patent applications and publications, are incorporated herein by reference for all purposes. The term "consisting essentially of..." when describing a combination should include the identified elements, ingredients, components or steps and other elements, ingredients, components or steps that do not materially affect the basic novel characteristics of the combination. The use of the terms "comprising" or "including" to describe a combination of elements, ingredients, components or steps herein also contemplates embodiments consisting essentially of these elements, ingredients, components or steps. By using the term "may", it is intended to indicate that any attribute described as "may" be optional.

[0085] Multiple elements, ingredients, parts or steps can be provided by a single integrated element, ingredient, part or step. Alternatively, a single integrated element, ingredient, part or step can be divided into separate multiple elements, ingredients, parts or steps. The disclosure of "a" or "an" to describe an element, ingredient, part or step is not intended to exclude other elements, ingredients, parts or steps.

[0086] It should be understood that the above description is for illustrative purposes only and is not intended to be limiting. Upon reading the above description, many embodiments and many applications beyond the examples provided will be apparent to those skilled in the art. Therefore, the scope of the present teachings should not be determined with reference to the above description, but should be determined with reference to the preceding claims and the full scope of equivalents to which such claims are entitled. For the purpose of comprehensiveness, all articles and references, including disclosures of patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the preceding claims is not a disclaimer of such subject matter, nor should it be interpreted that the applicant has not considered such subject matter to be part of the disclosed subject matter. Obviously, various changes and modifications may be made to the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is intended to encompass such changes and modifications if they fall within the scope of the claims and their equivalents.

Claims

1. A hardware protection circuit with self-locking and delayed reset, characterized in that: include: A trigger module, a first protection module, a second protection module, and a third protection module; The first end of the trigger module is externally connected to the protection hardware, the second end of the trigger module is connected to the first end of the first protection module and the first end of the second protection module, the second end of the trigger module is externally connected to a power supply, and the third end of the trigger module is connected to the second end of the first protection module and the first end of the third protection module; The third end of the first protection module is connected to the second end of the second protection module, the third end of the first protection module is connected to an external output port, the fourth end of the first protection module is connected to the third end of the second protection module and the second end of the third protection module, the second end of the third protection module is grounded, and the fourth end of the second protection module is connected to the third end of the third protection module; The trigger module is used to trigger the first protection module at a low level when a circuit fault occurs in the hardware to be protected. The first protection module is used to output a fault signal of the hardware to be protected and self-lock the fault signal; The second protection module is used to recover circuit faults of the hardware to be protected, determine the reset delay time of the first protection module, and control the first protection module to reset through the third protection module when the reset delay time times out.

2. The hardware protection circuit with self-locking and delayed reset function according to claim 1, characterized in that: The trigger module includes: a first trigger unit and a second trigger unit; The first end of the first trigger unit is externally connected to the hardware to be protected, and the second end of the first trigger unit is connected to the first end of the second trigger unit; The second end of the second trigger unit is connected to the first end of the first protection module and the first end of the second protection module, the second end of the second trigger unit is externally connected to a power supply, and the third end of the second trigger unit is connected to the second end of the first protection module and the first end of the third protection module. The first trigger unit is used to trigger a low-level signal when a circuit fault occurs in the hardware to be protected, and the second trigger unit is used to trigger the first protection module to turn on when receiving the low-level signal.

3. The hardware protection circuit with self-locking and delayed reset function according to claim 2, characterized in that: The first trigger unit includes: at least one parallel diode; The cathode of the at least one parallel diode is externally connected to the hardware to be protected, and the anode of the at least one parallel diode is connected to the first end of the second trigger unit.

4. The hardware protection circuit with self-locking and delayed reset function according to claim 2, wherein: The second trigger unit includes: a first switch tube and a first resistor; The gate of the first switching tube is connected to the first end of the first resistor and the second end of the first trigger module, the source of the first switching tube is connected to the second end of the first resistor and the first end of the first protection module, the source of the first switching tube is connected to an external power supply, and the drain of the first switching tube is connected to the second end of the first protection module and the first end of the third protection module.

5. The hardware protection circuit with self-locking and delayed reset function according to claim 1, characterized in that: The first protection module includes: a second switch tube, a third switch tube, a second resistor and a third resistor; The source of the second switching tube is connected to the first end of the second resistor, the drain of the second switching tube is connected to the gate of the third switching tube, the third end of the trigger module, and the first end of the third protection module, the gate of the second switching tube is connected to the drain of the third switching tube, the first end of the third resistor, and the second end of the second protection module, and the gate of the second switching tube is connected to the external output port.

6. The hardware protection circuit with self-locking and delayed reset function according to claim 5, characterized in that: The second end of the second resistor is connected to the second end of the third resistor, the second end of the trigger module, and the first end of the second protection module. The source of the third switch tube is connected to the third end of the second protection module and the second end of the third protection module.

7. The hardware protection circuit with self-locking and delayed reset function according to claim 1, wherein: The second protection module includes: a first protection unit and a second protection unit; The first end of the first protection unit is connected to the first end of the first protection module and the first end of the second protection unit, the second end of the first protection unit is connected to the third end of the first protection module, the third end of the first protection unit is connected to the fourth end of the first protection module, the second end of the third protection module, and the second end of the second protection unit, and the fourth end of the first protection unit is connected to the third end of the second protection unit; The fourth end of the second protection unit is connected to the third end of the third protection module; The first protection unit is used to determine the reset delay time of the first protection module when the circuit fault of the hardware to be protected is restored. The second protection unit is used to determine that the reset delay time has expired and control the first protection module to reset through the third protection module.

8. The hardware protection circuit with self-locking and delayed reset function according to claim 7, characterized in that: The first protection unit includes: a fourth switch tube, a capacitor and a fourth resistor; The gate of the fourth switching tube is connected to the third end of the first protection module, the source of the fourth switching tube is connected to the fourth end of the first protection module, the second end of the third protection module, the second end of the second protection unit, and the first end of the capacitor, and the drain of the fourth switching tube is connected to the second end of the capacitor, the first end of the fourth resistor, and the third end of the second protection module; The second end of the fourth resistor is connected to the first end of the second protection module.

9. The hardware protection circuit with self-locking and delayed reset function according to claim 7, wherein: The second protection unit includes: a fifth resistor, a sixth resistor, a seventh resistor and a comparator; The positive input terminal of the comparator is connected to the fourth terminal of the first protection unit, the negative input terminal of the comparator is connected to the first terminal of the fifth resistor and the first terminal of the sixth resistor, and the output terminal of the comparator is connected to the first terminal of the seventh resistor; The second end of the fifth resistor is connected to the first end of the first protection unit, the second end of the sixth resistor is connected to the third end of the first protection unit and the second end of the third protection module, and the second end of the seventh resistor is connected to the third end of the third protection module.

10. The hardware protection circuit with self-locking and delayed reset function according to claim 1, characterized in that: The third protection module includes: a fifth switch tube, an eighth resistor and a ninth resistor; The gate of the fifth switching tube is connected to the fourth terminal of the second protection module, the source of the fifth switching tube is connected to the fourth terminal of the first protection module, the third terminal of the second protection module, and the first terminal of the eighth resistor, the source of the fifth switching tube is grounded, and the drain of the fifth switching tube is connected to the first terminal of the ninth resistor; The second end of the eighth resistor is connected to the third end of the trigger module, the second end of the first protection module, and the second end of the ninth resistor.

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