A wake-up circuit and electronic device

Abstract

The application relates to a wake-up circuit, characterized in that the wake-up circuit comprises a first supercut-off stack structure, a first transistor and a second transistor connected in series with each other, wherein the drain electrode of the first transistor is electrically connected to a power supply, the source electrode is electrically connected to the source electrode of the second transistor, the gate electrode of the first transistor serves as a first signal input end, the gate electrode of the second transistor serves as a second signal input end, the first transistor is an N-type transistor, and the second transistor is a P-type transistor; a first resistor or a first current source, a first end of which is electrically connected to the drain electrode of the second transistor, and a second end of which is grounded; a first Schmitt trigger, an input end of which is electrically connected to a first node at which the drain electrode of the second transistor and the first end of the first resistor are electrically connected; or the wake-up circuit further comprises a first inverter, an input end of which is electrically connected to the output end of the first Schmitt trigger, and an output end of which serves as an output end of the wake-up circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a wake-up circuit and an electronic device. BACKGROUND

[0002] With the rapid development of emerging applications such as Internet of Things technology, wearable electronic devices and electric vehicles, the demand for high-efficiency energy management solutions for battery-powered systems has become unprecedentedly urgent. As the core component of prolonging the endurance time of the device and optimizing the energy utilization efficiency, the design of the low-power battery management system needs to balance between key performance indicators such as static power consumption, dynamic response speed and system reliability. Under this technical background, the wake-up receiver mechanism of the system plays a crucial role, and its performance directly determines the energy efficiency ratio and response time of the device from the deep sleep mode to the active state.

[0003] As a typical representative of ultra-low-power pure analog signal acquisition subsystems, the wake-up receiver plays an irreplaceable role in micro-energy Internet of Things systems. This kind of device continuously monitors low-frequency trigger signals in the environment to provide intelligent wake-up functions for power supply systems based on high-performance micro-batteries, so that the main system can maintain a near-zero power consumption state of nanowatts in standby state. Therefore, the power optimization of the receiver front end and the comparator and other key functional modules becomes the core challenge of system design. In the prior art, the wake-up of the wake-up device is realized by setting a clock signal, but this wake-up mode increases the power consumption of the system in the deep sleep mode.

[0004] However, the traditional circuit architecture often has difficulty in simultaneously achieving performance indicators under strict power consumption constraints (such as sub-microwatt level) and low power supply voltage (such as sub-threshold region). SUMMARY

[0005] In view of the technical problems in the prior art, the present application provides a wake-up circuit, which comprises a first super-cut-off stacked structure comprising a first transistor and a second transistor connected in series with each other, wherein the drain electrode of the first transistor is electrically connected to a power supply, the source electrode is electrically connected to the source electrode of the second transistor, the gate electrode of the first transistor serves as a first signal input end, the gate electrode of the second transistor serves as a second signal input end, the first transistor is an N-type transistor, and the second transistor is a P-type transistor; a first resistor or a first current source, a first end of which is electrically connected to the drain electrode of the second transistor, and a second end thereof is grounded; a first Schmitt trigger, an input end of which is electrically connected to a first node to which the drain electrode of the second transistor and the first end of the first resistor are electrically connected, and an output end of the Schmitt trigger serves as a wake-up device output end; or the wake-up circuit further comprises a first inverter, an input end of which is electrically connected to the output end of the first Schmitt trigger, and an output end of the inverter serves as an output end of the wake-up circuit.

[0006] In particular, the wake-up circuit is characterized in that the first Schmitt trigger comprises a third transistor, a fourth transistor and a fifth transistor, whose gates are electrically connected together as the input terminal of the first Schmitt trigger, wherein the source electrode of the third transistor is electrically connected to a power supply, the source electrode of the fifth transistor is grounded, the drain electrode of the third transistor is electrically connected to the source electrode of the fourth transistor, the drain electrode of the fourth transistor is electrically connected to the drain electrode of the fifth transistor, the drain electrode of a sixth transistor is grounded, and the source electrode of the sixth transistor is electrically connected to the drain electrode of the third transistor, the gate electrode of the sixth transistor is electrically connected to the drain electrode of the fourth transistor and the drain electrode of the fifth transistor, and serves as the output terminal of the first Schmitt trigger; wherein the type of the fifth transistor is complementary to that of the third transistor, the fourth transistor and the sixth transistor, and the width-length ratio of the fifth transistor is greater than that of the other transistors in the first Schmitt trigger.

[0007] The application also provides a wake-up circuit, characterized in that it comprises a second super-cut-off stack structure comprising a seventh transistor and an eighth transistor connected in series with each other, wherein the source electrode of the seventh transistor is electrically connected to the source electrode of the eighth transistor, the gate electrode of the seventh transistor serves as a first signal input terminal, the gate electrode of the eighth transistor serves as a second signal input terminal, the seventh transistor is an N-type transistor, and the eighth transistor is a P-type transistor; a second resistor or a second current source, whose first end is electrically connected to the drain electrode of the seventh transistor, and whose second end is electrically connected to a power supply; a second Schmitt trigger, whose input terminal is electrically connected to a second node at which the drain electrode of the seventh transistor and the first end of the second resistor are electrically connected, and whose output terminal serves as a wake-up output terminal; or the wake-up circuit further comprises a second inverter, whose input terminal is electrically connected to the output terminal of the second Schmitt trigger, and whose output terminal serves as the output terminal of the wake-up circuit.

[0008] In particular, the wake-up circuit is characterized in that the second Schmitt trigger comprises a ninth transistor, a tenth transistor and an eleventh transistor, whose gates are electrically connected together as an input terminal of the second Schmitt trigger, wherein the source electrode of the ninth transistor is electrically connected to a power supply, the source electrode of the eleventh transistor is grounded, the drain electrode of the eleventh transistor is electrically connected to the source electrode of the tenth transistor, the drain electrode of the ninth transistor is electrically connected to the drain electrode of the tenth transistor, the drain electrode of a twelfth transistor is connected to the power supply, and the source electrode of the twelfth transistor is electrically connected to the source electrode of the tenth transistor, the gate electrode of the twelfth transistor is electrically connected to the drain electrode of the ninth transistor and the drain electrode of the tenth transistor, and serves as an output terminal of the second Schmitt trigger; wherein the type of the ninth transistor is complementary to the tenth transistor, the eleventh transistor and the twelfth transistor, and the width-length ratio of the ninth transistor is greater than the width-length ratio of other transistors in the second Schmitt trigger.

[0009] The application also provides a wake-up circuit, characterized in that it comprises a third super-cut-off stack structure comprising a thirteenth transistor and a fourteenth transistor connected in series with each other, wherein the drain electrode of the thirteenth transistor is electrically connected to a power supply, the source electrode is electrically connected to the source electrode of the fourteenth transistor, the gate electrode of the thirteenth transistor serves as a first signal input terminal, the gate electrode of the fourteenth transistor serves as a second signal input terminal, the thirteenth transistor is an N-type transistor, and the fourteenth transistor is a P-type transistor; a fourth super-cut-off stack structure comprising a fifteenth transistor and a sixteenth transistor connected in series with each other, wherein the source electrode of the fifteenth transistor is electrically connected to the source electrode of the sixteenth transistor, the gate electrode of the fifteenth transistor serves as a first signal input terminal, the gate electrode of the sixteenth transistor serves as a second signal input terminal, the fifteenth transistor is an N-type transistor, and the sixteenth transistor is a P-type transistor; a third resistor or a third current source, whose first end is electrically connected to the drain electrode of the fourteenth transistor, and the second end is grounded; a fourth resistor or a fourth current source, whose first end is electrically connected to the drain electrode of the fifteenth transistor, and the second end is connected to a power supply; a third Schmitt trigger, whose input terminal is electrically connected to a third node where the drain electrode of the fourteenth transistor and the first end of the third resistor are electrically connected; a fourth Schmitt trigger, whose input terminal is electrically connected to a fourth node where the drain electrode of the fifteenth transistor and the first end of the fourth resistor are electrically connected; a third inverter, whose input terminal is electrically connected to the output terminal of the fourth Schmitt trigger; a first NAND gate, whose two input terminals are respectively electrically connected to the output terminal of the third inverter and the output terminal of the third Schmitt trigger, and the output terminal of the first NAND gate serves as an output terminal of the wake-up circuit.

[0010] In particular, the wake-up circuit is characterized in that the third Schmitt trigger comprises a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor, whose gates are electrically connected together as an input terminal of the third Schmitt trigger, wherein a source electrode of the seventeenth transistor is electrically connected to a power supply, a source electrode of the nineteenth transistor is grounded, a drain electrode of the seventeenth transistor is electrically connected to a source electrode of the eighteenth transistor, a drain electrode of the eighteenth transistor is electrically connected to a drain electrode of the nineteenth transistor, a drain electrode of a twentieth transistor is grounded, and a source electrode of the twentieth transistor is electrically connected to the drain electrode of the seventeenth transistor, a gate electrode of the twentieth transistor is electrically connected to the drain electrode of the eighteenth transistor and the drain electrode of the nineteenth transistor, and serves as an output terminal of the third Schmitt trigger, wherein the nineteenth transistor is complementary to the seventeenth transistor, the eighteenth transistor, and the twentieth transistor, and a width-length ratio of the nineteenth transistor is greater than width-length ratios of other transistors of the third Schmitt trigger; and / or the fourth Schmitt trigger comprises a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor, whose gates are electrically connected together as an input terminal of the fourth Schmitt trigger, wherein a source electrode of the twenty-first transistor is electrically connected to a power supply, a source electrode of the twenty-third transistor is grounded, a drain electrode of the twenty-third transistor is electrically connected to a source electrode of the twenty-second transistor, a drain electrode of the twenty-first transistor is electrically connected to a drain electrode of the twenty-second transistor, a drain electrode of a twenty-fourth transistor is electrically connected to the power supply, and a source electrode of the twenty-fourth transistor is electrically connected to the source electrode of the twenty-second transistor, a gate electrode of the twenty-fourth transistor is electrically connected to the drain electrode of the twenty-first transistor and the drain electrode of the twenty-second transistor, and serves as an output terminal of the fourth Schmitt trigger, wherein the twenty-first transistor is complementary to the twenty-second transistor, the twenty-third transistor, and the twenty-fourth transistor, and a width-length ratio of the twenty-first transistor is greater than width-length ratios of other transistors of the fourth Schmitt trigger.

[0011] The application also includes a wake-up circuit, characterized in that it comprises a fifth supercut-off stack structure comprising a twenty-fifth transistor and a twenty-sixth transistor connected in series with each other, wherein the drain electrode of the twenty-fifth transistor is electrically connected to a power supply, the source electrode is electrically connected to the source electrode of the twenty-sixth transistor, the gate electrode of the twenty-fifth transistor serves as a first signal input end, the gate electrode of the twenty-sixth transistor serves as a second signal input end, the twenty-fifth transistor is an N-type transistor, and the twenty-sixth transistor is a P-type transistor; a sixth supercut-off stack structure comprising a twenty-seventh transistor and a twenty-eighth transistor connected in series with each other, wherein the source electrode of the twenty-seventh transistor is electrically connected to the source electrode of the twenty-eighth transistor, the gate electrode of the twenty-seventh transistor serves as a first signal input end, the gate electrode of the twenty-eighth transistor serves as a second signal input end, the twenty-seventh transistor is an N-type transistor, and the twenty-eighth transistor is a P-type transistor; a fifth resistor or a fifth current source, the first end of which is electrically connected to the drain electrode of the twenty-sixth transistor, and the second end of which is grounded; a sixth resistor or a sixth current source, the first end of which is electrically connected to the drain electrode of the twenty-seventh transistor, and the second end of which is connected to a power supply; a fifth Schmitt trigger, the input end of which is electrically connected to a fifth node at which the drain electrode of the twenty-sixth transistor and the first end of the fifth resistor are electrically connected; a sixth Schmitt trigger, the input end of which is electrically connected to a sixth node at which the drain electrode of the twenty-seventh transistor and the first end of the sixth resistor are electrically connected; a fourth inverter, the input end of which is electrically connected to the output end of the fifth Schmitt trigger; a first OR gate, the two input ends of which are respectively electrically connected to the output end of the fourth inverter and the output end of the sixth Schmitt trigger, and the output end of the first OR gate serves as the output end of the wake-up circuit.

[0012] In particular, the wake-up circuit is characterized in that the fifth Schmitt trigger comprises a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor, whose gates are electrically connected together as the input terminal of the fifth Schmitt trigger, wherein the source electrode of the twenty-ninth transistor is electrically connected to a power supply, the source electrode of the thirty-first transistor is grounded, the drain electrode of the twenty-ninth transistor is electrically connected to the source electrode of the thirtieth transistor, the drain electrode of the thirtieth transistor is electrically connected to the drain electrode of the thirty-first transistor, the drain electrode of a thirty-second transistor is grounded, and the source electrode thereof is electrically connected to the drain electrode of the twenty-ninth transistor, the gate electrode of the thirty-second transistor is electrically connected to the drain electrode of the thirtieth transistor and the drain electrode of the thirty-first transistor, and serves as the output terminal of the fifth Schmitt trigger, wherein the type of the thirty-first transistor is complementary to the twenty-ninth transistor, the thirtieth transistor, and the thirty-second transistor, and the width-length ratio of the thirty-first transistor is greater than that of the other transistors of the fifth Schmitt trigger; and / or the sixth Schmitt trigger comprises a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, whose gates are electrically connected together as the input terminal of the sixth Schmitt trigger, wherein the source electrode of the thirty-third transistor is electrically connected to a power supply, the source electrode of the thirty-fifth transistor is grounded, the drain electrode of the thirty-fifth transistor is electrically connected to the source electrode of the thirty-fourth transistor, the drain electrode of the thirty-third transistor is electrically connected to the drain electrode of the thirty-fourth transistor, the drain electrode of a thirty-sixth transistor is electrically connected to the power supply, and the source electrode thereof is electrically connected to the source electrode of the thirty-fourth transistor, the gate electrode of the thirty-sixth transistor is electrically connected to the drain electrode of the thirty-third transistor and the drain electrode of the thirty-fourth transistor, and serves as the output terminal of the sixth Schmitt trigger, wherein the type of the thirty-third transistor is complementary to the thirty-fourth transistor, the thirty-fifth transistor, and the thirty-sixth transistor, and the width-length ratio of the thirty-third transistor is greater than that of the other transistors of the sixth Schmitt trigger.

[0013] The application also provides a wake-up circuit, characterized in that: a first wake-up unit, comprising a first wake-up subunit, comprising a seventh super-cut-off stack structure having one end electrically connected to a power supply and a seventh resistor or a seventh current source having one end connected in series with the seventh super-cut-off stack structure and the other end grounded; and / or a second wake-up subunit, comprising an eighth super-cut-off stack structure having one end grounded and an eighth resistor or an eighth current source having one end connected in series with the eighth super-cut-off stack structure and the other end electrically connected to the power supply; a first feedback circuit electrically connected to an output end of the first wake-up subunit and an output end of the second wake-up subunit and electrically connected to a first output unit of the first feedback circuit; a second wake-up unit, comprising a third wake-up subunit, comprising a ninth super-cut-off stack structure having one end electrically connected to the power supply and a ninth resistor or a ninth current source having one end connected in series with the ninth super-cut-off stack structure and the other end grounded; and / or a fourth wake-up subunit, comprising a tenth super-cut-off stack structure having one end grounded and a tenth resistor or a tenth current source having one end connected in series with the tenth super-cut-off stack structure and the other end electrically connected to the power supply; a second feedback circuit electrically connected to an output end of the third wake-up subunit and an output end of the fourth wake-up subunit and electrically connected to a second output unit of the second feedback circuit; the first feedback circuit is configured to receive an output of the second wake-up unit, and the second feedback circuit is configured to receive an output of the first wake-up unit.

[0014] In particular, the wake-up circuit is characterized in that: when the first wake-up unit comprises the first wake-up subunit and the second wake-up subunit, the first output unit comprises a seventh Schmitt trigger having an input end electrically connected to an output end of the first wake-up subunit, an eighth Schmitt trigger having an input end electrically connected to an output end of the second wake-up subunit, a fifth inverter and a second NAND gate, wherein an input end of the fifth inverter is electrically connected to an output end of the eighth Schmitt trigger, an output end of the fifth inverter and an output end of the seventh Schmitt trigger are electrically connected to input ends of the second NAND gate, and an output end of the second NAND gate serves as an output end of the first output unit; or a sixth inverter and a second OR gate, wherein an input end of the sixth inverter is electrically connected to an output end of the seventh Schmitt trigger, an output end of the sixth inverter and an output end of the eighth Schmitt trigger are electrically connected to input ends of the second OR gate, and an output end of the second OR gate serves as the output end of the first output unit; or when the first wake-up unit comprises the first wake-up subunit, the first output unit comprises a seventh Schmitt trigger and a sixth inverter, wherein an input end of the sixth inverter is electrically connected to an output end of the seventh Schmitt trigger, and an output end of the sixth inverter serves as the output end of the first output unit; or when the first wake-up unit comprises the second wake-up subunit, the first output unit comprises an eighth Schmitt trigger and a fifth inverter, wherein an input end of the fifth inverter is electrically connected to an output end of the eighth Schmitt trigger, and an output end of the fifth inverter serves as the output end of the first output unit.

[0015] In particular, the wake-up circuit is characterized in that, when the second wake-up unit comprises a third wake-up subunit and a fourth wake-up subunit, the second output unit comprises a ninth Schmitt trigger, an input terminal of which is electrically connected to an output terminal of the third wake-up subunit; a tenth Schmitt trigger, an input terminal of which is electrically connected to an output terminal of the fourth wake-up subunit; a seventh inverter and a third NAND gate, wherein an input terminal of the seventh inverter is electrically connected to an output terminal of the tenth Schmitt trigger, an output terminal of the seventh inverter and an output terminal of the ninth Schmitt trigger are electrically connected to input terminals of the third NAND gate; or an eighth inverter and a third OR gate, wherein an input terminal of the eighth inverter is electrically connected to an output terminal of the ninth Schmitt trigger, an output terminal of the eighth inverter and an output terminal of the tenth Schmitt trigger are electrically connected to input terminals of the third OR gate; or when the second wake-up unit comprises a third wake-up subunit, the second output unit comprises a ninth Schmitt trigger and an eighth inverter, wherein an input terminal of the eighth inverter is electrically connected to an output terminal of the ninth Schmitt trigger, an output terminal of the eighth inverter serves as an output terminal of the second output unit; or when the second wake-up unit comprises a fourth wake-up subunit, the second output unit comprises a tenth Schmitt trigger and a seventh inverter, wherein an input terminal of the seventh inverter is electrically connected to an output terminal of the tenth Schmitt trigger, an output terminal of the seventh inverter serves as an output terminal of the second output unit.

[0016] In particular, the wake-up circuit is characterized in that when the first wake-up unit comprises a first wake-up subunit and a second wake-up subunit, the first feedback circuit comprises a thirty-seventh transistor, a drain electrode of which is electrically connected to an input end of the eighth Schmitt trigger, a source electrode of which is electrically connected to a power supply; an eleventh resistor, one end of which is electrically connected to the power supply, and the other end of which is electrically connected to a gate electrode of the thirty-seventh transistor; a first capacitor, a first plate of which is electrically connected to the gate electrode of the thirty-seventh transistor; a ninth inverter, an input end of which is electrically connected to an output end of the second wake-up unit, and an output end of which is electrically connected to a second plate of the first capacitor; a thirty-eighth transistor, a drain electrode of which is electrically connected to an input end of the seventh Schmitt trigger, a source electrode of which is electrically connected to a first end of a twelfth resistor, and receives a ground potential, and a gate electrode of which is electrically connected to a second end of the twelfth resistor and a first plate of a second capacitor, a second plate of the second capacitor being electrically connected to an input end of the ninth inverter and the output end of the second wake-up unit; or when the first wake-up unit comprises the first wake-up subunit, the first feedback circuit comprises the twelfth resistor, a first end of which receives the ground potential; the thirty-eighth transistor, a drain electrode of which is electrically connected to the input end of the seventh Schmitt trigger, a source electrode of which is electrically connected to the first end of the twelfth resistor, and a gate electrode of which is electrically connected to a second end of the twelfth resistor and the first plate of the second capacitor; the second capacitor, a second plate of which is electrically connected to the output end of the second wake-up unit; or when the first wake-up unit comprises the second wake-up subunit, the first feedback circuit comprises the thirty-seventh transistor, a drain electrode of which is electrically connected to an input end of the eighth Schmitt trigger, a source electrode of which is electrically connected to a power supply; the eleventh resistor, one end of which is electrically connected to the power supply, and the other end of which is electrically connected to a gate electrode of the thirty-seventh transistor; the first capacitor, a first plate of which is electrically connected to the gate electrode of the thirty-seventh transistor; the ninth inverter, an input end of which is electrically connected to an output end of the second wake-up unit, and an output end of which is electrically connected to a second plate of the first capacitor.

[0017] In particular, the wake-up circuit is characterized in that when the second wake-up unit comprises a third wake-up subunit and a fourth wake-up subunit, the second feedback circuit comprises a thirty-ninth transistor, the drain electrode of which is electrically connected to the tenth Schmitt trigger input end, the source electrode of which is electrically connected to a power supply, a thirteenth resistor, one end of which is electrically connected to the power supply and the other end of which is electrically connected to the gate electrode of the thirty-ninth transistor; a third capacitor, the first plate of which is electrically connected to the gate electrode of the thirty-ninth transistor; a tenth inverter, the input end of which is electrically connected to the output end of the first wake-up unit and the output end of which is electrically connected to the second plate of the third capacitor; a fortieth transistor, the drain electrode of which is electrically connected to the ninth Schmitt trigger input end, the source electrode of which is electrically connected to the first end of a fourteenth resistor and receives a ground potential, and the gate electrode of which is electrically connected to the second end of the fourteenth resistor and the first plate of a fourth capacitor, the second plate of the fourth capacitor being electrically connected to the input end of the tenth inverter and the output end of the first wake-up unit; or when the second wake-up unit comprises a third wake-up subunit, the second feedback circuit comprises a fourteenth resistor, the first end of which receives a ground potential; a fortieth transistor, the drain electrode of which is electrically connected to the ninth Schmitt trigger input end, the source electrode of which is electrically connected to the first end of the fourteenth resistor, and the gate electrode of which is electrically connected to the second end of the fourteenth resistor and the first plate of a fourth capacitor, the second plate of the fourth capacitor being electrically connected to the output end of the first wake-up unit; or when the second wake-up unit comprises a fourth wake-up subunit, the second feedback circuit comprises a thirty-ninth transistor, the drain electrode of which is electrically connected to the tenth Schmitt trigger input end, the source electrode of which is electrically connected to a power supply; a thirteenth resistor, one end of which is electrically connected to the power supply and the other end of which is electrically connected to the gate electrode of the thirty-ninth transistor; a third capacitor, the first plate of which is electrically connected to the gate electrode of the thirty-ninth transistor; a tenth inverter, the input end of which is electrically connected to the output end of the first wake-up unit and the output end of which is electrically connected to the second plate of the third capacitor.

[0018] In particular, the wake-up circuit is characterized in that the seventh super-cut-off stack structure comprises a forty-first transistor and a forty-second transistor connected in series with each other, wherein the drain electrode of the forty-second transistor is electrically connected to the first end of the seventh resistor, the source electrode of the forty-second transistor is electrically connected to the source electrode of the forty-first transistor, the forty-first transistor is an N-type transistor, and the forty-second transistor is a P-type transistor; and / or the eighth super-cut-off stack structure comprises a forty-third transistor and a forty-fourth transistor connected in series with each other, wherein the drain electrode of the forty-third transistor is electrically connected to the first end of the eighth resistor, the source electrode of the forty-fourth transistor is electrically connected to the source electrode of the forty-third transistor, the forty-third transistor is an N-type transistor, and the forty-fourth transistor is a P-type transistor; and / or the ninth super-cut-off stack structure comprises a forty-fifth transistor and a forty-sixth transistor connected in series with each other, wherein the drain electrode of the forty-sixth transistor is electrically connected to the first end of the ninth resistor, the source electrode of the forty-fifth transistor is electrically connected to the source electrode of the forty-sixth transistor, the forty-fifth transistor is an N-type transistor, and the forty-sixth transistor is a P-type transistor; and / or the tenth super-cut-off stack structure comprises a forty-seventh transistor and a forty-eighth transistor connected in series with each other, wherein the drain electrode of the forty-seventh transistor is electrically connected to the first end of the tenth resistor, the source electrode of the forty-eighth transistor is electrically connected to the source electrode of the forty-seventh transistor, the forty-seventh transistor is an N-type transistor, and the forty-eighth transistor is a P-type transistor; wherein the gate electrodes of the forty-first transistor, the forty-third transistor, the forty-sixth transistor, and the forty-eighth transistor serve as a first signal input end; and the gate electrodes of the forty-second transistor, the forty-fourth transistor, the forty-fifth transistor, and the forty-seventh transistor serve as a second signal input end.

[0019] In particular, the wake-up circuit is characterized in that the seventh Schmitt trigger comprises a forty-ninth transistor, a fiftieth transistor, a fifty-first transistor, whose gates are electrically connected together as an input terminal of the seventh Schmitt trigger, wherein the source electrode of the forty-ninth transistor is electrically connected to a power supply, the source electrode of the fifty-first transistor is grounded, the drain electrode of the forty-ninth transistor is electrically connected to the source electrode of the fiftieth transistor, the drain electrode of the fiftieth transistor is electrically connected to the drain electrode of the fifty-first transistor, the drain electrode of a fifty-second transistor is grounded, and the source electrode thereof is electrically connected to the drain electrode of the forty-ninth transistor, the gate electrode of the fifty-second transistor is electrically connected to the drain electrode of the fiftieth transistor and the drain electrode of the fifty-first transistor, and serves as an output terminal of the seventh Schmitt trigger, wherein the type of the fifty-first transistor is complementary to the forty-ninth transistor, the fiftieth transistor and the fifty-second transistor, and the width-length ratio of the fifty-first transistor is greater than that of other transistors of the seventh Schmitt trigger; and / or the eighth Schmitt trigger comprises a fifty-third transistor, a fifty-fourth transistor, a fifty-fifth transistor, whose gates are electrically connected together as an input terminal of the eighth Schmitt trigger, wherein the source electrode of the fifty-third transistor is electrically connected to a power supply, the source electrode of the fifty-fifth transistor is grounded, the drain electrode of the fifty-fifth transistor is electrically connected to the source electrode of the fifty-fourth transistor, the drain electrode of the fifty-third transistor is electrically connected to the drain electrode of the fifty-fourth transistor, the drain electrode of a fifty-sixth transistor is electrically connected to the power supply, and the source electrode thereof is electrically connected to the source electrode of the fifty-fourth transistor, the gate electrode of the fifty-sixth transistor is electrically connected to the drain electrode of the fifty-third transistor and the drain electrode of the fifty-fourth transistor, and serves as an output terminal of the eighth Schmitt trigger, wherein the type of the fifty-third transistor is complementary to the fifty-fourth transistor, the fifty-fifth transistor and the fifty-sixth transistor, and the width-length ratio of the fifty-third transistor is greater than that of other transistors of the eighth Schmitt trigger.

[0020] In particular, the wake-up circuit is characterized in that the ninth Schmitt trigger comprises a fifty-seventh transistor, a fifty-eighth transistor and a fifty-ninth transistor, whose gates are electrically connected together as an input terminal of the ninth Schmitt trigger, wherein the source electrode of the fifty-seventh transistor is electrically connected to a power supply, the source electrode of the fifty-ninth transistor is grounded, the drain electrode of the fifty-seventh transistor is electrically connected to the source electrode of the fifty-eighth transistor, the drain electrode of the fifty-eighth transistor is electrically connected to the drain electrode of the fifty-ninth transistor, the drain electrode of a sixtieth transistor is grounded, and the source electrode of the sixtieth transistor is electrically connected to the drain electrode of the fifty-seventh transistor, the gate electrode of the sixtieth transistor is electrically connected to the drain electrode of the fifty-eighth transistor and the drain electrode of the fifty-ninth transistor, and serves as an output terminal of the ninth Schmitt trigger; wherein the type of the fifty-ninth transistor is complementary to the fifty-seventh transistor, the fifty-eighth transistor and the sixtieth transistor, and the width-length ratio of the fifty-ninth transistor is greater than that of other transistors of the ninth Schmitt trigger; and / or the tenth Schmitt trigger comprises a sixty-first transistor, a sixty-second transistor and a sixty-third transistor, whose gates are electrically connected together as an input terminal of the tenth Schmitt trigger, wherein the source electrode of the sixty-first transistor is electrically connected to a power supply, the source electrode of the sixty-third transistor is grounded, the drain electrode of the sixty-third transistor is electrically connected to the source electrode of the sixty-second transistor, the drain electrode of the sixty-first transistor is electrically connected to the drain electrode of the sixty-second transistor, the drain electrode of a sixty-fourth transistor is electrically connected to the power supply, and the source electrode of the sixty-fourth transistor is electrically connected to the source electrode of the sixty-second transistor, the gate electrode of the sixty-fourth transistor is electrically connected to the drain electrode of the sixty-first transistor and the drain electrode of the sixty-second transistor, and serves as an output terminal of the tenth Schmitt trigger; wherein the type of the sixty-first transistor is complementary to the sixty-second transistor, the sixty-third transistor and the sixty-fourth transistor, and the width-length ratio of the sixty-first transistor is greater than that of other transistors of the tenth Schmitt trigger.

[0021] The present application also provides an electronic device comprising the wake-up circuit according to any one of the above. BRIEF DESCRIPTION OF DRAWINGS

[0022] In the following, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, in which:

[0023] Figure 1 Fig. 1 shows a schematic diagram of a wake-up circuit according to an embodiment of the present application;

[0024] Figure 2 Fig. 2 shows a schematic diagram of a wake-up circuit according to another embodiment of the present application;

[0025] Figure 3 and Figure 4The diagram shown is a Schmitt trigger circuit diagram according to an embodiment of this application;

[0026] Figure 5 The diagram shown is a schematic diagram of a wake-up circuit according to another embodiment of this application;

[0027] Figure 6 The diagram shown is a schematic diagram of a wake-up circuit according to yet another embodiment of this application;

[0028] Figures 7-10 The diagram shown is a schematic diagram of a wake-up circuit according to other embodiments of this application;

[0029] Figure 11 The diagram shown is a timing diagram of a wake-up circuit according to an embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0032] Figure 1 The diagram shown is a schematic diagram of a wake-up circuit according to an embodiment of this application.

[0033] like Figure 1 As shown, according to one embodiment, the circuit includes a super-cutoff stacked structure 100 connected in series and a resistor R100.

[0034] According to one embodiment, the super-cutoff stack structure 100 includes an NMOS transistor MN100 and a PMOS transistor MP100, which are electrically connected in series. The drain electrode of the NMOS transistor MN100 receives a voltage source VDD, and its source electrode is electrically connected to the source electrode of the PMOS transistor MP100. The gate electrode of the transistor MN100 serves as the signal input terminal VGN, and the gate electrode of the transistor MP100 serves as the signal input terminal VGP.

[0035] According to one embodiment, the total threshold voltage of the super-cut-off stack structure can be adjusted by using MOS transistor devices with different threshold voltages. Hereinafter, Vthnis the threshold voltage of the NMOS transistor, and Vthpis the threshold voltage of the PMOS transistor.

[0036] According to one embodiment, the wake-up circuit can further include a Schmitt trigger ST100 having an input electrically connected to the drain electrode of the PMOS transistor MP100 in the super-cut-off stack structure 100 and the first end of the resistor R100. The second end of the resistor R100 receives a ground potential. According to one embodiment, the wake-up circuit further includes an inverter INV100 having an input electrically connected to the output of the Schmitt trigger ST100. According to one embodiment, the resistor R100 can be flexibly configured as a passive resistor or an active current source, which has high circuit compatibility. In the scheme using the resistor, no bias circuit is needed, thus further reducing power consumption.

[0037] According to one embodiment, the wake-up circuit using the resistor R100 in the above scheme can work under low supply voltage conditions. In conventional circuits, a bias circuit needs to be set to work normally, and the bias circuit consumes certain power consumption.

[0038] The transistor MP100 and the transistor MN100 in the super-cut-off stack structure 100 have equal current characteristics in the sub-threshold operating region, as shown in the following formula (1):

[0039]

[0040] where I0is a process-dependent constant (e.g., the transistor width-length ratio W / L), V th represents the transistor threshold voltage, n is the sub-threshold slope factor (assuming that n of each transistor is equal), kT / q is the thermal voltage. When the two transistor sizes are designed symmetrically so that I 0,n = I 0,p = I0, and considering that Vthn ≈ |Vthp| ≈ V th , the voltage V x at the node X between the transistor MN100 and the transistor MP100 will be equal to (VGN + VGP) / 2, and the current I generated thereby is as shown in the following formula (2):

[0041]

[0042] According to formula (2), the super-cut-off stack structure 100 is equivalent to a single transistor with a gate-source voltage of V GS = (VGN-VGP) / 2, where VGNis the gate input voltage of the transistor MN100, and VGPis the gate input voltage of the transistor MP100.

[0043] From the above formula (2), the super-cutoff stack structure 100 is equivalent to a threshold voltage of V. th Transistors.

[0044] According to one embodiment, when the two signals at the input of the super-cutoff stack structure 100 are common-mode signals, V GS =(VGN-VGP) / 2 equals 0 and must be less than V. th The super-cutoff stack structure 100 is in a super-cutoff state, that is, the voltage of the SEN_N100 node is 0.

[0045] According to one embodiment, when the two signals at the input terminals of the super-cutoff stacked structure 100 are differential signals, and the input differential voltage of the two signals at the input terminals is less than Vthn+|Vthp| (equivalent to V... GS Less than V th The super-cutoff stack structure 100 remains in the cutoff state.

[0046] According to one embodiment, when the two signals at the input terminals of the super-cutoff stacked structure 100 are differential signals, and the input differential voltage is greater than or equal to Vthn+|Vthp| (equivalent to V... GS Greater than or equal to V th When the super-cutoff stack structure is turned on, the voltage at node SEN_N100 rises from ground potential as the differential voltage increases.

[0047] In this application, since the transistor exhibits strictly matched exponential current-voltage transfer characteristics in the subthreshold operating region, the super-cutoff stack structure 100 operates in the super-cutoff state. Without any bias voltage exceeding the power rail (voltage source), the super-cutoff state leakage current can be achieved at a level far lower than that of conventional transistors, thereby reducing the power consumption of the circuit when it is in a static state.

[0048] According to one embodiment, the value of resistor R100 is related to the frequency of the two input terminals of the super-cutoff stack structure 100 when a differential signal is input. The lower the frequency, the larger the value of resistor R100, and the smaller the corresponding source-drain current, thus reducing the dynamic power consumption of the aforementioned sensing circuit. For example, when the frequency of the input differential signal is 2MHz, the value of resistor R100 can be 600KΩ~1.2MΩ.

[0049] If the voltage at node SEN_N100 is directly input to the inverter, the voltage will have a slow rise or fall, resulting in high power consumption when the inverter flips. Therefore, according to one embodiment, the voltage at node SEN_N100 can be supplied to the Schmitt trigger ST100 and then output through the series inverter INV100, further reducing the dynamic power consumption of the wake-up circuit.

[0050] According to one embodiment, a new Schmitt trigger is used in the scheme of the present application, which can further save power consumption compared with the traditional Schmitt trigger.

[0051] Figure 2 Fig. 2 shows a schematic diagram of a wake-up circuit according to another embodiment of the present application.

[0052] As shown in Fig. 2, according to one embodiment, the circuit includes a super cut-off stack structure 200 and a resistor R200 in series. Figure 2

[0053] According to one embodiment, the super cut-off stack structure 200 includes an NMOS transistor MN200 and a PMOS transistor MP200, which are electrically connected in series, wherein the drain electrode of the NMOS transistor MN200 is electrically connected to the first end of the resistor R200, the source electrode of the NMOS transistor MN200 is electrically connected to the source electrode of the PMOS transistor MP200, the gate electrode of the transistor MN200 is used as the input terminal of the signal VGN, and the gate electrode of the transistor MP200 is used as the input terminal of the signal VGP.

[0054] According to one embodiment, the wake-up circuit can further include a Schmitt trigger ST200, the input terminal of which is electrically connected to the drain electrode of the NMOS transistor MN200 and the first end of the resistor R200 in the super cut-off stack structure 200. The second end of the resistor R200 receives a power supply voltage VDD. According to one embodiment, the wake-up circuit further includes an inverter INV200, the input terminal of which is electrically connected to the output terminal of the Schmitt trigger ST200. According to one embodiment, the resistor R200 can be flexibly configured as a passive resistor or an active current source, which has high circuit compatibility. In the scheme using the resistor, no bias circuit is needed, thus further reducing power consumption.

[0055] According to one embodiment, the wake-up circuit using the resistor R200 in the above scheme can work under low power supply voltage conditions. In the traditional circuit, a bias circuit is needed to work normally, and the bias circuit consumes certain power consumption. According to the above formula (1) and formula (2), it can also be obtained that the super cut-off stack structure 200 is equivalent to a transistor with a threshold voltage of V th .

[0056] According to one embodiment, when the two signals at the input terminal of the super cut-off stack structure 200 are common mode signals, V GS =(VGN-VGP) / 2 is equal to 0, which is necessarily less than V th , and the super cut-off stack structure 200 is in the super cut-off state, that is, the voltage at the SEN_P200 node is VDD.

[0057] ​According to one embodiment, when the two input signals of the super cut-off stack structure 200 are differential mode signals, and the input differential voltage is less than Vthn+|Vthp| (equivalent to V GS th ), the super cut-off stack structure 200 is still in the cut-off state.

[0058] According to one embodiment, when the two input signals of the super cut-off stack structure 200 are differential mode signals, and the input differential voltage is greater than or equal to Vthn+|Vthp| (equivalent to V GS th ), the super cut-off stack structure is turned on, and as the differential voltage continues to increase, the voltage of the node SEN_P 200 decreases from the power supply voltage VDD.

[0059] In this application, because the transistor exhibits a strictly matched exponential current-voltage transfer characteristic in the sub-threshold operating zone, the super cut-off stack structure 200 works in the super cut-off state without any bias voltage condition beyond the power rail (voltage source), and the super cut-off state leakage current is much lower than the conventional transistor leakage current level, thereby reducing the power consumption of the circuit when working in a static state.

[0060] According to one embodiment, the resistance R200 is related to the frequency of the two input terminals of the super cut-off stack structure 200 when the input differential signal is input, and the lower the frequency, the greater the resistance R200 value, and the smaller the corresponding source-drain current, thereby reducing the dynamic power consumption of the above-mentioned sensing circuit. For example, when the input differential signal frequency is 2Mhz, the resistance R200 value can be 600KΩ~1.2MΩ.

[0061] If the voltage of the node SEN_P 200 is directly input to the inverter, because the voltage will have a slow rising or falling process, it will cause a large power consumption when the inverter flips. Therefore, according to one embodiment, the voltage of the node SEN_P 200 can be provided to the Schmitt trigger ST200, and then output through the series-connected inverter INV200, thereby further reducing the dynamic power consumption of the wake-up circuit.

[0062] According to one embodiment, a new type of Schmitt trigger is used in the scheme of the present application, which can further save power compared with the traditional Schmitt trigger.

[0063] The wake-up circuit using the super cut-off stack structure as shown in Figure 1 and Figure 2 does not require the clock in the traditional wake-up circuit, not only can reduce the power consumption, but also can achieve the simple wake-up function, only needs to satisfy that the input differential mode signal is greater than the opening threshold of the super cut-off stack structure.

[0064] ​​Figure 3 and Figure 4 The diagram shown is a Schmitt trigger circuit diagram according to an embodiment of this application.

[0065] like Figure 3 As shown, according to one embodiment, the gate electrodes of transistors P11, P12, and N11 are electrically connected and receive the input signal IN1. The source electrode of transistor P11 receives the power supply voltage VDD, and the source electrode of transistor N11 receives the ground potential. The drain electrode of transistor P11 is electrically connected to the source electrode of transistor P12, and the drain electrode of transistor P12 is electrically connected to the drain electrode of transistor N11. The drain electrode of transistor P13 receives the ground potential, and its source electrode is electrically connected to the drain electrode of transistor P11. The gate electrode of transistor P13 is electrically connected to the node NV11 between the drain electrodes of transistors P12 and N11, and outputs the signal OUT3 as the output terminal.

[0066] According to one embodiment, the width-to-length ratio (W / L) of transistor P11 can be 1 μm in width and 16 μm in length. According to one embodiment, the widths of transistors P12 and P13 can be 2 μm in width and 4 μm-6 μm in length. According to one embodiment, the width-to-length ratio (W / L) of transistor N11 can be 8 μm in width and 0.6 μm in length. That is, the width-to-length ratio of transistor N11 is much larger than that of the other transistors in the Schmitt trigger of this embodiment.

[0067] According to one embodiment, when the input signal IN1 of the Schmitt trigger rises, because the width-to-length ratio (W / L) of transistor N11 is large, it turns on quickly, and the potential of node NV11 and the output signal OUT3 are pulled down to ground potential; at this time, transistor P13 turns on, and the potential of node NV12 between transistors P11 and P12 is also pulled down to ground potential; the source and drain potentials of transistor P12 are both at ground potential, so no current flows through transistor P12, and the output signal OUT3 is controlled only by branch 1.

[0068] According to one embodiment, to prevent false triggering such as glitches and jitters during the rise of the input signal IN1, which could affect the output of OUT3, branch 2 has a hysteresis window function, directing the current generated by the false trigger signal to ground potential through transistors P11 and P13. Transistor P11 has a small aspect ratio, resulting in a smaller current flowing through branch 2, thereby reducing power consumption. Compared to a conventional Schmitt trigger, the input signal does not need to meet a high threshold to flip the voltage through branch 1. This is because in this embodiment, transistor N11 in the Schmitt trigger has a large aspect ratio, low on-resistance, and a low on-threshold, thus reducing dynamic power consumption.

[0069] like Figure 4As shown, according to one embodiment, the gate electrodes of the transistor P21, the transistor N21 and the transistor N22 are electrically connected and receive the input signal IN2, the source electrode of the transistor P21 receives the power supply voltage VDD, the source electrode of the transistor N22 receives the ground potential, the drain electrode of the transistor P21 is electrically connected with the drain electrode of the transistor N21, the source electrode of the transistor N21 is electrically connected with the drain electrode of the transistor N22, the drain electrode of the transistor N23 receives the power supply voltage VDD, the source electrode of the transistor N23 is electrically connected with the drain electrode of the transistor N22, the gate electrode of the transistor N23 is electrically connected with the node NV22 between the drain electrode of the transistor P21 and the drain electrode of the transistor N21, and outputs the signal OUT4 as an output terminal.

[0070] According to one embodiment, the width-length ratio W / L of the transistor N22 can be 1 μm in width and 16 μm in length. According to one embodiment, the width of the transistor N21 and the transistor N23 can be 2 μm and the length can be 4 μm-6 μm. According to one embodiment, the width-length ratio W / L of the transistor P21 can be 8 μm in width and 0.6 μm in length. That is, the width-length ratio of the transistor P21 is much larger than that of the other transistors in the Schmitt trigger of the embodiment.

[0071] According to one embodiment, when the input signal IN2 of the Schmitt trigger falls, the potential of the node NV22 and the output signal OUT4 are pulled to high potential due to the large width-length ratio W / L of the transistor P21 and the fast opening speed; at this time, the transistor N23 is opened, and the potential of the node NV21 between the transistor N21 and the transistor N22 is also pulled to high potential; the source-drain potential of the transistor N21 is high, thus no current flows through the transistor N21, and the output signal OUT4 is controlled only by the branch 4.

[0072] According to one embodiment, in order to prevent the false triggering of the input signal IN2 during the falling process, such as the glitch jitter, from affecting the output of OUT4, the branch 3 has a hysteresis window function, and the current generated by the false triggering signal is introduced into the ground potential through the transistor N22 and the transistor N23. Among them, the width-length ratio of the transistor N22 is small, and the current flowing through the branch 3 is small, thereby reducing the power consumption. Compared with the traditional Schmitt trigger, the input signal does not need to satisfy a lower threshold value, and the voltage can be flipped through the branch 4, because the width-length ratio of the transistor P21 in the Schmitt trigger of the embodiment is large, the on-resistance is small, and the on-threshold is low, thus the dynamic power consumption can be reduced.

[0073] Figure 5 Fig. 6 shows a schematic diagram of a wake-up circuit according to another embodiment of the present application.

[0074] Since the two input signals of the super-cut-off stack structure originate from the common-mode signal, such as Figure 1 and Figure 2As shown, the common-mode signal affects the potential V at the electrical connection point X in the two wake-up circuits, respectively. X .

[0075] According to one embodiment, enabling the Schmitt trigger ST100 requires the voltage at node SEN_N100 to rise sufficiently. When the received common-mode signal is low, the over-cutoff stack structure does not have enough differential voltage to fully turn on, resulting in the voltage at node SEN_N100 being too low to trigger the Schmitt trigger ST100. For example, when the common-mode signal is below (Vthn +|Vthp|) / 2, at a supply voltage of 1.2V, the input differential voltage cannot fully turn on the over-cutoff stack structure, and the voltage at node SEN_N100 cannot rise effectively. Figure 1 When the wake-up circuit shown operates, the over-cutoff stack structure requires a relatively high common-mode voltage, for example, higher than (Vthn + |Vthp|) / 2. According to one embodiment, enabling the Schmitt trigger ST200 requires the voltage at node SEN_P200 to drop sufficiently low. When the common-mode signal is relatively high, for example, higher than VDD - (Vthn + |Vthp|) / 2, the over-cutoff stack structure does not have a sufficient differential voltage to fully turn on, resulting in the voltage at node SEN_P200 not effectively decreasing. Figure 2 When the wake-up device shown is working, a low common-mode voltage needs to be input to the signal input terminal.

[0076] To ensure the wake-up circuit functions correctly even when the input signals at both input terminals of the super-cutoff stacked structure are in low or high common-mode conditions, this application provides the following... Figure 5 The wake-up circuit shown will Figure 1 and Figure 2 The wake-up circuit shown can be combined to make the input common-mode signal range unlimited, that is, to realize rail-to-rail input signal.

[0077] like Figure 5 As shown, according to one embodiment, in the super-cutoff stacked structure 501, the drain electrode of the PMOS transistor MP1 is electrically connected to the first terminal of the resistor R1 and the input terminal of the Schmitt trigger ST1, with the intersection voltage being the voltage of node SEN_N1, and the drain electrode of the NMOS transistor MN1 receiving the voltage source VDD. According to one embodiment, the Schmitt trigger ST1 can be as follows: Figure 3 The Schmitt trigger shown.

[0078] According to one embodiment, in the super-cutoff stacked structure 502, the drain electrode of the NMOS transistor MN2 is electrically connected to the first terminal of the resistor R2 and the input terminal of the Schmitt trigger ST2, with the intersection voltage being the voltage of node SEN_P1, and the drain electrode of the PMOS transistor MP2 receiving ground potential. According to one embodiment, the Schmitt trigger ST2 can be as follows:Figure 4 The Schmitt trigger is shown.

[0079] According to an embodiment, the gates of the NMOS transistors MN1 and MN2 of the two super-cut-off stacked structures are electrically connected to receive a signal VGN, and the gates of the PMOS transistors MP1 and MP2 are electrically connected to receive a signal VGP.

[0080] According to an embodiment, the second end of the resistor R1 receives a ground potential, and the second end of the resistor R2 receives a voltage source VDD. According to an embodiment, the resistors R1 and R2 have equal resistance values. According to an embodiment, the resistors R1 and R2 can be flexibly configured as passive resistors or active current sources.

[0081] According to an embodiment, the output end of the Schmitt trigger ST2 can be electrically connected to the input end of the inverter INV1, the output end of the inverter INV1 and the output end of the Schmitt trigger ST1 are two input ends of the NAND gate NAND1, and the output of the NAND gate NAND1 is the signal OUT5 output end of the entire circuit.

[0082] According to an embodiment, when the differential input signal satisfies Vthn+|Vthp|, the signal OUT5 output end of the entire circuit is 0. Figure 5 The wake-up circuit shown can realize rail-to-rail input, in which the two branches of the NAND gate input signal can complement each other, one being suitable for a common-mode low and the other being suitable for a common-mode high.

[0083] According to an embodiment, when the power supply voltage is 1.2V and the input differential voltage value is zero, the power consumption is only 132pW, and even when the input differential voltage is the power supply voltage 1.2V, the power consumption is only 410nW, and the energy efficiency is 0.103pJ / Hz at a communication frequency of 2MHz.

[0084] Figure 6 The wake-up circuit shown is according to another embodiment of the present application.

[0085] According to an embodiment, the drain electrode of the PMOS transistor MP3 in the super-cut-off stacked structure 601 is electrically connected to the first end of the resistor R3 and the input end of the Schmitt trigger ST3, and the intersection point voltage is the voltage of the node SEN_N2, and the drain electrode of the NMOS transistor MN3 receives a voltage source VDD. According to an embodiment, the Schmitt trigger ST3 can be a Schmitt trigger as shown. Figure 3 The Schmitt trigger is shown.

[0086] According to an embodiment, the drain electrode of NMOS transistor MN4 in the super cut-off stack structure 602 is electrically connected with the first end of resistor R4 and the input end of Schmitt trigger ST4, the intersection voltage is the voltage of node SEN_P2, and the drain electrode of PMOS transistor MP4 receives a ground potential. According to an embodiment, the Schmitt trigger ST4 can be a Schmitt trigger as shown in Figure 4 .

[0087] According to an embodiment, the gate electrodes of NMOS transistor MN3 and transistor MN4 of the two super cut-off stack structures are electrically connected and receive a signal VGN, and the gate electrodes of PMOS transistor MP3 and transistor MP4 are electrically connected and receive a signal VGP.

[0088] According to an embodiment, the second end of resistor R3 receives a ground potential, and the second end of resistor R4 receives a voltage source VDD. According to an embodiment, the resistances of resistor R3 and resistor R4 are equal. According to an embodiment, resistor R3 and resistor R4 can be flexibly configured as passive resistors or active current sources.

[0089] According to an embodiment, the output end of Schmitt trigger ST3 can be electrically connected with the input end of inverter INV2, the output end of inverter INV2 and the output end of Schmitt trigger ST4 are two input ends of or gate OR1, and the output of or gate OR1 is the signal OUT6 output end of the entire circuit.

[0090] According to an embodiment, when the differential input signal satisfies Vthn+|Vthp|, the wake-up circuit as shown in Figure 6 can realize rail-to-rail input, in which the two branches of the or gate input signal can complement each other, one for common mode low and one for common mode high.

[0091] According to an embodiment, under a power supply voltage of 1.2V, the power consumption when the input differential voltage value is zero is only 132pW, and even when the input differential voltage is the power supply voltage 1.2V, the power consumption is only 410nW, and under a communication frequency of 2MHz, the energy efficiency is 0.103pJ / Hz.

[0092] The double rail-to-rail wake-up circuit as shown in Figure 5 and Figure 6 does not need to consider the high and low of the common mode signal in the input signal, and as long as the differential mode signal satisfies the super cut-off stack structure conduction threshold condition, the wake-up function of the subsequent circuit can be realized.

[0093] However, when waking up the subsequent circuit, due to the existence of interference in the environment, the wake-up circuit as shown in Figure 5 or Figure 6 may cause the output signal to be not accurate enough, so two wake-up circuits as shown in Figure 5 and / or Figure 6The wake-up circuit shown judges whether to wake up the subsequent circuit by judging the synchronization state of the outputs of the two wake-up circuits.

[0094] Figures 7-10 The wake-up circuit shown is a schematic diagram of a wake-up circuit according to another embodiment of the application.

[0095] As Figure 7 The wake-up circuit shown adopts two wake-up units, and the input signals of the two wake-up units are opposite. According to an embodiment, the gates of the transistor MN11 and the transistor MN12 in the wake-up unit A1 and the gates of the transistor MP21 and the transistor MP22 in the wake-up unit A2 are electrically connected as a differential signal VGN input terminal, and the gates of the transistor MP11 and the transistor MP12 in the wake-up unit A1 and the gates of the transistor MN21 and the transistor MN22 in the wake-up unit A2 are electrically connected as a differential signal VGP input terminal. The wake-up unit has a fast rising response under the action of the voltage source VDD, but in the falling response, due to the limitation of the resistance value, it cannot respond quickly, and the long falling delay time limits its application in receiving fast signals, so that when the two wake-up units are in high-speed communication at the same time, the error output result that the output signals OUT71 and OUT72 are both high may occur. In order to realize the fast symmetric response of the input signal in the high-frequency state and solve the problem of asymmetric rising and falling time, as Figure 7 shown, the fast rising edge of the output signal OUT71 of the wake-up unit A1 and the output signal OUT72 of the wake-up unit A2 are used to feedback the other circuit in the two circuits.

[0096] According to an embodiment, the wake-up circuit can work at an input signal frequency greater than 500 KHZ.

[0097] According to an embodiment, the wake-up unit A1 includes a first wake-up subunit including a supercut-off stack structure 701 and a resistor R11, and a second wake-up subunit including a supercut-off stack structure 702 and a resistor R12; and a feedback circuit B1 and an output unit C1 electrically connected thereto in sequence, wherein the feedback circuit B1 includes a transistor MP13, a resistor R14, a capacitor C11, an inverter INV11, a capacitor C12, a resistor R13 and a transistor MN13, and the output unit C1 includes a Schmitt trigger ST11, a Schmitt trigger ST12, an inverter INV712 and a NAND gate NAND2.

[0098] According to an embodiment, the drain electrode of the PMOS transistor MP11 in the super cut-off stack structure 701 in the wake-up unit A1 is electrically connected to the first end of the resistor R11 and the input end of the Schmitt trigger ST11, the drain electrode of the NMOS transistor MN11 receives the power supply voltage VDD, the source electrode of the NMOS transistor MN11 is electrically connected to the source electrode of the transistor MP11, and the node SEN_N1 is the output end of the super cut-off stack structure 701.

[0099] According to an embodiment, the drain electrode of the NMOS transistor MN12 in the super cut-off stack structure 702 is electrically connected to the first end of the resistor R12 and the input end of the Schmitt trigger ST12, the drain electrode of the PMOS transistor MP12 receives the ground potential, the source electrode of the PMOS transistor MP12 is electrically connected to the source electrode of the transistor MN12, and the node SEN_N2 is the output end of the super cut-off stack structure 702.

[0100] According to an embodiment, the output end of the Schmitt trigger ST12 is electrically connected to the input end of the inverter INV712, the output end of the inverter INV712 and the output end of the Schmitt trigger ST11 are electrically connected to the input end of the NAND gate NAND2, and the output end of the NAND gate NAND2 is the output end OUT71 of the wake-up unit A1. According to an embodiment, the ST11 can be a Schmitt trigger as shown in Figure 3 According to an embodiment, the ST12 can be a Schmitt trigger as shown in Figure 4 .

[0101] According to an embodiment, the drain electrode of the transistor MP13 is electrically connected to the input end of the Schmitt trigger ST12, the source electrode of the transistor MP13 is electrically connected to the first end of the resistor R14 and configured to receive the power supply voltage VDD, the gate electrode of the transistor MP13 is electrically connected to the second end of the resistor R14 and the first plate of the capacitor C11, the second plate of the capacitor C11 is electrically connected to the output end of the inverter INV11, the drain electrode of the transistor MN13 is electrically connected to the input end of the Schmitt trigger ST11, the source electrode of the transistor MN13 is electrically connected to the first end of the resistor R13 and configured to receive the ground potential, the gate electrode of the transistor MN13 is electrically connected to the second end of the resistor R13 and the first plate of the capacitor C12, and the second plate of the capacitor C12 is electrically connected to the input end of the inverter INV11 and the output end of the output signal OUT72 of the wake-up unit A2.

[0102] According to an embodiment, the drain electrode of the PMOS transistor MP21 in the super cut-off stack structure 703 in the wake-up unit A2 is electrically connected to the first end of the resistor R21 and the voltage of the node SEN_N3 which is the input end of the Schmitt trigger ST21, the drain electrode of the NMOS transistor MN21 is configured to receive the power supply voltage VDD, and the node SEN_N3 is the output end of the super cut-off stack structure 703.

[0103] According to an embodiment, the drain electrode of the NMOS transistor MN22 in the super cut-off stack structure 704 is electrically connected to the first end of the resistor R22 and the node SEN_N4 which is the input end of the Schmitt trigger ST22, the drain electrode of the PMOS transistor MP22 receives the ground potential, the source electrode of the NMOS transistor MN22 is electrically connected to the source electrode of the transistor MP22, and the node SEN_N4 is the output end of the super cut-off stack structure 704.

[0104] According to an embodiment, the output end of the Schmitt trigger ST22 is electrically connected to the input end of the inverter INV722, the output end of the inverter INV722 and the output end of the Schmitt trigger ST21 are electrically connected to the input end of the NAND gate NAND3, and the output end of the NAND gate NAND3 is the output end OUT72 of the wake-up unit A2. According to an embodiment, the ST21 can be a Schmitt trigger as shown in Figure 3 According to an embodiment, the ST22 can be a Schmitt trigger as shown in Figure 4 .

[0105] According to an embodiment, the drain electrode of the transistor MP23 is electrically connected to the input end of the Schmitt trigger ST22, the source electrode of the transistor MP23 is electrically connected to the first end of the resistor R24 and configured to receive the power supply voltage VDD, the gate electrode of the transistor MP23 is electrically connected to the second end of the resistor R24 and the first plate of the capacitor C21, the second plate of the capacitor C21 is electrically connected to the output end of the inverter INV21, the drain electrode of the transistor MN23 is electrically connected to the input end of the Schmitt trigger ST21, the source electrode of the transistor MN23 is electrically connected to the first end of the resistor R23 and configured to receive the ground potential, the gate electrode of the transistor MN23 is electrically connected to the second end of the resistor R23 and the first plate of the capacitor C22, and the second plate of the capacitor C22 is electrically connected to the input end of the inverter INV21 and the output end of the signal OUT71 of the wake-up unit A1.

[0106] According to one embodiment, the wake-up unit A2 includes a third wake-up subunit including a super-cutoff stacked structure 703 and a resistor R21, a fourth wake-up subunit including a super-cutoff stacked structure 704 and a resistor R22; and a feedback circuit B2 and an output unit C2 connected thereto in sequence. The feedback circuit B2 includes a transistor MP23, a resistor R24, a capacitor C21, an inverter INV21, a capacitor C22, a resistor R23, and a transistor MN23. The output unit C2 includes a Schmitt trigger ST21, a Schmitt trigger ST22, an inverter INV722, and a NAND gate NAND3.

[0107] According to one embodiment, the wake-up unit A1 may only include a super-cutoff stack structure 701, a resistor R11, a Schmitt trigger ST11, an inverter (not shown in the figure), a transistor MN13, a resistor R13, and a capacitor C12. According to one embodiment, the output of the Schmitt trigger ST11 is electrically connected to the input of the inverter, and the output of the inverter serves as the signal output of the wake-up unit A1.

[0108] According to one embodiment, the wake-up unit A1 may only include a super-cutoff stack structure 702, a resistor R12, a Schmitt trigger ST12, an inverter INV712, an inverter INV11, a capacitor C11, a resistor R14, and a transistor MP13, with the output of the inverter INV712 serving as the output of the wake-up unit A1.

[0109] According to one embodiment, the wake-up unit A2 may only include a super-cutoff stack structure 703, a resistor R21, a Schmitt trigger ST21, an inverter (not shown in the figure), a transistor MN23, a resistor R23, and a capacitor C22. The output terminal of the Schmitt trigger ST21 is electrically connected to the input terminal of the inverter, and the output terminal of the inverter serves as the output terminal of the wake-up unit A2.

[0110] According to one embodiment, the wake-up unit A2 may only include a super-cutoff stack structure 704, a resistor R22, a Schmitt trigger ST22, an inverter INV722, an inverter INV21, a capacitor C21, a resistor R24, and a transistor MP23. The output terminal of the Schmitt trigger ST22 is electrically connected to the input terminal of the inverter INV722, and the output terminal of the inverter INV722 serves as the output terminal of the wake-up unit A2.

[0111] According to one embodiment, resistors R11, R12, R21, and R22 can be flexibly configured as passive resistors or active current sources.

[0112] like Figure 8 As shown, with Figure 7Similar parts are not described again, according to an embodiment, the output unit C1 can include a Schmitt trigger ST11, a Schmitt trigger ST12, an inverter INV812 and an OR gate OR2, wherein the output end of the Schmitt trigger ST11 is electrically connected to the input end of the inverter INV812, the output end of the inverter INV812 and the output end of the Schmitt trigger ST12 are electrically connected to the input end of the OR gate OR2, and the output end thereof is as the output end of the wake-up unit A1 signal OUT81. According to an embodiment, the output unit C2 can include a Schmitt trigger ST21, a Schmitt trigger ST22, an inverter INV722 and a NAND gate NAND3, wherein the output end of the Schmitt trigger ST22 is electrically connected to the input end of the inverter INV722, the output end of the inverter INV722 and the output end of the Schmitt trigger ST21 are electrically connected to the input end of the NAND gate NAND3, and the output end thereof is as the output end of the wake-up unit A2 signal OUT82.

[0113] As shown in Figure 9 , according to an embodiment, the output unit C1 can include a Schmitt trigger ST11, a Schmitt trigger ST12, an inverter INV712 and a NAND gate NAND2, wherein the output end of the Schmitt trigger ST12 is electrically connected to the input end of the inverter INV712, the output end of the inverter INV712 and the output end of the Schmitt trigger ST11 are electrically connected to the input end of the NAND gate NAND2, and the output end thereof is as the output end of the wake-up unit A1 signal OUT91. According to an embodiment, the output unit C2 can include a Schmitt trigger ST21, a Schmitt trigger ST22, an inverter INV922 and an OR gate OR3, wherein the output end of the Schmitt trigger ST21 is electrically connected to the input end of the inverter INV922, the output end of the inverter INV922 and the output end of the Schmitt trigger ST22 are electrically connected to the input end of the OR gate OR3, and the output end thereof is as the output end of the wake-up unit A2 signal OUT92.

[0114] As shown in Figure 10As shown, according to one embodiment, the output unit C1 can include a Schmitt trigger ST11, a Schmitt trigger ST12, an inverter INV812 and an OR gate OR2, wherein the output terminal of the Schmitt trigger ST11 is electrically connected to the input terminal of the inverter INV812, the output terminal of the inverter INV812 and the output terminal of the Schmitt trigger ST12 are electrically connected to the input terminal of the OR gate OR2, and the output terminal of the OR gate OR2 is the output terminal of the wake-up unit A1 signal OUT101. According to one embodiment, the output unit C2 can include a Schmitt trigger ST21, a Schmitt trigger ST22, an inverter INV922 and an OR gate OR3, wherein the output terminal of the Schmitt trigger ST21 is electrically connected to the input terminal of the inverter INV922, the output terminal of the inverter INV922 and the output terminal of the Schmitt trigger ST22 are electrically connected to the input terminal of the OR gate OR3, and the output terminal of the OR gate OR3 is the output terminal of the wake-up unit A2 signal OUT102.

[0115] Figure 11 As shown is a working timing diagram of the wake-up circuit according to one embodiment of the present application, for example Figure 7 Figure 11 As shown, according to one embodiment, in the t0-t1 stage, the input signals VGN and VGP start under the common mode condition, and as the differential mode signal gradually increases to a threshold voltage that satisfies VGN-VGP greater than or equal to Vthn+|Vthp|, the super cut-off stacked structures 701 and 702 in the wake-up unit A1 are turned on, the voltage of the node SEN_N1 gradually rises, and after passing through the Schmitt trigger ST11, a low potential signal is output; the voltage of the node SEN_N2 gradually decreases, and after passing through the Schmitt trigger ST12 and the inverter INV712, a low potential signal is output, the output signals of the Schmitt trigger ST11 and the inverter INV712 pass through the NAND gate NAND2, the output signal OUT71 rises from low potential to high potential, and the node FPP in the wake-up unit A2 transmits a short rising pulse voltage through the capacitor.

[0116] ​According to one embodiment, in the t1-t2 stage, as the input signal VGN and VGP differential mode voltage VGN-VGP decreases, the differential mode voltage VGP-VGN increases, the node SEN_N1 voltage gradually decreases, and the node SEN_N2 voltage gradually increases, but since the resistance R11 and the resistance R12 are large value devices, the node SEN_N1 voltage decreases very slowly, and the node SEN_N2 voltage increases very slowly. When the input signal VGN and VGP differential mode decreases to satisfy VGP-VGN greater than or equal to Vthn+|Vthp|, the super cut-off stacks 703 and 704 in the wake-up unit A2 are turned on, the node SEN_N3 voltage gradually rises, and a low potential signal is output after passing through the Schmitt trigger ST21; the node SEN_N4 voltage gradually decreases, and a low potential signal is output after passing through the Schmitt trigger ST22 and the inverter INV722, the Schmitt trigger ST21 and the inverter INV722 output signals pass through the NAND gate NAND3, and the output signal OUT72 changes from low potential to high potential. Due to the alternating current (AC) through direct current (DC) isolation characteristics of the capacitor C12, the resistance R13 can temporarily maintain the AC signal transmitted by the capacitor, that is, the node FNP temporarily rises in pulse voltage, the transistor MN13 is momentarily turned on, the node SEN_N1 voltage is rapidly reduced to low potential, and a high potential signal is output after passing through the Schmitt trigger ST11. At the same time, under the joint action of the inverter INV11, the capacitor C11 and the resistance R14, the transistor MP13 is quickly turned on, the node SEN_N2 voltage is rapidly pulled high to high potential, a high potential signal is output after passing through the Schmitt trigger ST12 and the inverter INV712, and the Schmitt trigger ST11 and the inverter INV712 output signals pass through the NAND gate NAND2, and the output signal OUT71 quickly changes to low potential.

[0117] According to one embodiment, in the t2-t3 stage, the input signal VGN and the differential mode signal VGP-VGN gradually decrease, the voltage of the node SEN_N3 gradually decreases, and the voltage of the node SEN_N4 gradually increases. However, the voltage of the node SEN_N3 decreases very slowly and the voltage of the node SEN_N4 increases very slowly because the resistance R21 and the resistance R22 are large-value devices. When the differential mode signal VGN-VGP is greater than or equal to the threshold voltage Vthn+|Vthp|, the super-cut-off stacked structures 701 and 702 in the wake-up unit A1 are turned on, the voltage of the node SEN_N1 gradually increases, and a low potential signal is output after passing through the Schmitt trigger ST11. The voltage of the node SEN_N2 gradually decreases, and a low potential signal is output after passing through the Schmitt trigger ST12 and the inverter INV712. The output signals of the Schmitt trigger ST11 and the inverter INV712 pass through the NAND gate NAND2, and the output signal OUT71 changes from a low potential to a high potential. At this time, the node FPP transmits a short rising pulse voltage through the capacitor, the transistor MN23 is momentarily turned on, the voltage of the node SEN_N3 is rapidly reduced to a low potential, a high potential signal is output after passing through the Schmitt trigger ST21, and the transistor MP23 is quickly turned on under the joint action of the inverter INV21, the capacitor C21 and the resistance R24. The voltage of the node SEN_N4 is rapidly pulled high to a high potential, a high potential signal is output after passing through the Schmitt trigger ST22 and the inverter INV722, and the output signal OUT72 quickly changes to a low potential after passing through the NAND gate NAND3.

[0118] Figures 7-10 The fast rising / falling edge of the output of one wake-up branch is used to reset the slow falling / rising edge of the other wake-up branch, so that symmetrical hysteresis and fast response can be achieved.

[0119] The application further provides an electronic device comprising the wake-up circuit.

[0120] The wake-up circuit of the application, by constructing the super cut-off stack structure of the PMOS transistor and the NMOS transistor in series, the super cut-off stack structure works in the super cut-off state when the system is in the sleep mode, that is, the static state, since the wake-up circuit of the application is threshold triggered, not periodic detection, so it is not necessary to use the clock signal, which greatly reduces the static power consumption of the wake-up circuit; by improving the traditional Schmidt trigger and using the combination of the super cut-off stack structure and the resistor in different forms in the circuit, two forms of wake-up sub-units are constructed, and the wake-up sub-units are combined, the output ends are respectively realized through the output unit to realize the rail-to-rail wake-up circuit output, and the outputs of the above two rail-to-rail wake-up circuits are combined in the form of mutual feedback circuit, on the one hand, the working efficiency of the wake-up circuit is improved, on the other hand, the dynamic power consumption of the wake-up circuit is reduced.

[0121] The above examples are only for illustrating the application, and are not a limitation of the application. Those skilled in the art can make various changes and modifications without departing from the scope of the application. Therefore, all equivalent technical solutions shall belong to the scope of the application.

Claims

1. A wake-up circuit, characterized by comprising, a first super cut-off stack structure comprising a first transistor and a second transistor connected in series with each other, wherein a drain electrode of the first transistor is electrically connected to a power supply, a source electrode is electrically connected to a source electrode of the second transistor, a gate electrode of the first transistor is as a first signal input terminal, a gate electrode of the second transistor is as a second signal input terminal, the first transistor is an N-type transistor, and the second transistor is a P-type transistor; a first resistor or a first current source, a first end of which is electrically connected to a drain electrode of the second transistor, and a second end of which is grounded; a first Schmitt trigger, an input terminal of which is electrically connected to a first node at which the drain electrode of the second transistor and the first end of the first resistor or the first current source are electrically connected, and an output terminal of which is as a wake-up device output terminal; or the wake-up device circuit further comprises a first inverter, an input terminal of which is electrically connected to an output terminal of the first Schmitt trigger, and an output terminal of which is as an output terminal of the wake-up device circuit.

2. The wake-up device circuit according to claim 1, wherein the first Schmitt trigger comprises a third transistor, a fourth transistor and a fifth transistor, gate electrodes of which are electrically connected together as an input terminal of the first Schmitt trigger, wherein a source electrode of the third transistor is electrically connected to a power supply, a source electrode of the fifth transistor is grounded, a drain electrode of the third transistor is electrically connected to a source electrode of the fourth transistor, a drain electrode of the fourth transistor is electrically connected to a drain electrode of the fifth transistor, a drain electrode of a sixth transistor is grounded, a source electrode of the sixth transistor is electrically connected to the drain electrode of the third transistor, a gate electrode of the sixth transistor is electrically connected to the drain electrode of the fourth transistor and the drain electrode of the fifth transistor, and is as an output terminal of the first Schmitt trigger; wherein the fifth transistor is complementary to the third transistor, the fourth transistor and the sixth transistor in type, and a width-length ratio of the fifth transistor is greater than width-length ratios of other transistors in the first Schmitt trigger.

3. A wake-up circuit, characterized by comprising, a second super cut-off stack structure comprising a seventh transistor and an eighth transistor connected in series with each other, wherein a source electrode of the seventh transistor is electrically connected to a source electrode of the eighth transistor, a gate electrode of the seventh transistor is as a first signal input terminal, a gate electrode of the eighth transistor is as a second signal input terminal, the seventh transistor is an N-type transistor, and the eighth transistor is a P-type transistor; a second resistor or a second current source, a first end of which is electrically connected to a drain electrode of the seventh transistor, and a second end of which is electrically connected to a power supply; a second Schmitt trigger, an input terminal of which is electrically connected to a second node at which the drain electrode of the seventh transistor and the first end of the second resistor or the second current source are electrically connected, and an output terminal of which is as a wake-up device output terminal; or the wake-up device circuit further comprises a second inverter, an input terminal of which is electrically connected to an output terminal of the second Schmitt trigger, and an output terminal of which is as an output terminal of the wake-up device circuit.

4. The wake-up device circuit according to claim 3, wherein the second Schmitt trigger comprises a ninth transistor, a tenth transistor, an eleventh transistor, whose gates are electrically connected together as an input terminal of the second Schmitt trigger, wherein a source electrode of the ninth transistor is electrically connected to a power supply, a source electrode of the eleventh transistor is grounded, a drain electrode of the eleventh transistor is electrically connected to a source electrode of the tenth transistor, a drain electrode of the ninth transistor is electrically connected to a drain electrode of the tenth transistor, a drain electrode of a twelfth transistor is connected to the power supply, and a source electrode of the twelfth transistor is electrically connected to the source electrode of the tenth transistor, a gate electrode of the twelfth transistor is electrically connected to the drain electrode of the ninth transistor and the drain electrode of the tenth transistor, and serves as an output terminal of the second Schmitt trigger; wherein the ninth transistor is complementary to the tenth transistor, the eleventh transistor and the twelfth transistor in type, and the width-length ratio of the ninth transistor is greater than that of other transistors in the second Schmitt trigger.

5. A wake-up circuit, characterized by comprises, a third super-cut-off stack structure comprising a thirteenth transistor and a fourteenth transistor connected in series with each other, wherein a drain electrode of the thirteenth transistor is electrically connected to a power supply, a source electrode is electrically connected to a source electrode of the fourteenth transistor, a gate electrode of the thirteenth transistor serves as a first signal input terminal, and a gate electrode of the fourteenth transistor serves as a second signal input terminal, the thirteenth transistor is an N-type transistor, and the fourteenth transistor is a P-type transistor; a fourth super-cut-off stack structure comprising a fifteenth transistor and a sixteenth transistor connected in series with each other, wherein a source electrode of the fifteenth transistor is electrically connected to a source electrode of the sixteenth transistor, a gate electrode of the fifteenth transistor serves as a first signal input terminal, and a gate electrode of the sixteenth transistor serves as a second signal input terminal, the fifteenth transistor is an N-type transistor, and the sixteenth transistor is a P-type transistor; a third resistor or a third current source, whose first end is electrically connected to a drain electrode of the fourteenth transistor, and whose second end is grounded, and a fourth resistor or a fourth current source, whose first end is electrically connected to a drain electrode of the fifteenth transistor, and whose second end is connected to the power supply; a third Schmitt trigger, whose input terminal is electrically connected to a third node at which the drain electrode of the fourteenth transistor and the first end of the third resistor or the third current source are electrically connected; a fourth Schmitt trigger, whose input terminal is electrically connected to a fourth node at which the drain electrode of the fifteenth transistor and the first end of the fourth resistor or the fourth current source are electrically connected; a third inverter, whose input terminal is electrically connected to an output terminal of the fourth Schmitt trigger; a first NAND gate, whose two input terminals are respectively electrically connected to an output terminal of the third inverter and an output terminal of the third Schmitt trigger, and an output terminal of the first NAND gate serves as an output terminal of the wake-up circuit.

6. The wake-up circuit according to claim 5, wherein The third Schmitt trigger comprises a seventeenth transistor, an eighteenth transistor and a nineteenth transistor whose gates are electrically connected together as an input terminal of the third Schmitt trigger, wherein a source electrode of the seventeenth transistor is electrically connected to a power supply, a source electrode of the nineteenth transistor is grounded, a drain electrode of the seventeenth transistor is electrically connected to a source electrode of the eighteenth transistor, a drain electrode of the eighteenth transistor is electrically connected to a drain electrode of the nineteenth transistor, a drain electrode of a twentieth transistor is grounded, a source electrode of the twentieth transistor is electrically connected to the drain electrode of the seventeenth transistor, a gate electrode of the twentieth transistor is electrically connected to the drain electrode of the eighteenth transistor and the drain electrode of the nineteenth transistor, and serves as an output terminal of the third Schmitt trigger, wherein the nineteenth transistor is complementary to the seventeenth transistor, the eighteenth transistor and the twentieth transistor, and a width-length ratio of the nineteenth transistor is greater than that of other transistors of the third Schmitt trigger; and / or, The fourth Schmitt trigger comprises a twenty-first transistor, a twenty-second transistor and a twenty-third transistor whose gates are electrically connected together as an input terminal of the fourth Schmitt trigger, wherein a source electrode of the twenty-first transistor is electrically connected to a power supply, a source electrode of the twenty-third transistor is grounded, a drain electrode of the twenty-third transistor is electrically connected to a source electrode of the twenty-second transistor, a drain electrode of the twenty-first transistor is electrically connected to a drain electrode of the twenty-second transistor, a drain electrode of a twenty-fourth transistor is connected to the power supply, and a source electrode of the twenty-fourth transistor is electrically connected to the source electrode of the twenty-second transistor, a gate electrode of the twenty-fourth transistor is electrically connected to the drain electrode of the twenty-first transistor and the drain electrode of the twenty-second transistor, and serves as an output terminal of the fourth Schmitt trigger, wherein the twenty-first transistor is complementary to the twenty-second transistor, the twenty-third transistor and the twenty-fourth transistor, and a width-length ratio of the twenty-first transistor is greater than that of other transistors of the fourth Schmitt trigger.

7. A wake-up circuit, characterized by The fifth supercut-off stack structure comprises a twenty-fifth transistor and a twenty-sixth transistor connected in series with each other, wherein a drain electrode of the twenty-fifth transistor is electrically connected to a power supply, a source electrode is electrically connected to a source electrode of the twenty-sixth transistor, a gate electrode of the twenty-fifth transistor serves as a first signal input terminal, a gate electrode of the twenty-sixth transistor serves as a second signal input terminal, the twenty-fifth transistor is an N-type transistor, and the twenty-sixth transistor is a P-type transistor; The sixth supercut-off stack structure comprises a twenty-seventh transistor and a twenty-eighth transistor connected in series with each other, wherein a source electrode of the twenty-seventh transistor is electrically connected to a source electrode of the twenty-eighth transistor, a gate electrode of the twenty-seventh transistor serves as a first signal input terminal, a gate electrode of the twenty-eighth transistor serves as a second signal input terminal, the twenty-seventh transistor is an N-type transistor, and the twenty-eighth transistor is a P-type transistor; ​ a fifth resistor or a fifth current source, a first end of which is electrically connected to the drain electrode of the twenty-sixth transistor, and a second end of which is grounded; and a sixth resistor or a sixth current source, a first end of which is electrically connected to the drain electrode of the twenty-seventh transistor, and a second end of which is connected to a power supply; a fifth Schmitt trigger, an input end of which is electrically connected to a fifth node at which the drain electrode of the twenty-sixth transistor and the first end of the fifth resistor or the fifth current source are electrically connected; a sixth Schmitt trigger, an input end of which is electrically connected to a sixth node at which the drain electrode of the twenty-seventh transistor and the first end of the sixth resistor or the sixth current source are electrically connected; a fourth inverter, an input end of which is electrically connected to an output end of the fifth Schmitt trigger; a first OR gate, two input ends of which are respectively electrically connected to an output end of the fourth inverter and an output end of the sixth Schmitt trigger, and an output end of the first OR gate serving as an output end of the wake-up circuit.

8. The wake-up circuit according to claim 7, characterized in that the fifth Schmitt trigger comprises a twenty-ninth transistor, a thirtieth transistor and a thirty-first transistor, gate electrodes of which are electrically connected together to serve as an input end of the fifth Schmitt trigger, wherein a source electrode of the twenty-ninth transistor is electrically connected to a power supply, a source electrode of the thirty-first transistor is grounded, a drain electrode of the twenty-ninth transistor is electrically connected to a source electrode of the thirtieth transistor, a drain electrode of the thirtieth transistor is electrically connected to a drain electrode of the thirty-first transistor, a drain electrode of a thirty-second transistor is grounded, and a source electrode of the thirty-second transistor is electrically connected to the drain electrode of the twenty-ninth transistor, a gate electrode of the thirty-second transistor is electrically connected to the drain electrode of the thirtieth transistor and the drain electrode of the thirty-first transistor, and serves as an output end of the fifth Schmitt trigger, wherein a type of the thirty-first transistor is complementary to the twenty-ninth transistor, the thirtieth transistor and the thirty-second transistor, and a width-length ratio of the thirty-first transistor is greater than width-length ratios of other transistors of the fifth Schmitt trigger; and / or the sixth Schmitt trigger comprises a thirty-third transistor, a thirty-fourth transistor and a thirty-fifth transistor, gate electrodes of which are electrically connected together to serve as an input end of the sixth Schmitt trigger, wherein a source electrode of the thirty-third transistor is electrically connected to a power supply, a source electrode of the thirty-fifth transistor is grounded, a drain electrode of the thirty-fifth transistor is electrically connected to a source electrode of the thirty-fourth transistor, a drain electrode of the thirty-third transistor is electrically connected to a drain electrode of the thirty-fourth transistor, a drain electrode of a thirty-sixth transistor is connected to the power supply, and a source electrode of the thirty-sixth transistor is electrically connected to the source electrode of the thirty-fourth transistor, a gate electrode of the thirty-sixth transistor is electrically connected to the drain electrode of the thirty-third transistor and the drain electrode of the thirty-fourth transistor, and serves as an output end of the sixth Schmitt trigger, wherein a type of the thirty-third transistor is complementary to the thirty-fourth transistor, the thirty-fifth transistor and the thirty-sixth transistor, and a width-length ratio of the thirty-third transistor is greater than width-length ratios of other transistors of the sixth Schmitt trigger.

9. A wake-up circuit, characterized by comprising, the first wake-up unit comprises, a seventh super cut-off stack structure having one end electrically connected to the power supply and a seventh resistor or a seventh current source having one end connected in series with the seventh super cut-off stack structure and the other end grounded; and / or, an eighth super cut-off stack structure having one end grounded and an eighth resistor or an eighth current source having one end connected in series with the eighth super cut-off stack structure and the other end electrically connected to the power supply; a first feedback circuit electrically connected to the output end of the first wake-up sub-unit and the output end of the second wake-up sub-unit; a first output unit electrically connected to the first feedback circuit; a second wake-up unit comprising, a ninth super cut-off stack structure having one end electrically connected to the power supply and a ninth resistor or a ninth current source having one end connected in series with the ninth super cut-off stack structure and the other end grounded; and / or, a tenth super cut-off stack structure having one end grounded and a tenth resistor or a tenth current source having one end connected in series with the tenth super cut-off stack structure and the other end electrically connected to the power supply; a second feedback circuit electrically connected to the output end of the third wake-up sub-unit and the output end of the fourth wake-up sub-unit; a second output unit electrically connected to the second feedback circuit; the first feedback circuit is configured to receive the output of the second wake-up unit, and the second feedback circuit is configured to receive the output of the first wake-up unit.

10. The wake-up circuit according to claim 9, wherein, when the first wake-up unit comprises a first wake-up sub-unit and a second wake-up sub-unit, the first output unit comprises, a seventh Schmitt trigger having an input end electrically connected to the output end of the first wake-up sub-unit; an eighth Schmitt trigger having an input end electrically connected to the output end of the second wake-up sub-unit; a fifth inverter and a second NAND gate, wherein the input end of the fifth inverter is electrically connected to the output end of the eighth Schmitt trigger, the output end of the fifth inverter and the output end of the seventh Schmitt trigger are electrically connected to the input end of the second NAND gate, and the output end of the second NAND gate is the output end of the first output unit; or a sixth inverter and a second OR gate, wherein the input end of the sixth inverter is electrically connected to the output end of the seventh Schmitt trigger, the output end of the sixth inverter and the output end of the eighth Schmitt trigger are electrically connected to the input end of the second OR gate, and the output end of the second OR gate is the output end of the first output unit; or when the first wake-up unit comprises a first wake-up sub-unit, the first output unit comprises, a seventh Schmitt trigger and a sixth inverter, wherein the input end of the sixth inverter is electrically connected to the output end of the seventh Schmitt trigger, and the output end of the sixth inverter is the output end of the first output unit; or when the first wake-up unit comprises a second wake-up sub-unit, the first output unit comprises, an eighth Schmitt trigger and a fifth inverter, wherein the input end of the fifth inverter is electrically connected to the output end of the eighth Schmitt trigger, and the output end of the fifth inverter is the output end of the first output unit.

11. The wake-up circuit according to claim 9, wherein, when the second wake-up unit comprises a third wake-up sub-unit and a fourth wake-up sub-unit, the second output unit comprises, a ninth Schmitt trigger, an input terminal of which is electrically connected to an output terminal of the third wake-up subunit; a tenth Schmitt trigger, an input terminal of which is electrically connected to an output terminal of the fourth wake-up subunit; a seventh inverter and a third NAND gate, wherein an input terminal of the seventh inverter is electrically connected to an output terminal of the tenth Schmitt trigger, an output terminal of the seventh inverter and an output terminal of the ninth Schmitt trigger are electrically connected to input terminals of the third NAND gate, and an output terminal of the third NAND gate serves as an output terminal of the second output unit; or an eighth inverter and a third OR gate, wherein an input terminal of the eighth inverter is electrically connected to an output terminal of the ninth Schmitt trigger, an output terminal of the eighth inverter and an output terminal of the tenth Schmitt trigger are electrically connected to input terminals of the third OR gate, and an output terminal of the third OR gate serves as an output terminal of the second output unit; or when the second wake-up unit comprises the third wake-up subunit, the second output unit comprises, a ninth Schmitt trigger and an eighth inverter, wherein an input terminal of the eighth inverter is electrically connected to an output terminal of the ninth Schmitt trigger, and an output terminal of the eighth inverter serves as an output terminal of the second output unit; or when the second wake-up unit comprises the fourth wake-up subunit, the second output unit comprises, a tenth Schmitt trigger and a seventh inverter, wherein an input terminal of the seventh inverter is electrically connected to an output terminal of the tenth Schmitt trigger, and an output terminal of the seventh inverter serves as an output terminal of the second output unit.

12. The wake-up circuit according to claim 10, wherein when the first wake-up unit comprises the first wake-up subunit and the second wake-up subunit, the first feedback circuit comprises, a thirty-seventh transistor, a drain electrode of which is electrically connected to an input terminal of the eighth Schmitt trigger, and a source electrode of which is electrically connected to a power supply; an eleventh resistor, one end of which is electrically connected to the power supply, and the other end of which is electrically connected to a gate electrode of the thirty-seventh transistor; a first capacitor, a first plate of which is electrically connected to the gate electrode of the thirty-seventh transistor; a ninth inverter, an input terminal of which is electrically connected to an output terminal of the second wake-up unit, and an output terminal of which is electrically connected to a second plate of the first capacitor; a thirty-eighth transistor, a drain electrode of which is electrically connected to an input terminal of the seventh Schmitt trigger, a source electrode of which is electrically connected to a first end of a twelfth resistor and receives a ground potential, and a gate electrode of which is electrically connected to a second end of the twelfth resistor and a first plate of a second capacitor, a second plate of the second capacitor being electrically connected to an input terminal of the ninth inverter and an output terminal of the second wake-up unit; or when the first wake-up unit comprises the first wake-up subunit, the first feedback circuit comprises, the twelfth resistor, a first end of which receives the ground potential; the thirty-eighth transistor, a drain electrode of which is electrically connected to the input terminal of the seventh Schmitt trigger, a source electrode of which is electrically connected to the first end of the twelfth resistor, and a gate electrode of which is electrically connected to the second end of the twelfth resistor and the first plate of the second capacitor; the second capacitor, a second plate of which is electrically connected to the output terminal of the second wake-up unit; or when the first wake-up unit comprises the second wake-up subunit, the first feedback circuit comprises, the twelfth resistor, a first end of which receives the ground potential; a thirty-seventh transistor, a drain electrode of which is electrically connected to an input terminal of the eighth Schmitt trigger, and a source electrode of which is electrically connected to a power supply; an eleventh resistor, one end of which is electrically connected to the power supply, and the other end of which is electrically connected to a gate electrode of the thirty-seventh transistor; a first capacitor, a first plate of which is electrically connected to the gate electrode of the thirty-seventh transistor; a ninth inverter, an input terminal of which is electrically connected to an output terminal of the second wake-up unit, and an output terminal of which is electrically connected to a second plate of the first capacitor.

13. The wake-up circuit according to claim 11, wherein when the second wake-up unit includes a third wake-up sub-unit and a fourth wake-up sub-unit, the second feedback circuit includes, a thirty-ninth transistor, a drain electrode of which is electrically connected to an input terminal of the tenth Schmitt trigger, and a source electrode of which is electrically connected to a power supply; a thirteenth resistor, one end of which is electrically connected to the power supply, and the other end of which is electrically connected to a gate electrode of the thirty-ninth transistor; a third capacitor, a first plate of which is electrically connected to the gate electrode of the thirty-ninth transistor; a tenth inverter, an input terminal of which is electrically connected to an output terminal of the first wake-up unit, and an output terminal of which is electrically connected to a second plate of the third capacitor; a fortieth transistor, a drain electrode of which is electrically connected to an input terminal of the ninth Schmitt trigger, a source electrode of which is electrically connected to a first end of a fourteenth resistor, and which receives a ground potential, and a gate electrode of which is electrically connected to a second end of the fourteenth resistor and a first plate of a fourth capacitor, a second plate of the fourth capacitor being electrically connected to an input terminal of the tenth inverter and an output terminal of the first wake-up unit; or when the second wake-up unit includes a third wake-up sub-unit, the second feedback circuit includes, a fourteenth resistor, a first end of which receives a ground potential; a fortieth transistor, a drain electrode of which is electrically connected to an input terminal of the ninth Schmitt trigger, a source electrode of which is electrically connected to a first end of a fourteenth resistor, and a gate electrode of which is electrically connected to a second end of the fourteenth resistor and a first plate of a fourth capacitor; a fourth capacitor, a second plate of which is electrically connected to an output terminal of the first wake-up unit; or when the second wake-up unit includes a fourth wake-up sub-unit, the second feedback circuit includes, a thirty-ninth transistor, a drain electrode of which is electrically connected to an input terminal of the tenth Schmitt trigger, and a source electrode of which is electrically connected to a power supply; a thirteenth resistor, one end of which is electrically connected to the power supply, and the other end of which is electrically connected to a gate electrode of the thirty-ninth transistor; a third capacitor, a first plate of which is electrically connected to the gate electrode of the thirty-ninth transistor; a tenth inverter, an input terminal of which is electrically connected to an output terminal of the first wake-up unit, and an output terminal of which is electrically connected to a second plate of the third capacitor.

14. The wake-up circuit according to claim 9, wherein the seventh super-cut-off stack structure, includes, a forty-first transistor and a forty-second transistor connected in series with each other, wherein a drain electrode of the forty-second transistor is electrically connected to a first end of a seventh resistor or a seventh current source, a source electrode of the forty-second transistor is electrically connected to a source electrode of the forty-first transistor, the forty-first transistor is an N-type transistor, and the forty-second transistor is a P-type transistor; and / or the eighth super-cut-off stack structure, includes, a forty-third transistor and a forty-fourth transistor connected in series with each other, wherein a drain electrode of the forty-third transistor is electrically connected to a first terminal of an eighth resistor or an eighth current source, a source electrode of the forty-third transistor is electrically connected to a source electrode of the forty-fourth transistor, the forty-third transistor is an N-type transistor, and the forty-fourth transistor is a P-type transistor; and / or the ninth over-barrier stack structure, comprises, a forty-fifth transistor and a forty-sixth transistor connected in series with each other, wherein a drain electrode of the forty-sixth transistor is electrically connected to a first terminal of a ninth resistor or a ninth current source, a source electrode of the forty-sixth transistor is electrically connected to a source electrode of the forty-fifth transistor, the forty-fifth transistor is an N-type transistor, and the forty-sixth transistor is a P-type transistor; and / or the tenth over-barrier stack structure, comprises, a forty-seventh transistor and a forty-eighth transistor connected in series with each other, wherein a drain electrode of the forty-seventh transistor is electrically connected to a first terminal of a tenth resistor or a tenth current source, a source electrode of the forty-seventh transistor is electrically connected to a source electrode of the forty-eighth transistor, the forty-seventh transistor is an N-type transistor, and the forty-eighth transistor is a P-type transistor; wherein gate electrodes of the forty-first transistor, the forty-third transistor, the forty-sixth transistor and the forty-eighth transistor serve as a first signal input end, and gate electrodes of the forty-second transistor, the forty-fourth transistor, the forty-fifth transistor and the forty-seventh transistor serve as a second signal input end.

15. The wake-up receiver circuit of claim 10, wherein the seventh Schmitt trigger comprises, a forty-ninth transistor, a fiftieth transistor and a fifty-first transistor connected together at gate electrodes as an input end of the seventh Schmitt trigger, wherein a source electrode of the forty-ninth transistor is electrically connected to a power supply, a source electrode of the fifty-first transistor is grounded, a drain electrode of the forty-ninth transistor is electrically connected to a source electrode of the fiftieth transistor, a drain electrode of the fiftieth transistor is electrically connected to a drain electrode of the fifty-first transistor, a drain electrode of a fifty-second transistor is grounded, a source electrode of the fifty-second transistor is electrically connected to the drain electrode of the forty-ninth transistor, a gate electrode of the fifty-second transistor is electrically connected to the drain electrode of the fiftieth transistor and the drain electrode of the fifty-first transistor as an output end of the seventh Schmitt trigger, wherein a type of the fifty-first transistor is complementary to the forty-ninth transistor, the fiftieth transistor and the fifty-second transistor, and a width-length ratio of the fifty-first transistor is greater than width-length ratios of other transistors of the seventh Schmitt trigger; and / or The eighth Schmitt trigger comprises a fifty-third transistor, a fifty-fourth transistor, and a fifty-fifth transistor whose gates are electrically connected together as an input terminal of the eighth Schmitt trigger, wherein a source electrode of the fifty-third transistor is electrically connected to a power supply, a source electrode of the fifty-fifth transistor is grounded, a drain electrode of the fifty-fifth transistor is electrically connected to a source electrode of the fifty-fourth transistor, a drain electrode of the fifty-third transistor is electrically connected to a drain electrode of the fifty-fourth transistor, a drain electrode of a fifty-sixth transistor is connected to the power supply, and a source electrode of the fifty-sixth transistor is electrically connected to the source electrode of the fifty-fourth transistor, a gate electrode of the fifty-sixth transistor is electrically connected to the drain electrode of the fifty-third transistor and the drain electrode of the fifty-fourth transistor, and serves as an output terminal of the eighth Schmitt trigger, wherein the type of the fifty-third transistor is complementary to the fifty-fourth transistor, the fifty-fifth transistor, and the fifty-sixth transistor, and the width-length ratio of the fifty-third transistor is greater than the width-length ratio of other transistors of the eighth Schmitt trigger.

16. The wake-up receiver circuit of claim 11, wherein, The ninth Schmitt trigger comprises a fifty-seventh transistor, a fifty-eighth transistor, and a fifty-ninth transistor whose gates are electrically connected together as an input terminal of the ninth Schmitt trigger, wherein a source electrode of the fifty-seventh transistor is electrically connected to a power supply, a source electrode of the fifty-ninth transistor is grounded, a drain electrode of the fifty-seventh transistor is electrically connected to a source electrode of the fifty-eighth transistor, a drain electrode of the fifty-eighth transistor is electrically connected to a drain electrode of the fifty-ninth transistor, a drain electrode of a sixtieth transistor is grounded, and a source electrode of the sixtieth transistor is electrically connected to the drain electrode of the fifty-seventh transistor, a gate electrode of the sixtieth transistor is electrically connected to the drain electrode of the fifty-eighth transistor and the drain electrode of the fifty-ninth transistor, and serves as an output terminal of the ninth Schmitt trigger, wherein the type of the fifty-ninth transistor is complementary to the fifty-seventh transistor, the fifty-eighth transistor, and the sixtieth transistor, and the width-length ratio of the fifty-ninth transistor is greater than the width-length ratio of other transistors of the ninth Schmitt trigger; and / or, The tenth Schmitt trigger comprises: sixty-first, sixty-second and sixty-third transistors with gates electrically connected together as an input terminal of the tenth Schmitt trigger, wherein a source electrode of the sixty-first transistor is electrically connected to a power supply, a source electrode of the sixty-third transistor is grounded, a drain electrode of the sixty-third transistor is electrically connected to a source electrode of the sixty-second transistor, a drain electrode of the sixty-first transistor is electrically connected to a drain electrode of the sixty-second transistor, a drain electrode of a sixty-fourth transistor is connected to the power supply, a source electrode of the sixty-fourth transistor is electrically connected to the source electrode of the sixty-second transistor, and a gate electrode of the sixty-fourth transistor is electrically connected to the drain electrode of the sixty-first transistor and the drain electrode of the sixty-second transistor, and serves as an output terminal of the tenth Schmitt trigger; wherein the sixty-first transistor is complementary to the sixty-second, sixty-third and sixty-fourth transistors, and a width-length ratio of the sixty-first transistor is greater than width-length ratios of other transistors of the tenth Schmitt trigger.

17. An electronic device comprising the wake-up circuit of any one of claims 1-16.

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