Printed circuit board and automatic driving area controller

Abstract

The embodiment of the invention provides a printed circuit board and an automatic driving domain controller, and relates to the technical field of printed circuits. The printed circuit board is applied to the automatic driving domain controller and comprises a plurality of conducting layers, the conducting layers comprise at least one first signal layer, at least one second signal layer, at least one power supply layer and at least one ground layer, and the signal transmission rate of the second signal layer is larger than or equal to the signal transmission rate of the first signal layer. The plurality of conductive layers are stacked together to form a laminated layer; the laminated layer comprises an inner layer, two middle layers stacked on the two sides of the inner layer, and surface layers stacked on the outer sides of the middle layers; wherein the at least one power supply layer is stacked on the inner layer, and the ground layers are stacked on the two sides of the at least one power supply layer; any middle layer comprises at least one second signal layer and at least one ground layer, and the second signal layers and the ground layers are stacked at intervals; the first signal layer is stacked outside the intermediate layer to form a surface layer. The printed circuit board is high in signal integrity and power supply integrity.

Description

Technical Field

[0001] The present application relates to the field of printed circuit technology, and in particular to a printed circuit board and an autonomous driving domain controller. Background Art

[0002] The autonomous driving domain controller is one of the core components that enables a vehicle's autonomous driving capabilities. It processes large amounts of data from onboard sensors, which are used to perceive the vehicle's surroundings and make autonomous driving decisions.

[0003] An autonomous driving domain controller typically consists of dedicated hardware and a software platform. The dedicated hardware is the hardware foundation of the software platform. The dedicated hardware typically includes a variety of electronic components and the printed circuit board (PCB) that carries these components.

[0004] The high-performance computing and high-speed data communication requirements of autonomous driving domain controllers require their printed circuit boards to have high signal integrity and power integrity. However, existing PCBs, due to structural design and other factors, have low signal integrity and power integrity, which cannot meet the requirements of autonomous driving domain controllers. Summary of the Invention

[0005] An embodiment of the present application provides a printed circuit board and an autonomous driving domain controller. The printed circuit board is configured according to the high-performance computing and high-speed data communication characteristics of the autonomous driving domain controller, and can achieve high signal integrity and power integrity, thereby meeting the requirements of the autonomous driving domain controller.

[0006] In a first aspect, an embodiment of the present application provides a printed circuit board, which is applied to an autonomous driving domain controller and includes multiple conductive layers, wherein the multiple conductive layers include at least one first signal layer, at least one second signal layer, at least one power supply layer and at least one ground layer. The signal transmission rate of the second signal layer is greater than or equal to the signal transmission rate of the first signal layer, and the multiple conductive layers are stacked together to form a stack; the stack includes an inner layer, two middle layers stacked on both sides of the inner layer, and a surface layer stacked on the outside of the middle layer; wherein at least one power supply layer is stacked on the inner layer, and a ground layer is stacked on both sides of at least one power supply layer; any middle layer includes at least one second signal layer and at least one ground layer, and the second signal layer and the ground layer are stacked alternately; the first signal layer is stacked on the outside of the middle layer to form a surface layer.

[0007] In a possible implementation, the inner layer includes two stacked power layers and two ground layers stacked outside the two power layers.

[0008] In a possible implementation, any middle layer includes two second signal layers and two ground layers, and one of the second signal layers is stacked close to the inner layer.

[0009] In one possible embodiment, the printed circuit board includes fourteen conductive layers, and the two surface layers of the stack are respectively a top layer and a bottom layer; from the top layer to the bottom layer, the fourteen conductive layers are stacked as the 1st to 14th layers of the stack, namely: the first signal layer of the 1st layer, the ground layer of the 2nd layer, the second signal layer of the 3rd layer, the ground layer of the 4th layer, the second signal layer of the 5th layer, the ground layer of the 6th layer, the power layer of the 7th layer, the power layer of the 8th layer, the ground layer of the 9th layer, the second signal layer of the 10th layer, the ground layer of the 11th layer, the second signal layer of the 12th layer, the ground layer of the 13th layer and the first signal layer of the 14th layer.

[0010] In one possible implementation, second-order blind buried vias are used between the first signal layer of the first layer and the ground layer of the second layer, between the ground layer of the second layer and the second signal layer of the third layer, between the second signal layer of the third layer and the second signal layer of the 12th layer, between the second signal layer of the 12th layer and the ground layer of the 13th layer, and between the ground layer of the 13th layer and the first signal layer of the 14th layer.

[0011] In a possible implementation manner, at least one conductive layer uses reverse-processed copper foil.

[0012] In a possible implementation, the surface of the surface layer is covered with R500 Z28DF solder resist ink to form a solder resist layer of the printed circuit board.

[0013] In a possible implementation, at least one insulating layer is stacked between any two conductive layers in the stack, and the insulating layer is used to support and insulate the conductive layers stacked therewith. The material of the at least one insulating layer is NPG-170N.

[0014] In a possible implementation, the insulating layer between the second signal layer and the ground layer, and / or the insulating layer between the first signal layer and the ground layer, is made of a flat semi-cured epoxy resin sheet.

[0015] In a second aspect, an embodiment of the present application provides an autonomous driving domain controller, which includes: at least one processor and a printed circuit board as described in the first aspect and / or various possible implementations of the first aspect above, wherein the processor is arranged on the printed circuit board, and the processor is used to execute computer execution instructions to achieve autonomous driving.

[0016] Embodiments of the present application provide a printed circuit board and an autonomous driving domain controller. The printed circuit board is used in an autonomous driving domain controller. The printed circuit board comprises a stacked layer comprising an inner layer, an intermediate layer, and a surface layer. The stacked layer structure is similar to an inner layer located within the core, two intermediate layers stacked on either side of the inner layer to encapsulate the inner layer, and the surface layer stacked on the outside of the intermediate layer. By stacking the ground layer on either side of the power layer to form the inner layer, the power layer is essentially built into the printed circuit board. The second signal layer has a higher transmission rate, making it a conductive layer for transmitting high-speed signals. The intermediate layer configuration provides for high-speed signal transmission, meeting the high-speed signal transmission requirements of the autonomous driving domain controller. By integrating the power layer into the core and stacking the two intermediate layers on either side of the inner layer, the power supply impedance is reduced by shortening the power path and increasing the area of ​​the power layer, providing a more stable voltage and reducing power supply noise and voltage fluctuations. Furthermore, the entire power layer located within the inner layer distributes current more evenly, reducing voltage drop and current congestion in the power distribution network and improving power integrity. In addition, the ground layer in the inner layer is equivalent to wrapping the power layer and stacking, so a capacitance effect can be formed between the ground layers to help filter out the high-frequency noise of the power layer and suppress the impact of power noise on signal transmission. The inner layer can also form a good reference plane, reduce the signal loop area, help reduce electromagnetic interference and electromagnetic radiation, and improve the signal integrity of high-speed signal transmission in the middle layer. Furthermore, the ground layer wraps the power layer and is placed as a whole in the inner layer, providing a good reference plane that can improve the characteristic impedance control of the signal transmission path and reduce signal reflection and crosstalk; at the same time, the second signal layer and the ground layer in the middle layer are stacked at intervals, which also helps to accurately control the characteristic impedance of the signal line and reduce signal reflection and distortion. In addition, the structure of the middle layer wrapping the inner layer is also conducive to the wiring of differential signal pairs, providing better common-mode noise suppression and signal integrity. Therefore, the printed circuit board of the present application, due to the above-mentioned structural setting, can achieve high signal integrity and power integrity of the printed circuit board, meeting the requirements of the autonomous driving domain controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of an autonomous driving domain controller provided in an embodiment of the present application;

[0019] Figure 2 Schematic diagram of a printed circuit board provided in an embodiment of the present application Figure 1 ;

[0020] Figure 3 Schematic diagram of a printed circuit board provided in an embodiment of the present application Figure 2;

[0021] Figure 4 A schematic diagram of a process for constructing a printed circuit board stack provided in an embodiment of the present application;

[0022] Figure 5 A schematic diagram of ports of a printed circuit board provided in an embodiment of the present application;

[0023] Figure 6 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 1 ;

[0024] Figure 7 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 2 ;

[0025] Figure 8 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 3 ;

[0026] Figure 9 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 4 ;

[0027] Figure 10 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 5 .

[0028] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0029] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0030] In the technical solutions of the embodiments of this application, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0031] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0032] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0033] In the embodiments of this application, if words such as "first" and "second" are used, they are intended to distinguish between identical or similar items with substantially the same functions and effects. For example, the first electronic device and the second electronic device are merely used to distinguish between different electronic devices and do not limit the order of precedence. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity or execution order, and words such as "first" and "second" do not necessarily mean that they are different.

[0034] In the embodiments of this application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0035] An autonomous driving domain controller (ADC) is a high-performance computing platform designed specifically for autonomous vehicles and autonomous aircraft. It plays a central role in autonomous driving systems, primarily responsible for processing and managing sensor data from autonomous devices, performing complex computing tasks, and controlling the device's behavior.

[0036] The autonomous driving domain controller includes a printed circuit board (PCB), which is primarily used to carry electronic components and provide electrical connections for them. Because the autonomous driving domain controller needs to process large amounts of data collected by sensors from multiple sources, it has high computing performance requirements. Due to the complexity and timeliness of autonomous driving, the autonomous driving domain controller also has high requirements for data communication speeds. Due to the high-performance computing and high-speed data communication characteristics of the autonomous driving domain controller, the PCB board of the autonomous driving domain controller must have high signal integrity and power integrity.

[0037] Some existing PCB boards are not designed for autonomous driving domain controllers, so these PCB boards are incompatible with autonomous driving domain controllers and cannot be used directly; some are designed for autonomous driving domain controllers, but these PCB boards have structural defects, resulting in low signal integrity and power integrity, which cannot meet the requirements of autonomous driving domain controllers.

[0038] For example, the signal integrity of some autonomous driving domain controller PCB boards is low, and they cannot simultaneously meet the high-speed data communication requirements of the high-speed interface standard (Peripheral Component Interconnect Express 4.0, PCIE4.0), the 10 Gigabit Ethernet interface standard (10Gigabit Attachment Unit Interface, XFI) and the high-speed universal serial bus (Universal Serial Bus, USB) (such as USB3.0), and do not meet the specification (SPEC) requirements in software engineering.

[0039] For example, some autonomous driving domain controller PCBs have low power integrity and fail to meet SPEC requirements for power ripple and noise. For example, SPEC requires that when the supply voltage is P12V (12 volts), the voltage drop generated by the PCB board should be within ±5% of the P12V specified voltage drop. Another example is SPEC requirements for the input voltages required by multiple sub-power modules, such as 0.7V, 1.2V, 1.8V, 3.3V, and 5V.

[0040] In view of this, an embodiment of the present application provides a printed circuit board for use in an autonomous driving domain controller. The printed circuit board comprises a stacked layer comprising an inner layer, an intermediate layer, and a surface layer. The stacked layer structure is equivalent to an inner layer within the core, two intermediate layers stacked on either side of the inner layer to enclose the inner layer, and the surface layer stacked on the outside of the intermediate layer. By stacking the ground layer on either side of the power layer to form the inner layer within the stack, the power layer is essentially built into the printed circuit board. The second signal layer has a higher transmission rate, making it a conductive layer for transmitting high-speed signals. The intermediate layer configuration provides the necessary conditions for high-speed signal transmission, meeting the high-speed signal transmission requirements of the autonomous driving domain controller. By building the power layer into the core and stacking the two intermediate layers on either side of the inner layer, the power supply impedance is reduced by shortening the power path length and increasing the power layer area, providing a more stable voltage and reducing power supply noise and voltage fluctuations. Furthermore, the entire power layer within the inner layer distributes current more evenly, reducing voltage drop and current congestion in the power distribution network, and improving power integrity. In addition, the ground layer in the inner layer is equivalent to wrapping the power layer and stacking, so a capacitance effect can be formed between the ground layers to help filter out the high-frequency noise of the power layer and suppress the impact of power noise on signal transmission. The inner layer can also form a good reference plane, reduce the signal loop area, help reduce electromagnetic interference and electromagnetic radiation, and improve the signal integrity of high-speed signal transmission in the middle layer. Furthermore, the ground layer wraps the power layer and is placed as a whole in the inner layer, providing a good reference plane that can improve the characteristic impedance control of the signal transmission path and reduce signal reflection and crosstalk; at the same time, the second signal layer and the ground layer in the middle layer are stacked at intervals, which also helps to accurately control the characteristic impedance of the signal line and reduce signal reflection and distortion. In addition, the structure of the middle layer wrapping the inner layer is also conducive to the wiring of differential signal pairs, providing better common-mode noise suppression and signal integrity. Therefore, the printed circuit board of the present application, due to the above-mentioned structural setting, can achieve high signal integrity and power integrity of the printed circuit board, meeting the requirements of the autonomous driving domain controller.

[0041] The technical solutions of the present application are described in detail below with reference to specific embodiments. The specific embodiments below may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0042] Figure 1 A schematic diagram of an autonomous driving domain controller provided in an embodiment of the present application is shown as follows: Figure 1As shown, the autonomous driving domain controller provided in the embodiment of the present application includes a printed circuit board (PCB), and multiple system-on-chips (SOCs) arranged on the PCB board. The system-on-chip can be understood as a processor or processing unit. Among them, the SOC may include components such as a central processing unit (CPU), a graphics processing unit (GPU) and / or a data processing unit (DPU). The PCB board of the autonomous driving domain controller is also provided with a power module (Power) and at least one connector (CON). The connector CON can be connected to a variety of devices. For example, the connector CON can be connected to a storage device such as a solid-state drive (SSD) through a cable (Cable). When establishing the connection, the interface protocol (Non-Volatile Memory Express, NVMe) can be executed, which can fully utilize the high-speed capability of the PCIe bus. The NVMe protocol provides higher performance and lower latency, and is suitable for applications that require fast data access, meeting the high-performance computing requirements of the autonomous driving domain controller.

[0043] For example, Figure 1 As shown, the autonomous driving domain controller can include four SOCs: SOC0, SOC1, SOC2, and SOC3. Any two of these SOCs can communicate with each other based on PCIE 4.0 and / or XFI. If SOC2 is the primary processing unit and SOC3 is the auxiliary processing unit, SOC0 can be used as a backup chip for SOC2, and SOC1 can be used as a backup chip for SOC3. SOC2 can connect to CON based on PCIE 4.0 to connect to external devices. The power module Power can provide P12V voltage level power to the SOC. SOC2 can process data input from devices such as image sensors, millimeter wave radar sensors, storage devices, and USB 3.0 interface devices; SOC3 can also process data input from image sensors, lidar sensors, and other devices. In addition to the SOC chip, other devices such as switch chips can also be set on the PCB board.

[0044] Figure 2 Schematic diagram of a printed circuit board provided in an embodiment of the present application Figure 1 ,This PCB is applied to autonomous driving domain controller, such as Figure 2As shown, the printed circuit board includes multiple conductive layers, the multiple conductive layers include at least one first signal layer, at least one second signal layer, at least one power layer and at least one ground layer, the signal transmission rate of the second signal layer is greater than or equal to the signal transmission rate of the first signal layer, and the multiple conductive layers are stacked together to form a stack; the stack includes an inner layer, two middle layers stacked on both sides of the inner layer, and a surface layer stacked on the outside of the middle layer; wherein, at least one power layer is stacked on the inner layer, and ground layers are stacked on both sides of at least one power layer; any middle layer includes at least one second signal layer and at least one ground layer, and the second signal layer and the ground layer are stacked at intervals; the first signal layer is stacked on the outside of the middle layer to form a surface layer.

[0045] For example, a conductive layer is a copper foil layer used for conducting electricity. This conductive layer forms a circuit path, thereby achieving electrical connections between the various electronic components installed on the PCB. Different conductive layers can be divided into signal layers, power layers, and ground layers based on their different functions.

[0046] The signal layer can be used to arrange signal routing and transmit electrical signals. In the embodiment of the present application, the signal layer can be divided into a first signal layer and a second signal layer according to the size of the signal transmission rate, wherein the signal transmission rate of the second signal layer is greater than or equal to the signal transmission rate of the first signal layer, then the second signal layer can be understood as a high-speed signal layer, and the first signal layer can be understood as a normal signal layer or a low-speed signal layer. For example, the signal transmission rate of the second signal layer can reach 10Mbps (megabits per second) or 100Mbps (megabits per second) or above.

[0047] The power plane distributes the supply voltage and transmits electrical energy. It can be a large copper layer that provides a stable supply voltage and minimizes voltage drop. The ground plane provides a common ground point for the circuit. The ground plane can be a solid copper surface, providing a low-impedance ground path to help reduce electromagnetic interference (EMI) and signal noise.

[0048] When obtaining the printed circuit board provided in the embodiments of the present application, multiple conductive layers are stacked together to form a laminate. It should be understood that when stacking the conductive layers, at least one insulating layer is stacked between any two conductive layers to provide support and insulation for the two conductive layers.

[0049] The stacked layers include an inner layer, two middle layers stacked on both sides of the inner layer, and a surface layer stacked outside the middle layer. Figure 2 As shown, the inner layer is in the inner core of the stack, two middle layers are stacked on both sides of the inner layer to wrap the inner layer, and the surface layer is stacked on the outside of the middle layer.

[0050] In the inner layer, the ground plane is stacked on both sides of the power layer, which is equivalent to the ground layer wrapping all power layers. This creates a capacitance effect between the ground layers, which helps filter out high-frequency noise from the power layer and suppresses the impact of power noise on signal transmission. Furthermore, this inner layer forms a good reference plane, reducing the signal loop area, helping to reduce electromagnetic interference and electromagnetic radiation. Furthermore, the power layer is located in the inner core of the PCB, which can more evenly distribute current, reduce voltage drop and current congestion in the power distribution network, and improve power integrity.

[0051] In one possible implementation, the inner layer includes two stacked power layers and two ground layers stacked outside the two power layers. Thus, with two power layers in the inner layer, the two power layers are close to the middle layer on either side. This structure can reduce the length of the power path between the power layer and the middle layer, thereby reducing power impedance and improving power integrity. Furthermore, this structure can optimize signal paths, reduce unnecessary vias, reduce signal delay and distortion, and improve the speed and quality of signal transmission.

[0052] For example, stacking two intermediate layers on both sides of the inner layer can reduce the power supply impedance by shortening the power path length and increasing the area of ​​the power layer, providing a more stable power supply for the entire PCB board. Since the ground layer and the second signal layer are spaced apart, the ground layer can wrap around both sides of the second signal layer, which can reduce the high-frequency noise of the signal. The stacking of the second signal layer and the ground layer in the intermediate layer also helps to accurately control the characteristic impedance of the signal line and reduce signal reflection and distortion. The structure of the intermediate layer wrapping the inner layer is also conducive to the routing of differential signal pairs, providing better common-mode noise suppression and signal integrity.

[0053] In one possible implementation, the middle layer includes two second signal layers and two ground layers, with one of the second signal layers stacked close to the inner layer. This allows the middle layer to provide two second signal layers for high-speed signal transmission, and one of the second signal layers is stacked close to the inner layer. The inner ground layer can then be used to envelop both second signal layers in the middle layer. This reduces electromagnetic interference and electromagnetic radiation during signal transmission on the second signal layer, further improving signal integrity.

[0054] A printed circuit board (PCB) provided in an embodiment of the present application is used in an autonomous driving domain controller. The PCB comprises a stacked layer comprising an inner layer, an intermediate layer, and a surface layer. The stacked layer structure is similar to an inner core, with two intermediate layers stacked on either side of the inner layer, encapsulating the inner layer, and the surface layer stacked on the outside of the intermediate layer. By stacking the ground layer on either side of the power layer to form the inner layer, the entire power layer is built into the printed circuit board. The second signal layer has a higher transmission rate, making it a conductive layer for transmitting high-speed signals. The intermediate layer configuration provides the necessary conditions for high-speed signal transmission, meeting the high-speed signal transmission requirements of the autonomous driving domain controller. By building the power layer into the inner core and stacking the two intermediate layers on either side of the inner layer, the power supply impedance is reduced by shortening the power path and increasing the area of ​​the power layer, providing a more stable voltage and reducing power supply noise and voltage fluctuations. Furthermore, the entire power layer is located in the inner layer, which distributes current more evenly, reduces voltage drop and current congestion in the power distribution network, and improves power integrity. In addition, the ground layer in the inner layer is equivalent to wrapping the power layer and stacking, so a capacitance effect can be formed between the ground layers to help filter out the high-frequency noise of the power layer and suppress the impact of power noise on signal transmission. The inner layer can also form a good reference plane, reduce the signal loop area, help reduce electromagnetic interference and electromagnetic radiation, and improve the signal integrity of high-speed signal transmission in the middle layer. Furthermore, the ground layer wraps the power layer and is placed as a whole in the inner layer, providing a good reference plane that can improve the characteristic impedance control of the signal transmission path and reduce signal reflection and crosstalk; at the same time, the second signal layer and the ground layer in the middle layer are stacked at intervals, which also helps to accurately control the characteristic impedance of the signal line and reduce signal reflection and distortion. In addition, the structure of the middle layer wrapping the inner layer is also conducive to the wiring of differential signal pairs, providing better common-mode noise suppression and signal integrity. Therefore, the printed circuit board of the present application, due to the above-mentioned structural setting, can achieve high signal integrity and power integrity of the printed circuit board, meeting the requirements of the autonomous driving domain controller.

[0055] In one possible implementation, the printed circuit board includes fourteen conductive layers, and the two surface layers of the stack are a top layer and a bottom layer respectively; from the top layer to the bottom layer, the fourteen conductive layers are stacked as the 1st to 14th layers of the stack, namely: the first signal layer of the 1st layer, the ground layer of the 2nd layer, the second signal layer of the 3rd layer, the ground layer of the 4th layer, the second signal layer of the 5th layer, the ground layer of the 6th layer, the power layer of the 7th layer, the power layer of the 8th layer, the ground layer of the 9th layer, the second signal layer of the 10th layer, the ground layer of the 11th layer, the second signal layer of the 12th layer, the ground layer of the 13th layer and the first signal layer of the 14th layer.

[0056] Figure 3 Schematic diagram of a printed circuit board provided in an embodiment of the present application Figure 2 ,like Figure 3As shown, the stack formed by stacking 14 conductive layers can be represented as: the first signal layer of the first layer, namely Layer 1; the ground layer of the second layer, namely Layer 2; the second signal layer of the third layer, namely Layer 3; the ground layer of the fourth layer, namely Layer 4; the second signal layer of the fifth layer, namely Layer 5; the ground layer of the sixth layer, namely Layer 6; the power layer of the seventh layer, namely Layer 7; the power layer of the eighth layer, namely Layer 8; the ground layer of the ninth layer, namely Layer 9; the second signal layer of the tenth layer, namely Layer 10; the ground layer of the eleventh layer, namely Layer 11; the second signal layer of the twelfth layer, namely Layer 12; the ground layer of the thirteenth layer, namely Layer 13; and the first signal layer of the fourteenth layer, namely Layer 14.

[0057] In one possible implementation, Figure 3 In the PCB stackup shown, layers 1 to 14 meet the parameters shown in Table 1 below.

[0058] Table 1 is the stacking parameter table of the PCB board

[0059]

[0060]

[0061]

[0062]

[0063] As shown in Table 1, Layer 1 is the first signal layer, Layer 1, which is also the top layer of the PCB board and is used to transmit low-speed signals (for example, less than 10 Mbps). The thickness of Layer 1 is 1.40 mil (one thousandth of an inch).

[0064] Layers 1, 2, 3, 6, 7, 8, 9, 12, 13, and 14 use 1oz copper foil, with 1 / 3oz starting copper for Layers 1, 3, 12, and 14. Layers 4, 5, 10, and 11 use 0.5oz copper foil. The board thickness of this PCB is 72.3 mils, and the board thickness is 1.84 mm.

[0065] In a possible implementation, at least one conductive layer uses reverse treated copper foil (RTF).

[0066] For example, as shown in Table 1, Layers 2 through 13 can all use RTF copper foil. RTF copper foil is an electrolytic copper foil with varying degrees of roughening on both sides. Its characteristic is that it reverses the rough and smooth surfaces of traditional electrolytic copper foil and enhances the smooth surface, thereby optimizing adhesion and etching performance during circuit board manufacturing.

[0067] Using RTF copper foil for the conductive layer can reduce surface roughness. A low-roughness surface helps reduce the skin effect and associated signal loss during high-frequency signal transmission, thereby improving the signal integrity of the PCB board. RTF copper foil can be divided into RTF1 (Rz ≤ 3.5μm), RTF2 (Rz ≤ 2.3μm), and RTF3 (Rz ≤ 2.1μm) according to surface roughness. For the conductive layer, RTF copper foil with a lower surface roughness, for example, RTF1, can be used.

[0068] Based on this, at least one conductive layer uses reverse-processed copper foil, which can reduce the skin effect of the conductive layer, increase the rate and signal quality of high-speed signal transmission, and further improve the signal integrity and power integrity of the printed circuit board.

[0069] In one possible implementation, second-order blind buried vias are used between the first signal layer of the first layer and the ground layer of the second layer, between the ground layer of the second layer and the second signal layer of the third layer, between the second signal layer of the third layer and the second signal layer of the 12th layer, between the second signal layer of the 12th layer and the ground layer of the 13th layer, and between the ground layer of the 13th layer and the first signal layer of the 14th layer.

[0070] For example, second-order blind buried vias are a connection process used to achieve high-density interconnection, which can establish electrical connections between different layers without having to penetrate the entire PCB board. In second-order blind buried vias, blind vias refer to holes drilled from the surface layer of the PCB board, but do not penetrate the entire PCB board, but are only connected to a certain internal layer. Buried vias are holes that are completely located inside the PCB board, are not connected to the surface layer, and can be used to connect two or more internal layers. Second-order blind buried vias can achieve higher circuit density in a limited space, reduce signal path length, and improve signal integrity. In addition, second-order blind buried vias can also provide more design freedom and are suitable for complex PCB board designs.

[0071] For the PCB board in the embodiment of the present application, Layer1-Layer2, Layer2-Layer3, Layer3-Layer12, Layer12-Layer13, and Layer13-Layer14 are connections between the signal layer and the ground layer, or between the signal layer and the signal layer. By adopting second-order blind and buried vias, blind or buried vias can be realized between the first signal layer, the second signal layer, and any two layers in the ground layer, which can achieve higher circuit density in a limited space, reduce the signal path length, reduce signal energy reflection, reduce the average impedance of the printed circuit board, and further improve the signal integrity of the printed circuit board.

[0072] For example, as shown in Table 1, Layer 7 and Layer 8 are both power layers. Layer 2, Layer 4, Layer 6, Layer 9, Layer 11, and Layer 13 are all ground layers. All high-speed signals go through Layer 3, Layer 5, Layer 10, and Layer 12. This structure allows the ground layers to wrap around both sides of the two power layers, shielding the interference of the power layers on signal transmission through the ground layers, thereby suppressing crosstalk and power supply noise generated by EMI. In addition, ground layers are stacked on both sides of each second signal layer, which can shield the radiation of the high-speed signal of the second signal layer. When the differential mode is converted to common mode, the signal can be returned through the ground layer, making the common mode as small as possible. The energy field of the signal can be shielded by the ground layer, thereby reducing the signal propagation path and preventing crosstalk.

[0073] PCBs used in autonomous driving domain controllers not only require high signal integrity and power integrity, but also have certain physical properties such as material stability, high temperature resistance, thermal expansion, and water absorption. For example, material stability requires the PCB to have good anti-vibration performance and low dielectric constant (DK) / dielectric constant (DF) loss; high temperature resistance requires the PCB to withstand temperatures of at least 170 degrees Celsius; and the thermal expansion coefficient requires that the PCB expand in the vertical direction (Z-axis) to be less than 30ppm / degree Celsius.

[0074] To simultaneously meet the high signal integrity, power integrity, and physical property requirements of autonomous driving domain controller PCBs, this embodiment of the present application provides a printed circuit board (PCB) stacking method for rapidly evaluating performance across these dimensions and designing a PCB that meets these requirements. This PCB stacking method can reduce the risk of developing both PCBs and autonomous driving domain controllers, shorten development cycles, and lower development costs.

[0075] Figure 4 A schematic diagram of a process for constructing a printed circuit board stack provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, when building a printed circuit board stackup, this can be achieved through the following steps:

[0076] S1. Confirm the project's requirements for PCB stackup. S2. Preliminarily determine the PCB insulation layer material, PCB process, and PCB conductive layer material based on the requirements. S3. Stack the PCB stackup to obtain the initial PCB stackup. S4. Determine whether the initial PCB stackup meets the signal integrity requirements through loss and impedance calculations based on signal integrity theory. S5. Determine whether the power ripple noise (including DC and AC) of the initial PCB stackup meets the power integrity requirements based on power integrity theory. S6. Complete the PCB stackup construction when the signal integrity, power integrity, and physical property requirements of the PCB board are all met.

[0077] If step S4 does not meet the requirements, the process returns to step S3 to analyze the cause and determine whether there is a stacking issue. The stacking is then redesigned until the requirements are met. If not, the process returns to step S2 to adjust the PCB insulation layer material, PCB process, and / or PCB conductive layer material until the requirements of step S4 are met. Step S5 is similar to step S4. If the requirements are not met, the process returns to step S3 or step S2 for further adjustments until the requirements of step S5 are met.

[0078] When adjusting the PCB insulation layer material, for example, the dielectric constant DK / dielectric constant DF can be adjusted. Alternatively, when adjusting the PCB process, for example, the via type can be adjusted. Alternatively, when adjusting the PCB conductive layer material, for example, the copper foil type can be adjusted. If signal integrity or power integrity does not meet requirements, one or more factors can be adjusted until both meet requirements, reaching step S6.

[0079] Figure 5 A schematic diagram of the ports of a printed circuit board provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, P1, P2, P3 and P4 are different ports, which can correspond to the input or output ends of the electronic components of the autonomous driving domain controller set on the PCB board. For example, the P1 port can correspond to an input or output end of the SOC2.

[0080] The single-ended to mixed-mode S-parameter conversion equations can be used to calculate the return loss, insertion loss, common-mode to differential-mode, differential-mode to common-mode, and common-mode to common-mode between the P1, P2, P3, and P4 ports on the PCB. Table 2 shows the single-ended to mixed-mode S-parameter conversion equations for the P1, P2, P3, and P4 ports.

[0081] Table 2 is the single-ended to mixed mode S parameter conversion equation table

[0082]

[0083] Among them, SDD11 and SDD22 represent return loss; SDD21 and SDD12 represent insertion loss; SDC11, SDC22, SDC12, and SDC21 represent common-mode to differential-mode conversion; SCD11, SCD22, SCD12, and SCD21 represent differential-mode to common-mode conversion; and SCC11, SCC22, SCC12, and SCC21 represent common-mode to common-mode conversion. S21, S23, and S41 represent corresponding elements in the S-parameter matrix.

[0084] For example, when determining signal integrity, the impedance of the PCB can be calculated using the following formula:

[0085]

[0086] Among them, L0 represents the parasitic inductance of the entire transmission line; C represents the parasitic capacitance of the entire transmission line; and Z0 represents the characteristic impedance of the entire transmission line.

[0087] For example, when determining power integrity, ripple and noise can be calculated using the following formula:

[0088]

[0089] Where i represents the current, R represents the DC resistance, L1 represents the AC inductance, di / dt represents the instantaneous current change in the power supply system, V drop Represents ripple and noise.

[0090] In a possible implementation, the surface of the surface layer is covered with R500 Z28DF type solder mask ink to form a solder mask (SM) layer of the printed circuit board.

[0091] For example, the solder mask is a layer of polymer material covering the surface of the PCB board, which is used to prevent solder bridging short circuits during soldering, reduce solder loss in non-soldering areas, and provide electrical environment and chemical resistance protection. Figure 3 As shown, both the top layer and the bottom layer are covered with a solder mask layer. As shown in Table 1, the thickness of the solder mask layer can be 0.8 mil.

[0092] Compared to other solder mask inks, such as standard epoxy or polyimide solder mask inks, the R500 Z28DF solder mask ink has optimized dielectric properties, which can reduce signal transmission losses and facilitate high-speed signal transmission. In addition, the R500 Z28DF has excellent high-temperature resistance and can withstand temperatures of up to 260°C or higher during the reflow soldering process. The R500 Z28DF also has good thermal expansion performance. The R500Z28DF solder mask layer has a low thermal expansion coefficient, which can reduce the expansion and contraction of the material during thermal cycling, thereby improving the overall reliability and stability of the PCB board and meeting the physical property requirements of the autonomous driving domain controller for the PCB board.

[0093] In a possible implementation, at least one insulating layer is stacked between any two conductive layers in the stack, and the insulating layer is used to support and insulate the conductive layers stacked therewith. The material of the at least one insulating layer is NPG-170N.

[0094] For example, the insulating layer is a layer in the PCB board used to support and insulate the conductive layer stacked therewith. The insulating layer can also be called a base material layer, a substrate layer or a dielectric layer. Figure 3 As shown, an insulating layer is stacked between any two conductive layers.

[0095] For example, as shown in Table 1, the insulating layer between Layer 1 and Layer 2 uses a semi-cured epoxy resin sheet (PrePreg) 1078x1 with a thickness of 3 mil; the insulating layer between Layer 2 and Layer 3 uses a Prepreg2113x1 with a thickness of 3.63 mil; the insulating layer between Layer 3 and Layer 4 uses a PrePreg 1078x2 with a thickness of 6.2 mil; the insulating layer between Layer 4 and Layer 5 uses a core board (Core) 2113x1 with a thickness of 3.5 mil; the insulating layer between Layer 5 and Layer 6 uses a PrePreg 1078x2 with a thickness of 5.68 mil; the insulating layer between Layer 6 and Layer 7 uses a Core 2113x1 with a thickness of 3.5 mil; the insulating layer between Layer 7 and Layer 8 uses a PrePreg 1080x2 with a thickness of 5.68 mil; the insulating layer between Layer 8 and Layer 9 uses a Core 2113x1 with a thickness of 3.5 mil. 2113x1; the insulation layer between Layer 9 and Layer 10 uses PrePreg 1078x2 with a thickness of 5.68 mil; the insulation layer between Layer 10 and Layer 11 uses Core 2113x1 with a thickness of 3.5 mil; the insulation layer between Layer 11 and Layer 12 uses PrePreg 1078x2 with a thickness of 6.2 mil; the insulation layer between Layer 12 and Layer 13 uses PrePreg2113x1 with a thickness of 3.63 mil; and PrePreg 1078x1 with a thickness of 3 mil is used between Layer 13 and Layer 14.

[0096] Prepreg, a semi-cured epoxy resin sheet, refers to a pre-impregnated material, typically glass fiber cloth impregnated with resin and then partially cured to facilitate handling as an insulating layer. The core is typically a glass fiber-reinforced epoxy resin laminate. Both the Prepreg and the Core insulation layers can be made of NPG-170N. NPG-170N is a PCB insulation material with high stability, high temperature resistance, and a low thermal expansion coefficient. It is a modified epoxy resin matrix with excellent electrical and mechanical properties. Compared to FR-4 or polyimide insulation layers, NPG-170N's insulation layer has a higher glass transition temperature (Tg), enabling it to maintain excellent mechanical and electrical properties in high-temperature environments. NPG-170N also has excellent dielectric constant and dielectric loss, making it suitable for high-frequency signal transmission. Its excellent mechanical strength and dimensional stability provide stable mechanical support for the conductive layers of the PCB, enhancing the overall stability and reliability of the PCB.

[0097] Based on this, the material of at least one insulating layer is NPG-170N. Due to the good stability, high temperature resistance and low thermal expansion coefficient of this material, it can provide good mechanical support and electrical insulation for the conductive layer, meeting the physical property requirements of the autonomous driving domain controller for the PCB board.

[0098] In a possible implementation, the insulating layer between the second signal layer and the ground layer, and / or the insulating layer between the first signal layer and the ground layer, is made of a flat semi-cured epoxy resin sheet.

[0099] An example of a flat semi-cured epoxy resin sheet is PrePreg1078 as shown in Table 1, and an example of a non-flat semi-cured epoxy resin sheet is PrePreg1080 as shown in Table 1. As shown in Table 1, for example, the insulating layer between Layer 5 and Layer 6 uses PrePreg1078, specifically PrePreg1078x2. Compared to the PrePreg1080x2 insulating layer between Layer 7 and Layer 8, since PrePreg1078 is flatter, the gaps within it are less than those of PrePreg1080, and the dielectric is more uniform. Therefore, the skew generated when Layer 5 transmits high-speed signals is smaller. For example, Layer 7 and Layer 8 are power layers, not high-speed signal layers, and the insulating layer between them can use ordinary PrePreg1080.

[0100] Based on this, when the insulating layer between the second signal layer and the ground layer, and / or the insulating layer between the first signal layer and the ground layer uses a flat semi-cured epoxy resin sheet, since the flat semi-cured epoxy resin sheet has a thinner thickness and fewer gaps than the non-flat semi-cured epoxy resin sheet, the dielectric layer is more uniform. These characteristics can reduce the difference in the path length of the signal propagating in the medium. Therefore, for differential signals, the signal skew can be reduced when the signal propagates at high speed, thereby further improving the signal integrity of the printed circuit board.

[0101] When constructing a PCB by the printed circuit board stacking construction method provided in the above embodiment, the PCB board can be tested by simulation to see whether it meets the signal integrity and power integrity requirements. Figure 3 The PCB board shown here is tested using simulation to see if it meets the signal integrity and power integrity requirements.

[0102] Figure 6 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 1 .against Figure 3 For the PCB board of the corresponding embodiment, assuming that the P1 port in the PCB board is a port for communication between the SOC and the CON, when simulating and testing whether it meets the signal integrity requirements of PCIE4.0 communication, an excitation signal with a frequency (freq) of 8 GHz (gigahertz) can be applied for testing. Figure 6 As shown in the figure, after applying an 8GHz excitation signal to the P1 port, the insertion loss SDD21 of the P1 port is measured to be -23.434dB (decibel), which is greater than the insertion loss requirement of -25dB. Therefore, the P1 port meets the PCIE4.0 requirements for insertion loss.

[0103] Figure 7 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 2 ,against Figure 3 The PCB board of the corresponding embodiment is as follows Figure 7 As shown, by applying an 8 GHz excitation signal to the P1 port, the return loss SDD11 of the P1 port is measured to be -29.701 dB, which is less than the return loss requirement of -10 dB. Therefore, the P1 port meets the return loss requirements of PCIE 4.0.

[0104] Figure 8 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 3 .against Figure 3 For the PCB board of the corresponding embodiment, assuming that the P1 port in the PCB board is a port for communication between SOCs, when simulating and testing whether it meets the signal integrity requirements of XFI communication, an excitation signal with a frequency of 5.5 GHz (gigahertz) can be applied for testing. Figure 8 As shown in FIG, after applying a 5.5 GHz excitation signal to the P1 port, the insertion loss SDD21 of the P1 port is measured to be -9.113 dB, which is greater than the insertion loss requirement of -9.6 dB. Therefore, the P1 port meets the XFI requirement for insertion loss.

[0105] Figure 9 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 4 ,against Figure 3 The PCB board of the corresponding embodiment is as follows Figure 9 As shown in the figure, by applying an excitation signal with a frequency of 5.5 GHz to the P1 port, the return loss SDD11 of the P1 port is measured to be -10.696 dB, which is less than the return loss requirement of -10 dB. Therefore, the P1 port meets the XFI return loss requirement.

[0106] Figure 10 Schematic diagram of the simulation test provided in the embodiment of the present application Figure 5 .against Figure 3 The PCB board of the corresponding embodiment is as follows Figure 10 As shown in the figure, the current of the simulated input P12V voltage at the power supply end (Source) is detected at both measurement point 1 (sink1) and measurement point 2 (sink2), with currents greater than 30A. This indicates that the ripple and noise of the PCB board under the P12V voltage meet the power integrity requirements.

[0107] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules is merely a logical function division. In actual implementation, other division methods may be used. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not implemented.

[0108] The above-mentioned integrated module implemented in the form of a software functional module can be stored in a computer-readable storage medium. The above-mentioned software functional module is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) or a processor to perform some steps of the method described in each embodiment of the present application.

[0109] It should be understood that the above-mentioned processor may be a CPU, or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The steps of the method disclosed in the application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor. The memory may include random access memory (RAM), and may also include non-volatile memory (NVM), such as at least one disk storage, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a disk or an optical disk, etc.

[0110] The above-mentioned storage device or storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0111] An exemplary storage medium is coupled to a processor, such that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an application-specific integrated circuit. Of course, the processor and storage medium can also exist as discrete components in an electronic device or a host control device.

[0112] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0113] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0114] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0115] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

[0116] Those skilled in the art will readily conceive of other implementations of the embodiments of the present application after considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the embodiments of the present application, which follow the general principles of the embodiments of the present application and include common knowledge or customary technical means in the art that are not disclosed in the embodiments of the present application.

[0117] It should be understood that the embodiments of the present application are not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the embodiments of the present application is limited only by the appended claims.

Claims

1. A printed circuit board, characterized in that: The printed circuit board is applied to an autonomous driving domain controller, comprising a plurality of conductive layers, wherein the plurality of conductive layers include at least one first signal layer, at least one second signal layer, at least one power layer, and at least one ground layer, wherein a signal transmission rate of the second signal layer is greater than or equal to a signal transmission rate of the first signal layer, and the plurality of conductive layers are stacked together to form a stack; The laminate includes an inner layer, two middle layers stacked on both sides of the inner layer, and a surface layer stacked outside the middle layers; Among them, the at least one power layer is stacked on the inner layer, and the ground layer is stacked on both sides of the at least one power layer; any of the middle layers includes at least one second signal layer and at least one ground layer, and the second signal layer and the ground layer are stacked at intervals; the first signal layer is stacked on the outside of the middle layer to form the surface layer.

2. The printed circuit board according to claim 1, wherein: The inner layer includes two stacked power layers and two ground layers stacked outside the two power layers.

3. The printed circuit board according to claim 2, wherein: Any of the middle layers includes two second signal layers and two ground layers, and one of the second signal layers is stacked close to the inner layer.

4. The printed circuit board according to claim 3, wherein: The printed circuit board includes fourteen conductive layers, and the two surface layers of the stack are respectively a top layer and a bottom layer; from the top layer to the bottom layer, the fourteen conductive layers are stacked as the 1st to 14th layers of the stack, which are respectively: the first signal layer of the 1st layer, the ground layer of the 2nd layer, the second signal layer of the 3rd layer, the ground layer of the 4th layer, the second signal layer of the 5th layer, the ground layer of the 6th layer, the power supply layer of the 7th layer, the power supply layer of the 8th layer, the ground layer of the 9th layer, the second signal layer of the 10th layer, the ground layer of the 11th layer, the second signal layer of the 12th layer, the ground layer of the 13th layer and the first signal layer of the 14th layer.

5. The printed circuit board according to claim 4, wherein: Second-order blind buried vias are used between the first signal layer of the first layer and the ground layer of the second layer, between the ground layer of the second layer and the second signal layer of the third layer, between the second signal layer of the third layer and the second signal layer of the 12th layer, between the second signal layer of the 12th layer and the ground layer of the 13th layer, and between the ground layer of the 13th layer and the first signal layer of the 14th layer.

6. The printed circuit board according to any one of claims 1 to 5, characterized in that: At least one of the conductive layers is made of reverse-processed copper foil.

7. The printed circuit board according to any one of claims 1 to 5, characterized in that: The surface of the surface layer is covered with R500 Z28DF type solder resist ink to form the solder resist layer of the printed circuit board.

8. The printed circuit board according to any one of claims 1 to 5, characterized in that: At least one insulating layer is stacked between any two conductive layers in the stack, and the insulating layer is used to support and insulate the conductive layers stacked therewith. The material of at least one of the insulating layers is NPG-170N.

9. The printed circuit board according to claim 8, wherein: The insulating layer between the second signal layer and the ground layer, and / or the insulating layer between the first signal layer and the ground layer is / are formed of a flat semi-cured epoxy resin sheet.

10. An autonomous driving domain controller, characterized in that: The autonomous driving domain controller includes: at least one processor and a printed circuit board according to any one of claims 1 to 9, wherein the processor is arranged on the printed circuit board, and the processor is used to execute computer execution instructions to realize autonomous driving.

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