Technological manufacturing method of deep groove reverse conducting IGBT without back photoetching
By pre-forming a ring-shaped doped region at the bottom of the deep trench and combining it with back-side non-photolithography ion implantation, the process complexity and alignment difficulties in RC-IGBT manufacturing are solved, and the process is simplified, the cost is reduced, and the performance consistency is improved. It is suitable for IGBT devices made of various semiconductor materials.
Patent Information
- Application Number
- CN202510706218.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-09-05
AI Technical Summary
The existing RC-IGBT manufacturing process is complex, requires backside lithography and is difficult to align, resulting in high cost, low yield and unstable performance.
A deep trench reverse conducting IGBT process without backside lithography is used. By pre-forming a ring-shaped doped region at the bottom of the deep trench and performing non-photolithography ion implantation on the back side, a collector short-circuit structure is formed, simplifying the process flow and avoiding backside alignment.
It significantly simplifies the process flow, reduces production costs, improves manufacturing yield and performance consistency, is suitable for different application requirements, and is applicable to silicon-based and silicon carbide IGBT devices.
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Figure CN120603264A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a process for manufacturing a deep trench reverse conducting IGBT without backside photolithography. Background Art
[0002] As an important power semiconductor device, the insulated gate bipolar transistor (IGBT) is widely used in industrial control, power electronics, consumer electronics, and other fields. Reverse-conducting IGBTs (RC-IGBTs) integrate a reverse fast recovery diode (FRD) into the traditional IGBT structure, effectively reducing module size, lowering costs, and increasing system power density. Therefore, they are highly favored in products such as air conditioners, inverters, and large power supplies. RC-IGBTs typically feature faster switching frequencies and more compact packaging.
[0003] In traditional RC-IGBT manufacturing, an additional photolithography step is typically required on the backside of the wafer to form the N+ region in the collector P+ layer to create the short-circuit structure. However, aligning the backside photolithography pattern with the frontside structure is a technical challenge. The alignment accuracy is difficult to control, the process is complex, and defects are easily introduced, affecting device yield and performance. Furthermore, the additional photolithography steps increase manufacturing costs.
[0004] To address these issues, the industry has been exploring ways to simplify the RC-IGBT manufacturing process, particularly by avoiding backside lithography. For example, some attempts have attempted to create the required N+ region on the backside through specialized implantation or diffusion processes. However, these methods often require high process control or struggle to precisely control the size and doping concentration of the N+ region.
[0005] Therefore, those skilled in the art are committed to developing an RC-IGBT manufacturing process that can form a collector short-circuit structure without backside lithography, in order to simplify the process flow, reduce manufacturing costs, and improve alignment accuracy while ensuring or even improving the electrical performance of the device. Summary of the Invention
[0006] The technical problem to be solved by the present invention is to overcome the defects of the prior art such as complex RC-IGBT manufacturing process, the need for back-side photolithography, difficult back-side alignment and high cost, and to provide a process for manufacturing a deep trench reverse conducting IGBT that does not require back-side photolithography. The method has simple process, low cost, does not require back-side alignment, and can effectively form a collector short-circuit structure.
[0007] To solve the above technical problems, the present invention provides a process for manufacturing a deep trench reverse conducting IGBT without backside lithography, comprising the following steps:
[0008] Step 1: providing a substrate, forming an epitaxial layer of a first conductivity type on the substrate, and then forming at least one deep trench on the front surface of the epitaxial layer of the first conductivity type;
[0009] Step 2: performing a first ion implantation on the bottom of the deep trench to form a ring-shaped region of the second conductivity type at the bottom of the deep trench;
[0010] Step 3: backfilling the deep trench;
[0011] Step 4: completing the fabrication of the IGBT main structure on the front surface of the first conductive type epitaxial layer;
[0012] Step 5: thinning the back side of the substrate until the bottom of the deep trench or its adjacent area is approached from the back side of the substrate;
[0013] Step six: performing a second ion implantation on the back side of the thinned substrate to form a region of the first conductivity type, wherein the region of the first conductivity type and the annular region of the second conductivity type together constitute a collector short-circuit structure.
[0014] Preferably, the first conductivity type is N-type, and the second conductivity type is P-type.
[0015] Preferably, the first conductivity type is P type, and the second conductivity type is N type.
[0016] Preferably, a pattern for forming the deep trench and a pattern for defining the second conductivity type ring-shaped region are defined by the same mask.
[0017] Preferably, the thinning process in step five is used to expose the bottom of the deep trench or its adjacent area to the back side of the substrate; alternatively, when the depth of the deep trench is sufficient to allow the annular region of the second conductive type to extend to the original back side of the substrate when it is formed, the thinning process in step five can be omitted or adjusted.
[0018] Preferably, the area ratio of the first conductive type region formed by the step six in the collector short-circuit structure can be adjusted by adjusting at least one of the dose of the second ion implantation, the pitch of the deep trench, the etching window size of the deep trench, and the sidewall angle of the deep trench to achieve regulation of the collector short-circuit structure pattern.
[0019] Preferably, in step 1, before forming the deep trench, the method further includes growing a hard mask layer on the epitaxial layer of the first conductive type, and forming the deep trench by etching the hard mask layer and the epitaxial layer of the first conductive type.
[0020] Preferably, in step 2, before performing the first ion implantation, the step further includes growing a protective layer on the sidewall of the deep trench.
[0021] Preferably, the protective layer is a SAC oxide layer with a thickness of to
[0022] Preferably, when the first conductivity type is N-type and the second conductivity type is P-type, in step 2, the first ion implantation is boron ion implantation with a dose of 1e15 cm -2 to 1e16 cm -2 , the injection energy is 25KeV.
[0023] Preferably, in step 2, after the first ion implantation, an annealing well-driving treatment is further performed.
[0024] Preferably, when the first conductivity type is N-type and the second conductivity type is P-type, in step three, the deep trench is backfilled with an epitaxial second conductivity type semiconductor.
[0025] Preferably, in step five, the precision of the thinning process is controlled within 1.5 μm.
[0026] Preferably, in step five, after the thinning process and before step six, hydrogen ions are injected to form a field stop layer, and low-temperature activation is performed. The depth of the field stop layer is 5 μm to 10 μm, and the low-temperature activation temperature is 400°C.
[0027] Preferably, when the first conductivity type is N-type, in step six, the second ion implantation is N-type impurity implantation, which is followed by laser annealing activation.
[0028] Preferably, in step two, the first ion implantation is performed to form impurities of a first conductive type, thereby forming an annular region at the bottom of the deep trench into an annular region of the first conductive type; and in step six, the second ion implantation is performed to form impurities of a second conductive type, thereby forming an area on the back side of the substrate into an area of the second conductive type.
[0029] Preferably, the deep trench has a depth of 50 μm, a sidewall angle of 88.5° to 88.7°, an etching window size of 4 μm, and a pitch of 5 μm.
[0030] Preferably, the semiconductor material of the substrate is silicon or silicon carbide.
[0031] The beneficial effects of the present invention are:
[0032] 1. Simplify the process and reduce costs: The present invention forms a collector short-circuit structure by pre-forming a ring-shaped doped region at the bottom of the deep trench and performing non-photolithographic ion implantation on the back side. This completely avoids the traditional back-side photolithography step and its related complex processes such as cleaning, coating, exposure, development, and etching, significantly simplifying the manufacturing process of the RC-IGBT, thereby effectively reducing production costs.
[0033] 2. No need for back-side alignment, improving yield: Since the positional relationship of the key parts of the collector short-circuit structure (i.e., the annular area at the bottom of the trench and the back-side injection area) is determined by the front-side process and self-alignment method, there is no need to align the back-side photolithography pattern with the front-side structure, fundamentally eliminating the risk of introducing back-side alignment errors and improving the manufacturing yield and performance consistency of the device.
[0034] 3. The structural pattern shares the same mask, and the process compatibility is good: the pattern for forming the deep groove and the pattern for defining the annular area at the bottom of the groove can be produced by the same mask plate. The process steps are highly integrated, and are compatible with the existing IGBT front process, making it easy to introduce into the existing production line.
[0035] 4. Flexible control of device characteristics: By adjusting the backside injection dose and the geometric parameters of the deep trench (such as pitch, window, angle), the area ratio and distribution of different conductive types in the collector short-circuit structure can be flexibly controlled, thereby optimizing and customizing the diode characteristics integrated in the RC-IGBT and the electrical performance of the IGBT itself to meet the needs of different applications.
[0036] 5. Wide applicability: The process method proposed in the present invention is not only applicable to silicon-based IGBTs, but also to the manufacture of IGBT devices made of wide-bandgap semiconductor materials such as silicon carbide, and has good technical scalability and application prospects.
[0037] Through the above technical solution, the present invention successfully provides an efficient, low-cost and easy-to-implement method for manufacturing deep trench reverse conducting IGBTs without backside lithography, which is of great significance for improving the production efficiency and market competitiveness of RC-IGBT devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 Shown is a schematic diagram of the process flow of the present invention;
[0039] Figure 2 Shown is a schematic diagram of forming a deep trench according to the present invention;
[0040] Figure 3 Schematic diagram showing the formation of a second conductivity type annular region at the bottom of a deep trench according to the present invention;
[0041] Figure 4 Shown is a schematic diagram of a backfilled deep trench according to the present invention;
[0042] Figure 5 It is a schematic diagram showing the fabrication of the IGBT main structure on the front side of the first conductivity type epitaxial layer according to the present invention;
[0043] Figure 6 Shown is a schematic diagram of thinning the back side of a substrate according to the present invention;
[0044] Figure 7 It is a schematic diagram showing a region where the first conductivity type is formed according to the present invention. DETAILED DESCRIPTION
[0045] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0046] See also Figure 1 The present invention provides a process for manufacturing a deep trench reverse conducting IGBT without backside lithography, comprising the following steps:
[0047] Step 1: providing a substrate 101 , and forming an epitaxial layer 102 of a first conductivity type on the substrate 101 , and then forming at least one deep trench on the front surface of the epitaxial layer 102 of the first conductivity type.
[0048] In some embodiments, in step 1, before forming the deep trench, the process further includes growing a hard mask layer 103 on the epitaxial layer 102 of the first conductive type, and forming a deep trench by etching the hard mask layer 103 and the epitaxial layer 102 of the first conductive type. Figure 2 By etching the hard mask layer 103, a steep deep trench with controllable morphology can be obtained, which lays the foundation for the precise construction of the subsequent super junction structure and protects the surface of the epitaxial layer 102 in the non-etched area.
[0049] Step 2: Perform a first ion implantation on the bottom of the deep trench to form a second conductive type annular region 105 at the bottom of the deep trench. Figure 3 The structure shown.
[0050] In some embodiments, in step 2, before the first ion implantation, a protective layer 104 is grown on the sidewalls of the deep trench. This protective layer 104, such as the SAC oxide layer described later, effectively prevents undesired doping or damage to the trench sidewalls during subsequent ion implantation, ensuring the insulation of the trench sidewalls. This is crucial for forming a high-quality superjunction structure and avoids leakage or reduced breakdown voltage caused by uneven sidewall doping or defects. After the first ion implantation, the protective layer 104 is typically removed.
[0051] In some embodiments, the protection layer 104 is a SAC oxide layer. The SAC (sacrificial) oxide layer has good step coverage and can function as an implantation barrier layer, thereby effectively protecting the trench sidewalls.
[0052] In some embodiments, the thickness of the SAC oxide layer is to The SAC oxide layer within this thickness range can provide sufficient sidewall protection without excessively increasing the complexity of the process or significantly affecting the trench size.
[0053] In some embodiments, when the first conductivity type is N-type and the second conductivity type is P-type, the first ion implantation in step 2 is boron ion implantation. Boron is a common element for forming P-type doping, and its implantation process is mature and easy to control.
[0054] In some embodiments, the dose of boron ion implantation is 1e15 cm -2 to 1e16 cm -2 The implantation energy is 25 KeV. At this dose and energy, a P-type ring region with a suitable concentration and junction depth can be formed at the bottom of the trench, laying the foundation for the subsequent formation of the collector short-circuit structure.
[0055] In some embodiments, in step 2, after the first ion implantation, an annealing well-driving process is also performed. Annealing well-driving not only repairs lattice damage caused by ion implantation, but also activates the implanted impurities and allows them to further diffuse, forming a doped region with a specific junction depth and concentration distribution, thereby optimizing the electrical properties of the annular region.
[0056] Step 3: Backfill the deep trench to form Figure 4 The structure shown.
[0057] In some embodiments, the deep trench is backfilled with an epitaxial second conductivity type semiconductor 106. When the first conductivity type is N-type and the second conductivity type is P-type, in step three, the deep trench is backfilled with an epitaxial second conductivity type, i.e., a P-type semiconductor. By epitaxially growing a P-type semiconductor backfilling the deep trench, it can form a P-pillar in the superjunction structure together with the P-type annular region at the bottom of the trench and the N-type region in the epitaxial layer 102, which is a key structure for achieving high withstand voltage and low on-resistance.
[0058] Step 4: Complete the fabrication of the IGBT main structure on the front surface of the first conductive type epitaxial layer 102 to form the following Figure 5 This step includes forming the conventional front-side structures of the IGBT device, including the gate, P-base region, N+ emitter region, contact holes, and metal electrodes. The formation of these structures is crucial to the basic switching function of the IGBT. The process is similar to that of the traditional TIGBT (trench gate IGBT) front side, ensuring the device's driving and conduction characteristics.
[0059] Step 5: Thin the back side of the substrate 101 until the bottom of the deep trench or its adjacent area is close to the back side of the substrate 101, forming a Figure 6 The thinning process not only reduces the overall thickness of the device, which is beneficial for heat dissipation and packaging, but more importantly, it enables subsequent backside processing to act on the area near the bottom of the deep trench, creating conditions for forming a collector short-circuit structure.
[0060] In some embodiments, the thinning process in step five is used to expose the bottom of the deep trench or its adjacent area to the back side of the substrate 101; alternatively, when the depth of the deep trench is sufficient to allow the second conductive type annular region 105 to extend to the original back side of the substrate 101 when it is formed, the thinning process in step five can be omitted or adjusted. This process flexibility enables the present invention to adapt to deep trenches with different design requirements. If the trench is designed to be deep enough so that the annular region formed by the injection has reached or is very close to the original back side of the wafer, the requirement for back side thinning can be reduced or even eliminated, further simplifying the process flow, reducing production costs, and reducing potential damage introduced by thinning.
[0061] In some embodiments, the thinning process in step 5 is controlled to an accuracy of less than 1.5 μm. High-precision thinning control ensures consistent wafer thickness and accurately thins the backside of the wafer to a predetermined depth. This is crucial for the subsequent precise formation of the field stop layer 107 and collector short-circuit structure, avoiding device performance variations caused by uneven thickness.
[0062] In some embodiments, after the thinning process and before step 6, step 5 further includes implanting hydrogen ions to form a field-stop layer 107, followed by low-temperature activation. Field-stop layer 107 optimizes the electric field distribution in the back region when the device is turned off, increasing the device's breakdown voltage and improving its turn-off characteristics, such as reducing tail current. Forming field-stop layer 107 using hydrogen ion implantation is a common process.
[0063] In some embodiments, the depth of the field stop layer 107 is 5 μm to 10 μm. The field stop layer 107 with such a depth can effectively block the electric field from penetrating to the collector without adversely affecting other performances of the device.
[0064] In some embodiments, the low temperature activation temperature is 400° C. Low temperature activation can effectively activate the implanted hydrogen ions to form the field stop layer 107 while preventing high temperature from adversely affecting the formed front structure and doping distribution, thereby maintaining the stability of the device structure.
[0065] Step 6: Perform a second ion implantation on the back of the thinned substrate 101 to form a first conductivity type region 108. The first conductivity type region 108 and the second conductivity type annular region 105 together form a collector short circuit structure, forming a structure as shown in FIG. Figure 7 The structure shown in Figure 1 is formed by directly implanting ions on the back side of the transistor. This region, in conjunction with the pre-formed second conductivity type annular region at the bottom of the deep trench, forms the collector short-circuit structure in the RC-IGBT. This structure involves inserting the N+ region (first conductivity type) into the P+ collector (composed of a P column and a P ring), thereby integrating the reverse-conducting diode function. This approach avoids traditional backside photolithography, significantly simplifying the process flow, reducing manufacturing costs, and eliminating the challenge of backside alignment, thereby improving production efficiency and yield.
[0066] In some embodiments, when the first conductivity type is N-type, the second ion implantation in step 6 is N-type impurity implantation. The N-type impurity implantation forms an N+ region on the back surface, which together with the P-type ring region constitutes the short-circuit structure of the RC-IGBT.
[0067] In some embodiments, in step six, after the second ion implantation, laser annealing activation is also performed. Laser annealing has the advantages of good selectivity in the heated area, fast heating rate, and minimal thermal impact on surrounding areas. It can effectively activate the implanted impurities and repair lattice damage, while limiting excessive diffusion of impurities, forming a steeper and more precise doping profile, which is beneficial for improving device performance.
[0068] In some embodiments, the first conductivity type is N-type, and the second conductivity type is P-type. This is a common conductivity type configuration in IGBT devices. The N-type epitaxial layer 102 serves as the drift region, the P-type ring region and the subsequent backfilled P-type semiconductor form the P collector / P column, and the back-implanted N-type region forms the N+ portion of the collector short-circuit structure.
[0069] In some embodiments, the first conductivity type is P-type, and the second conductivity type is N-type. This is another possible conductivity type configuration, which is not common in mainstream IGBTs but may be adopted in specific designs, and the method of the present invention is also applicable.
[0070] In some embodiments, the pattern for forming the deep trench and the pattern for defining the annular region 105 of the second conductivity type are defined by the same photomask, thereby avoiding the back alignment problem. This is a significant advantage of the present invention. Since the formation of the deep trench and the formation of the annular region at the bottom of the trench (injection is performed through the opening at the bottom of the trench) both rely on the photomask pattern defined by the same front lithography step, the relative position between them is precisely fixed. When another part of the collector short-circuit structure is subsequently formed on the back, since it is associated with the annular region at the bottom of the trench, there is no need for complex back alignment, which greatly simplifies the process, reduces the risk of alignment errors, and improves the yield and performance consistency of the device.
[0071] In some embodiments, the area ratio of the first conductive type region formed by step six in the collector short-circuit structure can be achieved by adjusting at least one of the dose of the second ion implantation, the pitch of the deep trench, the etching window size of the deep trench, and the sidewall angle of the deep trench to achieve regulation of the collector short-circuit structure pattern. By precisely controlling these process parameters, the proportion and distribution of the first conductive type region (such as the N+ region) formed on the back side in the entire collector region can be flexibly adjusted. This is crucial for optimizing the characteristics of the anti-parallel diode integrated in the RC-IGBT (such as forward voltage drop, reverse recovery speed, etc.) and the switching characteristics of the IGBT itself (such as saturation voltage drop, turn-off loss, etc.). It is possible to achieve fine customization of the electrical performance of the device to meet the needs of different application scenarios.
[0072] In some embodiments, the ratio of the deep trench pitch to the etch window size is selected from one or more combinations of 2:3, 3:4, 4:5, and 5:6, and the deep trench aspect ratio is greater than 5. These specific pitch, window size ratio, and aspect ratio greater than 5 represent the typical parameter range for forming a superjunction structure with effective charge compensation. Deep trenches with high aspect ratios facilitate achieving higher blocking voltages within limited cell dimensions. By adjusting these geometric parameters, the balance between the device's withstand voltage capability and on-resistance can be further optimized, thereby improving the device's overall performance.
[0073] In some embodiments, in step 2, the first ion implantation forms impurities of the first conductivity type, thereby forming an annular region at the bottom of the deep trench into an annular region of the first conductivity type; and in step 6, the second ion implantation forms impurities of the second conductivity type, thereby forming an area on the back side of the substrate 101 into an area of the second conductivity type. This doping type configuration, which is opposite to the mainstream embodiment described above, can also form a collector short-circuit structure using the method of the present invention, providing more possibilities for device design, for example, allowing for the construction of device variants with specific electrical characteristics.
[0074] In some embodiments, the deep trench has a depth of 50 μm, which is sufficient to form an effective superjunction structure in a typical IGBT design to support a higher blocking voltage.
[0075] In some embodiments, the sidewall angle of the deep trench is 88.5° to 88.7°. A near-vertical trench sidewall angle helps improve cell density and ensures the quality of subsequent backfilling processes, which is important for forming a uniform superjunction structure.
[0076] In some embodiments, the deep trench etch window size is 4μm and the pitch is 5μm. These specific dimensional parameters are examples of IGBT designs that achieve specific performance indicators. Combined with the trench depth, they determine the charge balance of the superjunction structure and the device's withstand voltage rating.
[0077] In some embodiments, the semiconductor material of substrate 101 is silicon or silicon carbide. The method of the present invention is not only applicable to traditional silicon-based IGBTs, but is also applicable to the manufacture of IGBT devices made of wide-bandgap semiconductor materials such as silicon carbide, which have higher operating frequencies, higher operating temperatures, and lower loss potential, demonstrating good technical compatibility and application prospects.
[0078] In summary, the present invention cleverly achieves a collector short-circuit structure for a deep-trench reverse-conducting IGBT without backside lithography by preforming a ring-shaped doped region at the bottom of the deep trench, combined with subsequent backside thinning and non-photolithographic implantation. This method not only simplifies the process flow, reduces manufacturing costs, avoids the challenge of backside alignment, and improves device manufacturing yield and consistency, but also allows for flexible control of the device's electrical characteristics by adjusting relevant process parameters, thus possessing significant industrial application value.
[0079] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.
[0080] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A process for manufacturing a deep trench reverse conducting IGBT without backside lithography, characterized in that: At least: Step 1: providing a substrate, forming an epitaxial layer of a first conductivity type on the substrate, and then forming at least one deep trench on the front surface of the epitaxial layer of the first conductivity type; Step 2: performing a first ion implantation on the bottom of the deep trench to form a ring-shaped region of the second conductivity type at the bottom of the deep trench; Step 3: backfilling the deep trench; Step 4: Complete the fabrication of the IGBT main structure on the front surface of the first conductive type epitaxial layer; Step 5: thinning the back side of the substrate until the bottom of the deep trench or its adjacent area is approached from the back side of the substrate; Step six: performing a second ion implantation on the back side of the thinned substrate to form a region of the first conductivity type, wherein the region of the first conductivity type and the annular region of the second conductivity type together constitute a collector short-circuit structure.
2. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type.
3. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.
4. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: The pattern for forming the deep trench and the pattern for defining the second conductivity type ring-shaped region are defined by the same photomask, thereby avoiding the backside alignment problem.
5. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: The thinning process in step five is used to expose the bottom of the deep trench or its adjacent area to the back side of the substrate; alternatively, when the depth of the deep trench is sufficient to allow the second conductive type annular region to extend to the original back side of the substrate when it is formed, the thinning process in step five can be omitted or adjusted.
6. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: The area ratio of the first conductive type region formed by the step six in the collector short-circuit structure can be adjusted by adjusting at least one of the dose of the second ion implantation, the pitch of the deep trench, the etching window size of the deep trench, and the sidewall angle of the deep trench to achieve regulation of the collector short-circuit structure pattern.
7. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 6, characterized in that: The ratio of the pitch of the deep trench to the size of the etching window is selected from one or more combinations of 2:3, 3:4, 4:5, and 5:6, and the aspect ratio of the deep trench is greater than 5.
8. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: In step 1, before forming the deep trench, the method further includes growing a hard mask layer on the epitaxial layer of the first conductive type, and forming the deep trench by etching the hard mask layer and the epitaxial layer of the first conductive type.
9. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 8, characterized in that: In step 2, before performing the first ion implantation, a protective layer is grown on the sidewall of the deep trench.
10. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 9, characterized in that: The protective layer is a SAC oxide layer.
11. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 10, characterized in that: The thickness of the SAC oxide layer is to 12. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 2, characterized in that: In step 2, the first ion implantation is boron ion implantation.
13. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 12, characterized in that: The dose of the boron ion implantation is 1e15 cm -2 to 1e16 cm -2 , the injection energy is 25KeV.
14. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, wherein: In step 2, after the first ion implantation, an annealing well-driving treatment is also performed.
15. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 2, characterized in that: In step three, the deep trench is backfilled with an epitaxial second conductivity type semiconductor.
16. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: In step five, the precision of the thinning process is controlled within 1.5 μm.
17. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: In step five, after the thinning process is performed and before step six, hydrogen ions are implanted to form a field stop layer, and activation is performed.
18. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 17, characterized in that: The field stop layer has a depth of 5 μm to 10 μm.
19. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 17 or 18, characterized in that: The activation temperature of the field stop layer is 400°C.
20. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 2, characterized in that: In step six, the second ion implantation is N-type impurity implantation.
21. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: In step six, after the second ion implantation, laser annealing activation is further performed.
22. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: In step 2, the first ion implantation uses impurities of the first conductivity type, so that the annular region at the bottom of the deep trench is formed into an annular region of the first conductivity type; Furthermore, in step six, the second ion implantation uses impurities of the second conductivity type, thereby forming a region of the back side of the substrate into a region of the second conductivity type.
23. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: The depth of the deep trench is 50 μm.
24. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: The sidewall angle of the deep trench is 88.5° to 88.7°.
25. The process for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, characterized in that: The etching window size of the deep trench is 4 μm, and the pitch is 5 μm.
26. The method for manufacturing a deep trench reverse conducting IGBT without backside lithography according to claim 1, wherein: The semiconductor material of the substrate is silicon or silicon carbide.