Silicon carbide power device and preparation method thereof

Abstract

The invention relates to a silicon carbide power device and a preparation method thereof, and belongs to the technical field of semiconductor devices.The preparation method comprises the following steps that a silicon carbide substrate is polished; growing a buffer layer and an active layer on the silicon carbide substrate to form an epitaxial layer; growing a gate oxide layer on the surface of the active layer; photoresist is spin-coated on the gate oxide layer; forming a source electrode and a drain electrode on the active layer through ion implantation and annealing processes; forming a field limiting ring on the active layer; the silicon carbide power device has the beneficial effects that the buffer layer in the epitaxial layer adopts the gradient doping structure, so that lattice mismatch and stress between the substrate and the active layer can be effectively relieved, the reliability and stability of the device are improved, and the preparation efficiency of the silicon carbide power device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a silicon carbide power device and a preparation method thereof. Background Art

[0002] In the fields of energy conversion and power electronics, silicon carbide (SiC) power devices, with their wide bandgap, high critical breakdown electric field strength, and high electron saturation drift velocity, have become core components driving the development of new energy vehicles, smart grids, and rail transit. Compared to traditional silicon-based power devices, SiC power devices can operate stably at higher temperatures, higher voltages, and higher frequencies, effectively reducing device on-resistance and switching losses, significantly improving system energy conversion efficiency. However, silicon carbide power devices currently face numerous challenges in structural design and fabrication. In terms of device structure, the gate oxide interface quality of conventional silicon carbide power devices is poor, which easily generates interface states and trapped charges. This leads to unstable device threshold voltage and increased gate leakage current, severely impacting device reliability and service life. Furthermore, the high ohmic contact resistance between the source and drain electrodes limits further improvements in device conduction performance. Furthermore, the design of conventional field-limiting ring structures is not optimal, making it difficult to effectively suppress edge electric field concentration, which reduces the device's breakdown voltage.

[0003] In terms of fabrication, existing epitaxial growth processes struggle to precisely control the doping concentration and thickness of the buffer and active layers, resulting in poor device performance consistency. During gate oxide fabrication, nitrogen doping is difficult to achieve uniform distribution and precise control, impacting the electrical properties of the gate oxide. The ohmic contact process for the source and drain electrodes is complex, resulting in high contact resistance dispersion and hindering large-scale production. Furthermore, traditional fabrication processes suffer from deficiencies in parameter control and process integration across various stages, resulting in low device fabrication efficiency and difficulty in improving yield rates. Summary of the Invention

[0004] The present invention provides a silicon carbide power device and a preparation method thereof, which are used to solve the technical problem of low preparation efficiency of existing silicon carbide power devices. By adopting a gradient doping structure in the buffer layer of the epitaxial layer, the lattice mismatch and stress between the substrate and the active layer can be effectively alleviated, the reliability and stability of the device can be improved, and the preparation efficiency of the silicon carbide power device is improved.

[0005] In order to achieve the above object, the present invention is implemented through the following technical solutions: A silicon carbide power device, comprising: The silicon carbide substrate has a square plate structure, the surface roughness Ra of the silicon carbide substrate is less than 0.5nm, the silicon carbide substrate is an n-type silicon carbide substrate, the doping element is nitrogen, and the doping concentration is controlled at 1.2×10 18cm -3 -1.8×10 20 cm -3 ; The epitaxial layer on the silicon carbide substrate consists of a buffer layer and an active layer. The buffer layer is tightly attached to the upper surface of the silicon carbide substrate, and the active layer covers the upper surface of the buffer layer. The buffer layer adopts a gradient doping structure, and the doping concentration on the side close to the silicon carbide substrate is 5×10 16 cm -3 , the doping concentration close to the active layer is 2×10 17 cm -3 The thickness of the buffer layer is 0.8-1.8 μm; the thickness of the active layer is 2.5-4.5 μm, the doping type of the active layer is n-type, the doping element is phosphorus, and the doping concentration is 5×10 16 cm -3 -8×10 16 cm -3 ; The gate structure formed on the active layer includes a gate oxide layer and a gate electrode. The gate oxide layer is grown on the upper surface of the active layer by a thermal oxidation process and is uniformly doped with nitrogen. The doping concentration of nitrogen is 1.2×10 18 cm -3 -1.5×10 20 cm -3 The thickness of the gate structure is 8-15 nm; the gate electrode is located on the upper surface of the gate oxide layer and is made of polysilicon material or metal material. When the gate electrode is made of polysilicon material, the doping type of the polysilicon material is p-type, and the ratio of its doping concentration to the doping concentration of the active layer is in the range of 1:5-1:10; The source and drain are located on both sides of the active layer. The source and the active layer are in ohmic contact through a multilayer metal structure of titanium / aluminum / nickel / gold. The drain passes through the active layer and the buffer layer in sequence. The drain and the silicon carbide substrate are in ohmic contact through a multilayer metal structure of titanium / aluminum / nickel / gold. There are multiple field limiting rings on the lower side of the gate structure. The field limiting rings are arranged in the same layer as the active layer. The width of the field limiting rings is 2.5-4.5μm, the spacing between adjacent field limiting rings is 1.2-2.8μm, and the doping concentration of the field limiting rings is 3×10 17 cm -3 -5×10 17 cm -3 .

[0006] Optionally, in the multi-metal layer between the source electrode and the active layer, the thickness of the titanium layer is 50-100 nm, the thickness of the aluminum layer is 500-1000 nm, the thickness of the nickel layer is 100-200 nm, and the thickness of the gold layer is 200-500 nm.

[0007] Optionally, when the gate electrode is made of metal material, the metal material is tungsten or molybdenum, and the thickness of the gate electrode is 300-800 nm.

[0008] Optionally, the thickness of the silicon carbide substrate is 300-600 μm, and the edge of the silicon carbide substrate is provided with a chamfer structure with a width of 1-3 mm.

[0009] A method for preparing a silicon carbide power device comprises the following steps: Providing a silicon carbide substrate that has been subjected to chemical mechanical polishing, and cleaning the silicon carbide substrate in a mixture of sulfuric acid and hydrogen peroxide at a temperature of 120-150° C. for 15-30 minutes, wherein the volume ratio of sulfuric acid to hydrogen peroxide is 3:1; A buffer layer and an active layer are sequentially grown on a silicon carbide substrate using a low-pressure chemical vapor deposition method to form an epitaxial layer. When growing the buffer layer, the growth temperature is 1600-1750° C., the growth pressure is 20-60 Torr, the silicon source gas is silane with a flow rate of 10-30 sccm, the carbon source gas is propane with a flow rate of 5-15 sccm, and the nitrogen source gas is ammonia with a flow rate of 1-5 sccm. When growing the active layer, the growth temperature is 1650-1800° C., the growth pressure is 30-80 Torr, the silicon source gas is silane with a flow rate of 20-40 sccm, the carbon source gas is methane with a flow rate of 8-20 sccm, and the phosphorus source gas is phosphine with a flow rate of 0.5-2 sccm. A gate oxide layer is grown on the surface of the active layer using a dry oxygen oxidation process at a temperature of 950-1050°C for 60-100 minutes. During the oxidation process, a mixed gas of oxygen and argon is introduced into the reaction chamber at a flow ratio of 1:3-1:5. Nitrogen is introduced into the gate oxide layer by an ion implantation process at an ion implantation energy of 20-50 keV and an implantation dose of 5×10 13 cm -2 -1×10 14 cm -2 After the implantation, the device is annealed in a nitrogen atmosphere at a temperature of 1000-1100°C for 30-60 minutes, and the nitrogen doping concentration is controlled to be 1.2×10 18 cm -3 -1.5×10 20 cm -3 ; Spin-coat photoresist on the gate oxide layer with a thickness of 1.5-2.5 μm and use deep ultraviolet lithography for exposure with an exposure energy of 180-250 mJ / cm 2 , forming a gate electrode pattern after development; removing the excess gate oxide layer and the active layer by reactive ion etching process, the etching gas is a mixture of sulfur hexafluoride and oxygen, the flow ratio is 5:1-8:1, and the etching power is 100-200W; The source and drain are formed on both sides of the active layer by ion implantation and annealing. The energy of ion implantation is 80-150keV and the implantation dose is 1.2×10 15 -1.8×10 16 cm -2 The implanted element is phosphorus; after implantation, the substrate is annealed in an argon atmosphere at a temperature of 1650-1750°C for 2-4 minutes; titanium / aluminum / nickel / gold multilayer metals are deposited in sequence using an electron beam evaporation process, and the vacuum degree during the deposition process is maintained at 1×10 -5 -5×10 -5 Pa, the deposition rate of the titanium layer is 0.1-0.3 nm / s, the deposition rate of the aluminum layer is 0.5-1 nm / s, the deposition rate of the nickel layer is 0.2-0.5 nm / s, and the deposition rate of the gold layer is 0.3-0.8 nm / s, and then annealed at a temperature of 400-600 ° C for 5-15 minutes through a rapid thermal annealing process to achieve ohmic contact; If the silicon carbide power device includes a field limiting ring, before forming the source and drain, a photoresist is spin-coated on the active layer. The thickness of the photoresist is 1-3 μm, and the exposure is performed using photolithography technology with an exposure energy of 150-300 mJ / cm 2 After development, a field-limiting ring pattern is formed; nitrogen is injected into the field-limiting ring region by ion implantation, with an ion implantation energy of 30-80 keV and an implantation dose of 2×10 14 cm 2 - 5×10 14 cm 2 After the injection, the substrate is annealed in a nitrogen atmosphere at a temperature of 1200-1400°C for 20-40 minutes; the excess active layer is then removed by reactive ion etching. The etching gas is a mixture of chlorine and argon with a flow ratio of 3:1-5:1 and an etching power of 80-150W.

[0010] Optionally, during the growth of the gate oxide layer, the flow ratio of the mixed gas of oxygen and argon is 1:3-1:5, and the oxidation time is 45-90 minutes.

[0011] Optionally, before growing the buffer layer and the active layer, the silicon carbide substrate is pre-treated by hydrogen etching, with an etching temperature of 1200-1400° C., an etching time of 10-30 minutes, and a hydrogen flow rate of 50-100 sccm.

[0012] Optionally, after forming the gate electrode pattern, the gate electrode is subjected to a high-temperature annealing treatment, the annealing temperature is 1000-1200° C., the annealing time is 15-30 minutes, and the annealing atmosphere is nitrogen.

[0013] Optionally, after forming the source and drain, the entire silicon carbide power device is passivated by depositing a silicon dioxide passivation layer using plasma enhanced chemical vapor deposition. The deposition temperature is 300-400°C, the deposition pressure is 10-50Pa, the silicon source gas is silane, the flow rate is 10-30sccm, the oxygen source gas is nitrous oxide, the flow rate is 20-60sccm, and the deposition thickness is 200-500nm.

[0014] Optionally, during the entire preparation process, the background vacuum of the reaction chamber was maintained at 1×10 -6 -5×10 -6 Pa.

[0015] Beneficial effects of the present invention: The buffer layer in the epitaxial layer of the present invention adopts a gradient doping structure, which can effectively alleviate the lattice mismatch and stress between the substrate and the active layer, improve the reliability and stability of the device, and also facilitate the transmission of electrons between the layers. The thickness and doping concentration of the active layer are designed to optimize the device's on-resistance and carrier mobility, thereby improving the device's power conversion efficiency. The gate oxide layer of the gate structure is grown through a thermal oxidation process and uniformly doped with nitrogen, improving the quality and stability of the gate oxide layer and increasing its dielectric constant, thereby improving the gate control performance of the device. The doping concentration ratio of the gate electrode to the active layer is designed to facilitate the formation of a good pn junction and achieve effective control of the device channel current. The source and drain electrodes achieve ohmic contact through a specific multilayer metal structure, reducing contact resistance, improving current transmission efficiency, and reducing device conduction losses. The provision of field-limiting rings can effectively regulate the electric field distribution, improve the device's voltage resistance, prevent device breakdown under high voltage, and improve the production efficiency of silicon carbide power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 It is a schematic diagram of the cross-sectional structure of the present invention; Figure 2 Schematic diagram of the workflow of the present invention. DETAILED DESCRIPTION

[0018] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0019] In the description of this application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0020] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installation," "connection," and "connection" should be understood in a broad sense. For example, they can refer to welding, bolting, or riveting; fixed connection, detachable connection, or integral connection; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0021] Example 1 like Figure 1 As shown, the silicon carbide substrate 1 has a square plate structure, the surface roughness Ra of the silicon carbide substrate 1 is less than 0.5 nm, the silicon carbide substrate 1 is an n-type silicon carbide substrate, the doping element is nitrogen, and the doping concentration is controlled at 1.2×10 18 cm -3 -1.8×10 20 cm -3 ; The epitaxial layer on the silicon carbide substrate 1 consists of a buffer layer 2 and an active layer 3. The buffer layer 2 is tightly attached to the upper surface of the silicon carbide substrate 1, and the active layer 3 covers the upper surface of the buffer layer 2. The buffer layer 2 adopts a gradient doping structure, and the doping concentration on the side close to the silicon carbide substrate 1 is 5×10 16 cm -3 , the doping concentration close to the active layer 3 is 2×10 17 cm -3 The thickness of the buffer layer 2 is 0.8-1.8 μm; the thickness of the active layer 3 is 2.5-4.5 μm, the doping type of the active layer 3 is n-type, the doping element is phosphorus, and the doping concentration is 5×10 16 cm -3 -8×10 16 cm -3 ; The gate structure 6 formed on the active layer 3 includes a gate oxide layer 7 and a gate electrode 8. The gate oxide layer 7 is grown on the upper surface of the active layer 3 by a thermal oxidation process and is uniformly doped with nitrogen. The doping concentration of nitrogen is 1.2×10 18 cm-3 -1.5×10 20 cm -3 , the thickness of the gate structure 6 is 8-15 nm; the gate electrode 8 is located on the upper surface of the gate oxide layer 7 and is made of polysilicon material or metal material. When the gate electrode 8 is made of polysilicon material, the doping type of the polysilicon material is p-type, and the ratio of its doping concentration to the doping concentration of the active layer is in the range of 1:5-1:10; The active layer 3 is provided with a source 4 and a drain 10 on both sides. The source 4 and the active layer 3 are in ohmic contact through a titanium / aluminum / nickel / gold multilayer metal structure 5. The drain 10 passes through the active layer 3 and the buffer layer 2 in sequence. The drain 10 and the silicon carbide substrate 1 are in ohmic contact through the titanium / aluminum / nickel / gold multilayer metal structure 5. There are multiple field limiting rings 9 on the lower side of the gate structure 6. The field limiting rings 9 are arranged in the same layer as the active layer 3. The width of the field limiting rings 9 is 2.5-4.5μm, the spacing between adjacent field limiting rings 9 is 1.2-2.8μm, and the doping concentration of the field limiting rings 9 is 3×10 17 cm -3 -5×10 17 cm -3 .

[0022] The surface roughness Ra of the silicon carbide substrate 1 is less than 0.5nm, which facilitates the subsequent growth of the epitaxial layer, improves the bonding between the epitaxial layer and the substrate, and reduces defects and interface states. The n-type silicon carbide substrate is doped with nitrogen, with the concentration controlled within a certain range, to precisely adjust the substrate's electrical properties, providing a foundation for the device's conductivity and stability.

[0023] The buffer layer 2 in the epitaxial layer adopts a gradient doping structure, which effectively alleviates the lattice mismatch and stress between the substrate and the active layer 3, improving device reliability and stability while also facilitating electron transport between the layers. The thickness and doping concentration of the active layer 3 are designed to optimize the device's on-resistance and carrier mobility, thereby improving its power conversion efficiency.

[0024] The gate oxide layer 7 of the gate structure is grown through a thermal oxidation process and uniformly doped with nitrogen. This improves the quality and stability of the gate oxide layer 7, increases its dielectric constant, and thus improves the device's gate control performance, such as threshold voltage stability and switching speed. The gate electrode 8 is made of polycrystalline silicon or metal. When using polycrystalline silicon, the doping concentration ratio of the gate electrode 8 to the active layer 3 is designed to facilitate the formation of a good pn junction, effectively controlling the device's channel current.

[0025] The source 4 and drain 10 achieve ohmic contact through a specific multilayer metal structure 5, which reduces contact resistance, improves current transmission efficiency, and reduces device conduction losses. The field-limiting rings effectively regulate the electric field distribution, improving the device's withstand voltage and preventing device breakdown under high voltage.

[0026] Furthermore, in the multi-metal layer 5 between the source electrode 4 and the active layer 3, the thickness of the titanium layer is 50-100 nm, the thickness of the aluminum layer is 500-1000 nm, the thickness of the nickel layer is 100-200 nm, and the thickness of the gold layer is 200-500 nm. The thickness of each layer of the multi-metal layer 5 between the source electrode 4 and the active layer 3 can precisely control the performance of the metal layers, ensuring the quality and stability of the ohmic contact, reducing contact resistance, improving current transmission efficiency, and reducing power loss. It also helps to improve the heat dissipation performance of the device.

[0027] When gate electrode 8 is made of a metal material, such as tungsten or molybdenum, the thickness of gate electrode 8 is 300-800 nm. When gate electrode 8 is made of tungsten or molybdenum, specifying the thickness range is beneficial for optimizing the electrical and physical properties of gate electrode 8. Metal gate electrode 8 has excellent conductivity and stability, which can improve the switching speed and reliability of the device. A suitable thickness ensures good contact between gate electrode 8 and gate oxide layer 7, reducing contact resistance and parasitic capacitance.

[0028] The silicon carbide substrate 1 has a thickness of 300-600 μm, and its edges are chamfered with a width of 1-3 mm. This thickness is designed to be between 300 and 600 μm to optimize the device's heat dissipation and electrical performance while ensuring mechanical strength. The chamfered edges reduce edge electric field concentration, improve the device's withstand voltage, and prevent edge breakdown, thereby enhancing device reliability and stability.

[0029] Example 2 Based on Example 1, Figure 2 As shown, this embodiment provides a method for preparing a silicon carbide power device, comprising the following steps: Providing a silicon carbide substrate 1 that has been subjected to chemical mechanical polishing, and cleaning the silicon carbide substrate 1 in a mixed solution of sulfuric acid and hydrogen peroxide at a temperature of 120-150° C. for 15-30 minutes, wherein the volume ratio of sulfuric acid to hydrogen peroxide is 3:1; A buffer layer 2 and an active layer 3 are sequentially grown on a silicon carbide substrate 1 by low-pressure chemical vapor deposition to form an epitaxial layer. When growing the buffer layer 2, the growth temperature is 1600-1750° C., the growth pressure is 20-60 Torr, the silicon source gas is silane with a flow rate of 10-30 sccm, the carbon source gas is propane with a flow rate of 5-15 sccm, and the nitrogen source gas is ammonia with a flow rate of 1-5 sccm. When growing the active layer 3, the growth temperature is 1650-1800° C., the growth pressure is 30-80 Torr, the silicon source gas is silane with a flow rate of 20-40 sccm, the carbon source gas is methane with a flow rate of 8-20 sccm, and the phosphorus source gas is phosphine with a flow rate of 0.5-2 sccm. A gate oxide layer 7 is grown on the surface of the active layer 3 by dry oxygen oxidation process, with an oxidation temperature of 950-1050°C and an oxidation time of 60-100 minutes. During the oxidation process, a mixed gas of oxygen and argon is introduced into the reaction chamber with a flow ratio of 1:3-1:5. Nitrogen is introduced into the gate oxide layer 7 by ion implantation process, with an ion implantation energy of 20-50 keV and an implantation dose of 5×10 13 cm -2 -1×10 14 cm -2 After the implantation, the device is annealed in a nitrogen atmosphere at a temperature of 1000-1100°C for 30-60 minutes, and the nitrogen doping concentration is controlled to be 1.2×10 18 cm -3 -1.5×10 20 cm -3 ; Spin-coat photoresist on the gate oxide layer 7. The thickness of the photoresist is 1.5-2.5 μm. Use deep ultraviolet lithography technology for exposure. The exposure energy is 180-250 mJ / cm 2 , forming a gate electrode 8 pattern after development; removing excess gate oxide layer 7 and active layer 3 by reactive ion etching process, etching gas is a mixture of sulfur hexafluoride and oxygen, the flow ratio is 5:1-8:1, and the etching power is 100-200W; The source 4 and drain 10 are formed on the left and right sides of the active layer 3 by ion implantation and annealing. The energy of the ion implantation is 80-150 keV and the implantation dose is 1.2×10 15 -1.8×10 16 cm -2 The implanted element is phosphorus; after implantation, the substrate is annealed in an argon atmosphere at a temperature of 1650-1750°C for 2-4 minutes; titanium / aluminum / nickel / gold multilayer metals are deposited in sequence using an electron beam evaporation process, and the vacuum degree during the deposition process is maintained at 1×10 -5 -5×10 -5 Pa, the deposition rate of the titanium layer is 0.1-0.3 nm / s, the deposition rate of the aluminum layer is 0.5-1 nm / s, the deposition rate of the nickel layer is 0.2-0.5 nm / s, and the deposition rate of the gold layer is 0.3-0.8 nm / s, and then annealed at a temperature of 400-600 ° C for 5-15 minutes through a rapid thermal annealing process to achieve ohmic contact; If the silicon carbide power device includes a field limiting ring 9, before forming the source 4 and the drain 10, a photoresist is spin-coated on the active layer 3. The thickness of the photoresist is 1-3 μm, and the exposure is performed using a photolithography technique with an exposure energy of 150-300 mJ / cm 2After development, a field limiting ring 9 pattern is formed; nitrogen is injected into the field limiting ring 9 region by ion implantation process, the ion implantation energy is 30-80keV, and the implantation dose is 2×10 14 cm 2 -5×10 14 cm 2 After the injection, annealing is performed in a nitrogen atmosphere at a temperature of 1200-1400°C for 20-40 minutes; then the excess active layer 3 is removed by a reactive ion etching process, the etching gas is a mixture of chlorine and argon, the flow ratio is 3:1-5:1, and the etching power is 80-150W.

[0030] Using a mixed solution of sulfuric acid and hydrogen peroxide at a specific temperature and ratio to clean the silicon carbide substrate can effectively remove impurities and pollutants on the substrate surface, improve the cleanliness of the substrate surface, and provide good surface conditions for subsequent epitaxial layer growth.

[0031] By using low-pressure chemical vapor deposition (LPCVD) and precisely controlling the growth temperature, pressure, and gas flow parameters, high-quality buffer layer 2 and active layer 3 can be grown, ensuring the crystal structure integrity and doping uniformity of the epitaxial layer, thereby improving the performance and reliability of the device.

[0032] The gate oxide layer 7 is grown using a dry oxygen oxidation process, and nitrogen is introduced through ion implantation and annealing processes. The quality, thickness and nitrogen doping concentration of the gate oxide layer 7 can be precisely controlled, thereby optimizing the gate control performance and stability of the device.

[0033] The gate electrode 8 pattern is formed by photolithography and etching processes, and the size and shape of the gate electrode 8 can be precisely controlled to ensure the consistency and performance stability of the device.

[0034] The source 4 and drain 10 are formed by ion implantation and annealing processes, and the multilayer metal 5 is deposited by electron beam evaporation process. This can accurately control the doping concentration and depth of the source 4 and drain 10, as well as the ohmic contact quality between the multilayer metal 5 and the active layer 3, thereby improving the conduction performance and current transmission efficiency of the device.

[0035] The field limiting ring 9 is formed through photolithography, ion implantation and etching processes.

[0036] During the growth of the gate oxide layer 7, the flow ratio of the mixed gas of oxygen and argon is 1:3-1:5, and the oxidation time is 45-90 minutes. Furthermore, optimizing the flow ratio of the mixed gas of oxygen and argon and the oxidation time is beneficial to improving the quality and performance of the gate oxide layer 7, such as increasing the density of the gate oxide layer 7 and reducing the interface state density, thereby improving the gate control performance and reliability of the device.

[0037] Before growing the buffer layer 2 and active layer 3, the silicon carbide substrate 1 undergoes hydrogen etching pretreatment at a temperature of 1200-1400°C, for 10-30 minutes, and at a hydrogen flow rate of 50-100 sccm. This removes the oxide layer and impurities on the substrate surface, improves the crystal structure of the substrate surface, enhances the bonding strength between the epitaxial layer and the substrate, reduces defects and dislocations, and thus improves device performance and reliability.

[0038] After the gate electrode 8 pattern is formed, the gate electrode 8 is subjected to a high-temperature annealing treatment at a temperature of 1000-1200° C. for 15-30 minutes in a nitrogen atmosphere. This high-temperature annealing treatment helps eliminate stress and defects generated during the fabrication of the gate electrode 8, improves the crystal structure and electrical properties of the gate electrode 8, and enhances the interface quality between the gate electrode 8 and the gate oxide layer 7.

[0039] After forming the source electrode 4 and the drain electrode 10, the entire silicon carbide power device is passivated. A silicon dioxide passivation layer is deposited using plasma-enhanced chemical vapor deposition (PECVD). The deposition temperature is 300-400°C, the pressure is 10-50 Pa, the silicon source gas is silane with a flow rate of 10-30 sccm, and the oxygen source gas is nitrous oxide with a flow rate of 20-60 sccm. The deposition thickness is 200-500 nm. After forming the source electrode 4 and the drain electrode 10, the entire device is passivated. Depositing the silicon dioxide passivation layer protects the device surface from external environmental influences, reduces surface charge accumulation and scattering, improves the stability and anti-interference capability of the device, and also helps improve the device's insulation performance.

[0040] During the entire preparation process, the background vacuum of the reaction chamber was maintained at 1×10 -6 -5×10 -6 Pa. It is beneficial to reduce the mixing of impurity gases, improve the purity and controllability of the process, ensure the stability and repeatability of each process step, and thus improve the performance and consistency of the device.

[0041] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope of the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A silicon carbide power device, characterized in that: include: A silicon carbide substrate (1) with a square plate-like structure, wherein the surface roughness Ra of the silicon carbide substrate (1) is less than 0.5 nm, the silicon carbide substrate (1) is an n-type silicon carbide substrate, the doping element thereof is nitrogen, and the doping concentration is controlled at 1.2×10 18 cm -3 -1.8×10 20 cm -3 ; The epitaxial layer located on the silicon carbide substrate (1) is composed of a buffer layer (2) and an active layer (3), the buffer layer (2) is closely attached to the upper surface of the silicon carbide substrate (1), and the active layer (3) covers the upper surface of the buffer layer (2); the buffer layer (2) adopts a gradient doping structure, and the doping concentration of the side close to the silicon carbide substrate (1) is 5×10 16 cm -3 , the doping concentration close to the active layer (3) is 2×10 17 cm -3 , the thickness of the buffer layer (2) is 0.8-1.8 μm; The thickness of the active layer (3) is 2.5-4.5 μm, the doping type of the active layer (3) is n-type, the doping element is phosphorus, and the doping concentration is 5×10 16 cm -3 -8×10 16 cm -3 ; The gate structure (6) formed on the active layer (3) includes a gate oxide layer (7) and a gate electrode (8). The gate oxide layer (7) is grown on the upper surface of the active layer (3) by a thermal oxidation process, and is uniformly doped with nitrogen elements. The doping concentration of the nitrogen elements is 1.2×10 18 cm -3 -1.5×10 20 cm -3 The gate structure (6) has a thickness of 8-15 nm; the gate electrode (8) is located on the upper surface of the gate oxide layer (7) and is made of polysilicon material or metal material. When the gate electrode (8) is made of polysilicon material, the doping type of the polysilicon material is p-type, and the ratio of its doping concentration to the doping concentration of the active layer is in the range of 1:5-1:10; The active layer (3) is provided with a source electrode (4) and a drain electrode (10), the source electrode (4) and the active layer (3) are in ohmic contact via a titanium / aluminum / nickel / gold multilayer metal structure (5), the drain electrode (10) passes through the active layer (3) and the buffer layer (2) in sequence, and the drain electrode (10) and the silicon carbide substrate (1) are in ohmic contact via the titanium / aluminum / nickel / gold multilayer metal structure (5); a plurality of field limiting rings (9) are provided on the lower side of the gate structure (6), the field limiting rings (9) and the active layer (3) are arranged in the same layer, the width of the field limiting rings (9) is 2.5-4.5 μm, the spacing between adjacent field limiting rings (9) is 1.2-2.8 μm, and the doping concentration of the field limiting rings (9) is 3×10 17 cm -3 -5×10 17 cm -3 .

2. A silicon carbide power device according to claim 1, characterized in that: In the multi-metal layer (5) between the source electrode (4) and the active layer (3), the thickness of the titanium layer is 50-100 nm, the thickness of the aluminum layer is 500-1000 nm, the thickness of the nickel layer is 100-200 nm, and the thickness of the gold layer is 200-500 nm.

3. The silicon carbide power device according to claim 1, characterized in that: When the gate electrode (8) is made of metal material, the metal material is tungsten or molybdenum, and the thickness of the gate electrode (8) is 300-800 nm.

4. The silicon carbide power device according to claim 1, characterized in that: The thickness of the silicon carbide substrate (1) is 300-600 μm, and the edge of the silicon carbide substrate (1) is provided with a chamfer structure with a width of 1-3 mm.

5. A method for preparing a silicon carbide power device, performed according to a silicon carbide power device according to any one of claims 1 to 4, characterized in that: The following steps are involved: Providing a silicon carbide substrate (1) that has been subjected to chemical mechanical polishing, and placing the silicon carbide substrate (1) in a mixed solution of sulfuric acid and hydrogen peroxide at a temperature of 120-150° C. for cleaning for 15-30 minutes, wherein the volume ratio of sulfuric acid to hydrogen peroxide is 3:1; A buffer layer (2) and an active layer (3) are sequentially grown on a silicon carbide substrate (1) by a low-pressure chemical vapor deposition method to form an epitaxial layer; when growing the buffer layer (2), the growth temperature is 1600-1750° C., the growth pressure is 20-60 Torr, the silicon source gas is silane, the flow rate is 10-30 sccm, the carbon source gas is propane, the flow rate is 5-15 sccm, and the nitrogen source gas is ammonia, the flow rate is 1-5 sccm; when growing the active layer (3), the growth temperature is 1650-1800° C., the growth pressure is 30-80 Torr, the silicon source gas is silane, the flow rate is 20-40 sccm, the carbon source gas is methane, the flow rate is 8-20 sccm, and the phosphorus source gas is phosphine, the flow rate is 0.5-2 sccm; A gate oxide layer (7) is grown on the surface of the active layer (3) using a dry oxygen oxidation process with an oxidation temperature of 950-1050° C. and an oxidation time of 60-100 minutes. During the oxidation process, a mixed gas of oxygen and argon is introduced into the reaction chamber with a flow ratio of 1:3-1:

5. Nitrogen is introduced into the gate oxide layer (7) using an ion implantation process with an ion implantation energy of 20-50 keV and an implantation dose of 5×10 13 cm -2 -1×10 14 cm -2 After the implantation, the device is annealed in a nitrogen atmosphere at a temperature of 1000-1100°C for 30-60 minutes, and the nitrogen doping concentration is controlled to be 1.2×10 18 cm -3 -1.5×10 20 cm -3 ; Spin-coat a photoresist on the gate oxide layer (7), the thickness of the photoresist is 1.5-2.5 μm, and expose it using deep ultraviolet lithography technology with an exposure energy of 180-250 mJ / cm 2 , forming a gate electrode (8) pattern after development; removing the redundant gate oxide layer (7) and the active layer (3) by a reactive ion etching process, wherein the etching gas is a mixed gas of sulfur hexafluoride and oxygen, the flow ratio is 5:1-8:1, and the etching power is 100-200W; A source electrode (4) and a drain electrode (10) are formed on both sides of the active layer (3) by ion implantation and annealing, wherein the energy of the ion implantation is 80-150 keV and the implantation dose is 1.2×10 15 -1.8×10 16 cm -2 The implanted element is phosphorus; after implantation, the substrate is annealed in an argon atmosphere at a temperature of 1650-1750°C for 2-4 minutes; titanium / aluminum / nickel / gold multilayer metals are deposited in sequence using an electron beam evaporation process, and the vacuum degree during the deposition process is maintained at 1×10 -5 -5×10 -5 Pa, the deposition rate of the titanium layer is 0.1-0.3 nm / s, the deposition rate of the aluminum layer is 0.5-1 nm / s, the deposition rate of the nickel layer is 0.2-0.5 nm / s, and the deposition rate of the gold layer is 0.3-0.8 nm / s, and then annealed at a temperature of 400-600 ° C for 5-15 minutes through a rapid thermal annealing process to achieve ohmic contact; If the silicon carbide power device includes a field limiting ring (9), before forming the source (4) and the drain (10), a photoresist is spin-coated on the active layer (3), the thickness of the photoresist is 1-3 μm, and exposure is performed using a photolithography technique with an exposure energy of 150-300 mJ / cm 2 After development, a field limiting ring (9) pattern is formed; nitrogen is injected into the field limiting ring (9) region by an ion implantation process, the ion implantation energy is 30-80 keV, and the implantation dose is 2×10 14 cm 2 - 5×10 14 cm 2 After the injection, the film is annealed in a nitrogen atmosphere at a temperature of 1200-1400° C. for 20-40 minutes; and then the excess active layer (3) is removed by a reactive ion etching process, wherein the etching gas is a mixture of chlorine and argon, the flow ratio is 3:1-5:1, and the etching power is 80-150W.

6. The method for preparing a silicon carbide power device according to claim 5, characterized in that: During the growth of the gate oxide layer (7), the mixed gas flow ratio of oxygen and argon is 1:3-1:5, and the oxidation time is 45-90 minutes.

7. A silicon carbide power device and a method for preparing the same according to claim 5, characterized in that: Before growing the buffer layer (2) and the active layer (3), the silicon carbide substrate (1) is subjected to hydrogen etching pretreatment, with an etching temperature of 1200-1400° C., an etching time of 10-30 minutes, and a hydrogen flow rate of 50-100 sccm.

8. A silicon carbide power device and a method for preparing the same according to claim 5, characterized in that: After forming the gate electrode (8) pattern, the gate electrode (8) is subjected to a high-temperature annealing treatment, wherein the annealing temperature is 1000-1200° C., the annealing time is 15-30 minutes, and the annealing atmosphere is nitrogen.

9. A silicon carbide power device and a method for preparing the same according to claim 5, characterized in that: After forming the source electrode (4) and the drain electrode (10), the entire silicon carbide power device is passivated by using a plasma enhanced chemical vapor deposition method to deposit a silicon dioxide passivation layer, with a deposition temperature of 300-400° C., a deposition pressure of 10-50 Pa, silane as the silicon source gas, with a flow rate of 10-30 sccm, and nitrous oxide as the oxygen source gas, with a flow rate of 20-60 sccm, and a deposition thickness of 200-500 nm.

10. A silicon carbide power device and a method for preparing the same according to claim 5, characterized in that: During the entire preparation process, the background vacuum of the reaction chamber was maintained at 1×10 -6 -5×10 -6 Pa.

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