Asymmetric square cellular MOSFET (metal-oxide-semiconductor field effect transistor) and preparation method thereof

Abstract

The invention relates to an asymmetric square cellular MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a preparation method thereof, and the MOSFET comprises an N-epitaxial layer which is arranged on a substrate layer; the JFET region and the P well region are arranged on the N-epitaxial layer; the N + source region is arranged in the P well region; the P + source region is asymmetrically arranged on one side region of the P well region through ion implantation on the P well region; the gate oxide region is arranged on the N + source region; the gate oxide region covers the JFET region and partially covers the P well region, the N + source region and the P + source region respectively; the gate region, the SiO2 layer and the Si3N4 layer are sequentially arranged on the gate oxide region from bottom to top; the Ni metal region is arranged on the N + source region and is respectively adjacent to the N + source region and the P + source region; and the aluminum metal layer is arranged on the Si3N4 layer. According to the invention, the P + source region is asymmetrically arranged at one side region of the P well region, so that the current carrying capacity is improved and the power density is optimized.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor power device technology, and in particular relates to an asymmetric square cell MOSFET and a preparation method thereof. Background Art

[0002] The development of silicon carbide (SiC) power devices stems from the urgent need for high efficiency, low power consumption, high energy density, and sustainable development in power electronics systems. Compared to silicon, silicon carbide has approximately ten times the breakdown field strength, three times the thermal conductivity, and a wider bandgap. This enables it to be better applied in high-temperature, high-voltage, and high-frequency fields. Using SiC MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) in photovoltaic inverters can improve energy conversion efficiency and reduce energy losses. For example, the high-voltage 800V charging platform for electric vehicles relies on the high power density of silicon carbide. Silicon carbide devices are very promising in defense weapons, industrial motors, and aerospace.

[0003] In the fabrication of traditional square-cell silicon carbide power MOSFET devices, a hole is typically opened in the center of the P-well. The cell is a symmetrical square, with the hole located in the center of the cell. Due to the symmetrical structure, the dimensions of the symmetrical square cell have a minimum value, which determines the channel density and JFET region density, leaving little room for optimization. Therefore, it is necessary to optimize the hole structure of the MOSFET device to increase the channel density and improve the device's on-current capability. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an asymmetric square cell MOSFET and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides an asymmetric square cellular MOSFET, comprising: a substrate layer; an N-epitaxial layer, arranged on the substrate layer; a JFET region and a P-well region, both arranged on the N-epitaxial layer, the P-well region being located in a central region, and the JFET region being located on the periphery of the P-well region; an N+ source region, arranged in the P-well region; a P+ source region, asymmetrically arranged on one side of the P-well region on the P-well region by ion implantation; a gate oxide region, arranged on the N+ source region; the gate oxide region covering the JFET region, and the gate oxide region partially covering the P-well region, the N+ source region and the P+ source region respectively; a gate region, a SiO2 layer and a Si3N4 layer, arranged in sequence from bottom to top on the gate oxide region; a Ni metal region, arranged on the N+ source region and adjacent to the N+ source region and the P+ source region respectively; and an aluminum metal layer, arranged on the Si3N4 layer and adjacent to the SiO2 layer and the Ni metal region respectively.

[0006] In one embodiment of the present invention, the contact area between the Ni metal region and the N+ source region is expressed as follows: x +2L ch -W oxide )*2L x +L x 2 Among them, W x L is the size of the opening when the N+ source region is formed by ion implantation; ch is the channel length; W oxide L is the distance between the edge of the gate region and the edge of the Ni metal region; x It is the distance between the edge of one side of the P+ source region close to the central area of ​​the P well region and the edge of the same side of the Ni metal region.

[0007] In one embodiment of the present invention, the contact area between the Ni metal region and the N+ source region is at least 1 square micron.

[0008] In one embodiment of the present invention, the side length of the gate oxide region is expressed as follows: x +2L ch +L x )+W oxide Among them, W x +2L ch +L x is the side length of the Ni metal area.

[0009] In one embodiment of the present invention, the gate oxide region partially covers the N+ source region, and the minimum size of the N+ source region is expressed as follows: x +2L ch +Lx )+W oxide +2W poly Among them, W poly is the distance between one side edge of the gate region and the same side edge of the N+ source region.

[0010] In one embodiment of the present invention, the minimum size of the P-well region is expressed as: x +4L ch +L x +W oxide +2W poly .

[0011] In one embodiment of the present invention, the expression for the size of the asymmetric square cell MOSFET is: x +4L ch +L x +W oxide +2W poly +W jfet Among them, W jfet is the width of the JFET region.

[0012] The present invention also provides a method for preparing an asymmetric square cellular MOSFET, which is used to prepare the above-mentioned asymmetric square cellular MOSFET. The preparation method comprises:

[0013] Step 1: Clean and remove impurities to prepare a 4H-SiC wafer as the substrate layer;

[0014] Step 2: growing an N-epitaxial layer on the substrate layer by chemical vapor deposition;

[0015] Step 3: forming a JFET region and a P-well region on the N-epitaxial layer by ion implantation;

[0016] Step 4: using a self-aligned process to open a hole in a corner of the P-well region away from the center along a diagonal direction, and forming an N+ source region by ion implantation;

[0017] Step 5: Form a P+ source region at the opening position by ion implantation to form an asymmetric square cell;

[0018] Step 6: growing a gate oxide region on the asymmetric square cell, depositing polysilicon on the gate oxide region 7 to form a gate region 8, and sequentially growing a SiO2 layer 9 and a Si3N4 layer 10 on the gate oxide region 7 and the gate region 8;

[0019] Step 7: Prepare a Ni metal region in the central area, and prepare an aluminum metal layer on the asymmetric square cell with the Ni metal region prepared, thereby completing the preparation of the asymmetric square cell MOSFET.

[0020] In one embodiment of the present invention, the substrate layer has a thickness of 350 μm and is doped with phosphorus at a doping concentration of 2e15 cm -3 .

[0021] In one embodiment of the present invention, the N-epitaxial layer has a thickness of 10 μm and is doped with phosphorus at a doping concentration of 8e15 cm -3 .

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The asymmetric square cellular MOSFET of this invention utilizes an innovative structural design, asymmetrically placing the P+ source region on one side of the P-well region, breaking through the layout limitations of traditional symmetrical cells. Compared to a centrally opened structure, this optimizes the contact between the Ni metal region and the source region, significantly reducing metal overlay redundancy and increasing channel density. This increased channel density offers numerous advantages for power MOSFETs, including lower on-resistance, increased current carrying capacity, and optimized power density. Furthermore, by eliminating spatial redundancy in symmetrical structures, it improves reliability and wafer utilization.

[0024] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic diagram of the density analysis model structure of an existing symmetrical square cell MOSFET;

[0026] Figure 2 1 is a schematic diagram of a cross-sectional structure of an asymmetric square cell MOSFET provided by an embodiment of the present invention;

[0027] Figure 3 Schematic diagram of the density analysis model structure of the asymmetric square cell MOSFET provided by an embodiment of the present invention;

[0028] Figure 4 This is a flow chart of a method for preparing an asymmetric square cell MOSFET provided by an embodiment of the present invention;

[0029] Figures 5a to 5i This is a diagram of the preparation process of the asymmetric square cell MOSFET provided by an embodiment of the present invention.

[0030] Figure numerals: 1-substrate layer; 2-N-epitaxial layer; 3-JFET region; 4-P-well region; 5-N+ source region; 6-P+ source region; 7-gate oxide region; 8-gate region; 9-SiO2 layer; 10-Si3N4 layer; 11-Ni metal region; 12-aluminum metal layer. DETAILED DESCRIPTION

[0031] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of an asymmetric square cell MOSFET and a preparation method thereof proposed in accordance with the present invention in combination with the accompanying drawings and specific implementation methods.

[0032] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0033] Example 1

[0034] like Figure 1 As shown, Figure 1 This is a schematic diagram of the density analysis model structure of an existing symmetrical square cell MOSFET. In a symmetrical square cell, the Ni metal layer fully covers the P+ source region and must also cover a certain area of ​​the N+ source region. This results in a minimum Ni metal layer size. Due to gate-source isolation requirements, the gate oxide region must extend to a certain width to prevent reliability issues caused by gate-source shorting or local electric field concentration. This width is also subject to process limitations, so the square area enclosed by the gate oxide region also has a minimum size, currently around 0.6μm. Furthermore, the gate must cover a certain width of the N+ source region (approximately 0.3μm) to prevent the channel from turning on, which also results in a minimum N+ source size. The channel length also has certain requirements: it cannot be too long to prevent excessive channel resistance, nor too short to prevent the short channel effect. Therefore, the P-well region also has a minimum size. Furthermore, if the JFET region width is too large, the resistance of the JFET region will increase. If the width is too small, it will be limited by process and reliability. Therefore, the JFET region is generally set to 1.5-3μm. Under the above-mentioned constraints, the size of a cell has a minimum value, and the size of this value determines the channel density and JFET area density. On this basis, the minimum value of the cell size is optimized through structural optimization to increase the channel density, thereby increasing the device's on-current capability and improving reliability while reducing power consumption. In view of this, the first aspect of the present invention provides an asymmetric square cell MOSFET, such as Figure 2As shown, Figure 2 It is a schematic diagram of the cross-sectional structure of an asymmetric square cell MOSFET provided by an embodiment of the present invention.

[0035] In this embodiment, the asymmetric square cellular MOSFET includes: a substrate layer 1, an N-epitaxial layer 2, a JFET region 3, a P-well region 4, an N+ source region 5, a P+ source region 6, a gate oxide region 7, a gate region 8, a SiO2 layer 9, a Si3N4 layer 10, a Ni metal region 11 and an aluminum metal layer 12.

[0036] Specifically, the N-epitaxial layer 2 is arranged on the substrate layer 1; the JFET region 3 and the P-well region 4 are both arranged on the N-epitaxial layer 2, the P-well region 4 is located in the central area, and the JFET region 3 is located on the periphery of the P-well region 4; the N+ source region 5 is arranged in the P-well region 4; the P+ source region 6 is asymmetrically arranged on one side of the P-well region 4 on the P-well region 4 by ion implantation; the gate oxide region 7 is arranged on the N+ source region 5; the gate oxide region 7 covers the JFET region 3, and the gate oxide region 7 partially covers the P-well region 4, the N+ source region 5 and the P+ source region 6 respectively; the gate region 8, the SiO2 layer 9 and the Si3N4 layer 10 are arranged on the gate oxide region 7 in sequence from bottom to top; the Ni metal region 11 is arranged on the N+ source region 5, and is adjacent to the N+ source region 5 and the P+ source region 6 respectively; the aluminum metal layer 12 is arranged on the Si3N4 layer 10, and is adjacent to the SiO2 layer 9 and the Ni metal region 11 respectively.

[0037] For example, when forming the N+ source region 5 by ion implantation, it is necessary to open a hole to form a square region. Specifically, the square region is formed by a self-alignment process, and its side length is W. x +2L ch .

[0038] For example, when forming the gate oxide region 7, it covers the entire upper surface of the device. The corresponding area will be etched away during the subsequent fabrication of the structure. Therefore, the gate oxide region 7 needs to cover a portion of the P+ source region 6, a portion of the N+ source region 5, the P-well region 4 between the N+ source region 5 and the JFET region 3, and all of the JFET region 3.

[0039] In an optional embodiment, the contact area between the Ni metal region 11 and the N+ source region 5 is expressed as:

[0040] (W x +2L ch -W oxide )*2L x +L x 2 ;

[0041] Among them, W x L is the size of the opening when the N+ source region 5 is formed by ion implantation; chis the channel length, i.e. the width of the P-well region 4 between the N+ source region 5 and the JFET region 3; W oxide L is the distance between the edge of the gate region 8 and the edge of the Ni metal region 11; x It is the distance between one side edge of the P+ source region 6 close to the central area of ​​the P well region 4 and the same side edge of the Ni metal region 11 .

[0042] Preferably, the contact area between the Ni metal region 11 and the N+ source region 5 is at least 1 square micron.

[0043] In an optional embodiment, the side length of the gate oxide region 7 is expressed as:

[0044] (W x +2L ch +L x )+W oxide ;

[0045] Among them, W x +2L ch +L x is the side length of the Ni metal region 11 .

[0046] In an optional embodiment, the gate oxide region 7 partially covers a portion of the N+ source region 5, and the minimum size of the N+ source region 5 is expressed as:

[0047] (W x +2L ch +L x )+W oxide +2W poly ;

[0048] Among them, W poly is the distance between one side edge of the gate region 8 and the same side edge of the N+ source region 5. In an optional embodiment, the minimum size of the P-well region 4 is expressed as:

[0049] W x +4L ch +L x +W oxide +2W poly .

[0050] In an optional embodiment, the expression for the size of the asymmetric square cell MOSFET is:

[0051] W x +4L ch +L x +W oxide +2W poly +W jfet ;

[0052] Among them, Wjfet is the width of the JFET region 3.

[0053] Based on the same inventive concept, the second aspect of the present invention provides a method for preparing an asymmetric square cellular MOSFET, which is used to prepare the asymmetric square cellular MOSFET of the first aspect. The preparation method provided by the present invention is described in detail below with reference to the accompanying drawings.

[0054] like Figure 4 、 Figures 5a to 5i As shown, Figure 4 This is a flow chart of a method for preparing an asymmetric square cell MOSFET provided by an embodiment of the present invention; Figures 5a to 5i : is a diagram of a process for preparing an asymmetric square cell MOSFET provided by an embodiment of the present invention. The method specifically includes the following steps:

[0055] Step 1: Clean and remove impurities, and prepare a 4H-SiC wafer as substrate layer 1;

[0056] Step 2: Grow an N-epitaxial layer 2 on the substrate layer 1 by chemical vapor deposition.

[0057] In an optional embodiment, the substrate layer 1 has a thickness of 350 μm and is doped with phosphorus at a doping concentration of 2e15 cm -3 .

[0058] In an optional embodiment, the N-epitaxial layer 2 has a thickness of 10 μm and is doped with phosphorus at a doping concentration of 8e15 cm -3 .

[0059] Step 3: forming a JFET region 3 and a P-well region 4 on the N-epitaxial layer 2 by ion implantation;

[0060] Step 4: A hole is opened in a corner of the P-well region 4 away from the center region along a diagonal direction using a self-aligned process, and an N+ source region 5 is formed by ion implantation;

[0061] Step 5: forming a P+ source region 6 at the opening position by ion implantation to form an asymmetric square cell;

[0062] Step 6: A gate oxide region 7 is grown on the asymmetric square cell, polysilicon is deposited on the gate oxide region 7 to form a gate region 8, and a SiO2 layer 9 and a Si3N4 layer 10 are sequentially grown on the gate oxide region 7 and the gate region 8;

[0063] Step 7: Prepare a Ni metal region 11 in the central area, and prepare an aluminum metal layer 12 on the asymmetric square cell with the Ni metal region 11, thereby completing the preparation of the asymmetric square cell MOSFET.

[0064] Specifically, a 4H-SiC wafer is first prepared as a substrate layer 1, organic impurities and metal impurities are removed by cleaning, and then a low-doping concentration N-epitaxial layer 2 is grown on the substrate layer 1 by chemical vapor deposition as a voltage-resistant layer. Figure 5a and Figure 5b As shown, the thickness of the N-epitaxial layer 2 can be set according to the withstand voltage requirement. Secondly, the JFET region 3 and the P-well region 4 are formed on the N-epitaxial layer 2 by ion implantation. A hole is opened in a corner of the P-well region 4 away from the center area along the diagonal direction using a self-aligned process, such as the lower left corner. Then, an N+ source region 5 is formed by ion implantation, as shown in FIG. Figure 5c Next, a P+ source region 6 is formed at the opening position by ion implantation to form an asymmetric square cell, as shown in FIG. Figure 5d Then, a gate oxide region 7 is grown on the asymmetric square cell, so that the gate oxide region 7 partially covers the N+ source region 5 and reserves a position for the Ni metal region 11, and field oxygen isolation is formed through the gate oxide region 7, as shown in FIG. Figure 5e To prevent the gate from not fully covering the channel due to overlay deviation, which in turn causes the device to not turn on, polysilicon is deposited on the gate oxide region 7 to form a gate region 8, and the gate region 8 covers a certain area of ​​the N+ source region 5 along the projection direction, as shown in FIG. Figure 5f As shown. A SiO2 layer 9 and a Si3N4 layer 10 are sequentially grown on the gate oxide region 7 and the gate region 8. For example, the SiO2 layer 9 is formed by thermal oxidation, and the Si3N4 layer 10 is formed by PECVD deposition, as shown. Figure 5g Finally, a Ni metal region 11 is prepared in the central region, as shown in FIG. Figure 5h As shown, an aluminum metal layer 12 is prepared on the asymmetric square cell of the prepared Ni metal region 11, as shown Figure 5i As shown, at this point, the preparation of the asymmetric square cell MOSFET is completed.

[0065] It should be noted that the chemical vapor deposition process, self-aligned process, PECVD process, ion implantation process, etc. used in the preparation of the asymmetric square cellular MOSFET in this embodiment are all existing mature processes, and the corresponding parameter settings can be implemented by referring to existing related technologies. In addition, the preparation method provided in the second aspect of the present invention can be used to prepare the asymmetric square cellular MOSFET provided in the first aspect, and therefore has similar beneficial effects as the device embodiment of the first aspect. For technical details not disclosed in the preparation method embodiment of the present invention, please refer to the description of the device embodiment for understanding.

[0066] In order to further illustrate the advantage of the asymmetric square cell MOSFET of the first aspect of the present invention over the existing symmetric square cell in terms of channel density, in the third aspect of the present invention, channel density analysis models of the existing symmetric square cell and the asymmetric square cell MOSFET of the first aspect of the present invention are established, respectively. Figure 1 and Figure 3 As shown, Figure 3 Schematic diagram of the density analysis model structure of the asymmetric square cell MOSFET provided by an embodiment of the present invention.

[0067] Taking the density analytical model of the existing symmetrical square cell as an example, after forming the P-well region on the N-epitaxial layer by ion implantation, a hole is opened in the central area of ​​the P-well region. After the self-alignment process is completed, the size of the hole is W. x +2L ch In addition to covering the P+ source region, the Ni metal layer also covers a certain area of ​​the N+ source region to ensure the normal conduction capability of the device. For example, the contact area between the two is 1 square micron, and the distance from the Ni metal layer to the boundary of the P+ source region can be defined as W Ni The contact area between the Ni metal layer and the N+ source region is 4*(W x +2L ch )*W Ni +4W Ni 2 =1, then W Ni =0.12, the size of the Ni metal layer is W x +2L ch +2W Ni The side length of the gate oxide region generated by gate-source isolation is W x +2L ch +2W Ni +2W oxide Through gate-source isolation, electrical isolation can be achieved to prevent short circuit between gate and source. It also plays a role in modulating the electric field at the gate edge to prevent breakdown caused by electric field concentration. In addition, it also plays a role in parasitic capacitance control, which can reduce gate-source capacitance and increase switching speed. In order to prevent the existence of overlay deviation, the gate does not cover the entire channel. Therefore, the gate must cover a certain size of the N+ source region. Therefore, the minimum size of the N+ source region is W x +2L ch +2W Ni +2W oxide +2W poly During the self-alignment process, a length of L is formed. ch The channel also makes the size of the opening become W x +2L ch , so the minimum size of the P-well region 4 is W x +4L ch +2WNi +2W oxide +2W poly The width of the JFET region is defined as W ifet When the device is turned on, the current flows from the drain to the source through the channel and must pass through the JFET region. The resistance of the JFET region is proportional to the inverse of the width of the JFET region. When the device is blocked, the JFET region must withstand a large voltage, which affects the device's withstand voltage characteristics. Therefore, there are requirements for the width of the JFET region. The width of the JFET region is defined as W. jfet , so the size of an existing symmetric square cell is W x +4L ch +2W Ni +2W oxide +2W poly +2W jfet .

[0068] Taking the density analytical model of preparing asymmetric square cell MOSFET as an example, the position of the opening is set at the edge of the gate oxide region 7, such as the lower left corner, the opening area is 1 square micron, and the size of the P+ source region 6 after the self-alignment process is W x +2L ch Similarly, in order to ensure the normal conduction of the device, the contact area between the Ni metal region 11 and the N+ source region 5 is at least 1 square micron. The distance between the central boundary of the P well region 4 of the P+ source region 6 and the right boundary of the Ni metal region 11 is L. x , then the expression of contact area is (W x +2L ch -2W oxide )*2L x +L x 2 =1, where W x , L ch and W oxide The sizes of are 1μm, 0.5μm and 0.6μm respectively, then L x is about 0.32μm, and the size of the Ni metal area 11 is W x +2L ch +L x The side length of the gate oxide region 7 generated by the gate-source isolation is W x +2L ch +L x +W oxide , the minimum size of the N+ source region 5 is W x +2L ch +L x +W oxide +2W poly During the self-alignment process, a length of L is formed. ch The channel also makes the size of the opening become W x+2L ch , so the minimum size of the P-well region 4 is W x +2L ch +L x +W oxide +2W poly The width of the JFET region 3 is defined as W ifet , then the size of the asymmetric square cell MOSFET is W x +4L ch +L x +W oxide +2W poly +W ifet .

[0069] In order to more intuitively compare the ability of asymmetric openings to improve the channel density and JFET region 3 density, the classic sizes of the relevant parameters of the two analytical models are summarized, as shown in Table 1.

[0070] Table 1 Dimensions of the two analytical models

[0071] Wx <![CDATA[L ch ]]> <![CDATA[W oxide ]]> <![CDATA[W poly ]]> <![CDATA[W Ni ]]> Lx <![CDATA[W ifet ]]> 1 0.5 0.6 0.3 0.12 0.32 2

[0072] Based on the above two analytical models, three channel density definition methods (channel inner width, channel middle width and channel outer width) are used for calculation:

[0073] The channel density of a power MOSFET is usually defined as the effective channel width per unit chip area, which directly affects the device's on-resistance and current drive capability. The basic definition of channel density is:

[0074]

[0075] Where D is the channel density; W total is the total width of all parallel channels; A is the active area of ​​the chip.

[0076] For symmetric cells and asymmetric square cells, the formula for calculating the channel density is the same, and the expression is:

[0077]

[0078] Wherein, W1 is the single-side channel width of the symmetrical square cell or the asymmetrical square cell.

[0079] Calculated using the inner width of the channel, the channel density of the symmetrical square cell is:

[0080]

[0081] The channel density of the asymmetric square cell is:

[0082]

[0083] Using the middle width of the channel, the channel density of the symmetrical square cell is calculated as:

[0084]

[0085] The channel density of the asymmetric square cell is:

[0086]

[0087] Using the outer width of the channel to calculate, the channel density of the symmetrical square cell is:

[0088]

[0089] The channel density of the asymmetric square cell is:

[0090]

[0091] It can be seen that any of the three methods above, including asymmetric openings and asymmetric arrangement of the P+ source region 6, can increase channel density and optimize the effective chip area, thereby achieving the goals of reducing on-resistance, improving current driving capability, optimizing power density, and enhancing reliability.

[0092] The asymmetric square cellular MOSFET of this invention overcomes the layout limitations of traditional symmetrical cellular structures through an innovative structural design, asymmetrically placing the P+ source region on one side of the P-well region. Compared to a centrally opened structure, this optimizes the contact between the Ni metal region and the source region, significantly reducing metal overlay redundancy and increasing channel density. This increased channel density offers numerous advantages for power MOSFETs, including lower on-resistance, increased current carrying capacity, and optimized power density. Furthermore, by eliminating spatial redundancy in symmetrical structures, it improves reliability and wafer utilization.

[0093] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0094] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. An asymmetric square cell MOSFET, characterized in that: include: substrate layer (1); An N-epitaxial layer (2) is disposed on the substrate layer (1); The JFET region (3) and the P-well region (4) are both arranged on the N-epitaxial layer (2), the P-well region (4) is located in the central region, and the JFET region (3) is located on the periphery of the P-well region (4); An N+ source region (5) is disposed in the P well region (4); A P+ source region (6) is asymmetrically arranged on a side region of the P-well region (4) by ion implantation on the P-well region (4); A gate oxide region (7) is provided on the N+ source region (5); the gate oxide region (7) covers the JFET region (3), and the gate oxide region (7) partially covers the P well region (4), the N+ source region (5), and the P+ source region (6); A gate region (8), a SiO2 layer (9) and a Si3N4 layer (10) are sequentially arranged on the gate oxide region (7) from bottom to top; A Ni metal region (11) is disposed on the N+ source region (5) and is adjacent to the N+ source region (5) and the P+ source region (6) respectively; An aluminum metal layer (12) is disposed on the Si3N4 layer (10) and is adjacent to the SiO2 layer (9) and the Ni metal region (11) respectively.

2. The asymmetric square cell MOSFET according to claim 1, characterized in that: The expression for the contact area between the Ni metal region (11) and the N+ source region (5) is: (W x +2L ch -W oxide )*2L x +L x 2 ; Among them, W x L is the size of the opening when the N+ source region (5) is formed by ion implantation; ch is the channel length; W oxide L is the distance between the edge of the gate region (8) and the edge of the Ni metal region (11); x It is the distance between the edge of one side of the P+ source region (6) close to the central area of ​​the P well region (4) and the edge of the same side of the Ni metal region (11).

3. The asymmetric square cell MOSFET according to claim 2, characterized in that: The contact area between the Ni metal region (11) and the N+ source region (5) is at least 1 square micron.

4. The asymmetric square cell MOSFET according to claim 1, characterized in that: The expression for the side length of the gate oxide region (7) is: (W x +2L ch +L x )+W oxide ; Among them, W x +2L ch +L x is the side length of the Ni metal region (11).

5. The asymmetric square cell MOSFET according to claim 1, characterized in that: The gate oxide region (7) partially covers a portion of the N+ source region (5), and the minimum size of the N+ source region (5) is expressed as: (W x +2L ch +L x )+W oxide +2W poly ; Among them, W poly is the distance between one side edge of the gate region (8) and the same side edge of the N+ source region (5).

6. The asymmetric square cell MOSFET according to claim 1, characterized in that: The expression for the minimum size of the P-well region (4) is: <h2 style=";text-align:left;direction:ltr">W<h2 style=";text-align:left;direction:ltr"> x <h2 style=";text-align:left;direction:ltr"> +4L<h2 style=";text-align:left;direction:ltr"> ch <h2 style=";text-align:left;direction:ltr"> +L<h2 style=";text-align:left;direction:ltr"> x <h2 style=";text-align:left;direction:ltr"> +W<h2 style=";text-align:left;direction:ltr"> oxide <h2 style=";text-align:left;direction:ltr"> +2W<h2 style=";text-align:left;direction:ltr"> poly <h2 style=";text-align:left;direction:ltr"> 。 7. The asymmetric square cell MOSFET according to claim 1, characterized in that: The expression for the size of an asymmetric square cell MOSFET is: <h2 style=";text-align:left;direction:ltr">W<h2 style=";text-align:left;direction:ltr"> x <h2 style=";text-align:left;direction:ltr"> +4L<h2 style=";text-align:left;direction:ltr"> ch <h2 style=";text-align:left;direction:ltr"> +L<h2 style=";text-align:left;direction:ltr"> x <h2 style=";text-align:left;direction:ltr"> +W<h2 style=";text-align:left;direction:ltr"> oxide <h2 style=";text-align:left;direction:ltr"> +2W<h2 style=";text-align:left;direction:ltr"> poly <h2 style=";text-align:left;direction:ltr"> +W<h2 style=";text-align:left;direction:ltr"> jfet <h2 style=";text-align:left;direction:ltr"> ; Among them, W jfet is the width of the JFET region (3).

8. A method for preparing an asymmetric square cell MOSFET, characterized in that: For preparing the asymmetric square cell MOSFET according to any one of claims 1 to 7, the preparation method comprises: Step 1: Clean and remove impurities to prepare a 4H-SiC wafer as the substrate layer; Step 2: growing an N-epitaxial layer on the substrate layer by chemical vapor deposition; Step 3: forming a JFET region and a P-well region on the N-epitaxial layer by ion implantation; Step 4: using a self-aligned process to open a hole in a corner of the P-well region away from the center along a diagonal direction, and forming an N+ source region by ion implantation; Step 5: Form a P+ source region at the opening position by ion implantation to form an asymmetric square cell; Step 6: growing a gate oxide region on the asymmetric square cell, depositing polysilicon on the gate oxide region 7 to form a gate region 8, and sequentially growing a SiO2 layer 9 and a Si3N4 layer 10 on the gate oxide region 7 and the gate region 8; Step 7: Prepare a Ni metal region in the central area, and prepare an aluminum metal layer on the asymmetric square cell with the Ni metal region prepared, thereby completing the preparation of the asymmetric square cell MOSFET.

9. The method for preparing an asymmetric square cell MOSFET according to claim 8, wherein: The thickness of the substrate layer is 350 μm and phosphorus-doped with a doping concentration of 2e15 cm -3 .

10. The method for preparing an asymmetric square cell MOSFET according to claim 8, wherein: The thickness of the N-epitaxial layer is 10 μm and it is doped with phosphorus at a doping concentration of 8e15 cm -3 .

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