Field effect transistor

Abstract

The field effect transistor comprises a silicon carbide N + substrate, an N-type drift region, a P well and a P column, the N-type drift region is formed above the silicon carbide N + substrate, the P well is formed above the N-type drift region, and the P column is arranged in the N-type drift region and located below the P well. According to the field effect transistor provided by the embodiment of the invention, the P column is injected below the P well, so that the short-circuit endurance capability of the device is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor device technology, and in particular relates to a field effect transistor. Background Art

[0002] Silicon carbide (SiC) vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOSFETs), due to their high breakdown field strength, excellent thermal conductivity, and high-frequency characteristics, have become core components in high-voltage, high-power systems such as new energy vehicles and photovoltaic inverters. However, their reliability under short-circuit conditions still faces severe challenges. When a short-circuit fault occurs, the bus voltage is directly applied to the device. After the gate is turned on, the excessive current density causes a transient temperature rise within the device. The temperature rise rate far exceeds that of silicon-based devices, resulting in a significant reduction in the short-circuit withstand time (SCWT), seriously affecting the safe operation of the system.

[0003] While the industry can currently improve short-circuit withstand capabilities to a limited extent by optimizing cell structure and cell size, existing structural improvements have reached their limits due to the inherent properties of SiC materials and require sacrificing device conduction performance to achieve limited improvements. Short short-circuit withstand times struggle to meet the stringent robustness requirements of industrial and automotive-grade power systems. Therefore, achieving increased short-circuit withstand time through innovative device structural design while maintaining forward conduction characteristics has become a key path to breaking through the bottleneck of improving short-circuit withstand capabilities. Summary of the Invention

[0004] In response to the problems existing in the above-mentioned related technologies, an embodiment of the present application provides a field effect transistor, which improves the short-circuit tolerance of the device by injecting a P column under the P well.

[0005] An embodiment of the present application provides a field effect transistor, including a silicon carbide N+ substrate, an N-type drift region, a P-well and a P-pillar, wherein the N-type drift region is formed above the silicon carbide N+ substrate, the P-well is formed above the N-type drift region, and the P-pillar is arranged inside the N-type drift region and below the P-well.

[0006] Furthermore, the doping concentration of the P column is consistent with that of the P well.

[0007] Furthermore, there are multiple P-pillars, and the lengths of the multiple P-pillars are shortened successively.

[0008] Furthermore, the plurality of P pillars are arranged at equal intervals.

[0009] Furthermore, the widths of the multiple P-pillars are consistent.

[0010] Furthermore, it also includes a P+ body region and an N+ source region, and the P+ body region and the N+ source region are arranged inside the P well.

[0011] Furthermore, it also includes a gate oxide, and the gate oxide is arranged above the N-type drift region.

[0012] Furthermore, it also includes a polysilicon gate, which is arranged inside the gate oxide.

[0013] Furthermore, it also includes a metal source, which is arranged above the P+ body region, the N+ source region and the gate oxide, and is in contact with the P+ body region, the N+ source region and the gate oxide.

[0014] Furthermore, a metal drain is included, and the metal drain is arranged below the silicon carbide N+ substrate.

[0015] The field-effect transistor provided in the embodiments of the present application includes a silicon carbide N+ substrate, an N-type drift region, a P-well, and a P-pillar. The N-type drift region is formed above the silicon carbide N+ substrate, the P-well is formed above the N-type drift region, and the P-pillar is disposed within the N-type drift region and below the P-well. By injecting the P-pillar below the P-well, a portion of the short-circuit current flow path is blocked, reducing the short-circuit current. This also increases the base diffusion length of a portion of the parasitic BJT transistor, thereby suppressing conduction of the parasitic transistor and ultimately improving the short-circuit withstand capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0017] Figure 1 A schematic diagram of the structure of a field effect transistor provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram comparing the improved effects of the field effect transistor provided in the embodiments of the present application;

[0019] Figure 3 A schematic diagram comparing the output characteristics of the field effect transistors provided in the embodiments of the present application.

[0020] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0022] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0023] It should also be understood that the terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. Those of ordinary skill in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0024] See Figure 1 , an embodiment of the present application provides an embodiment of the present application provides a field effect transistor, including a silicon carbide N+ substrate 1, an N-type drift region 2, a P-well 4 and a P-pillar 3, the N-type drift region 2 is formed above the silicon carbide N+ substrate 1, the P-well 4 is formed above the N-type drift region 2, and the P-pillar 3 is arranged inside the N-type drift region 2 and located below the P-well 4.

[0025] Specifically, the embodiments of the present application provide a silicon carbide (SiC) vertical double diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET), wherein the N+ substrate 1 is the base layer of the FET and is composed of a high concentration of N-type (negatively charged) doped silicon carbide material. N+ indicates that the layer has a high free electron concentration, which helps to provide good electrical conductivity and thermal stability. Silicon carbide (SiC) as a substrate material, due to its high hardness, high thermal conductivity and wide bandgap characteristics, enables this FET to withstand high temperature and high power operation, and is suitable for power electronics applications.

[0026] The N-type drift region 2, located above the N+ substrate 1, is also made of N-type doped silicon carbide, but with a lower doping concentration (relative to the N+ substrate). The drift region is designed to provide an area for smooth current flow while withstanding high voltages during FET operation. A thicker drift region supports higher blocking voltages but also increases the device's on-resistance.

[0027] The P-pillar 3 is a structure embedded within the N-type drift region, and its material is P-type (positively charged) doped silicon carbide. The presence of the P-pillar can significantly affect the electrical performance of the FET. The presence of the P-pillar will slightly increase the on-resistance of the device, but the device's electric field distribution will be more uniform, and it can improve the short-circuit capability with minimal impact on the on-resistance, thereby improving the reliability of the device. In addition, the P-pillar can also serve as a charge balancing structure, helping to increase the breakdown voltage of the device.

[0028] The P-well 4, located above the N-type drift region 2, is the controlled region of the FET. By applying a suitable electric field to this region, the FET can be turned on and off. When the gate voltage is high enough, a conductive channel forms at the interface above the P-well 4, allowing current to flow from the source (typically connected to the P-well 4) to the drain.

[0029] In summary, refer to Figure 2 and Figure 3 Compared with the existing field effect transistor, the field effect transistor provided by the embodiment of the present application includes a silicon carbide N+ substrate 1, an N-type drift region 2, a P-well 4 and a P-pillar 3. The N-type drift region 2 is formed above the silicon carbide N+ substrate, the P-well is formed above the N-type drift region, and the P-pillar is arranged inside the N-type drift region and below the P-well. By injecting the P-pillar 3 below the P-well 4, part of the flow path of the short-circuit current is blocked, the magnitude of the short-circuit current is reduced, and at the same time, the base diffusion length of part of the parasitic BJT transistor is increased, thereby suppressing the conduction of the parasitic transistor, and ultimately improving the short-circuit tolerance of the device. In addition, as Figure 3 As shown, compared to the traditional SiC VDMOSFET structure, the multi-P pillar structure has only a slight decrease in drain current at the same gate voltage and drain voltage, that is, a slight decrease in conduction capability. Furthermore, in some embodiments of the present application, the doping concentration of the P pillar 3 is consistent with that of the P well 4.

[0030] Specifically, the doping concentration of the P-pillar is set to be consistent with that of the P-well, which first helps to achieve a more uniform charge distribution when the FET is operating. This not only enhances the uniformity of the device's electric field distribution and reduces the risk of local overheating and electric field concentration, but also improves the device's breakdown voltage and reliability. Secondly, consistent doping concentration helps simplify the FET manufacturing process. During the manufacturing process, there is no need to adjust the doping concentration for the P-pillar and P-well separately, thereby reducing production complexity and cost.

[0031] Further, refer again to Figure 1 In some embodiments of the present application, there are multiple P-pillars 3 , and the lengths of the multiple P-pillars 3 are shortened sequentially.

[0032] Specifically, multiple P-pillar structures with successively shorter lengths can more effectively manage the electric field distribution within the FET. The shorter P-pillar 3 can minimize the impact on the current flow path during normal device operation, while effectively "blocking" the flow path of short-circuit current in the N-type drift region, thereby reducing short-circuit current and improving the device's short-circuit withstand capability. Secondly, it also helps to enhance the uniformity of the electric field distribution, reduce the risk of local electric field concentration, and further increase the device's breakdown voltage.

[0033] like Figure 1 As shown, in some embodiments of the present application, there are four P-pillars 3, each of which is shortened in length. When the device enters a short-circuit state, the four P-pillars 3-1, 3-2, 3-3, and 3-4 reduce the short-circuit current flow path in the N-drift region to a certain extent, thereby reducing the short-circuit current. Furthermore, the four P-pillars can extend the base region of the parasitic BJT, making it more difficult for it to parasitically turn on, thereby improving the device's short-circuit withstand capability.

[0034] It should be noted that the above-mentioned structure of four P pillars can actually also be designed with 3P pillars, 2P pillars, or even 1P pillars to achieve improved short-circuit tolerance. However, the fewer the number of pillars, the worse the short-circuit tolerance effect, but it is simpler to manufacture and has a lower cost. Vice versa, it can also be designed with 5P pillars or more.

[0035] Furthermore, in some embodiments of the present application, the plurality of P pillars 3 are arranged at equal intervals.

[0036] Specifically, the equally spaced P-pillar layout helps to further optimize the electric field distribution inside the FET. When the P-pillars 3 are arranged at uniform intervals, they can more effectively "disperse" the electric field, reduce the phenomenon of local electric field concentration, and thus improve the breakdown voltage and long-term reliability of the device. Secondly, the equally spaced P-pillar design also helps to simplify the manufacturing process of the FET. During the manufacturing process, there is no need to individually position and adjust the spacing for each P-pillar, thereby reducing production complexity and cost. This standardized manufacturing process is also easier to achieve automation and large-scale production, improving production efficiency.

[0037] Furthermore, in some embodiments of the present application, the widths of the plurality of P-pillars 3 are consistent.

[0038] Specifically, the multiple P pillars 3 are equally spaced and have uniform widths, maintaining a uniform distribution of the electric field within the FET, preventing breakdown caused by excessive local electric fields, and improving the device's breakdown voltage and long-term reliability. Furthermore, this design simplifies the manufacturing process, reduces production complexity and costs, and facilitates automated and large-scale production.

[0039] Furthermore, in some embodiments of the present application, the field effect transistor further includes a P+ body region 5 and an N+ source region 6 , and the P+ body region 5 and the N+ source region 6 are arranged inside the P well 4 .

[0040] Specifically, the P+ body region 5 in the silicon carbide VDMOSFET is designed to make the P-well 4 form an ohmic contact with the metal source region above, so that the N+ source region 6 and the P+ body region 5 are short-circuited, thereby suppressing parasitic effects. Secondly, it can also optimize the body diode to reduce switching losses and improve reverse recovery. Finally, it can also optimize the electric field distribution of the P-well 4, increase the breakdown voltage, and avoid local breakdown.

[0041] Furthermore, in some embodiments of the present application, the field effect transistor further includes a gate oxide 9 , and the gate oxide 9 is disposed above the N-type drift region 2 .

[0042] Specifically, gate oxide 9, located above the N-type drift region 2, plays a crucial role as an insulating layer between the gate and the FET channel. It not only isolates the gate from the channel, preventing gate current from flowing directly into the channel, but also influences the gate's ability to control the channel through its thickness and dielectric constant. The presence of gate oxide 9 enables the FET to precisely control the flow of current by turning the channel on or off by controlling the gate voltage.

[0043] Furthermore, in some embodiments of the present application, the field effect transistor further includes a polysilicon gate 8 , and the polysilicon gate 8 is disposed inside the gate oxide 9 .

[0044] Specifically, the polysilicon gate 8 is disposed within the gate oxide 9 and, together with the gate oxide 9, forms the control structure of the FET. The polysilicon gate 8 acts as a carrier of the gate voltage, forming a capacitive coupling with the FET channel through the gate oxide 9, thereby achieving precise control of the channel conductivity. The introduction of the polysilicon gate not only improves the gate's conductivity but also enhances the gate's ability to control the channel, further improving the FET's switching performance.

[0045] Furthermore, in some embodiments of the present application, the field effect transistor also includes a metal source 7-2, which is arranged above the P+ body region 5, the N+ source region 6 and the gate oxide 9, and is in contact with the P+ body region 5, the N+ source region 6 and the gate oxide 9.

[0046] Specifically, the metal source 7-2 is disposed above the P+ body region 5, the N+ source region 6, and the gate oxide 9, and forms good electrical contact with them. As the electron input terminal of the FET, the metal source 7-2 not only provides good conductivity, ensuring that electrons can efficiently flow into the channel region of the FET, but also enhances the switching speed and efficiency of the FET through its excellent electrical contact performance.

[0047] Furthermore, in some embodiments of the present application, the field effect transistor further includes a metal drain 7 - 1 , and the metal drain 7 - 1 is disposed below the silicon carbide N+ substrate 1 .

[0048] Specifically, the metal drain 7-1 is disposed below the silicon carbide N+ substrate 1 and serves as the electron output terminal of the FET, forming a good electrical contact with the silicon carbide N+ substrate 1. This design ensures that electrons can efficiently flow out of the FET, improving the current handling capability and efficiency of the FET.

[0049] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A field effect transistor, characterized in that: The invention comprises a silicon carbide N+ substrate, an N-type drift region, a P-well and a P-column, wherein the N-type drift region is formed above the silicon carbide N+ substrate, the P-well is formed above the N-type drift region, and the P-column is arranged inside the N-type drift region and below the P-well.

2. The field effect transistor according to claim 1, wherein The doping concentration of the P column is consistent with that of the P well.

3. The field effect transistor according to claim 2, wherein There are multiple P-pillars, and the lengths of the multiple P-pillars are shortened successively.

4. The field effect transistor according to claim 3, wherein The multiple P pillars are arranged at equal intervals.

5. The field effect transistor according to claim 4, wherein The widths of the plurality of P pillars are consistent.

6. The field effect transistor according to any one of claims 1 to 5, characterized in that It also includes a P+ body region and an N+ source region, and the P+ body region and the N+ source region are arranged inside the P well.

7. The field effect transistor according to claim 6, wherein A gate oxide is also included, and the gate oxide is disposed above the N-type drift region.

8. The field effect transistor according to claim 7, wherein Also included is a polysilicon gate disposed within the gate oxide.

9. The field effect transistor according to claim 8, wherein The invention also includes a metal source electrode, which is arranged above the P+ body region, the N+ source region and the gate oxide and contacts the P+ body region, the N+ source region and the gate oxide.

10. The field effect transistor according to claim 9, wherein It also includes a metal drain, which is arranged below the silicon carbide N+ substrate.

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