Array substrate, preparation method thereof and display panel

Abstract

The invention provides an array substrate, a preparation method thereof and a display panel. The preparation method of the array substrate comprises the following steps: preparing a substrate layer, wherein the substrate layer comprises a first region and a second region at least partially surrounding the first region; preparing a first metal layer on one side of the substrate layer, wherein the first metal layer comprises a first metal part located in the second region; preparing an insulating film layer and a conductive film layer on one side, away from the substrate layer, of the first metal layer; a first via hole is formed in the side, away from the substrate layer, of the insulating film layer, the first via hole corresponds to the first metal part, and the depth of the first via hole is smaller than the thickness of the insulating film layer; forming an interlayer dielectric layer on one side, deviating from the substrate layer, of the insulating film layer; patterning the insulating film layer and the interlayer dielectric layer to form a second via hole in the second region and a third via hole in the first region; the second via hole is communicated with the first via hole, and at least part of the surface of the first metal part is exposed in the second via hole.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display panels.

[0003] However, in related display technologies, static electricity in the display panel is not easily transmitted and is easily accumulated to cause damage, thereby affecting the display quality of the display panel. Summary of the Invention

[0004] The object of the present invention is to provide an array substrate and a method for preparing the same, and a display panel, so as to solve the technical problem in related display technologies that the display panel is susceptible to electrostatic damage, thereby affecting the display quality of the display panel.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing an array substrate, comprising: preparing a substrate layer, the substrate layer including a first region and a second region at least partially surrounding the first region; preparing a first metal layer on one side of the substrate layer, the first metal layer including a first metal portion located in the second region; preparing an insulating film layer and a conductive film layer on a side of the first metal layer facing away from the substrate layer; forming a first via on a side of the insulating film layer facing away from the substrate layer, the first via corresponding to the first metal portion and having a depth less than the thickness of the insulating film layer; forming an interlayer dielectric layer on a side of the insulating film layer facing away from the substrate layer; and patterning the insulating film layer and the interlayer dielectric layer to simultaneously form a second via located in the second region and a third via located in the first region. The second via is connected to the first via, and at least a portion of the surface of the first metal portion is exposed in the second via. At least a portion of the surface of the conductive film layer is exposed in the third via.

[0006] Furthermore, before the step of forming an insulating film layer and a conductive film layer on a side of the first metal layer facing away from the substrate layer, the method further includes forming a buffer layer on a side of the first metal layer facing away from the substrate layer. Preferably, the step of forming a first via hole on a side of the insulating film layer facing away from the substrate layer includes forming the first via hole through the insulating film layer and extending into the buffer layer.

[0007] Furthermore, the step of forming an insulating film layer on a side of the first metal layer facing away from the substrate layer includes forming an active layer on a side of the buffer layer facing away from the substrate layer. Preferably, the first metal layer further includes a second metal portion disposed corresponding to the active layer. Preferably, the active layer is made of polycrystalline silicon.

[0008] Furthermore, the step of preparing an insulating film layer on the side of the first metal layer facing away from the substrate layer includes: forming a gate insulating layer covering the active layer on the side of the buffer layer facing away from the substrate layer; forming a capacitor insulating layer on the side of the gate insulating layer facing away from the substrate layer; the capacitor insulating layer and the gate insulating layer constitute the insulating film layer. Preferably, before the step of forming the capacitor insulating layer on the side of the gate insulating layer facing away from the substrate layer, the step of preparing a second metal layer on the side of the gate insulating layer facing away from the substrate layer includes: preparing a first electrode and a gate portion corresponding to the active layer. Preferably, after the step of forming the capacitor insulating layer on the side of the gate insulating layer facing away from the substrate layer, the step of preparing a third metal layer on the side of the capacitor insulating layer facing away from the substrate layer includes: preparing a second electrode corresponding to the first electrode.

[0009] Furthermore, the step of patterning the insulating film layer and the interlayer dielectric layer to synchronously form a second via located in the second area and a third via located in the first area includes: synchronously forming a first sub-via in the first area, the first sub-via penetrating the interlayer dielectric layer and the capacitor insulating layer, and at least a portion of the surface of the gate portion arranged corresponding to the active layer is exposed in the first sub-via; synchronously forming a second sub-via in the first area, the second sub-via penetrating the interlayer dielectric layer, and at least a portion of the surface of the second electrode plate arranged corresponding to the first electrode plate is exposed in the second sub-via.

[0010] Furthermore, the step of patterning the insulating film layer and the interlayer dielectric layer to simultaneously form a second via located in the second region and a third via located in the first region includes: simultaneously forming a third sub-via and a fourth sub-via in the first region, wherein the third sub-via and the fourth sub-via penetrate the interlayer dielectric layer, the capacitor insulating layer, and the gate insulating layer. At least a portion of the surface of the active layer is exposed in the third sub-via and the fourth sub-via, and the third sub-via and the fourth sub-via are respectively located at both ends of the active layer. Preferably, the active layer includes a channel portion corresponding to the gate portion and a first doped portion and a second doped portion respectively located on both sides of the channel portion, wherein at least a portion of the surface of the first doped portion is exposed in the third sub-via, and at least a portion of the surface of the second doped portion is exposed in the fourth sub-via.

[0011] Furthermore, the preparation method of the array substrate also includes: preparing a fourth metal layer on the side of the interlayer dielectric layer facing away from the substrate layer, the fourth metal layer covering the exposed surfaces of the first metal part, the second metal layer and the third metal layer in the second via, the first sub-via and the second sub-via.

[0012] Furthermore, the step of preparing a buffer layer on a side of the first metal layer facing away from the substrate layer includes: forming a first sub-buffer layer on a side of the first metal layer facing away from the substrate layer; and forming a second sub-buffer layer on a side of the first sub-buffer layer facing away from the substrate layer. Preferably, in the step of forming a first via hole on a side of the insulating film layer facing away from the substrate layer, the first via hole penetrates the insulating film layer and extends into the second sub-buffer layer.

[0013] The present invention further provides an array substrate, which is prepared by the above-mentioned method for preparing the array substrate.

[0014] The present invention further provides a display panel, which includes the array substrate described above.

[0015] The advantages of the present invention are: in an array substrate and its preparation method, and a display panel of the present invention, by simultaneously opening vias that contact the metal structure in the display area and the non-display area, an electrostatic transmission path that conducts the contact metal is formed in the display area and the non-display area. The static electricity can be distributed on the metal structures conducted by different vias, preventing static electricity from accumulating on a single metal structure, avoiding the phenomenon of electrostatic damage to the metal structure in the array substrate due to excessive static electricity accumulation, and thereby improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 Schematic diagram of partitions of an array substrate according to an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of the layered structure of an array substrate in an embodiment of the present invention;

[0019] Figure 3 Schematic diagram of the process of preparing an array substrate according to an embodiment of the present invention;

[0020] Figure 4 Schematic diagram of the substrate layer structure after forming the first metal layer in an embodiment of the present invention;

[0021] Figure 5 Schematic diagram of the substrate layer structure after the active layer is formed in an embodiment of the present invention;

[0022] Figure 6 Schematic diagram of the substrate layer structure after forming the second metal layer in an embodiment of the present invention;

[0023] Figure 7 Schematic diagram of the substrate layer structure after the third metal layer is formed in an embodiment of the present invention;

[0024] Figure 8 Schematic diagram of the substrate layer structure after the first via hole is formed in an embodiment of the present invention;

[0025] Figure 9 Schematic diagram of the substrate layer structure after the second via hole and the third via hole are formed in an embodiment of the present invention;

[0026] Figure 10 4 is a schematic diagram of a step-by-step flow chart of step S40 in an embodiment of the present invention.

[0027] The components in the figure are shown as follows:

[0028] Array substrate 1; first area AA; second area NA; substrate layer 10; first flexible layer 11; first barrier layer 12; second flexible layer 13; second barrier layer 14; first metal layer 20; second metal portion 21; first metal portion 22; third barrier layer 30; buffer layer 40; first sub-buffer layer 41; second sub-buffer layer 42; active layer 50; channel portion 51; first doped portion 52; second doped portion 53; insulating film layer 60; gate insulating layer 61; capacitor insulation layer Insulation layer 62; interlayer dielectric layer 63; second metal layer 70; gate portion 71; first electrode 72; third metal layer 80; second electrode 81; fourth metal layer 90; source portion 91; drain portion 92; first transmission portion 93; second transmission portion 94; third transmission portion 95; first via 110; second via 120; third via 130; first sub-via 131; second sub-via 132; third sub-via 133; fourth sub-via 134; driver chip 2. DETAILED DESCRIPTION

[0029] The following describes preferred embodiments of the present invention with reference to the accompanying drawings to demonstrate that the present invention can be implemented. These embodiments will fully introduce the present invention to those skilled in the art, making the technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments described herein.

[0030] In the drawings, components with identical structures are denoted by the same reference numerals, and components with similar structures or functions are denoted by similar reference numerals. The size and thickness of each component shown in the drawings are arbitrary and are not limited by the present invention. For clarity, the thickness of components in some places in the drawings is appropriately exaggerated.

[0031] In addition, the following descriptions of the various embodiments of the invention are made with reference to the attached diagrams to illustrate specific embodiments of the invention in which the present invention may be implemented. The directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", "inner", "outer", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present invention, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0032] When some components are described as being "on" another component, the component may be directly placed on the other component; there may also be an intermediate component with the component placed on the intermediate component, and the intermediate component placed on the other component. When a component is described as being "mounted to" or "connected to" another component, the two can be understood to be directly "mounted" or "connected" or indirectly "mounted to" or "connected to" the other component through an intermediate component.

[0033] In related display technologies, compared with small-sized display panels, medium-sized display panels have a larger area and stronger surface charge adsorption capacity. In particular, in the array substrate (Array) process, there are fewer transmission paths for static electricity, and static electricity is not easily transmitted. It is easy for static electricity to accumulate in the devices and traces in the medium-sized display panel, causing static electricity damage. This damage is not only costly to repair, but may also cause the entire panel to be scrapped.

[0034] Based on the technical problems raised in the above-mentioned related display technologies, a display panel is provided in an embodiment of the present invention. The display panel can be used in smart terminals such as mobile phones, computers, and tablet computers, and is used to display image pictures. The display panel includes a stacked array substrate 1 and a light-emitting layer. A plurality of light-emitting devices are provided in the light-emitting layer, and the light-emitting devices are connected to the array substrate 1. The array substrate 1 controls the brightness of each light-emitting device according to the display signal, thereby lighting up the display panel and realizing the display of the image. A preparation method for preparing the array substrate 1 is also proposed in an embodiment of the present invention. In this preparation method, by changing the order of opening holes in the array substrate 1, the array substrate 1 is enabled to have an electrostatic conduction path in both the display area and the non-display area, thereby preventing the occurrence of static electricity accumulation damage.

[0035] Specifically, such as Figure 1 As shown in , the array substrate 1 includes a first area AA and a second area NA that is at least partially arranged around the first area AA. Specifically, the first area AA corresponds to the display area of ​​the display panel for presenting the picture, and the second area NA corresponds to the non-display area of ​​the display panel where the signal wiring is arranged. In the first area AA, the array substrate 1 is provided with a plurality of thin film transistors, and the light-emitting devices in the display panel are electrically connected to the corresponding thin film transistors. The thin film transistors light up the corresponding light-emitting devices under the drive of the display signal, so that the display panel can display the image. The signal wiring in the array substrate 1 is electrically connected to the corresponding thin film transistor, and extends from the first area AA to the second area NA, and the other end thereof is electrically connected to the driver chip (IC) 2, that is, the driver chip 2 transmits the display signal to the corresponding thin film transistor through the signal wiring to drive the thin film transistor to light up or turn off the corresponding light-emitting device, thereby realizing the change of the display picture.

[0036] like Figure 2 As shown in FIG, the array substrate 1 includes a substrate layer 10, a first metal layer 20, an active layer 50, an insulating film layer 60, and a conductive film layer. The conductive film layer includes multiple metal film layers and an active layer 50 containing semiconductor materials.

[0037] The substrate layer 10 extends from the first area AA to the second area NA and includes a first flexible layer 11, a first barrier layer 12, a second flexible layer 13, and a second barrier layer 14. The first flexible layer 11 is located on the side of the substrate layer 10 away from the first metal layer 20. The first barrier layer 12 is disposed on the surface of the first flexible layer 11 facing the first metal layer 20. The second flexible layer 13 is disposed on the surface of the first barrier layer 12 facing away from the first flexible layer 11. The second barrier layer 14 is disposed on the surface of the second flexible layer 13 facing away from the first flexible layer 11. Specifically, the first barrier layer 12 and the second barrier layer 14 include inorganic materials, such as silicon oxide (SiOx), to prevent external static electricity from affecting the internal circuits of the array substrate 1. The materials of the first flexible layer 11 and the second flexible layer 13 include polyimide (PI). Selecting polyimide as one of the main materials in the substrate layer 10 can make the array substrate 1 have flexible characteristics, thereby enabling the display panel using the array substrate 1 to realize special display technologies such as foldable display, curved display, and curled display. This not only expands the use scenarios of display devices, but also meets consumers' demand for portability and personalized display. Furthermore, in other embodiments of the present invention, the first flexible layer 11 and the second flexible layer 13 in the substrate layer 10 can also be replaced with a hard film layer, such as glass, quartz, etc. The use of a hard film layer can give the substrate layer 10 better support performance. When used in large-scale display devices such as televisions and monitors, the hard substrate can effectively resist external physical impact, prevent internal structural damage caused by collision and extrusion, and ensure the reliability of the image display.

[0038] The first metal layer 20 is disposed on one side of the substrate layer 10, that is, on the surface of the second barrier layer 14 facing away from the first flexible layer 11, and includes a second metal portion 21 and a first metal portion 22. Specifically, as Figure 2 As shown in , the second metal portion 21 is located in the first area AA, and the orthographic projection of the active layer 50 of the thin film transistor on the substrate layer 10 is located within the orthographic projection range of the second metal portion 21 on the substrate layer 10, so that the second metal portion 21 can shield the active layer 50 of the thin film transistor from light incident from the back side of the array substrate 1 (the back side of the array substrate 1 is the surface of the substrate layer 10 facing away from the first metal layer 20), reducing the exposure of the active layer 50 of the thin film transistor to light, preventing the active layer 50 from generating additional carriers under the exposure of light and affecting the switching performance of the thin film transistor, thereby improving the electrical stability of the thin film transistor. The first metal portion 22 is located in the second area NA. The first metal portion 22 can be grounded to discharge static electricity accumulated in the array substrate 1, preventing the components and traces in the array substrate 1 from being damaged by static electricity and causing the substrate to be scrapped, thereby improving the product yield.

[0039] Furthermore, the array substrate 1 also includes a third barrier layer 30 and a buffer layer 40. The third barrier layer 30 is arranged on the side of the second barrier layer 14 facing away from the substrate layer 10, and extends from the first area AA to the second area NA, covering the exposed surfaces of the second metal portion 21 and the first metal portion 22 in the first metal layer 20, thereby insulating and protecting the first metal layer 20. Optionally, the material of the third barrier layer 30 is the same as that of the first barrier layer 12 and the second barrier layer 14. The buffer layer 40 is arranged on the side of the third barrier layer 30 facing away from the substrate layer 10, and includes a first sub-buffer layer 41 and a second sub-buffer layer 42. The first sub-buffer layer 41 is arranged on the surface of the third barrier layer 30 facing away from the substrate layer 10, and the second sub-buffer layer 42 is arranged on the surface of the first sub-buffer layer 41 facing away from the substrate layer 10. Optionally, the material of the buffer layer 40 includes an inorganic material. Among them, the material of the first sub-buffer layer 41 includes silicon nitride (SiNx), which makes the first sub-buffer have better density and prevents the metal particles in the substrate layer 10 from diffusing into the active layer 50 of the thin film transistor; the material of the second sub-buffer layer 42 includes silicon oxide (SiOx), which makes the second sub-buffer layer 42 have better insulation and thermal insulation properties, reduces the heat conduction rate, and helps the active layer 50 in the thin film transistor to form larger crystal grains.

[0040] The active layer 50 is disposed on the surface of the second sub-buffer layer 42 facing away from the substrate layer 10. The active layer 50 is made of polycrystalline silicon, which can be produced using an LTPS (Low Temperature Poly-Silicon) process. Specifically, the active layer 50 includes a channel portion 51, a first doped portion 52, and a second doped portion 53. The channel portion 51 is disposed corresponding to the gate portion 71 in the second metal layer 70, and the first doped portion 52 and the second doped portion 53 are located on either side of the channel portion 51. The first doped portion 71 and the second doped portion 72 are comprised of polycrystalline silicon that has undergone a conductorization process, meaning that the conductivity of the first doped portion 71 and the second doped portion 72 is greater than that of the channel portion 71. One of the first doped portion 52 and the second doped portion 53 is a source region, and the other is a drain region. In one embodiment of the present invention, the first doped portion 52 is a source region, and the second doped portion 53 is a drain region. In other embodiments, the first doped portion 52 may be a drain region, and the second doped portion 53 may be a source region.

[0041] The insulating film layer 60 and the metal film layer are both disposed on the side of the active layer 50 facing away from the substrate layer 10 . Specifically, the insulating film layer 60 includes a gate insulating layer 61 and a capacitor insulating layer 62 , and the metal film layer includes a second metal layer 70 and a third metal layer 80 .

[0042] The gate insulating layer 61 is disposed on the side of the buffer layer 40 facing away from the substrate layer 10 and extends from the first area AA to the second area NA, covering the exposed surface of the active layer 50, thereby insulating and isolating the active layer 50 from the second metal layer 70. The second metal layer 70 is disposed on the side of the gate insulating layer 61 facing away from the substrate layer 10 and includes a gate portion 71 and a first electrode plate 72. The orthographic projection of the gate portion 71 on the substrate layer 10 is located within the orthographic projection range of the active layer 50 on the substrate layer 10, and the orthographic projection of the first electrode plate 72 on the substrate layer 10 is located outside the orthographic projection range of the active layer 50 on the substrate layer 10. The capacitor insulating layer 62 is disposed on the side of the gate insulating layer 61 facing away from the substrate layer 10 and extends from the first area AA to the second area NA, covering the exposed surfaces of the gate portion 71 and the first electrode plate 72 in the second metal layer 70, thereby insulating and isolating the second metal layer 70 from the third metal layer 80. The third metal layer 80 is arranged on the side of the capacitor insulating layer 62 away from the substrate layer 10, and includes a second electrode 81. The orthographic projection of the second electrode 81 on the substrate layer 10 at least partially overlaps with the orthographic projection of the first electrode 72 on the substrate layer 10, and a low capacitance is formed between the second electrode 81 and the first electrode 72. Optionally, the material of the insulating film layer 60 includes an inorganic material, and the material of the metal film layer includes a metal. Preferably, the material of the gate insulating layer 61 includes silicon oxide (SiOx), the material of the capacitor insulating layer 62 includes silicon nitride (SiNx), and the materials of the second metal layer 70 and the third metal layer 80 include metal molybdenum (Mo).

[0043] Furthermore, the array substrate 1 further includes an interlayer dielectric layer 63 , which is disposed on the side of the capacitor insulating layer 62 away from the substrate layer 10 and extends from the first area AA to the second area NA, covering the exposed surface of the second electrode 81 in the second metal.

[0044] The array substrate 1 has a plurality of via holes, such as Figure 2 As shown in FIG, the via hole includes a first via hole 110 and a second via hole 120 located in the second area NA and a plurality of third via holes 130 located in the first area AA. The plurality of third via holes 130 include a first sub-via hole 131, a second sub-via hole 132, a third sub-via hole 133 and a fourth sub-via hole 134.

[0045] The first via 110 penetrates the interlayer dielectric layer 63 and the insulating film layer 60 and extends into the buffer layer 40, that is, the first via 110 sequentially penetrates the interlayer dielectric layer 63, the capacitor insulating layer 62, and the gate insulating layer 61, and extends into the second sub-buffer layer 42. The second via 120 is located on the side of the first via 110 close to the substrate layer 10, and the first via 110 is connected to the second via 120, that is, the second via 120 sequentially penetrates the second sub-buffer layer 42 and the first sub-buffer layer 41. The first via 110 and the second via 120 are both located in the second area NA, and the orthographic projections of the first via 110 and the second via 120 on the substrate layer 10 are located within the orthographic projection range of the first metal portion 22 on the substrate layer 10, so that part of the surface of the first metal portion 22 is exposed in the corresponding second via 120. The first sub-via 131 penetrates the interlayer dielectric layer 63 and the capacitor insulation layer 62, and the second sub-via 132 penetrates the interlayer dielectric layer 63, and the first sub-via 131 and the second sub-via 132 are both located in the first area AA. The orthographic projection of the first sub-via 131 on the substrate layer 10 is located within the orthographic projection range of the gate portion 71 on the substrate layer 10, and the orthographic projection of the second sub-via 132 on the substrate layer 10 is located within the orthographic projection range of the second electrode plate 81 on the substrate layer 10, thereby causing a portion of the surface of the gate portion 71 in the second metal layer 70 to be exposed in the first sub-via 131, and causing a portion of the surface of the second electrode plate 81 in the third metal layer 80 to be exposed in the second sub-via 132. The third sub-via 133 and the fourth sub-via 134 sequentially penetrate the interlayer dielectric layer 63, the capacitor insulating layer 62 and the gate insulating layer 61, and the third sub-via 133 and the fourth sub-via 134 are both located in the first area AA. The orthographic projection of the third sub-via 133 on the active layer 50 and the orthographic projection of the fourth sub-via 134 on the active layer 50 are respectively located at two ends of the active layer 50, that is, at least part of the surface of the first doped portion 52 is exposed in the third sub-via 133, and at least part of the surface of the second doped portion 53 is exposed in the fourth sub-via 134. The source portion 91 and the drain portion 92 in the fourth metal layer 90 can be electrically connected to the active layer 50 through the third sub-via 133 and the fourth sub-via 134, respectively.

[0046] Furthermore, the metal film layer in the array substrate 1 also includes a fourth metal layer 90, which is disposed on the side of the interlayer dielectric layer 63 facing away from the substrate layer 10. The fourth metal layer 90 includes a source-drain portion 91, a drain portion 92, a first transmission portion 93, a second transmission portion 94, and a third transmission portion 95. The source-drain portion 91 and the drain portion 92 are connected to the first doped portion 52 and the second doped portion 53 of the active layer 50 through a third sub-via 133 and a fourth sub-via 134, respectively. The first transmission portion 93 is connected to the first metal portion 22 through a first via 110 and a second via 120. The second transmission portion 94 and the third transmission portion 95 are connected to the gate portion 71 and the second electrode plate 81 through a third via 130 and a second sub-via 132, respectively, and transmit potential signals to the gate portion 71 and the capacitor, respectively.

[0047] The present invention also provides a method for preparing an array substrate 1, which is used to prepare the array substrate 1 as described above. The process of the array substrate 1 is as follows: Figure 3 As shown in , it includes steps S10-S90.

[0048] Step S10) preparing the substrate layer 10:

[0049] A polyimide material is deposited on a substrate to form a first flexible layer 11. An inorganic material is deposited on a surface of the first flexible layer 11 facing away from the substrate to form a first barrier layer 12. A further layer of polyimide material is deposited on a surface of the first barrier layer 12 facing away from the first flexible layer 11 to form a second flexible layer 13. A further layer of inorganic material is deposited on a surface of the second flexible layer 13 facing away from the first flexible layer 11 to form a second barrier layer 14. The first flexible layer 11, the first barrier layer 12, the second flexible layer 13, and the second barrier layer 14 are combined to form a substrate layer 10, which includes a first area AA and a second area NA surrounding the first area AA. The first flexible layer 11 and the second flexible layer 13 are made of polyimide, and the first barrier layer 12 and the second barrier layer 14 are made of silicon oxide (SiOx).

[0050] Step S20) preparing a first metal layer 20 on one side of the substrate layer 10:

[0051] A layer of metal material is deposited on the surface of the second barrier layer 14 away from the first flexible layer 11 to form a first metal material layer; the first metal material layer is patterned by a photolithography process to form Figure 4 The second metal portion 21 is located in the first area AA and the first metal portion 22 is located in the second area NA; the second metal portion 21 and the first metal portion 22 are combined to form the first metal layer 20.

[0052] Step S30) preparing a buffer layer 40 and a third barrier layer 30 on the side of the first metal layer 20 facing away from the substrate layer 10:

[0053] A layer of inorganic material covering the first metal layer 20 is deposited on the side of the second barrier layer 14 facing away from the first flexible layer 11 to form a third barrier layer 30. A layer of inorganic material is deposited on the surface of the third barrier layer 30 facing away from the substrate layer 10 to form a first sub-buffer layer 41. A layer of inorganic material is deposited on the surface of the first sub-buffer layer 41 facing away from the substrate layer 10 to form a second sub-buffer layer 42. The first sub-buffer layer 41 and the second sub-buffer layer 42 are combined to form the buffer layer 40. The material of the first sub-buffer layer 41 includes silicon nitride (SiNx), and the material of the third barrier layer and the second sub-buffer layer 42 includes silicon oxide (SiOx).

[0054] Step S40) Prepare an insulating film layer 60 and a conductive film layer on the side of the first metal layer 20 facing away from the substrate layer 10: This step includes the following steps: Figure 10 The sub-steps S41-S45 shown in .

[0055] Step S41) preparing an active layer 50 on the side of the buffer layer 40 facing away from the substrate layer 10:

[0056] A semiconductor material is deposited on the surface of the buffer layer 40 away from the substrate layer 10 to form a semiconductor layer; wherein the semiconductor material is polysilicon; the semiconductor layer is patterned by a photolithography process to remove excess semiconductor material to form a semiconductor layer. Figure 5 The active layer 50 shown in FIG. The active layer 50 includes a channel portion 51 and a first doping portion 52 and a second doping portion 53 respectively located on both sides of the channel portion 51.

[0057] Step S42) forming a gate insulating layer 61 covering the active layer 50 on the side of the buffer layer 40 facing away from the substrate layer 10:

[0058] A layer of inorganic material covering the active layer 50 is deposited on the side of the buffer layer 40 facing away from the substrate layer 10 to form a gate insulating layer 61 .

[0059] Step S43) preparing a second metal layer 70 on the side of the gate insulating layer 61 facing away from the substrate layer 10:

[0060] A layer of metal material is deposited on the surface of the gate insulating layer 61 away from the substrate layer 10 to form a second metal material layer; the second metal material layer is patterned by a photolithography process to form a Figure 6 The gate portion 71 and the first electrode plate 72 are shown in FIG. ; the gate portion 71 and the first electrode plate 72 are combined to form the second metal layer 70 .

[0061] Step S44) forming a capacitor insulating layer 62 on the side of the gate insulating layer 61 facing away from the substrate layer 10:

[0062] A layer of inorganic material covering the second metal layer 70 is deposited on the side of the gate insulating layer 61 facing away from the substrate layer 10 to form a capacitor insulating layer 62. The capacitor insulating layer 62 and the gate insulating layer 61 constitute an insulating film layer 60.

[0063] Step S45) forming a third metal layer 80 on the side of the capacitor insulating layer 62 facing away from the substrate layer 10:

[0064] A layer of metal material is deposited on the side of the capacitor insulating layer 62 away from the substrate layer 10 to form a third metal material layer; the third metal material layer is patterned by a photolithography process to form a Figure 7 The second electrode plate 81 shown in FIG. 8 is included in the third metal layer 80 .

[0065] Furthermore, the inorganic material selected for the gate insulating layer 61 includes silicon oxide (SiOx), the inorganic material selected for the capacitor insulating layer 62 includes silicon nitride (SiNx), and the metal material selected for the second metal layer 70 and the third metal layer 80 is molybdenum (Mo). In other embodiments of the present invention, the metal material may also be a stacked combination of one or more highly conductive metal materials such as titanium (Ti), aluminum (Al), copper (Cu), and silver (Ag).

[0066] Step S50) forming a first via hole 110 on the side of the insulating film layer 60 facing away from the substrate layer 10:

[0067] A layer of photoresist covering the third metal layer 80 is coated on the side of the capacitor insulating layer 62 away from the substrate layer 10, and the photoresist layer is patterned; the patterned photoresist layer is used as a mask to pattern the insulating film layer 60 and the buffer layer 40 located in the second area NA through an etching process to form a Figure 8 The first via hole 110 corresponding to the first metal portion 22 is shown in FIG; the photoresist is removed.

[0068] During the photolithography process, the metal mask used in photoresist patterning generates frictional charges during contact and separation, and a large amount of static electricity is generated when etching the photoresist. In related display technologies, the third via and the first via are usually opened first, followed by the second via. During the photolithography process of opening the second via, the exposed metal surfaces in other vias in the display area are covered with photoresist, leaving only the metal surface corresponding to the second via exposed. Therefore, the static electricity generated during the photolithography process will be concentrated in the second via. After accumulating too much static electricity, the metal structure corresponding to the second via will suffer static damage, which will affect the quality of the array substrate and the yield rate of the production line. In an embodiment of the present invention, a first via hole 110 that is not connected to the first metal part 22 is first opened on the insulating film layer. That is, at this time, the surface of the metal film layer in the substrate (especially the first metal part 22) is covered and protected by the insulating film layer. Therefore, the static electricity generated in the photolithography process used in the process of forming the first via hole 110 cannot pass through the insulating film layer and be transmitted to the metal film layer in the substrate, thereby failing to damage the metal structure in the substrate. The static electricity generated in this step can be conducted to the outside of the substrate through the conductive structure (such as the metal mask, metal bracket, etc.) in the photolithography equipment, thereby improving the production quality of the array substrate 1 and the yield rate of the production line.

[0069] Step S60) forming an interlayer dielectric layer 63 on the side of the insulating film layer 60 facing away from the substrate layer 10:

[0070] A layer of inorganic material covering the third metal layer 80 is deposited on the side of the capacitor insulating layer 62 facing away from the substrate layer 10 to form an interlayer dielectric layer 63 .

[0071] Step S70) Patterning the insulating film layer 60 and the interlayer dielectric layer 63 to simultaneously form the second via hole 120 located in the second area NA and the third via hole 130 located in the first area AA:

[0072] A layer of photoresist is coated on the side of the interlayer dielectric layer 63 facing away from the substrate layer 10, and the photoresist layer is patterned; the patterned photoresist layer is used as a mask to pattern the interlayer dielectric layer 63, the insulating film layer 60 and the buffer layer 40 in the first area AA and the second area NA through an etching process, and the following are simultaneously formed: Figure 9 The second and third via holes 120 and 130 shown in FIG are formed, and the aperture of the first via hole 110 is further enlarged; the photoresist is removed. The third via hole 130 includes a first sub-via hole 131 corresponding to the gate portion 71, a second sub-via hole 132 corresponding to the second electrode plate 81, a third sub-via hole 133 corresponding to the first doped portion 52, and a fourth sub-via hole 134 corresponding to the second doped portion 53.

[0073] In this step, the second via 120 located in the second area NA and the third via 130 located in the first area AA can be opened at the same time, so that the vias in the first area AA and the second area NA can simultaneously form a conductive path for the conductive contact metal, and the static electricity generated in the photolithography process used in the patterning of the insulating film layer 60 and the interlayer dielectric layer 63 can be distributed on the metal structures (i.e., the first metal part 22, the gate part 71 and the second plate 81) connected by different vias (i.e., the second via 120, the first sub-via 131 and the second sub-via 132). Compared with the related display technology of opening the third via first and the first via later, The drilling process of the second via hole can effectively reduce the total amount of static electricity accumulated on the first metal part 22 in the second area NA, that is: in the embodiment of the present invention, by simultaneously conducting multiple via holes in contact with the metal structure, multiple static electricity transmission paths are simultaneously formed on the array substrate 1, and the total amount of static electricity generated in the same photolithography process can be distributed and transmitted through the multiple static electricity transmission paths, thereby reducing the amount of static electricity borne by the metal structure corresponding to a single via hole, and further preventing static electricity from accumulating only on the metal structure conducted by a single via hole and causing static electricity damage, thereby improving the production quality of the array substrate 1 and the yield of the production line.

[0074] Step S80) preparing a fourth metal layer 90 on the side of the interlayer dielectric layer 63 facing away from the substrate layer 10:

[0075] A layer of metal material is deposited on the surface of the interlayer dielectric layer 63 facing away from the substrate layer 10 to fill and cover the surface of the metal film layer exposed in the second via hole 120 and the third via hole 130 to form a fourth metal material layer; the fourth metal material layer is patterned by a photolithography process to form a Figure 2 The source portion 91 , the drain portion 92 , the first transfer portion 93 , the second transfer portion 94 and the third transfer portion 95 shown in FIG. 9 are combined to form a fourth metal layer 90 .

[0076] In an embodiment of the present invention, by simultaneously opening vias in contact with the metal structure in the display area (i.e., the first area) and the non-display area (i.e., the second area), an electrostatic transmission path that conducts the contact metal is formed in both the display area and the non-display area. Static electricity can be distributed on the metal structures conducted by different vias, preventing static electricity from concentrating and accumulating on a single metal structure, avoiding electrostatic damage to the metal structure in the array substrate due to excessive static electricity accumulation, and thereby improving the product yield.

[0077] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the invention. It should be understood that many modifications may be made to the illustrative embodiments, and that other arrangements may be devised, without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in ways other than those described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be employed in conjunction with other described embodiments.

Claims

1. A method for preparing an array substrate, characterized in that: include: preparing a substrate layer, the substrate layer comprising a first region and a second region at least partially surrounding the first region; Prepare a first metal layer on one side of the substrate layer, wherein the first metal layer includes a first metal portion located in the second region; forming an insulating film layer and a conductive film layer on a side of the first metal layer facing away from the substrate layer; forming a first via hole on a side of the insulating film layer facing away from the substrate layer, wherein the first via hole corresponds to the first metal portion and a depth of the first via hole is less than a thickness of the insulating film layer; forming an interlayer dielectric layer on a side of the insulating film layer facing away from the substrate layer; patterning the insulating film layer and the interlayer dielectric layer to simultaneously form a second via hole located in the second region and a third via hole located in the first region; The second via hole is connected to the first via hole, and at least a portion of the surface of the first metal portion is exposed in the second via hole; At least a portion of the surface of the conductive film layer is exposed in the third via hole.

2. The method for preparing an array substrate according to claim 1, wherein: Before the step of preparing an insulating film layer and a conductive film layer on a side of the first metal layer facing away from the substrate layer, the step further includes: preparing a buffer layer on a side of the first metal layer facing away from the substrate layer; Preferably, the step of forming a first via hole on a side of the insulating film layer away from the substrate layer includes: the first via hole penetrates the insulating film layer and extends into the buffer layer.

3. The method for preparing an array substrate according to claim 2, wherein: The step of preparing an insulating film layer and a conductive film layer on a side of the first metal layer facing away from the substrate layer includes: preparing an active layer on a side of the buffer layer facing away from the substrate layer; Preferably, the first metal layer further includes a second metal portion arranged corresponding to the active layer; Preferably, the material of the active layer includes polysilicon.

4. The method for preparing an array substrate according to claim 3, wherein: The step of preparing an insulating film layer and a conductive film layer on a side of the first metal layer facing away from the substrate layer includes: forming a gate insulating layer covering the active layer on a side of the buffer layer away from the substrate layer; forming a capacitor insulating layer on a side of the gate insulating layer away from the substrate layer; The capacitor insulating layer and the gate insulating layer constitute the insulating film layer; Preferably, before the step of forming a capacitor insulating layer on a side of the gate insulating layer away from the substrate layer, the method further comprises: preparing a second metal layer on a side of the gate insulating layer away from the substrate layer, the second metal layer comprising a first electrode plate and a gate portion provided corresponding to the active layer; Preferably, after the step of forming a capacitor insulating layer on the side of the gate insulating layer away from the substrate layer, the step includes: preparing a third metal layer on the side of the capacitor insulating layer away from the substrate layer, the third metal layer including a second electrode plate arranged corresponding to the first electrode plate.

5. The method for preparing an array substrate according to claim 4, wherein: The step of patterning the insulating film layer and the interlayer dielectric layer to simultaneously form a second via hole located in the second area and a third via hole located in the first area comprises: Synchronously forming a first sub-via in the first region, the first sub-via penetrating the interlayer dielectric layer and the capacitor insulating layer, with at least a portion of the surface of the gate portion corresponding to the active layer exposed in the first sub-via; A second sub-via is simultaneously formed in the first region, the second sub-via penetrating the interlayer dielectric layer, and at least a portion of the surface of the second electrode plate corresponding to the first electrode plate is exposed in the second sub-via.

6. The method for preparing an array substrate according to claim 4, wherein: The step of patterning the insulating film layer and the interlayer dielectric layer to simultaneously form a second via hole located in the second area and a third via hole located in the first area comprises: Synchronously forming a third sub-via and a fourth sub-via in the first area, wherein the third sub-via and the fourth sub-via penetrate the interlayer dielectric layer, the capacitor insulating layer, and the gate insulating layer; At least a portion of the surface of the active layer is exposed in the third sub-via hole and the fourth sub-via hole, and the third sub-via hole and the fourth sub-via hole are respectively located at two ends of the active layer; Preferably, the active layer includes a channel portion arranged corresponding to the gate portion and a first doped portion and a second doped portion respectively located on both sides of the channel portion, at least part of the surface of the first doped portion is exposed in the third sub-via, and at least part of the surface of the second doped portion is exposed in the fourth sub-via.

7. The method for preparing an array substrate according to claim 6, wherein: Also includes: A fourth metal layer is prepared on a side of the interlayer dielectric layer facing away from the substrate layer, and the fourth metal layer covers exposed surfaces of the first metal portion, the second metal layer and the third metal layer in the second via, the first sub-via and the second sub-via.

8. The method for preparing an array substrate according to claim 2, wherein: The step of preparing a buffer layer on a side of the first metal layer facing away from the substrate layer includes: forming a first sub-buffer layer on a side of the first metal layer facing away from the substrate layer; forming a second sub-buffer layer on a side of the first sub-buffer layer facing away from the substrate layer; Preferably, in the step of forming the first via hole on the side of the insulating film layer facing away from the substrate layer, the first via hole penetrates the insulating film layer and extends into the second sub-buffer layer.

9. An array substrate, characterized in that: The array substrate is prepared by the method for preparing the array substrate according to any one of claims 1 to 8.

10. A display panel, characterized in that: The invention comprises the array substrate as claimed in claim 9.

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