Array substrate, manufacturing method thereof and display panel

Abstract

The invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a first transparent electrode, an insulating layer and a second transparent electrode which are sequentially arranged on a substrate in a stacked mode, and the material of the insulating layer comprises an insulating material which generates hydrogen ions in the process of forming the insulating layer; the buffer layer is arranged between the first transparent electrode and the insulating layer, the buffer layer comprises a first buffer layer and a second buffer layer which are arranged in a stacked mode, the first buffer layer is arranged close to the first transparent electrode, and the density of the second buffer layer is larger than that of the insulating layer. The volume density ratio of N-H bonds to Si-H bonds in the first buffer layer is larger than that of N-H bonds to Si-H bonds in the second buffer layer, and the thickness of the first buffer layer is smaller than that of the second buffer layer. Therefore, the array substrate has both high transmittance and low undercut risk.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] Thin Film Field Effect Transistor Liquid Crystal Display (TFT-LCD) currently dominates the flat panel display market, particularly in large-size displays. Transmittance is a key performance indicator for large-size LCDs. As the resolution of large-size display products evolves from 4K to 8K, low transmittance is a pressing issue for 8K products. Summary of the Invention

[0003] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

[0004] To this end, in one aspect of the present invention, an array substrate is provided, comprising: a first transparent electrode, an insulating layer, and a second transparent electrode sequentially stacked on a base substrate, wherein the insulating layer is made of an insulating material that generates hydrogen ions during the formation of the insulating layer; and a buffer layer disposed between the first transparent electrode and the insulating layer, the buffer layer comprising a first buffer layer and a second buffer layer stacked together, the first buffer layer being disposed adjacent to the first transparent electrode, the second buffer layer having a greater density than the insulating layer, the ratio of the bulk density of NH bonds to Si-H bonds in the first buffer layer being greater than the ratio of the bulk density of NH bonds to Si-H bonds in the second buffer layer, and the thickness of the first buffer layer being less than the thickness of the second buffer layer. Thus, the array substrate achieves both high transmittance and low undercut risk.

[0005] Furthermore, the volume density ratio of NH bonds to Si—H bonds in the first buffer layer is 1.1-3 times the volume density ratio of NH bonds to Si—H bonds in the second buffer layer.

[0006] Furthermore, the thickness of the first buffer layer is

[0007] Furthermore, the thickness of the buffer layer is

[0008] Furthermore, the insulating layer includes a gate insulating layer and a passivation layer that are stacked, the gate insulating layer is arranged close to the buffer layer, and the density of the second buffer layer is greater than the density of the gate insulating layer.

[0009] Furthermore, the insulating layer includes a passivation layer, and a gate insulating layer is provided between the base substrate and the first transparent electrode.

[0010] Furthermore, the insulating layer and the buffer layer are made of silicon nitride, and the first transparent electrode and the second transparent electrode are made of at least one of indium tin oxide and indium zinc oxide.

[0011] In another aspect of the present invention, a display panel is provided, which includes the aforementioned array substrate. Therefore, the display panel has all the features and benefits of the aforementioned array substrate, which will not be described in detail here.

[0012] In another aspect of the present invention, a method for manufacturing an array substrate is proposed. The method includes: forming a first transparent electrode on a base substrate; forming a buffer layer on a side of the first transparent electrode away from the base substrate, the buffer layer including a first buffer layer and a second buffer layer stacked, the first buffer layer being arranged close to the first transparent electrode, the volume density ratio of NH bonds to Si-H bonds in the first buffer layer being greater than the volume density ratio of NH bonds to Si-H bonds in the second buffer layer, and the thickness of the first buffer layer being less than the thickness of the second buffer layer; forming an insulating layer on a side of the buffer layer away from the first transparent electrode, the material of the insulating layer including an insulating material that generates hydrogen ions during the formation of the insulating layer, the density of the second buffer layer being greater than the density of the insulating layer; forming a second transparent electrode on a side of the insulating layer away from the buffer layer. The array substrate manufactured by this method takes into account both high transmittance and low undercut risk, and can be manufactured using existing production lines, with mass production capabilities.

[0013] Furthermore, the buffer layer is formed by chemical vapor deposition, and the chemical vapor deposition gas includes silane, ammonia and nitrogen. The silane flow rate for forming the first buffer layer is less than the silane flow rate for forming the second buffer layer, and / or the ammonia flow rate for forming the first buffer layer is greater than the ammonia flow rate for forming the second buffer layer.

[0014] Furthermore, the buffer layer is formed by chemical vapor deposition, and the chemical vapor deposition gas includes silane, ammonia and nitrogen. The silane flow rate for forming the first buffer layer is less than the silane flow rate for forming the second buffer layer, and the difference between the two is not less than 200 sccm; and / or, the ammonia flow rate for forming the first buffer layer is greater than the ammonia flow rate for forming the second buffer layer, and the difference between the two is not less than 1000 sccm.

[0015] Furthermore, the silane flow rate for forming the second buffer layer and the silane flow rate for forming the first buffer layer are 600-1400 sccm respectively, and the ammonia flow rate for forming the second buffer layer and the ammonia flow rate for forming the first buffer layer are 2000-10000 sccm respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 shows a structural schematic diagram of an array substrate according to an embodiment of the present invention;

[0018] Figure 2 shows a structural schematic diagram of an array substrate according to another embodiment of the present invention;

[0019] Figure 3 Shows a structural schematic diagram of an array substrate in related art;

[0020] Figure 4 A schematic diagram showing the principle of the reduction reaction between hydrogen ions and ITO during the process of directly depositing the gate insulating layer on the first transparent electrode;

[0021] Figure 5 A schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the present invention is shown.

[0022] Reference numerals:

[0023] 10 / 100: base substrate; 20 / 200: first transparent electrode; 30: buffer layer of gate insulating layer; 300: buffer layer; 310: first buffer layer; 320: second buffer layer; 40 / 400: gate insulating layer; 50 / 500: passivation layer; 60 / 600: second transparent electrode. DETAILED DESCRIPTION

[0024] The following embodiments of the present invention are described in detail. The embodiments described below are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention. Where specific techniques or conditions are not specified in the embodiments, the techniques or conditions described in the literature in the art or in the product specifications shall be followed.

[0025] The Advanced Super Dimension Switch (ADS) display mode is one of the mainstream display modes of liquid crystal displays. It has advantages such as wide viewing angle and small color deviation, and is widely used in the field of large-size displays. Figure 3 The current advanced super-dimensional field switching array substrate generally includes a first transparent electrode 20, a buffer layer 30 of a gate insulating layer, a gate insulating layer 40, a passivation layer 50 and a second transparent electrode 60 stacked in sequence on a base substrate 10.

[0026] The material of the gate insulating layer 40 is usually silicon nitride, and the deposition of silicon nitride usually uses a plasma enhanced chemical vapor deposition (PECVD) process, and the deposition gases used are silane (SiH4), ammonia (NH3) and nitrogen. Considering the production cycle, higher power, gas flow and pressure are used in the process of depositing the gate insulating layer 40. The above deposition conditions will cause a large number of reducing radicals, mainly hydrogen radicals, to exist in the plasma. If the gate insulating layer 40 is directly deposited on the first transparent electrode 20, the hydrogen ions generated during the deposition process will reduce the In2O3 in the material of the first transparent electrode (usually indium tin oxide, ITO) into InO or In particles (refer to Figure 4 ), the InO and In particles are gray-brown, resulting in the precipitation of a large number of small black spots on the first transparent electrode 20, affecting the transmittance of the first transparent electrode and further affecting the transmittance of the array substrate.

[0027] Therefore, currently, before depositing the gate insulation layer 40, a buffer layer 30 is first deposited on the first transparent electrode 20. Silane, ammonia, and nitrogen are also used as deposition gases, but the deposition process uses lower power, gas flow, and pressure to reduce the amount of reducing hydrogen ions generated in the plasma during deposition, reduce the precipitation of small black spots, and improve the transmittance of the array substrate. It should be noted that the lower power, gas flow, and pressure used in the deposition of the buffer layer 30 are relative to the deposition conditions of the gate insulation layer 40. The silane flow, ammonia flow, and nitrogen flow rates of the buffer layer 30 are significantly lower than those of the gate insulation layer 40.

[0028] At present, the transmittance of the array substrate is only 90%, which still needs to be improved. The inventors found that based on the deposition conditions of the existing buffer layer 30, the buffer layer 30 can be deposited by reducing the silane flow rate, or increasing the ammonia flow rate, or reducing the silane flow rate while increasing the ammonia flow rate, thereby improving the reduction phenomenon of the first transparent electrode and improving the transmittance of the array substrate. However, the above deposition method will bring new problems. Reducing the silane flow rate and increasing the ammonia flow rate will soften the buffer layer 30. In the process of etching the gate insulating layer 40 and the buffer layer 30, the softened buffer layer 30 will cause lateral over-etching (undercut) in the deep hole, resulting in deep hole overlap failure and excessively high via resistance. Even if the module inspection has no point or line defects, during the reliability evaluation or use after shipment, it is easy to cause the via to burn out due to local heating for a long time due to excessive resistance, resulting in poor screen NG and other defects. Therefore, the current array substrate has the problem of not being able to balance the improvement of transmittance and the low risk of undercut.

[0029] To this end, in one aspect of the present invention, the present invention provides an array substrate. In some embodiments of the present invention, reference is made to Figure 1 The array substrate includes a first transparent electrode 200, a buffer layer 300, an insulating layer (such as Figure 1 The gate insulating layer 400 and the passivation layer 500 shown in the figure) and the second transparent electrode 600, wherein the material of the insulating layer includes an insulating material that generates hydrogen ions during the formation of the insulating layer, and the buffer layer 300 includes a first buffer layer 310 and a second buffer layer 320 stacked, the first buffer layer 310 is arranged close to the first transparent electrode 200, and the density of the second buffer layer 320 is greater than the density of the insulating layer (as shown in the figure). Figure 1 As shown, the insulating layer is composed of a gate insulating layer 400 and a passivation layer 500. In this case, the density of the second buffer layer 320 is greater than that of the gate insulating layer 400. The ratio of the bulk density of NH bonds to Si-H bonds in the first buffer layer 310 is greater than the ratio of the bulk density of NH bonds to Si-H bonds in the second buffer layer 320. Furthermore, the thickness of the first buffer layer 310 is less than that of the second buffer layer 320. Thus, the array substrate can achieve both high transmittance and low undercut risk.

[0030] To facilitate understanding, the following first describes in detail the principle of the array substrate achieving both high transmittance and low undercut risk:

[0031] The present invention provides two buffer layers between the insulating layer and the first transparent electrode. The second buffer layer has a higher density than the insulating layer, meaning it is a hard film. During etching of the insulating layer and buffer layer 300, the second buffer layer mitigates the risk of undercutting. The second buffer layer is formed using a plasma-enhanced chemical vapor deposition process using a mixture of silane, ammonia, and nitrogen as the deposition gas. This deposition process utilizes lower power, gas flow, and pressure than that used to deposit the insulating layer. In other words, the second buffer layer can be deposited under the same conditions as the buffer layer 30 of the conventional gate insulating layer. This allows for a more complete reaction of the deposition gas, resulting in a denser second buffer layer.

[0032] The volume density ratio of NH bonds to Si-H bonds in the first buffer layer is greater than the volume density ratio of NH bonds to Si-H bonds in the second buffer layer. Specifically, the first buffer layer can be formed by reducing the silane flow rate, increasing the ammonia flow rate, or both reducing the silane flow rate and increasing the ammonia flow rate, based on the deposition conditions of the second buffer layer, so that the volume density ratio of NH bonds to Si-H bonds in the first buffer layer is greater than the volume density ratio of NH bonds to Si-H bonds in the second buffer layer. Because the gas flow rate for depositing the second buffer layer is lower than the gas flow rate for depositing the insulating layer, the amount of hydrogen ions generated during the deposition of the second buffer layer is reduced. Therefore, the above-mentioned conditions for forming the first buffer layer result in fewer hydrogen ions generated during the deposition of the first buffer layer, and thus fewer small black spots deposited on the first transparent electrode, thereby improving the transmittance of the array substrate.

[0033] Since reducing the silane flow rate and increasing the ammonia flow rate will soften the first buffer layer, the thickness of the first buffer layer is made smaller than that of the second buffer layer, so that the second buffer layer can play a good role in avoiding the undercut risk and the first buffer layer can play a good role in improving the transmittance of the array substrate.

[0034] By adjusting the film structure of the array substrate, the present invention can increase the transmittance of the array substrate to over 91% while reducing the risk of undercutting, thereby improving the transmittance of the display panel. Furthermore, the present invention's solution requires minimal structural changes to the array substrate, making it suitable for mass production without affecting production capacity or product reliability.

[0035] The display panel transmittance is roughly linearly related to the array substrate transmittance. Taking a 5% display panel transmittance as a benchmark, a 1% increase in the array substrate transmittance results in a 1% increase in the display panel transmittance (from 5% to 5.05%). The solution of the present invention increases the array substrate transmittance by more than 1%, significantly improving the display panel transmittance.

[0036] It should be noted that the volume density of NH bonds and Si—H bonds can be analyzed using infrared spectroscopy. Specifically, the volume density of NH bonds and Si—H bonds can be characterized by the peak area of ​​infrared spectrum.

[0037] The following is a detailed description of the various structures of the array substrate:

[0038] In some preferred embodiments of the present invention, the ratio of the bulk density of NH bonds to Si-H bonds in the first buffer layer 310 is 1.1-3 times, for example, 1.1 times, 1.5 times, 2 times, 2.5 times, or 3 times, the bulk density ratio of NH bonds to Si-H bonds in the second buffer layer 320. The inventors have discovered that by adjusting the silane flow rate and / or the ammonia flow rate used in depositing the first buffer layer so that the bulk density ratio of NH bonds to Si-H bonds in the first buffer layer 310 is greater than 1.1 times the bulk density ratio of NH bonds to Si-H bonds in the second buffer layer 320, the amount of hydrogen ions generated during the deposition of the first buffer layer can be significantly reduced, thereby significantly reducing the amount of small black spots deposited on the first transparent electrode, and significantly improving the transmittance of the array substrate. At the same time, the volume density ratio of NH bonds to Si-H bonds in the first buffer layer 310 is set to be less than 3 times the volume density ratio of NH bonds to Si-H bonds in the second buffer layer 320. On the one hand, within the above range, the transmittance of the array substrate can be significantly improved. On the other hand, the equipment capacity, energy saving and production cost are comprehensively considered to optimize the production process.

[0039] In some embodiments of the present invention, the thickness of the first buffer layer 310 may be For example, At this thickness, the first buffer layer effectively blocks the hydrogen ions generated during the deposition of the second buffer layer from reacting with the first transparent electrode material, resulting in a high transmittance for the array substrate. Although the first buffer layer softens compared to the second buffer layer, its thinness does not increase the risk of undercutting. The first buffer layer primarily serves to improve the transmittance of the array substrate, while the reduction in undercutting risk is primarily achieved through the thicker and denser second buffer layer.

[0040] In some embodiments of the present invention, the total thickness of the buffer layer 300 may be For example, The thickness of the second buffer layer is Can effectively reduce the risk of undercut.

[0041] The insulating layer may be formed using a plasma-enhanced chemical vapor deposition process using a mixture of silane, ammonia, and nitrogen as the deposition gas. During the deposition process, the silane, ammonia, and nitrogen react to form silicon nitride and generate hydrogen ions. The materials for the buffer layer 300 and the insulating layer may include, but are not limited to, silicon nitride.

[0042] In some embodiments of the present invention, the material of the first and second transparent electrodes may include at least one of indium tin oxide and indium zinc oxide. The first and second transparent electrodes have high transmittance and good conductivity. The first transparent electrode may be a plate-shaped electrode or a strip-shaped electrode, and the second transparent electrode may be a plate-shaped electrode or a strip-shaped electrode. The specific design can be determined based on the specific situation and is not particularly limited.

[0043] In some embodiments of the present invention, reference Figure 1 The insulating layer may include a stacked gate insulating layer 400 and a passivation layer 500. The gate insulating layer 400 is disposed adjacent to the buffer layer 300. In this case, the second buffer layer 320 has a greater density than the gate insulating layer 400. During etching of the gate insulating layer and the buffer layer, the second buffer layer can mitigate the risk of undercutting. The array substrate of this embodiment corresponds to an ADS array substrate. In this case, the first transparent electrode 200 serves as a common electrode, and the second transparent electrode 600 serves as a pixel electrode.

[0044] In this embodiment, the material of the gate insulating layer may include silicon nitride, and the material of the passivation layer may be the same as or different from the material of the gate insulating layer. For example, the passivation layer may be a silicon nitride film layer, or the passivation layer may be a composite film layer of silicon nitride and silicon oxide. According to specific embodiments of the present invention, the gate insulating layer 400 may be a high-speed deposited gate insulating layer. In other specific embodiments, a low-speed deposited gate insulating layer may be disposed between the high-speed deposited gate insulating layer and the passivation layer. In this case, the density of the second buffer layer is greater than the density of the high-speed deposited gate insulating layer.

[0045] In other embodiments of the present invention, reference Figure 2 The insulating layer may include a passivation layer 500, and a gate insulating layer 400 is disposed between the first transparent electrode 200 and the base substrate 100. In this case, the density of the second buffer layer 320 is greater than that of the passivation layer 600. During the etching process of the passivation layer and the buffer layer, the second buffer layer can avoid the risk of undercutting. The array substrate of this embodiment corresponds to a high-aperture advanced super-dimensional field switching (HADS) array substrate. In this case, the first transparent electrode 200 is a pixel electrode, and the second transparent electrode 600 is a common electrode.

[0046] In this embodiment, the material of the passivation layer may include silicon nitride, and the material of the gate insulating layer may be the same as or different from the material of the passivation layer. For example, the gate insulating layer may be a silicon nitride film layer, or the gate insulating layer may be a composite film layer of silicon nitride and silicon oxide. According to specific embodiments of the present invention, the passivation layer 600 may be a high-speed deposition passivation layer. In other specific embodiments, a low-speed deposition passivation layer may be further provided between the high-speed deposition passivation layer and the second transparent electrode. In this case, the density of the second buffer layer is greater than the density of the high-speed deposition passivation layer.

[0047] There is no particular limitation on the material of the base substrate. For example, the base substrate may be a glass substrate.

[0048] The array substrate of the present invention also includes a thin film transistor, which includes a gate, a gate insulation layer, an active layer, a source / drain metal layer, a passivation layer and other structures. Among them, the gate insulation layer and the gate insulation layer 400 in the thin film transistor can be the same film layer, and the passivation layer and the passivation layer 500 in the thin film transistor can be the same film layer.

[0049] In another aspect, the present invention provides a display panel. The display panel includes the array substrate described above. Thus, the display panel has all the features and benefits of the array substrate described above. In general, the display panel has a low undercut risk during the manufacturing process and a high transmittance.

[0050] There are no special requirements for the specific type of display device having the display panel, and technicians in this field can flexibly choose according to actual needs. For example, the display device can be any device and apparatus with display function, such as a mobile phone, a television, a notebook, an iPad, a game console, a Kindle, a car display device, etc.

[0051] Those skilled in the art will appreciate that, in addition to the display panel described above, the display device also includes structures or components necessary for a conventional display device, and may also include structures such as an audio module, a camera module, and a touch module.

[0052] In another aspect of the present invention, a method for manufacturing an array substrate is provided. The array substrate manufactured by this method may be the array substrate described above. Thus, the array substrate manufactured by this method may have the same features and benefits as the array substrate described above, and thus will not be described in detail here.

[0053] In some embodiments of the present invention, reference Figure 5 , the method comprising:

[0054] S100: forming a first transparent electrode on a base substrate.

[0055] In this step, a first transparent electrode is formed on the base substrate. The material and shape of the first transparent electrode have been described in detail above and will not be repeated here. The method for forming the first transparent electrode is not particularly limited, and those skilled in the art can use common processes to form the first transparent electrode.

[0056] S200: forming a buffer layer on a side of the first transparent electrode away from the base substrate.

[0057] In this step, a buffer layer is formed on a side of the first transparent electrode away from the base substrate. The formed buffer layer includes a first buffer layer and a second buffer layer stacked together. The first buffer layer is disposed adjacent to the first transparent electrode. The ratio of the bulk density of NH bonds to Si-H bonds in the first buffer layer is greater than the ratio of the bulk density of NH bonds to Si-H bonds in the second buffer layer. The first buffer layer is also thinner than the second buffer layer.

[0058] In some embodiments of the present invention, the buffer layer is formed by chemical vapor deposition, specifically, plasma-enhanced chemical vapor deposition, with the deposited gases including silane, ammonia, and nitrogen. The density of the formed second buffer layer is greater than the density of the subsequently formed insulating layer. During the fabrication process, the deposition power, gas flow rate, and pressure for forming the second buffer layer can be respectively lower than the deposition power, gas flow rate, and pressure for forming the insulating layer, so that the deposited gas fully reacts to obtain a second buffer layer with a higher density. This can prevent undercutting risks when etching the insulating layer and the buffer layer.

[0059] In this step, a first buffer layer is first formed on the side of the first transparent electrode away from the base substrate, and then a second buffer layer is formed on the side of the first buffer layer away from the first transparent electrode. The silane flow rate for forming the first buffer layer is less than the silane flow rate for forming the second buffer layer. In this case, the ammonia flow rate for forming the first buffer layer is consistent with the ammonia flow rate for forming the second buffer layer, and preferably, the difference between the silane flow rate for forming the second buffer layer and the silane flow rate for forming the first buffer layer is not less than 200 sccm. Alternatively, the ammonia flow rate for forming the first buffer layer is greater than the ammonia flow rate for forming the second buffer layer. In this case, the silane flow rate for forming the first buffer layer is consistent with the silane flow rate for forming the second buffer layer, and preferably, the difference between the ammonia flow rate for forming the first buffer layer and the ammonia flow rate for forming the second buffer layer is not less than 1000 sccm. Alternatively, the silane flow rate for forming the first buffer layer is less than the silane flow rate for forming the second buffer layer, and the ammonia flow rate for forming the first buffer layer is greater than the ammonia flow rate for forming the second buffer layer. Preferably, the difference between the silane flow rate for forming the second buffer layer and the silane flow rate for forming the first buffer layer is no less than 200 sccm, and the difference between the ammonia flow rate for forming the first buffer layer and the ammonia flow rate for forming the second buffer layer is no less than 1000 sccm. Because the gas flow rate for depositing the second buffer layer is lower than the gas flow rate for depositing the insulating layer, the hydrogen ions generated during the deposition of the second buffer layer are reduced. Therefore, the above-mentioned conditions for forming the first buffer layer result in fewer hydrogen ions generated during the deposition of the first buffer layer, and thus fewer small black spots precipitated on the first transparent electrode, thereby improving the transmittance of the array substrate.

[0060] In some embodiments of the present invention, the silane flow rate for forming the second buffer layer can be 600-1400 sccm, for example, 600 sccm, 800 sccm, 1000 sccm, 1200 sccm, 1300 sccm, or 1400 sccm, and the ammonia flow rate for forming the second buffer layer can be 2000-10000 sccm, for example, 2000 sccm, 4000 sccm, 6000 sccm, 8000 sccm, or 10000 sccm. Under the above gas flow rates, a second buffer layer having a higher density than the insulating layer can be obtained, and less hydrogen ions are generated during the formation of the second buffer layer. In some specific embodiments of the present invention, the deposition power for forming the second buffer layer can be 12 kW and the pressure can be 1000 mT.

[0061] The gas flow rate of the first buffer layer can be adjusted based on the gas flow rate of the second buffer layer to obtain a first buffer layer that can improve the transmittance of the array substrate. The silane flow rate for forming the first buffer layer can be in the range of 600-1400 sccm, and the ammonia flow rate for forming the first buffer layer can be in the range of 2000-10000 sccm, and the ammonia flow rate for forming the first buffer layer is consistent with the ammonia flow rate for forming the second buffer layer, and the silane flow rate for forming the first buffer layer is less than the silane flow rate for forming the second buffer layer. Preferably, the difference in the silane flow rates of the two is not less than 200 sccm. Alternatively, the silane flow rate for forming the first buffer layer is consistent with the silane flow rate for forming the second buffer layer, and the ammonia flow rate for forming the first buffer layer is greater than the ammonia flow rate for forming the second buffer layer. Preferably, the difference in the ammonia flow rates of the two is not less than 1000 sccm. Alternatively, the silane flow rate for forming the first buffer layer is less than the silane flow rate for forming the second buffer layer, and the ammonia flow rate for forming the first buffer layer is greater than the ammonia flow rate for forming the second buffer layer. Preferably, the difference between the silane flow rates is no less than 200 sccm, and the difference between the ammonia flow rates is no less than 1000 sccm. Under these preferred gas flow rates, the ratio of the bulk density of NH bonds to Si-H bonds in the formed first buffer layer can be 1.1-3 times the ratio of the bulk density of NH bonds to Si-H bonds in the second buffer layer, significantly improving the transmittance of the array substrate.

[0062] Since reducing the silane flow rate and increasing the ammonia flow rate will soften the first buffer layer, the thickness of the first buffer layer is made smaller than that of the second buffer layer, so that the second buffer layer can play a good role in avoiding the undercut risk and the first buffer layer can play a good role in improving the transmittance of the array substrate.

[0063] The specific thicknesses of the first buffer layer and the second buffer layer have been described in detail above and will not be repeated here.

[0064] S300: forming an insulating layer on a side of the buffer layer away from the first transparent electrode.

[0065] In this step, an insulating layer is formed on a side of the buffer layer away from the first transparent electrode. The insulating layer is made of an insulating material that generates hydrogen ions during the formation of the insulating layer. Specifically, the insulating layer can be formed by a plasma-enhanced chemical vapor deposition process using a deposition gas comprising silane, ammonia, and nitrogen. During the deposition process, the silane, ammonia, and nitrogen react to form silicon nitride and generate hydrogen ions.

[0066] In this step, a gate insulating layer can be first formed on the side of the buffer layer away from the first transparent electrode, and then a passivation layer can be formed on the side of the gate insulating layer away from the buffer layer. The gate insulating layer and the passivation layer constitute the insulating layer to form the ADS array substrate. In this case, the density of the second buffer layer is greater than the density of the gate insulating layer. This step also includes the steps of etching the gate insulating layer and the buffer layer to obtain patterned gate insulating layer and buffer layer, and etching the passivation layer to obtain a patterned passivation layer.

[0067] Alternatively, before S100, a gate insulating layer is first formed on the base substrate, and then a first transparent electrode is formed on the side of the gate insulating layer away from the base substrate. In this step, a passivation layer is formed on the side of the buffer layer away from the first transparent electrode, and the passivation layer constitutes the insulating layer to form the HADS array substrate. In this case, the density of the second buffer layer is greater than the density of the passivation layer. This step also includes the step of etching the passivation layer and the buffer layer to obtain a patterned passivation layer and buffer layer.

[0068] There is no particular limitation on the specific parameters for forming the gate insulating layer and the passivation layer, and those skilled in the art can design them according to actual conditions.

[0069] S400: forming a second transparent electrode on a side of the insulating layer away from the buffer layer.

[0070] In this step, a second transparent electrode is formed on the side of the insulating layer away from the buffer layer. The material and shape of the second transparent electrode have been described in detail previously and will not be repeated here. The method for forming the second transparent electrode is not particularly limited, and those skilled in the art can use conventional processes to form the second transparent electrode.

[0071] The present invention forms two buffer layers through a chemical vapor deposition process, forming a denser second buffer layer at lower power, gas flow, and pressure. Based on the deposition conditions of the second buffer layer, the first buffer layer is formed by reducing the silane flow and / or increasing the ammonia flow. The thickness of the first buffer layer is thinner than that of the second buffer layer. The first buffer layer is used to increase the transmittance of the array substrate, and the second buffer layer is used to reduce the undercut risk, so that the obtained array substrate has a lower undercut risk and a higher transmittance. The buffer layer formation process is the same as the insulating layer formation process, and only the process parameters are adjusted. Therefore, the buffer layer can be produced using existing production lines. The production process is simple and easy to implement, has mass production capabilities, and does not affect production capacity and product reliability evaluation.

[0072] The following examples illustrate the present invention using specific gas flow rates during the deposition of the first and second buffer layers. It should be noted that the following examples are intended only to illustrate the present invention and should not be construed as limiting its scope. Where specific techniques or conditions are not specified in the examples, the techniques or conditions described in relevant literature or in the product specifications shall prevail.

[0073] Example 1

[0074] The array substrate includes a first transparent electrode, a first buffer layer, a second buffer layer, a gate insulating layer, a passivation layer, and a second transparent electrode stacked in sequence on a glass substrate. The first transparent electrode and the second transparent electrode are made of ITO. The first buffer layer, the second buffer layer, the gate insulating layer, and the passivation layer are all formed using a plasma-enhanced chemical vapor deposition process, and the deposition gas is a mixture of silane, ammonia, and nitrogen.

[0075] The deposition power of the first buffer layer is 12kw, the pressure is 1000mT, the silane flow rate is 1000sccm, the ammonia flow rate is 4000sccm, the nitrogen flow rate is 52800sccm, and the ventilation time is 3s. The deposition power of the second buffer layer is 12kw, the pressure is 1000mT, the silane flow rate is 1200sccm, the ammonia flow rate is 2000sccm, the nitrogen flow rate is 52800sccm, and the ventilation time is 11s.

[0076] The transmittance TR of the array substrate in this embodiment can reach 92.38%.

[0077] Example 2

[0078] This embodiment is basically the same as embodiment 1, except that the deposition time of the first buffer layer is 5 seconds, and the deposition time of the second buffer layer is 9 seconds.

[0079] The transmittance TR of the array substrate in this embodiment can reach 92.55%.

[0080] Example 3

[0081] This embodiment is basically the same as embodiment 2, except that the silane flow rate of the second buffer layer is 1400 sccm.

[0082] The transmittance TR of the array substrate in this embodiment can reach 92.54%.

[0083] Example 4

[0084] This embodiment is basically the same as the embodiment 1, except that the ammonia flow rate of the first buffer layer is 2000 sccm.

[0085] The transmittance TR of the array substrate in this embodiment can reach 91.42%.

[0086] Example 5

[0087] This embodiment is substantially the same as the embodiment 1, except that the silane flow rate of the first buffer layer is 1200 sccm.

[0088] The transmittance TR of the array substrate in this embodiment can reach 91.8%.

[0089] Comparative Example 1

[0090] The difference between Comparative Example 1 and Example 1 is that only the second buffer layer is produced without producing the first buffer layer, and the ventilation time of the second buffer layer is 14 s.

[0091] The transmittance TR of the array substrate in Comparative Example 1 can reach 90.3%.

[0092] Comparative Example 2

[0093] The difference between Comparative Example 2 and Comparative Example 1 is that the silane flow rate of the second buffer layer is 1000 sccm, and the ammonia flow rate is 4000 sccm.

[0094] The transmittance TR of the array substrate in Comparative Example 2 can reach 92.56%.

[0095] The transmittance of the array substrates of Examples 1-5 and Comparative Examples 1-2 was tested. Table 1 shows the deposition conditions of the buffer layers of the various Examples and Comparative Examples, as well as the transmittance of the array substrates.

[0096] Table 1

[0097]

[0098] As can be seen from Examples 1-5 and Comparative Example 1, the present invention significantly improves the transmittance of the array substrate by providing two buffer layers and, based on the deposition conditions of the second buffer layer, reducing the silane flow rate and / or increasing the ammonia flow rate to form the first buffer layer. This improvement is greater than 1% (TR improvement is the ratio of the difference between the transmittance of each example and the transmittance of Comparative Example 1 to the transmittance of Comparative Example 1). Furthermore, when both the silane flow rate is reduced and the ammonia flow rate is increased, such as in Examples 1-3, the transmittance of the array substrate can be improved by more than 2%.

[0099] The array substrates of Examples 1-5 have a low undercut risk and all pass the reliability evaluation.

[0100] As can be seen from Example 1 and Comparative Example 2, Comparative Example 2 uses a single buffer layer. Compared to Comparative Example 1, the silane flow rate during the deposition of the single buffer layer in Comparative Example 2 was reduced, while the ammonia flow rate was increased. Although the transmittance of Comparative Example 2 was significantly improved, its undercut risk was high, and it failed the reliability evaluation, resulting in poor display. The array substrate of Example 1 had a lower undercut risk, passed the reliability evaluation, and achieved a transmittance comparable to that of Comparative Example 2. In other words, the addition of a thinner first buffer layer achieved a transmittance improvement equivalent to that of a full buffer layer in Comparative Example 2.

[0101] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0102] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0103] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. An array substrate, characterized in that: include: A first transparent electrode, an insulating layer, and a second transparent electrode are sequentially stacked on a base substrate, wherein a material of the insulating layer includes an insulating material that generates hydrogen ions during the formation of the insulating layer; as well as A buffer layer is arranged between the first transparent electrode and the insulating layer, the buffer layer includes a first buffer layer and a second buffer layer arranged in a stacked manner, the first buffer layer is arranged close to the first transparent electrode, the density of the second buffer layer is greater than the density of the insulating layer, the ratio of the volume density of NH bonds to Si-H bonds in the first buffer layer is greater than the ratio of the volume density of NH bonds to Si-H bonds in the second buffer layer, and the thickness of the first buffer layer is less than the thickness of the second buffer layer.

2. The array substrate according to claim 1, wherein: The volume density ratio of NH bonds to Si—H bonds in the first buffer layer is 1.1-3 times the volume density ratio of NH bonds to Si—H bonds in the second buffer layer.

3. The array substrate according to claim 1, wherein: The thickness of the first buffer layer is 4. The array substrate according to claim 3, wherein: The thickness of the buffer layer is 5. The array substrate according to claim 1, wherein: The insulating layer includes a gate insulating layer and a passivation layer that are stacked. The gate insulating layer is arranged close to the buffer layer, and the density of the second buffer layer is greater than the density of the gate insulating layer.

6. The array substrate according to claim 1, wherein: The insulating layer includes a passivation layer, and a gate insulating layer is provided between the base substrate and the first transparent electrode.

7. The array substrate according to claim 1, wherein: The insulating layer and the buffer layer are made of silicon nitride, and the first transparent electrode and the second transparent electrode are made of at least one of indium tin oxide and indium zinc oxide.

8. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 7.

9. A method for manufacturing an array substrate, characterized in that: include: forming a first transparent electrode on the base substrate; forming a buffer layer on a side of the first transparent electrode away from the base substrate, the buffer layer comprising a first buffer layer and a second buffer layer stacked, the first buffer layer being disposed close to the first transparent electrode, the ratio of the volume density of NH bonds to Si-H bonds in the first buffer layer being greater than the ratio of the volume density of NH bonds to Si-H bonds in the second buffer layer, and the thickness of the first buffer layer being less than the thickness of the second buffer layer; forming an insulating layer on a side of the buffer layer away from the first transparent electrode, wherein the insulating layer is made of an insulating material that generates hydrogen ions during the formation of the insulating layer, and the density of the second buffer layer is greater than that of the insulating layer; A second transparent electrode is formed on a side of the insulating layer away from the buffer layer.

10. The method according to claim 9, characterized in that The buffer layer is formed by chemical vapor deposition, wherein the gas used for the chemical vapor deposition includes silane, ammonia and nitrogen. The silane flow rate for forming the first buffer layer is smaller than the silane flow rate for forming the second buffer layer, and / or the ammonia flow rate for forming the first buffer layer is larger than the ammonia flow rate for forming the second buffer layer.

11. The method according to claim 9, characterized in that The buffer layer is formed by chemical vapor deposition, wherein the gas used for the chemical vapor deposition includes silane, ammonia and nitrogen. The silane flow rate for forming the first buffer layer is less than the silane flow rate for forming the second buffer layer, and the difference between the two is not less than 200 sccm; and / or, The ammonia flow rate for forming the first buffer layer is greater than the ammonia flow rate for forming the second buffer layer, and the difference between the two is not less than 1000 sccm.

12. The method according to claim 10 or 11, characterized in that The silane flow rates for forming the second buffer layer and the silane flow rates for forming the first buffer layer are 600-1400 sccm respectively, and the ammonia flow rates for forming the second buffer layer and the ammonia flow rates for forming the first buffer layer are 2000-10000 sccm respectively.

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