Preparation method of heterojunction solar cell and heterojunction solar cell

Abstract

The invention discloses a preparation method of a heterojunction solar cell and the heterojunction solar cell. The preparation method comprises the following steps: sequentially preparing a first transparent conductive oxide film layer and a second transparent conductive oxide film layer on the main surface of a battery substrate in a laminating manner; covering the second transparent conductive oxide film layer by using a first mask layer with a grid line groove; removing the part, corresponding to the grid line groove, in the second transparent conductive oxide film layer through an acid solution; forming a metal grid line in the grid line groove; the first mask layer is removed, and the reaction rate of the first transparent conductive oxide film layer and the acid solution is smaller than that of the second transparent conductive oxide film layer and the acid solution. Therefore, the integrity of the first transparent conductive oxide film layer can be ensured, the first transparent conductive oxide film layer can be ensured to be in close contact with the metal grid line, the risk that the metal grid line is broken or falls off is reduced, and the performance of the heterojunction solar cell can be improved.

Description

Technical Field

[0001] The invention relates to a preparation method of a heterojunction solar cell and a heterojunction solar cell. Background Art

[0002] Currently, using copper electroplating instead of low-temperature silver paste printing is one of the main means of reducing the production cost of heterojunction solar cells. Specifically, a transparent conductive oxide layer is formed on the cell substrate, and a metal seed layer is deposited on the transparent conductive oxide layer. The metal seed layer is patterned, and then the structure with the patterned metal seed layer is immersed in an acidic electroplating solution, whereupon metal grid lines are formed on the patterned metal seed layer by electroplating. After the structure with the patterned metal seed layer is immersed in the acidic electroplating solution, the transparent conductive oxide layer comes into contact with the acidic electroplating solution. The acidic electroplating solution corrodes the transparent conductive oxide layer, weakening the bonding between the transparent conductive oxide layer and the metal seed layer. This increases the risk of grid breakage or grid line detachment, and results in poor performance of the grid lines and heterojunction solar cells, such as short-circuit current, open-circuit voltage, efficiency, and reliability. Summary of the Invention

[0003] In view of this, the present invention provides a method for preparing a heterojunction solar cell and a heterojunction solar cell. The method for preparing a heterojunction solar cell can prevent the first transparent conductive oxide film layer from being corroded, ensure the integrity of the first transparent conductive oxide film layer, and ensure that the first transparent conductive oxide film layer is in close contact with the metal grid line, thereby reducing the risk of the metal grid line breaking or falling off, and helping to improve the performance of the heterojunction solar cell.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0005] In a first aspect, the present invention provides a method for preparing a heterojunction solar cell, comprising:

[0006] Step 1: sequentially stacking a first transparent conductive oxide film layer and a second transparent conductive oxide film layer on the main surface of the battery substrate, wherein the corrosion resistance of the first transparent conductive oxide film layer is higher than that of the second transparent conductive oxide film layer;

[0007] Step 2: Covering the second transparent conductive oxide film layer with a first mask layer having a gate line groove;

[0008] Step 3: removing the portion of the second transparent conductive oxide film layer corresponding to the gate line groove using an acid solution;

[0009] Step 4: forming a metal gate line in the gate line groove;

[0010] Step 5: removing the first mask layer.

[0011] In a second aspect, an embodiment of the present invention provides a heterojunction solar cell, comprising: a cell substrate, a first transparent conductive oxide film layer, a discontinuous second transparent conductive oxide film layer, and a metal grid line, wherein:

[0012] The metal grid lines are embedded in the discontinuous positions of the second transparent conductive oxide film layer.

[0013] The metal grid line is in contact with a cross section of the second transparent conductive oxide film layer and a main surface of the first transparent conductive oxide film layer.

[0014] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects:

[0015] The technical solution provided by the embodiment of the present invention is to prepare a first transparent conductive oxide film layer and a second transparent conductive oxide film layer with different corrosion resistance by sequentially stacking on the surface of the battery substrate, and cooperate with a first mask layer with a gate line groove and an acid solution treatment. Since the corrosion resistance of the first transparent conductive oxide film layer is higher than that of the second transparent conductive oxide film layer, and with the cooperation of the first mask layer with the gate line groove, the portion of the second transparent conductive oxide film layer corresponding to the gate line groove is first exposed to the acid solution, so that while the portion of the second transparent conductive oxide film layer corresponding to the gate line groove is removed, the first transparent conductive oxide film layer can be prevented from being corroded, thereby ensuring the integrity of the first transparent conductive oxide film layer and ensuring close contact between the first transparent conductive oxide film layer and the metal gate line, thereby reducing the risk of the metal gate line being broken or falling off, and helping to improve the performance of heterojunction solar cells.

[0016] In addition, since the corrosion resistance of the first transparent conductive oxide film layer is higher than that of the second transparent conductive oxide film layer, that is, the first transparent conductive oxide film layer and the second transparent conductive oxide film layer have different acid sensitivities, and with the cooperation of the first mask layer having the gate line groove, the portion of the second transparent conductive oxide film layer corresponding to the gate line groove is first contacted with the acid solution, so that the acid solution removes the portion of the second transparent conductive oxide film layer corresponding to the gate line groove while retaining the first transparent conductive oxide film layer. This has a relatively wide operational process window, making the above technical solution industrializable. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1 is a schematic diagram of the main process of a method for preparing a heterojunction solar cell according to an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of the main process of a method for preparing a heterojunction solar cell according to another embodiment of the present invention;

[0019] Figure 3 is a method according to an embodiment of the present invention corresponding to Figure 1 Schematic diagram of structural changes from step S101 to step S103;

[0020] Figure 4 is a method according to an embodiment of the present invention corresponding to Figure 1 Schematic diagram of the structural changes from step S103 to step S105;

[0021] Figure 5 is a method according to an embodiment of the present invention corresponding to Figure 2 Schematic diagram of the structural changes from step S101 to step S103;

[0022] Figure 6 is a method according to an embodiment of the present invention corresponding to Figure 2 Schematic diagram of the structural change from step S103 to step S105;

[0023] Figure 7 This is a schematic diagram of the main flow of a specific implementation of step S104 according to an embodiment of the present invention;

[0024] Figure 8 is a schematic diagram of a first structural change corresponding to a specific implementation of step S104 according to an embodiment of the present invention;

[0025] Figure 9 is a schematic diagram of a second structural change corresponding to a specific implementation of step S104 according to an embodiment of the present invention;

[0026] Figure 10 is a schematic diagram of a first structure of a heterojunction solar cell according to an embodiment of the present invention;

[0027] Figure 11 is a schematic diagram of a second structure of a heterojunction solar cell according to an embodiment of the present invention;

[0028] Figure 12 is a schematic diagram of a third structure of a heterojunction solar cell according to an embodiment of the present invention;

[0029] Figure 13 3 is a schematic diagram of a fourth structure of a heterojunction solar cell according to an embodiment of the present invention.

[0030] Reference numerals:

[0031] 10 - battery substrate; 20 - first transparent conductive oxide film layer; 30 - second transparent conductive oxide film layer; 40 - first mask layer; 41 - grid line groove; 50 - metal grid line; 51 - metal seed layer; 52 - second mask layer; 53 - electroplating layer; 54 - conductive protective layer; 60 - protective layer. DETAILED DESCRIPTION

[0032] Using electroplating technology instead of low-temperature printing is a research hotspot for reducing the cost of heterojunction solar cells. As described in the background art, the current main process of the electroplating process is: depositing a metal seed layer (such as a copper seed layer) on the surface of the transparent conductive oxide film layer of the battery substrate → patterning the metal seed layer → immersing it in an acidic electroplating solution for electroplating to electroplate metal on the remaining metal seed layer. In the existing electroplating process, after patterning the metal seed layer, the transparent conductive oxide film layer will be exposed. The exposed transparent conductive oxide film layer will come into contact with the acidic electroplating solution and will be corroded by the acidic electroplating solution. This corrosion is uncontrollable and will affect the transparent conductive oxide film area covered by the patterned metal seed layer. In particular, the transparent conductive oxide film layer prepared under the suede structure is more susceptible to corrosion in the acidic electroplating solution, resulting in a weakened bonding force between the patterned metal seed layer and the transparent conductive oxide film layer and poor contact. In addition, the corrosion of the transparent conductive oxide film layer will affect the carrier transport capacity of the heterojunction solar cell and affect the efficiency of the heterojunction solar cell.

[0033] In order to solve the above problems existing in the prior art, embodiments of the present invention provide a method for preparing a heterojunction solar cell and a heterojunction solar cell with a novel structure.

[0034] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0035] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features specified as "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise explicitly and specifically defined. For example, the first transparent conductive oxide film layer 20 and the second transparent conductive oxide film layer 30 are used to distinguish two transparent conductive oxide film layers with different reaction rates with acid solutions, different corrosion resistance, and different relative positional relationships. That is, the reaction rate of the first transparent conductive oxide film layer 20 with the acid solution is lower than the reaction rate of the second transparent conductive oxide film layer 30 with the acid solution, the corrosion resistance of the first transparent conductive oxide film layer 20 is higher than the corrosion resistance of the second transparent conductive oxide film layer 30, and the first transparent conductive oxide film layer 20 is located between the battery substrate 10 and the second transparent conductive oxide film layer 30. For another example, the first mask layer 40 is formed before the metal seed layer 51, and the second mask layer 52 is formed after the metal seed layer 51.

[0036] The outside of a structure (or the outside of a structure) in embodiments of the present invention is generally based on the battery substrate 10 or the silicon substrate 11. In the thickness direction of the battery substrate 10 or the silicon substrate 11, the side of a structure that is away from the battery substrate 10 or the silicon substrate 11 is the outside of the structure or the outside of the structure. For example, the first photosensitive material is coated on the outside of the second transparent conductive oxide film 30. That is, in the thickness direction of the battery substrate 10, the first photosensitive material is coated on the side of the second transparent conductive oxide film 30 that is away from the battery substrate 10.

[0037] in, Figure 1 A schematic diagram showing the main process of a method for preparing a heterojunction solar cell provided by one embodiment of the present invention; Figure 2 A schematic diagram showing the main process of another method for preparing a heterojunction solar cell provided by another embodiment of the present invention; Figure 3 and Figure 4 Show Figure 1 Schematic diagram of structural changes corresponding to the provided preparation method; Figure 5 and Figure 6 Shown corresponding to Figure 2 A schematic diagram of the structural changes of the preparation method provided; Figure 7 A schematic diagram showing the main flow of a specific implementation of step S104; Figure 8 and Figure 9 Shown separately Figure 7 A schematic diagram of structural changes corresponding to a specific implementation of step S104 is shown; Figures 10 to 13 Schematic diagrams showing cross-sectional structures of heterojunction solar cells with different structures provided by embodiments of the present invention.

[0038] like Figure 1 As shown, the method for preparing the heterojunction solar cell may include the following steps:

[0039] Step S101 : sequentially stacking a first transparent conductive oxide film layer 20 and a second transparent conductive oxide film layer 30 on a main surface of a battery substrate 10 .

[0040] The battery substrate 10 is generally the basis for forming the first transparent conductive oxide film layer 20 and the second transparent conductive oxide film layer 30. For example, Figure 3 and Figure 4As shown, the battery substrate 10 may include a silicon substrate 11, a first intrinsic silicon thin film layer 12 and a second intrinsic silicon thin film layer 14 respectively disposed on the two main surfaces of the silicon substrate, a first doped layer 13 stacked on the outside of the first intrinsic silicon thin film layer 12, and a second doped layer 15 stacked on the outside of the second intrinsic silicon thin film layer 14. In addition, the battery substrate 10 may also include a silicon substrate 11, a first tunneling oxide layer and a second tunneling oxide layer respectively disposed on the two main surfaces of the silicon substrate, a first doped polysilicon layer stacked on the outside of the first tunneling oxide layer, and a second doped polysilicon layer stacked on the outside of the second tunneling oxide layer. It is worth noting that Figure 3 and Figure 4 The following describes the structural changes during the manufacturing process using a battery substrate 10 comprising a silicon substrate 11, a first intrinsic silicon thin film layer 12, a second intrinsic silicon thin film layer 14, a first doped layer 13, and a second doped layer 15 as an example. Based on this, those skilled in the art will be able to understand the structural changes during the manufacturing process of battery substrates 10 with other structures.

[0041] For example, the battery substrate 10 may include a silicon substrate 11, a first intrinsic silicon thin film layer 12 and a second intrinsic silicon thin film layer 14 disposed on two main surfaces of the silicon substrate, a first doped layer 13 stacked on the outside of the first intrinsic silicon thin film layer 12, and a second doped layer 15 stacked on the outside of the second intrinsic silicon thin film layer 14. When the silicon substrate 11 is an N-type silicon substrate, the first doped layer 13 may be an N-type doped amorphous silicon layer, and the second doped layer 15 may be a P-type doped amorphous silicon layer. More specifically, the first doped layer 13 may be an N-type doped amorphous silicon layer, and the second doped layer 15 may be a P-type doped amorphous silicon layer. The preparation order of the first intrinsic silicon thin film layer 12, the second intrinsic silicon thin film layer 14, the N-type doped amorphous silicon layer, and the P-type doped amorphous silicon layer is generally as follows: second intrinsic silicon thin film layer 14 → first intrinsic silicon thin film layer 12 → N-type doped amorphous silicon layer → P-type doped amorphous silicon layer. The first intrinsic silicon thin film layer 12 and the N-type doped amorphous silicon layer are located on the front side of the heterojunction solar cell, and the second intrinsic silicon thin film layer 14 and the P-type doped amorphous silicon layer are located on the back side of the heterojunction solar cell. The first intrinsic silicon thin film layer 12, the N-type doped amorphous silicon layer, the second intrinsic silicon thin film layer 14, and the P-type doped amorphous silicon layer can be formed by low-temperature plasma chemical vapor deposition. During the deposition process, the gas flow ratio SiH4 / (SiH4+H2) in the deposition chamber is controlled to be 1:1 to 8:1 (wherein SiH4 and a SiH4+H2 mixed gas are introduced into the deposition chamber, respectively. It is worth noting that SiH4+H2 is a mixed gas of SiH4 and H2. Generally, H2 cannot be introduced alone and is prone to explosion, so it is generally presented in the form of a mixed gas. In this embodiment, it is presented as a SiH4+H2 mixed gas). For example, the gas flow ratio can be 1:1, 2:1, 1:3, 1:5, 1:6, or 1:8. The power used for low-temperature plasma chemical vapor deposition is 0.5 W / cm 2 ~3.5W / cm 2 , for example, the power can be 0.5W / cm 2 , 1W / cm 2 , 1.5W / cm 2 , 2W / cm 2 , 2.5W / cm 2 、3W / cm 2 or 3.5W / cm 2The temperature used for low-temperature plasma chemical vapor deposition can be 373K~473K. For example, the temperature can be 373K, 383K, 393K, 403K, 413K, 423K, 433K, 453K or 473K. Furthermore, the thickness of the first intrinsic silicon thin film layer 12 is generally 3nm~6nm (for example, the thickness of the first intrinsic silicon thin film layer 12 may be 3nm, 4nm, 5nm or 6nm, etc.), the thickness of the N-type doped amorphous silicon layer is generally 5nm~10nm (for example, the thickness of the first intrinsic silicon thin film layer 12 may be 5nm, 6nm, 8nm or 10nm, etc.), the thickness of the second intrinsic silicon thin film layer 14 is generally 3nm~9nm (for example, the thickness of the second intrinsic silicon thin film layer 14 may be 3nm, 4nm, 5nm, 6nm, 8nm or 9nm, etc.), and the thickness of the P-type doped amorphous silicon layer is generally 5nm~15nm (for example, the thickness of the first intrinsic silicon thin film layer 12 may be 5nm, 6nm, 8nm, 10nm, 12nm or 15nm, etc.).

[0042] The first transparent conductive oxide film layer 20 can be a single layer or a stacked layer. For the stacked layer of the first transparent conductive oxide film layer 20, the components contained in each layer are basically the same. In addition, the second transparent conductive oxide film layer 30 can be a single layer or a stacked layer. For the stacked layer of the second transparent conductive oxide film layer 30, the components contained in each layer are also basically the same. However, the components contained in the first transparent conductive oxide film layer 20 and the components contained in the second transparent conductive oxide film layer 30 are different and / or the first transparent conductive oxide film layer 20 and the second transparent conductive oxide film layer 30 have different densities (high density, high corrosion resistance, low density, low corrosion resistance), so that the reaction rate of the first transparent conductive oxide film layer 20 with the acid solution is lower than the reaction rate of the second transparent conductive oxide film layer 30 with the acid solution. That is, the components contained in the first transparent conductive oxide film layer 20 may be different from the components contained in the second transparent conductive oxide film layer 30, or the first transparent conductive oxide film layer 20 may have a higher density than the second transparent conductive oxide film layer 30. Generally speaking, the first transparent conductive oxide film layer 20 has a higher corrosion resistance than the second transparent conductive oxide film layer 30.

[0043] It is worth noting that the corrosion resistance involved in the embodiments of the present invention generally refers to acid corrosion resistance, that is, the acid corrosion resistance of the first transparent conductive oxide film layer 20 is higher than that of the second transparent conductive oxide film layer 30. In other words, when the first transparent conductive oxide film layer 20 and the second transparent conductive oxide film layer 30 are in the same acidic environment (such as oxalic acid solution), the second transparent conductive oxide film layer 30 is more easily corroded, so that the reaction rate of the first transparent conductive oxide film layer 20 with the acid solution is lower than the reaction rate of the second transparent conductive oxide film layer 30 with the acid solution.

[0044] In addition, the surface of the battery substrate 10 can have a velvet structure or a polished surface structure. The drawings provided in the embodiments of the present invention illustrate the polished surface structure as an example. Based on this, those skilled in the art can understand the relative positional relationship between the various structures on the velvet structure and the structural changes corresponding to each step.

[0045] For the velvet structure, the planar silicon substrate 11 can be subjected to the steps of rough polishing, pre-cleaning, velveting, cleaning, pickling, drying, etc. in sequence to remove the damaged layer and impurities on the surface of the silicon wafer, and form a pyramid velvet structure on the front and back of the silicon wafer. Among them, KOH and hydrogen peroxide are generally used for pre-cleaning, and the bath temperature is 333K~343K (for example, the bath temperature can be 333K, 338K, 340K or 343K, etc.), and the processing time is 60s~180s (for example, the processing time can be 60s, 90s, 100s, 120s, 150s, 170s or 180s, etc.); KOH and additives are used for velvet, and the bath temperature is 333K~343K (for example, the bath temperature of the treatment process can be 333K, 338K, 340K or 343K, etc.), and the processing time is 120s. ~600s (for example, the processing time can be 120s, 150s, 170s, 180s, 200s, 250s, 300s, 350s, 400s, 450s, 500s, 540s or 600s, etc.); HF and HCl pickling are used, the pickling bath temperature is 298K~308K (for example, the bath temperature of the treatment process can be 298K, 308K, etc.), and the processing time is 60s~180s (for example, the processing time can be 60s, 90s, 100s, 120s, 150s, 170s or 180s, etc.). After the pure water cleaning is completed, the silicon substrate is cleaned again with hot water at a water temperature of about 323K to 333K (for example, the water temperature of this treatment process can be 323K, 333K, etc.). Each cleaning batch takes 60s to 180s (for example, the treatment time can be 60s, 90s, 100s, 120s, 150s, 170s or 180s, etc.). Finally, the silicon substrate is dried by blowing hot air from top to bottom to obtain a suede structure.

[0046] Step S102 : using a first mask layer 40 having a gate line groove 41 to cover the second transparent conductive oxide film layer 30 .

[0047] The gate line groove 41 is a through groove, which can partially expose the second transparent conductive oxide film layer 30 .

[0048] Step S103 : removing the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41 by using an acid solution.

[0049] In this step, a weak acid is generally selected to remove the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41. Preferably, oxalic acid is selected in this step.

[0050] The structural changes corresponding to the above steps S101 to S103 can be as follows: Figure 3 shown.

[0051] like Figure 3 As shown, due to the presence of the first mask layer 40, step S103 only removes the portion of the second transparent conductive oxide film 30 corresponding to the gate line groove 41, retaining the portion of the second transparent conductive oxide film 30 covered by the first mask layer 40. Furthermore, because the second transparent conductive oxide film 30 has lower acid corrosion resistance than the first transparent conductive oxide film 20, it is possible to effectively control the removal of only the second transparent conductive oxide film 30, while preserving the first transparent conductive oxide film 20 relatively intact. In particular, for a velvet structure, the solution provided by the embodiment of the present invention can also relatively completely preserve the first transparent conductive oxide film 20. During the acid treatment process, even if the first transparent conductive oxide film 20 is partially corroded, the presence of the second transparent conductive oxide film 30 will only increase the surface roughness of the first transparent conductive oxide film 20 without damaging the first transparent conductive oxide film 20. The increased roughness of the surface of the first transparent conductive oxide film layer 20 helps to improve the bonding strength between the subsequently formed metal grid lines 50 and the first transparent conductive oxide film layer 20, thereby improving the electrical stability of the metal grid lines 50, thereby effectively improving the photoelectric performance and stability of the heterojunction solar cell, and further improving the open circuit voltage and fill factor of the heterojunction solar cell.

[0052] Step S104 : forming a metal gate line 50 in the gate line groove 41 .

[0053] This step mainly forms the metal gate line 50 by electroplating.

[0054] Step S105 : removing the first mask layer 40 .

[0055] The structural changes brought about by the processing of step S104 and step S105 are as follows: Figure 4 shown.

[0056] from Figure 4As can be seen, the formed metal grid lines 50 not only form electrical contact with the first transparent conductive oxide film layer 20, but also the side surfaces of the metal grid lines 50 can contact the second transparent conductive oxide film layer 30, further improving electrical contact stability and preventing grid breakage or grid line detachment. Furthermore, if the metal grid lines 50 are copper grid lines, the presence of the second transparent conductive oxide film layer 30 can protect the copper grid lines' sides, preventing oxidation.

[0057] Furthermore, after the above step S101 and before step S102, the following may be further included: step S102', forming a protective layer 60 on the outer side of the second transparent conductive oxide film layer 30. Based on this, before step S103, the following may be further included: step S103', removing the portion of the protective layer 60 corresponding to the gate line groove 41 using a hydrofluoric acid solution. Specifically, for the embodiment including step S102' and step S103', as shown in FIG. Figure 2 As shown, it may include the following steps:

[0058] Step S101 : sequentially stacking a first transparent conductive oxide film layer 20 and a second transparent conductive oxide film layer 30 on a main surface of a battery substrate 10 .

[0059] The reaction rate of the first transparent conductive oxide film 20 with the acid solution is lower than that of the second transparent conductive oxide film 30 with the acid solution, that is, the acid corrosion resistance of the first transparent conductive oxide film 20 is higher than that of the second transparent conductive oxide film 30 .

[0060] The various structures involved in this step are above Figure 1 This has been described in the provided embodiments and will not be repeated here.

[0061] Step S102 ′: forming a protective layer 60 on the outer side of the second transparent conductive oxide film layer 30 .

[0062] The structural changes corresponding to this step are as follows Figure 5 shown.

[0063] The protective layer 60 can be a single layer or a stacked layer formed by plasma chemical deposition. The single layer or stacked layer includes one of silicon nitride, silicon oxynitride, and silicon oxide. The protective layer 60 can subsequently serve as a passivation anti-reflection layer for the heterojunction solar cell to improve the light utilization efficiency of the heterojunction solar cell. Furthermore, the protective layer 60 can protect the remaining portion of the second transparent conductive oxide film layer 30, further ensuring stable electrical contact between the metal grid line 50, the second transparent conductive oxide film layer 30, and the first transparent conductive oxide film layer 20.

[0064] For example, for a structure in which the protective layer 60 includes silicon nitride, the specific process is as follows: SiN is deposited on the outside of the second transparent conductive oxide film layer 30 in a mixed atmosphere with a flow ratio of SiH4 to NH3 of 1:5 to 2:1 and a pressure of 0.1 Pa to 10 Pa. x film layer. For example, the flow ratio of SiH4 and NH3 can be 1:5, 1:4, 1:2, 1:1 or 2:1, etc. In particular, the flow rate of SiH4 is in the range of 10sccm~20sccm (for example, the flow rate of SiH4 can be 10sccm, 12sccm, 15sccm or 20sccm, etc.), and the flow rate of NH3 is in the range of 10sccm~50sccm (for example, the flow rate of NH3 can be 10sccm, 15sccm, 20sccm, 30sccm, 35sccm, 40sccm or 50sccm, etc.). Preferably, the deposition temperature is controlled to be 373K~473K and the deposition time is 2min~4min. For example, the deposition temperature can be 373K, 383K, 398K, 423K, 433K, 453K, 463K or 473K, etc. More preferably, SiN x The thickness of the film layer can be 10nm~50nm. For example, the SiN x The thickness of the film layer can be 10nm, 15nm, 20nm, 25nm, 28nm, 30nm, 35nm, 38nm, 40nm, 45nm, 48nm or 50nm. x The deposition time required for the film layer is generally 120s~240s. For example, the formation of SiN x The deposition time required for the film layer is 120s, 180s or 240s, etc.

[0065] Step S102 : using a first mask layer 40 having a gate line groove 41 to cover the second transparent conductive oxide film layer 30 .

[0066] The first mask layer 40 is a hollow structure, which can expose the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41 .

[0067] Step S103 ′: using a hydrofluoric acid solution to remove the portion of the protection layer 60 corresponding to the gate line groove 41 .

[0068] The hydrofluoric acid will corrode the protective layer 60. Although this step will also have a certain corrosive effect on the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41, since the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41 needs to be removed in a subsequent step, the hydrofluoric acid in this step will not affect the subsequent acquisition of the desired groove structure.

[0069] The mass fraction of the hydrofluoric acid solution in this step is generally 15% to 20%. For example, the mass fraction of the hydrofluoric acid solution can be 15%, 17%, 18% or 20%.

[0070] Step S103 : removing the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41 by using an acid solution.

[0071] Regarding the above steps S101 → step S102' → step S102 → step S103' → step S103, the resulting structural changes are as follows: Figure 5 shown.

[0072] Step S104 : forming a metal gate line 50 in the gate line groove 41 .

[0073] Step S105 : removing the first mask layer 40 .

[0074] against Figure 1 or Figure 2 In the illustrated embodiment, a first transparent conductive oxide film layer 20 and a second transparent conductive oxide film layer 30 having different corrosion resistances are sequentially stacked on the surface of a cell substrate 10. Subsequently, a first mask layer 40 having a gateline groove and an acid solution treatment are performed. Because the acid corrosion resistance of the first transparent conductive oxide film layer 20 is higher than that of the second transparent conductive oxide film layer 30, i.e., the reaction rate of the first transparent conductive oxide film layer 20 with the acid solution is lower than that of the second transparent conductive oxide film layer 30 with the acid solution. Furthermore, with the cooperation of the first mask layer 40 having a gateline groove 41, the portion of the second transparent conductive oxide film layer 30 corresponding to the gateline groove 41 is first exposed to the acid solution. This allows the portion of the second transparent conductive oxide film layer 30 corresponding to the gateline groove 41 to be removed while corrosion of the first transparent conductive oxide film layer 20 is avoided, thereby ensuring the integrity of the first transparent conductive oxide film layer 20 and ensuring close contact between the first transparent conductive oxide film layer 20 and the metal gate line 50. This reduces the risk of the metal gate line 50 breaking or falling off, thereby helping to improve the performance of the heterojunction solar cell.

[0075] In addition, since the acid corrosion resistance of the first transparent conductive oxide film layer 20 is higher than that of the second transparent conductive oxide film layer 30, that is, the first transparent conductive oxide film layer 20 and the second transparent conductive oxide film layer 30 have different acid sensitivities, and with the cooperation of the first mask layer 40 having the gate line groove 41, the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41 is first exposed to the acid solution, so that the acid solution removes the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41 while retaining the first transparent conductive oxide film layer 20. This has a relatively wide operational process window, making the above technical solution suitable for industrialization.

[0076] Furthermore, by removing the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41, a groove for accommodating the metal gate line 50 can be formed in the second transparent conductive oxide film layer 30. This not only enables the metal gate line 50 to form a stable electrical contact with the second transparent conductive oxide film layer 30 and the first transparent conductive oxide film layer 20, but also ensures the stability of the metal gate line 50, reducing the risk of the metal gate line 50 being broken or falling off.

[0077] In addition, for Figure 2 In the embodiment shown, by introducing the protective layer 60, on the one hand, the non-removed area of ​​the second transparent conductive oxide film layer 30 and the first transparent conductive oxide film layer 20 can be better protected. On the other hand, the protective layer 60 can subsequently serve as a passivation anti-reflection layer to improve the light utilization rate of the prepared heterojunction solar cell, thereby improving the photoelectric conversion efficiency of the heterojunction solar cell.

[0078] Specifically, for the above Figure 1 or Figure 2 In the provided embodiment, a specific implementation of the above step S101 may include the following steps S1011 and S1012:

[0079] Step S1011 : forming a first transparent conductive oxide film layer 20 by magnetron sputtering under magnetron conditions of a power density of 1 W / mm-5 W / mm, an Ar flow rate of 50 sccm-200 sccm, and a pressure of 0.1 Pa-0.4 Pa.

[0080] The power density may be 1 W / mm, 2 W / mm, 2.5 W / mm, 3 W / mm, 3.5 W / mm, 4 W / mm, or 5 W / mm, etc. The Ar flow rate may be 50 sccm, 70 sccm, 100 sccm, 120 sccm, 150 sccm, 170 sccm, 180 sccm, or 200 sccm, etc. The pressure may be 0.1 Pa, 0.2 Pa, 0.3 Pa, or 0.4 Pa, etc.

[0081] Specifically, the first transparent conductive oxide film 20 prepared in this step contains an indium oxide content of no less than 97% by mass. In other words, any target material that can form a transparent conductive oxide film containing no less than 97% indium oxide by mass is sufficient. Exemplary targets include indium tin oxide, indium oxide, indium zinc oxide, indium gallium oxide, and indium cerium oxide. It can be understood that when an indium oxide target is used to prepare the first transparent conductive oxide film layer 20, the first transparent conductive oxide film layer 20 contains only indium oxide, and the mass fraction of the indium oxide is 100%. When an indium tin oxide, indium zinc oxide, indium gallium oxide, or indium cerium oxide target is used, the first transparent conductive oxide film layer 20 formed therefrom may contain, in addition to indium oxide, other metal oxides derived from the target. For example, when an indium tin oxide target is used, the first transparent conductive oxide film layer 20 may also contain tin oxide; when an indium zinc oxide target is used, the first transparent conductive oxide film layer 20 may also contain zinc oxide; when an indium gallium oxide target is used, the first transparent conductive oxide film layer 20 may also contain gallium oxide; and when an indium cerium oxide target is used, the first transparent conductive oxide film layer 20 may also contain cerium oxide. Generally speaking, the mass fraction of indium oxide in the first transparent conductive oxide film layer 20 is substantially consistent with the mass fraction of indium oxide in the target. That is, in this step, the first transparent conductive oxide film layer 20 can be prepared by selecting a target containing an indium oxide mass fraction of not less than 97%.

[0082] The mass fraction of indium oxide in the first transparent conductive oxide film layer 20 is not less than 97%, and the mass fraction of indium oxide can reach 100%. For example, the mass fraction of indium oxide can be 97%, 97.5%, 98%, 99%, 99.5%, 99.8% or 100%. Studies have found that the higher the mass fraction of indium oxide, the stronger its acid corrosion resistance. By controlling the mass fraction of indium oxide in the first transparent conductive oxide film layer 20 to be not less than 97%, a relatively good reaction rate gradient can be formed between the reaction rate of the first transparent conductive oxide film layer 20 with the acid solution and the reaction rate of the second transparent oxide film layer 30 with the acid solution. This reaction rate gradient can ensure that the second transparent oxide film layer 30 is removed by the acid solution while maintaining the film integrity of the first transparent conductive oxide film layer 20.

[0083] Step S1012: Under magnetron conditions of a power density of 2 W / mm~10 W / mm, an Ar flow rate of 50 sccm~200 sccm, and a pressure of 0.1 Pa~0.4 Pa, a second transparent conductive oxide film layer 30 is formed by magnetron sputtering, wherein the power density used to form the second transparent conductive oxide film layer 30 is greater than the power density used to form the first transparent conductive oxide film layer 20.

[0084] The power density may be 2 W / mm, 3 W / mm, 4 W / mm, 5 W / mm, 6 W / mm, 7 W / mm, 8 W / mm, 9 W / mm, or 10 W / mm, etc. The Ar flow rate may be 50 sccm, 70 sccm, 100 sccm, 120 sccm, 150 sccm, 170 sccm, 180 sccm, or 200 sccm, etc. The pressure may be 0.1 Pa, 0.2 Pa, 0.3 Pa, or 0.4 Pa, etc. Generally speaking, when the first transparent conductive oxide film layer 20 is prepared using a power density of 2 W / mm in step S1011, the power density used in step S1012 is greater than 2 W / mm; when the first transparent conductive oxide film layer 20 is prepared using a power density of 3 W / mm in step S1011, the power density used in step S1012 is greater than 3 W / mm; when the first transparent conductive oxide film layer 20 is prepared using a power density of 4 W / mm in step S1011, the power density used in step S1012 is greater than 4 W / mm; when the first transparent conductive oxide film layer 20 is prepared using a power density of 5 W / mm in step S1011, the power density used in step S1012 is greater than 5 W / mm.

[0085] The study found that within a certain power density range, the density of the transparent conductive oxide film layer can be regulated by controlling the power density. Specifically, the greater the power density, the lower the transparent conductive oxide film layer, and the lower the power density, the larger the transparent conductive oxide film layer. The higher the density of the transparent conductive oxide film layer, the higher the acid corrosion resistance, and the lower the density of the transparent conductive oxide film layer, the lower the acid corrosion resistance. By controlling the power density used in preparing the second transparent conductive oxide film layer 30 in step S1012 to be greater than the power density used in preparing the first transparent conductive oxide film layer 20 in step S1011, the density of the first transparent conductive oxide film layer 20 can be made greater than that of the second transparent conductive oxide film layer 30, thereby ensuring that the first transparent conductive oxide film layer 20 has better acid corrosion resistance and making the reaction rate of the first transparent conductive oxide film layer 20 with the acid solution lower than the reaction rate of the second transparent conductive oxide film layer 30 with the acid solution.

[0086] Furthermore, with respect to step S1012, the mass fraction of indium oxide in the prepared second transparent conductive oxide film 30 is no greater than 1%. Specifically, the mass fraction of indium oxide in step S1012 can be 0. For example, a target material containing no indium or a target material with a low indium content can be used to prepare the second transparent conductive oxide film 30, so that the mass fraction of indium oxide in the prepared second transparent conductive oxide film 30 is no greater than 1%. For example, the magnetron sputtering target used in this step can be indium tin oxide, indium zinc oxide, indium gallium oxide, indium cerium oxide, tin oxide, zinc oxide, gallium oxide, or cerium oxide. It can be understood that when a target material containing no indium oxide is used to prepare the second transparent conductive oxide film 30, the mass fraction of indium oxide in the second transparent conductive oxide film 30 is 0. For example, when a tin oxide target material is used, the second transparent conductive oxide film 30 is composed of tin oxide; when a zinc oxide target material is used, the second transparent conductive oxide film 30 is composed of zinc oxide; when a gallium oxide target material is used, the second transparent conductive oxide film 30 is composed of gallium oxide; and when a cerium oxide target material is used, the second transparent conductive oxide film 30 is composed of cerium oxide. When a target material containing indium oxide is used to prepare the second transparent conductive oxide film 30, the mass fraction of indium oxide in the second transparent conductive oxide film 30 is generally consistent with the indium oxide contained in the target material. Therefore, the mass fraction of indium oxide in the target material selected in this step is no more than 1%. Exemplarily, a second transparent conductive oxide film layer 30 is prepared for an indium tin oxide target, and the components of the second transparent conductive oxide film layer 30 are indium oxide and tin oxide; a second transparent conductive oxide film layer 30 is prepared for an indium zinc oxide target, and the components of the second transparent conductive oxide film layer 30 are indium oxide and zinc oxide; a second transparent conductive oxide film layer 30 is prepared for an indium gallium oxide target, and the components of the second transparent conductive oxide film layer 30 are indium oxide and gallium oxide; a second transparent conductive oxide film layer 30 is prepared for an indium cerium oxide target, and the components of the second transparent conductive oxide film layer 30 are indium oxide and cerium oxide.

[0087] By selecting the mass fraction of indium oxide in the second transparent conductive oxide film 30 to be no greater than 1%, a better reaction rate gradient can be formed between the reaction rates of the first transparent conductive oxide film 20 and the acid solution and the reaction rates of the second transparent oxide film 30 and the acid solution. This reaction rate gradient can ensure that the second transparent oxide film 30 is removed by the acid solution while maintaining the integrity of the first transparent conductive oxide film 20. It can also provide the process with a relatively wide process window, enabling the preparation scheme of the heterojunction solar cell provided in the embodiment of the present invention to be industrialized, and can also provide the preparation scheme with stability and reliability, so that the large-scale heterojunction solar cells prepared have structural stability and reliability.

[0088] Furthermore, by matching the power density for preparing the first transparent conductive oxide film layer 20 with the mass fraction of indium oxide in the first transparent conductive oxide film layer 20 being no less than 97%, and matching the power density for preparing the second transparent conductive oxide film layer 30 with the mass fraction of indium oxide in the second transparent conductive oxide film layer 30 being no more than 1%, a better reaction rate gradient is formed between the reaction rate of the first transparent conductive oxide film layer 20 with the acid solution and the reaction rate of the second transparent oxide film layer 30 with the acid solution, thereby ensuring that the second transparent oxide film layer 30 is removed by the acid solution while maintaining the film integrity of the first transparent conductive oxide film layer 20.

[0089] Furthermore, the thickness of the first transparent conductive oxide film layer 20 prepared in each of the above embodiments is 50 nm to 100 nm. For example, the thickness of the first transparent conductive oxide film layer 20 can be 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm. By controlling the thickness of the first transparent conductive oxide film layer 20 and combining it with the acid solution to remove the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41, the roughness of the portion of the first transparent conductive oxide film layer 20 corresponding to the gate line groove 41 can be increased, ensuring the bonding strength between the first transparent conductive oxide film layer 20 and the metal gate line 50. Furthermore, the roughened portion can be ensured to still have a relatively good carrier transport effect, without increasing the risk of carrier recombination and short circuit.

[0090] Furthermore, the thickness of the second transparent conductive oxide film layer 30 prepared in each of the above embodiments is generally between 10 nm and 50 nm. For example, the thickness of the second transparent conductive oxide film layer 30 can be 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm. Controlling the thickness of the second transparent conductive oxide film layer 30 provides a relatively wide process window for step S103, ensuring the industrialization of the heterojunction solar cell fabrication method and reducing process difficulty and complexity. Furthermore, by controlling the thickness of the second transparent conductive oxide film layer 30, in conjunction with the first transparent conductive oxide film layer 20, carrier transport can be ensured while reducing the risk of carrier recombination and short circuits.

[0091] Furthermore, the above Figure 1 or Figure 2 In the embodiment provided, for the above step S102, its specific implementation method may include the following steps S1021 and S1022:

[0092] Step S1021 : coating a first photosensitive material on the outer side of the second transparent conductive oxide film layer 30 , curing the first photosensitive material, and performing an interval exposure process on the first photosensitive material.

[0093] Wherein, the first photosensitive material can be a negative photosensitive material or a positive photosensitive material. If the first photosensitive material is a negative photosensitive material, its unexposed area is the grid line groove 41, and the exposed area is other areas outside the grid line groove 41 area. If the first photosensitive material is a positive photosensitive material, its exposed area is the grid line groove 41 area. Preferably, the first photosensitive material is a negative photosensitive material. Wherein, the thickness uniformity of the first photosensitive material is not more than 5%, wherein the thickness uniformity means that the difference between the thicknesses detected by multiple detection points is not more than 5%. Furthermore, the margin of the first photosensitive material from the side of the battery matrix 10 is less than 0.5mm. Wherein, the temperature used for curing the first photosensitive material is generally 333K~363K. For example, the curing temperature can be 333K, 343K, 353K or 363K. The curing time can be 100s~500s, for example, the curing time is 100s, 120s, 200s, 240s, 300s, 360s, 400s, 440s, 460s, 480s, 500s, 550s or 600s.

[0094] The wavelength of the light used for exposure is generally 310 nm to 440 nm. For example, the wavelength of the light may be 310 nm, 330 nm, 350 nm, 360 nm, 380 nm, 420 nm, or 440 nm.

[0095] Step S1022 : removing the exposed area or the unexposed area of ​​the first photosensitive material by using a developer to form a first mask layer 40 having gate line grooves 41 .

[0096] The developer used in this step is a NaCO solution with a mass concentration of 0.05% to 2.38%. The development temperature is 298K to 308K, and the development time is 60s to 120s. For example, the mass concentration of the developer can be 0.05%, 0.5%, 1%, 1.2%, 1.5%, 2%, or 2.38%. For example, the development temperature can be 298K, 300K, 305K, or 308K, and the development time can be 60s, 90s, or 120s.

[0097] If the first photosensitive material is a negative photosensitive material, the developer removes the unexposed area to form the grid line groove 41. If the first photosensitive material is a positive photosensitive material, the developer removes the exposed area to form the grid line groove 41.

[0098] The first mask layer 40 having the gate line groove 41 is formed by the above process, thereby avoiding the alignment process between the first mask layer 40 and the cell substrate 10 , thereby effectively improving the production efficiency and yield rate of the heterojunction solar cell.

[0099] In addition, a specific embodiment of step S103 may include: using an oxalic acid solution with a mass fraction of 10% to 30% at a temperature of 298K to 323K to remove the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41, and controlling the contact time between the second transparent conductive oxide film layer 30 and the oxalic acid solution to be 10s to 50s. The mass fraction of oxalic acid in the oxalic acid solution may be 10%, 12%, 15%, 18%, 20%, 23%, 25%, 28%, or 30%, etc. The temperature may be 298K, 300K, 305K, 310K, 315K, 318K, 320K, or 323K, etc. By selecting an oxalic acid solution, step S103 has a relatively wide process window, ensuring that the portion of the second transparent conductive oxide film layer 30 corresponding to the gate line groove 41 is completely removed while increasing the roughness of the portion of the first transparent conductive oxide film layer 20 corresponding to the gate line groove 41.

[0100] Furthermore, if Figure 7 As shown, the specific implementation of the above step S104 may include the following steps:

[0101] Step S1041 : forming a metal seed layer 51 in the gate line groove 41 and outside the first mask layer 40 .

[0102] Regarding step S1041, a specific implementation method may include: forming a metal seed layer 51 by magnetron sputtering, wherein the control conditions of the magnetron sputtering method are: vacuum degree 5.0E-4Pa (5.0×10 -4 Pa); sputtering power 5 kW to 15 kW; voltage 300 V to 600 V; Ar input pressure 0.1 Pa to 0.5 Pa; sputtering temperature 323 K to 473 K; target material used is Cu. Sputtering power can be 5 kW, 8 kW, 10 kW, 12 kW, or 15 kW, among others. Voltage can be 300 V, 350 V, 380 V, 400 V, 450 V, 480 V, 500 V, 520 V, 540 V, 550 V, 580 V, or 600 V, among others. Ar pressure can be 0.1 Pa, 0.2 Pa, 0.3 Pa, 0.4 Pa, or 0.5 Pa, among others.

[0103] Preferably, the thickness of the metal seed layer 51 may be 30 nm to 150 nm. For example, the thickness of the metal seed layer 51 may be 30 nm, 40 nm, 50 nm, 70 nm, 90 nm, 100 nm, 120 nm, 140 nm, or 150 nm.

[0104] The structure corresponding to step S1041 can be as follows Figure 8 or Figure 9 shown.

[0105] Step S1042 : forming a second mask layer 52 outside the metal seed layer 51 .

[0106] Regarding step S1042, a specific implementation method may include: coating a second photosensitive material on the outside of the metal seed layer 51, curing the second photosensitive material, and performing an interval exposure process on the second photosensitive material, and removing the area of ​​the second photosensitive material corresponding to the grid line groove 41 using a developer, wherein the area of ​​the coated second photosensitive material corresponding to the grid line groove 41 is an exposed area or an unexposed area. The wavelength of the light used for exposure is generally 310nm to 440nm, for example, the wavelength of the light can be 310nm, 330nm, 350nm, 360nm, 380nm, 420nm, or 440nm.

[0107] The second photosensitive material formed in this step can be applied by spraying or scraping, and the structure of the applied second photosensitive material can be as follows: Figure 8 As shown, a second photosensitive material is formed on the main surface of the metal seed layer 51 and the bottom of the gate line groove 41. Figure 9 As shown, a second photosensitive material is formed on the main surface of the metal seed layer 51 , the bottom of the gate line groove 41 and the side surface of the gate line groove 41 .

[0108] Among them, for the formation Figure 8 The second photosensitive material of the structure shown in the figure can be a positive photosensitive material or a negative photosensitive material. Figure 8 The second photosensitive material of the structure shown is a positive photosensitive material. By irradiating the gate line groove 41 with light and then developing, the portion of the second mask layer 52 corresponding to the gate line groove 41 can be removed, thereby exposing the metal seed layer 51 located in the gate line groove 41. Figure 8 The second photosensitive material of the structure shown is a negative photosensitive material. By irradiating the area outside the grid line groove 41 with light and then developing it, the portion corresponding to the grid line groove 41 can be removed.

[0109] Targeted formation Figure 9 The second photosensitive material of the structure shown is generally a positive photosensitive material. By irradiating the gate line groove 41 with light and then developing it, the portion of the second mask layer 52 corresponding to the gate line groove 41 can be removed, thereby exposing the metal seed layer 51 located in the gate line groove 41.

[0110] The coating thickness of the second photosensitive material may be 5 μm to 50 μm, the uniformity may be less than or equal to 5%, and the effective margin may be less than 0.5 mm. For example, the thickness of the second photosensitive material may be 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 40 μm, 45 μm, or 50 μm. The uniformity less than or equal to 5% means that the difference in thickness between various detection points of the coated second photosensitive material is less than or equal to 5%.

[0111] Step S1043 : removing the portion of the second mask layer 52 corresponding to the gate line groove 41 to expose the metal seed layer 51 in the gate line groove 41 .

[0112] It is worth noting that for Figure 9 As shown in the structure in which the second photosensitive material is formed on the main surface of the metal seed layer 51, the bottom of the gate line groove 41 and the side of the gate line groove 41, in the process of removing the portion of the second mask layer 52 corresponding to the gate line groove 41 by light irradiation, the second photosensitive material on the side of the gate line groove 41 will remain. This is because the thickness of the second photosensitive material on the side of the gate line groove 41 is greater than the thickness of the second photosensitive material at the bottom of the gate line groove 41. After the second photosensitive material at the bottom of the gate line groove 41 is completely removed, the second photosensitive material on the side of the gate line groove 41 will remain.

[0113] The developer used in this step is a NaCO3 solution with a concentration of 0.05% to 2.38%. The development temperature can be 298K to 308K, and the development time can be 60s to 120s. For example, the concentration of the NaCO3 solution can be 0.05%, 1%, 1.2%, 1.5%, 1.8%, 2%, or 2.38%, the development temperature can be 298K or 308K, and the development time can be 60s, 90s, 100s, or 120s.

[0114] Step S1044 : forming an electroplating layer 53 on the metal seed layer 51 in the gate line groove 41 by electroplating.

[0115] The electroplating solution selected for use in step S1044 comprises 10g / L~200g / L CuSO4 of mass concentration and 10ml / L~100ml / L concentrated sulfuric acid of volumetric concentration. For example, the mass concentration of CuSO4 can be 10g / L, 20g / L, 50g / L, 70g / L, 80g / L, 100g / L, 120g / L, 140g / L, 150g / L, 160g / L, 180g / L or 200g / L etc. The volumetric concentration of the concentrated sulfuric acid can be 10ml / L, 20ml / L, 30ml / L, 50ml / L, 60ml / L, 80ml / L or 100ml / L etc. It is worth noting that the volumetric concentration of the concentrated sulfuric acid refers to the volume of the concentrated sulfuric acid added in every liter of electroplating solution.

[0116] Preferably, the thickness of the electroplated layer 53 in step S1044 may be 1 μm to 50 μm. For example, the thickness of the electroplated layer 53 in step S1044 may be 1 μm, 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 20 μm, 25 μm, 28 μm, 30 μm, 35 μm, 40 μm, 45 μm, 48 μm or 50 μm. The corresponding structural changes after this step are as follows: Figure 8 and Figure 9 shown.

[0117] Step S1045 : removing the remaining second mask layer 52 and the metal seed layer 51 located outside the first mask layer 40 .

[0118] In the case where the second mask layer 52 is a positive photosensitive material, the remaining second mask layer 52 can be removed by light irradiation.

[0119] The metal seed layer 51 located outside the first mask layer 40 can be removed by etching.

[0120] In addition, the second mask layer 52 and the metal seed layer 51 located outside the first mask layer 40 can be removed together by etching.

[0121] Further, for Figure 8 The structure shown or similar Figure 8 The structure shown in FIG. 1 may further include, after step S1044 and before step S1045, electroplating a conductive protective layer 54 on the outer side of the electroplating layer 53. Preferably, the electroplating system of tin methanesulfonate / stannous methanesulfonate is used to electroplated the conductive protective layer 54 on the electroplating layer 53, wherein the mass concentration of the tin methanesulfonate concentrate is 250 g / L to 350 g / L, and the electroplating current is 1 A / dm 2 ~2A / dm 2, electroplating for 10s to 100s at a temperature of 298K to 338K. More preferably, the thickness of the conductive protective layer 54 is 0.1μm to 5μm. Figure 8 The structure obtained in step S1044 in the embodiment can be formed by electroplating the conductive protective layer 54 for the electroplating layer 53. Figure 10 The structure shown. During the treatment process, the mass concentration of the tin methanesulfonate concentrate can be 250 g / L, 280 g / L, 300 g / L, 320 g / L or 350 g / L. The current applied during electroplating can be 1 A / dm 2 , 1.2A / dm 2 , 1.5A / dm 2 , 1.8A / dm 2 or 2A / dm 2 The electroplating temperature may be 298K, 300K, 305K, 310K, 315K, 320K, 325K, 330K, 335K, or 338K. The electroplating time may be 10s, 20s, 30s, 50s, 60s, 80s, 90s, or 100s. The thickness of the conductive protective layer 54 electroplated in this step may be 0.1μm, 0.5μm, 1μm, 1.5μm, 1.8μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, or 5μm.

[0122] Further, for Figure 9 The structure shown in FIG. 1 (with positive photosensitive material on the side of the gate line groove 41) may further include, after step S1045, step S1046 (not shown): electroplating a conductive protective layer 54 on the electroplating layer 53. Compared with the structure in step S1044, the structure obtained after processing in steps S1045 and S1046 is changed as follows: Figure 10 As shown. For electroplating the conductive protective layer 54, a tin methanesulfonate / stannous methanesulfonate electroplating system can be used to electroplate the conductive protective layer 54 as the electroplating layer 53, wherein the mass concentration of the tin methanesulfonate concentrate is 250 g / L~350 g / L, and the electroplating current is 1A / dm 2 ~2A / dm 2 , at a temperature of 298K~338K, the electroplating is performed for 10s~100s. By electroplating the conductive protective layer 54 for the electroplating layer 53, a conductive protective layer 54 can be formed as shown in FIG. Figure 9 and Figure 12 The structure shown. During the treatment process, the mass concentration of the tin methanesulfonate concentrate can be 250 g / L, 270 g / L, 280 g / L, 290 g / L, 300 g / L, 320 g / L, 330 g / L or 350 g / L. The current applied during electroplating can be 1 A / dm 2 , 1.2A / dm 2 , 1.5A / dm 2, 1.8A / dm 2 or 2A / dm 2 The electroplating temperature may be 298K, 300K, 305K, 310K, 315K, 320K, 325K, 330K, 335K, or 338K. The electroplating time may be 10s, 20s, 30s, 50s, 60s, 80s, 90s, or 100s. The thickness of the conductive protective layer 54 electroplated in this step may be 0.1μm, 0.5μm, 1μm, 1.5μm, 1.8μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, or 5μm. In addition, in this processing step, the thickness of the conductive protective layer 54 formed on the side of the electroplating layer 53 can be controlled by limiting the width of the electroplating layer 53 and the width of the gate line groove 41, and the width of the metal gate line 50 finally formed can be effectively controlled through the gate line groove 41, so as to achieve the purpose of controlling the shading area of ​​the metal gate line 50.

[0123] In addition, the above step S1046 can also be completed after the above step S105, which will not be repeated here.

[0124] It is worth noting that if Figures 3 to 6 as well as Figure 8 and Figure 9 As shown, the technical solution provided by the embodiment of the present invention simultaneously prepares various structures such as the first transparent conductive oxide film layer 20, the second transparent conductive oxide film layer 30, the first mask layer 40, the metal grid line 50, etc. on both sides of the battery substrate 10. The removal of various structures such as the first mask layer 40 and the second mask layer 52 can be carried out in one step or multiple steps, which is not limited here.

[0125] Furthermore, if Figures 10 to 13 As shown, an embodiment of the present invention further provides a heterojunction solar cell. The heterojunction solar cell may include: a cell substrate 10, a first transparent conductive oxide film layer 20, a discontinuous second transparent conductive oxide film layer 30 and a metal grid line 50, wherein:

[0126] The metal grid lines 50 are embedded in the discontinuous positions of the second transparent conductive oxide film layer 30;

[0127] The metal grid line 50 is aligned with the cross section of the second transparent conductive oxide film layer 30 and the main surface of the first transparent conductive oxide film layer 20 .

[0128] By cooperating with the first transparent conductive oxide film layer 20 and the discontinuous second transparent conductive oxide film layer 30, that is, at least the distribution of the metal grid line 50 is embedded in the discontinuous second transparent conductive oxide film layer 30, the bonding strength between the metal grid line 50 and the first transparent conductive oxide film layer 20 can be effectively improved, and the risk of the metal grid line 50 being broken or falling off can be avoided.

[0129] The heterojunction solar cell can be prepared by the preparation method provided in the above embodiment.

[0130] The mass fraction of indium oxide in the first transparent conductive oxide film layer 20 is not less than 97%. By controlling the mass fraction of indium oxide to be not less than 97%, the carrier transport capability of the first transparent conductive oxide film layer 20 can be effectively improved.

[0131] The thickness of the first transparent conductive oxide film layer 20 may be 50 nm to 100 nm. For example, the thickness of the first transparent conductive oxide film layer 20 may be 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm.

[0132] Furthermore, the mass fraction of indium oxide in the second transparent conductive oxide film 30 is no greater than 1%, thereby ensuring the integrity of the first transparent conductive oxide film 20 during the formation of the discontinuous structure of the second transparent conductive oxide film 30. Furthermore, the second transparent conductive oxide film 30 cooperates with the first transparent conductive oxide film 20 to ensure the conductivity of the heterojunction solar cell.

[0133] The thickness of the second transparent conductive oxide film layer 30 may be 10 nm to 50 nm. For example, the thickness of the second transparent conductive oxide film layer 30 may be 10 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm.

[0134] Furthermore, if Figure 11 and Figure 13 As shown, the heterojunction solar cell may further include a protective layer 60 stacked on the outside of the second transparent conductive oxide film layer 30. The protective layer 60 can protect the second transparent conductive oxide film layer 30 from being damaged and can also improve the passivation anti-reflection effect of the heterojunction solar cell.

[0135] Among them, such as Figure 12 and Figure 13 As shown, the above-mentioned metal grid line 50 may include: a metal seed layer 51 and an electroplating layer 53, wherein the metal seed layer 51 is adhered to the main surface of the first transparent conductive oxide film layer 20; the electroplating layer 53 is stacked on the side of the metal seed layer 51 away from the first transparent conductive oxide film layer 20.

[0136] Furthermore, if Figure 10 and Figure 11 As shown, the heterojunction solar cell further includes a conductive protective layer 54 disposed outside the electroplating layer 53 .

[0137] In addition, if Figure 12 and Figure 13As shown, the heterojunction solar cell may further include a conductive protection layer 54 wrapping the electroplating layer 53 and the metal seed layer 51 .

[0138] The conductive protection layer 54 can protect the metal gate line 50 .

[0139] The conductive protective layer 54 may be an electroplated tin layer.

[0140] The following is formed Figure 12 Taking the structure of the heterojunction solar cell shown in FIG2 as an example, the preparation process of the heterojunction solar cell is described in detail.

[0141] Example:

[0142] Step A: Deposit an intrinsic amorphous silicon film (ia-Si:H) and an n-type amorphous silicon film (pa-Si:H) on the front side of an N-type single-crystal silicon wafer with a size of 182 mm × 182 mm and a thickness of 120 μm to 150 μm. Deposit an intrinsic amorphous silicon film (ia-Si:H) and a p-type amorphous silicon film (na-Si:H) on the back side of the N-type single-crystal silicon wafer.

[0143] Specifically, the production process of this step is as follows: first, on the back side of an N-type single crystal silicon wafer with a size of 182mm×182mm and a thickness of 120μm~150μm, the concentration ratio of the gas SiH4 / SiH4+H2 is controlled to 2, and the power of the plasma chemical deposition chamber is 1W / cm 2 The reaction temperature was controlled at 373K. A 5nm thick intrinsic amorphous silicon film (ia-Si:H) was deposited on the back of an N-type single crystal silicon wafer. Then, a SiH4 / SiH4+H2 concentration ratio of 3 was controlled on the front of the N-type single crystal silicon wafer. The power of the plasma chemical deposition chamber was 2W / cm 2 , controlling the reaction temperature at 383K, depositing a 4nm thick intrinsic amorphous silicon film (ia-Si:H) on the front side of the N-type single crystal silicon wafer; then depositing a 7nm thick n-type amorphous silicon film (pa-Si:H) on the intrinsic amorphous silicon film (ia-Si:H) on the front side of the N-type single crystal silicon wafer, and then depositing a 10nm thick p-type amorphous silicon film (pa-Si:H) on the intrinsic amorphous silicon film (ia-Si:H) on the back side of the N-type single crystal silicon wafer.

[0144] Step B: A first transparent conductive oxide film layer with a thickness of 80 nm and containing 98% by mass of indium oxide and a second transparent conductive oxide film layer with a thickness of 30 nm and containing 1% by mass of indium are sequentially stacked on the N-type amorphous silicon film on the front side of the N-type single-crystalline silicon wafer and the P-type amorphous silicon film on the back side of the N-type single-crystalline silicon wafer, respectively. The first transparent conductive oxide film layer is formed under the following conditions: a power density of 2 W / mm, an Ar flow of 100 sccm, and a pressure of 0.2 Pa; the second transparent conductive oxide film layer is formed under the following conditions: a power density of 5 W / mm, an Ar flow of 100 sccm, and a pressure of 0.2 Pa.

[0145] Step C: Control the reaction gas SiH4 flow rate to 15 sccm, NH3 flow rate to 25 sccm, chamber pressure to 5 Pa, RF Power to 3.5 W / cm 2 , temperature 383K, reaction time 3min, and a SiNx protective layer with a thickness of 30nm was prepared on the second transparent conductive oxide film layer on the front and back sides.

[0146] Step D: A negative photosensitive material with a thickness of 30 μm is laminated on the outside of the SiNx protective layer on the front and back sides, and the negative photosensitive material is cured at a temperature of 363 K for 300 seconds, wherein the uniformity of the coated negative photosensitive material is 95%, and the distance between the coated negative photosensitive material and the edge is 0.3 mm.

[0147] Step E: Use a light source with a wavelength of 326nm to irradiate the negative photosensitive material with intermittent light, and develop the negative photosensitive material with a 1.5% mass concentration NaCO3 developer to remove the unexposed area and form grid line grooves, wherein the exposure temperature is 303K and the exposure time is 90s.

[0148] Step F: using a hydrofluoric acid solution with a mass fraction of 15% at a temperature of 313 K for 30 seconds to remove the portion of the SiNx protective layer corresponding to the gate line groove.

[0149] Step G: Use 15% oxalic acid solution by mass at 313K for 30s to remove the portion of the second transparent conductive oxide film layer corresponding to the gate line groove, and cause micro-corrosion on the portion of the first transparent conductive oxide film layer corresponding to the gate line groove, thereby increasing the roughness of the portion of the first transparent conductive oxide film layer corresponding to the gate line groove.

[0150] Step H: Wash the acid solution remaining in step G with water at a temperature of 298K for 30s and dry it.

[0151] Step I: Using a copper target, magnetron sputtering was performed to form a metal seed layer with a thickness of 50 nm at a vacuum of 1 Pa, a sputtering power of 10 kW, a voltage of 400 V, a sputtering gas Ar pressure of 0.3 Pa, and a chamber temperature of 333 K.

[0152] Step J: Layer a negative photosensitive material with a thickness of 30 μm on the outside of the metal seed layer on the front and back sides, and cure the negative photosensitive material at a temperature of 363 K for 300 seconds, wherein the uniformity of the coated negative photosensitive material is 95%, and the distance between the coated negative photosensitive material and the edge is 0.3 mm.

[0153] Step K: Use a light source with a wavelength of 326nm to irradiate the negative photosensitive material with intermittent light, and develop the negative photosensitive material with a 1.5% mass concentration NaCO3 developer to remove the unexposed area and expose the metal seed layer at the bottom of the gate line groove. The exposure temperature is 303K and the exposure time is 90s.

[0154] Step L: Electroplating copper treatment. The metal seed layer exposed at the bottom of the gate line groove is used as the negative electrode and connected to the electroplating tank electrode. The current density is controlled at 2A / dm 2 The electroplating temperature is 313K, the electroplating time is 250s, and a plating layer with a thickness of 30μm is formed. The electroplating solution contains 150g / L CuSO4, 80ml / L concentrated sulfuric acid and additives.

[0155] Step M: electroplating protective layer treatment, using methanesulfonic acid / stannous methanesulfonate electroplating system (wherein the concentration of stannous methanesulfonate concentrate is 300g / L), applying current 2A / dm 2 At a temperature of 313 K, the electroplating time was controlled to be 60 s, and a plating layer with a thickness of 3 μm was electroplated.

[0156] Step N, etching and stripping the exposed negative photosensitive material, the metal seed layer inside the negative photosensitive material, and the negative photosensitive material inside the metal seed layer after the treatment in step K, thereby obtaining Figure 12 The structure shown.

[0157] The above steps are merely provided to help understand the structure, method, and core concept of the present invention. It will be apparent to those skilled in the art that various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a heterojunction solar cell, characterized in that: include: Step 1: sequentially stacking a first transparent conductive oxide film layer (20) and a second transparent conductive oxide film layer (30) on the main surface of the battery substrate (10); Step 2: using a first mask layer (40) having a gate line groove (41) to cover the second transparent conductive oxide film layer (30); Step 3: removing the portion of the second transparent conductive oxide film layer (30) corresponding to the gate line groove (41) using an acid solution; Step 4: forming a metal gate line (50) in the gate line groove (41); Step 5: removing the first mask layer (40); The reaction rate of the first transparent conductive oxide film layer (20) with the acid solution is lower than the reaction rate of the second transparent conductive oxide film layer (30) with the acid solution.

2. The preparation method according to claim 1, characterized in that Step 1 includes: The mass fraction of indium oxide in the first transparent conductive oxide film layer (20) prepared in step 1 is not less than 97%; The mass fraction of indium oxide in the second transparent conductive oxide film layer (30) prepared in step 1 is not higher than 1%; and / or, The thickness of the first transparent conductive oxide film layer (20) prepared in step 1 is 50 nm to 100 nm; and / or, The thickness of the second transparent conductive oxide film layer (30) prepared in step 1 is 10 nm to 50 nm.

3. The preparation method according to claim 1 or 2, characterized in that Step 1 includes: Step 11, preparing a first transparent conductive oxide film layer (20) by magnetron sputtering under magnetron conditions of a power density of 1 W / mm~5 W / mm, an Ar flow rate of 50 sccm~200 sccm and a pressure of 0.1 Pa~0.4 Pa; Step 12: Under magnetron conditions of a power density of 2 W / mm to 10 W / mm, an Ar flow rate of 50 sccm to 200 sccm, and a pressure of 0.1 Pa to 0.4 Pa, a second transparent conductive oxide film layer (30) is prepared by magnetron sputtering, wherein the power density used to prepare the second transparent conductive oxide film layer (30) is greater than the power density used to prepare the first transparent conductive oxide film layer (20).

4. The preparation method according to claim 1, characterized in that Step 2 includes: Step 21: coating a first photosensitive material on the outer side of the second transparent conductive oxide film layer (30), curing the first photosensitive material, and performing an interval exposure process on the first photosensitive material; Step 22: removing the exposed area or the unexposed area of ​​the first photosensitive material by using a developer to form a first mask layer (40) having a gate line groove (41).

5. The preparation method according to claim 1, characterized in that Step 3 includes: Using an oxalic acid solution with a mass fraction of 10% to 30%, at a temperature of 298 K to 323 K, a portion of the second transparent conductive oxide film layer (30) corresponding to the gate line groove (41) is removed, and the contact time between the second transparent conductive oxide film layer (30) and the oxalic acid solution is controlled to be 10 seconds to 50 seconds.

6. The preparation method according to claim 1, characterized in that Step 4 includes: Step 41: forming a metal seed layer (51) in the gate line groove (41) and outside the first mask layer (40); Step 42: forming a second mask layer (52) outside the metal seed layer (51); Step 43: removing the portion of the second mask layer (52) corresponding to the gate line groove (41) to expose the metal seed layer (51) located in the gate line groove (41); Step 44: forming an electroplating layer (53) on the metal seed layer (51) located in the gate line groove (41) by electroplating; Step 45: remove the remaining second mask layer (52) and the metal seed layer (51) located outside the first mask layer (40).

7. The preparation method according to claim 6, characterized in that Step 41 comprises: forming the metal seed layer (51) by magnetron sputtering, wherein the control conditions of the magnetron sputtering are: vacuum degree 5.0E~4Pa; sputtering power 5KW~15KW; voltage 300V~600V; input Ar pressure 0.1Pa~0.5Pa; sputtering temperature 323K~473K; the target material used is Cu; preferably, the thickness of the metal seed layer (51) is 30nm~150nm; and / or, Step 42 comprises: coating a second photosensitive material on the outside of the metal seed layer (51), curing the second photosensitive material, and performing an interval exposure process on the second photosensitive material, removing the area of ​​the second photosensitive material corresponding to the grid line groove (41) by a developer, wherein the area of ​​the coated second photosensitive material corresponding to the grid line groove (41) is an exposed area or an unexposed area; and / or, The electroplating solution selected in step 44 contains 10 g / L~200 g / L CuSO4 by mass concentration and 10 ml / L~100 ml / L concentrated sulfuric acid by volume concentration; preferably, the thickness of the electroplated layer (53) in step 44 is 1 μm~50 μm; and / or, After step 44 and before step 45, the method further includes: electroplating a conductive protective layer (54) on the outside of the electroplating layer (53); preferably, a tin methanesulfonate / stannous methanesulfonate electroplating system is used to electroplate the conductive protective layer (54) on the electroplating layer (53), wherein the mass concentration of the tin methanesulfonate concentrated solution is 250 g / L~350 g / L, and the current applied during electroplating is 1A / dm 2 ~2A / dm 2 , electroplating for 10s~100s at a temperature of 298K~338K; more preferably, the thickness of the conductive protective layer (54) is 0.1μm~5μm; or, After step 45 or step 5, the method further includes: electroplating a conductive protective layer (54) on the outside of the electroplating layer (53); preferably, a tin methanesulfonate / stannous methanesulfonate electroplating system is used to electroplate the conductive protective layer (54) on the electroplating layer (53), wherein the mass concentration of the tin methanesulfonate concentrated solution is 250 g / L~350 g / L, and the current applied during electroplating is 1 A / dm 2 ~2A / dm 2 , at a temperature of 298K~338K, electroplating for 10s~100s; more preferably, the thickness of the conductive protective layer (54) is 0.1μm~5μm.

8. The preparation method according to any one of claims 1, 2 and 4 to 7, characterized in that After step 1 and before step 2, the method further includes: step 2', forming a protective layer (60) outside the second transparent conductive oxide film layer (30); After step 2 and before step 3, the method further includes: step 3', removing the portion of the protective layer (60) corresponding to the gate line groove (41) using a hydrofluoric acid solution; Preferably, the mass fraction of the hydrofluoric acid solution is 15% to 20%; More preferably, step 2' comprises: In a mixed atmosphere with a flow ratio of SiH4 to NH3 of 1:5 to 2:1 and an atmosphere with a pressure of 0.1 Pa to 10 Pa, SiN is deposited on the outside of the second transparent conductive oxide film layer (30). x membrane layer; More preferably, the deposition temperature is controlled to be 373K~473K and the deposition time is controlled to be 2min~4min; More preferably, SiN x The thickness of the film layer is 10nm~50nm.

9. A heterojunction solar cell, characterized in that: include: A battery substrate (10), a first transparent conductive oxide film layer (20), a discontinuous second transparent conductive oxide film layer (30), and a metal grid line (50), wherein: The metal grid lines (50) are embedded in discontinuous positions of the second transparent conductive oxide film layer (30); The metal grid line (50) is in contact with the cross section of the second transparent conductive oxide film layer (30) and the main surface of the first transparent conductive oxide film layer (20).

10. The heterojunction solar cell according to claim 9, characterized in that: The first transparent conductive oxide film layer (20) contains an indium oxide mass fraction of not less than 97%; The mass fraction of indium oxide contained in the second transparent conductive oxide film layer (30) is not higher than 1%; and / or, The thickness of the first transparent conductive oxide film layer (20) is 50 nm to 100 nm; and / or, The thickness of the second transparent conductive oxide film layer (30) is 10 nm to 50 nm; and / or, The heterojunction solar cell further comprises: a protective layer (60) stacked on the outside of the second transparent conductive oxide film layer (30); and / or, The metal grid line (50) comprises: a metal seed layer (51) and an electroplating layer (53), wherein: The metal seed layer (51) is bonded to the main surface of the first transparent conductive oxide film layer (20); The electroplating layer (53) is stacked on a side of the metal seed layer (51) away from the first transparent conductive oxide film layer (20); and / or, The heterojunction solar cell further comprises: a conductive protective layer (54) arranged outside the electroplating layer (53) or a conductive protective layer (54) wrapping the electroplating layer (53) and the metal seed layer (51).

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