N-type TOPCon battery back structure, TOPCon battery and preparation method

Abstract

The invention provides an N-type TOPCon cell back structure, a TOPCon cell and a preparation method, and relates to the technical field of photovoltaic cells. The back structure of the N-type TOPCon battery comprises a grid line area and a non-grid line area, and the non-grid line area comprises an aluminum oxide layer and a silicon nitride layer which are sequentially arranged on the surface of a silicon wafer in an overlapped mode and does not contain a tunneling silicon oxide layer and a doped polycrystalline silicon layer. In the back structure of the N-type TOPCon cell provided by the invention, the grid line position is the textured surface, the non-grid line area is the polished surface, the structure is AlOx + silicon nitride, the grid line position design reduces the loss of cell filling factors, the polishing design of the non-grid line area increases the short-circuit current of the cell, the AlOx + silicon nitride ensures the passivation effect and the antireflection effect of the back surface, the parasitic absorption of light is avoided, and the performance of the N-type TOPCon cell is improved. The short-circuit current and the open-circuit voltage of the battery are improved, and the conversion efficiency of the battery is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and in particular to an N-type TOPCon cell back structure, a TOPCon cell and a preparation method thereof. Background Art

[0002] The existing N-type TOPCon battery structure is as follows Figure 1 As shown, with N-type silicon as the substrate, the front structure of the battery is: boron-doped emitter, AlO x 、SiN x ; The back structure of the battery is tunnel SiO x , phosphorus-doped polysilicon layer, SiN x layer, in which SiO x The doped polysilicon layer acts as a tunneling passivation layer. The manufacturing process is as follows: texturing → high-temperature boron diffusion → wet cleaning and edge insulation → SiO2+polysilicon preparation → high-temperature phosphorus diffusion → wet cleaning and edge insulation → front aluminum oxide preparation → front silicon nitride preparation → back silicon nitride preparation → metallization. Existing N-type TOPCon cells have a fully polished back-surface design, using a combination of deposited tunneling silicon oxide + doped polysilicon + silicon nitride for passivation and anti-reflection. While this design prevents the gate lines from contacting the silicon substrate, thereby avoiding loss of fill factor, it suffers from severe parasitic absorption, which affects the cell's conversion efficiency. Furthermore, the polishing design is not conducive to metal contact, which affects the fill factor and reduces the cell's conversion efficiency. The most important way to enhance the competitiveness of N-type cells is to achieve high efficiency and low cost. Therefore, improving the conversion efficiency of N-type TOPCon cells is a pressing issue.

[0003] Prior art CN117995944A discloses a TOPCon cell and its preparation method. In the disclosed TOPCon cell, the back velvet Finger region comprises a first tunneling silicon oxide layer, a first polysilicon layer, a second tunneling silicon oxide layer, and a second polysilicon layer in sequence, and the polished non-Finger region comprises a first tunneling silicon oxide layer and a first polysilicon layer in sequence. The thickness of the second tunneling silicon oxide layer is controlled to be relatively thin, which significantly reduces the series resistance of the TOPCon cell and significantly improves the fill factor and conversion efficiency. However, the parasitic absorption phenomenon in the non-gateline region of the back structure of the TOPCon cell has not been significantly improved, the short-circuit current and open-circuit voltage of the cell have not been improved, and the overall cell conversion efficiency needs to be further improved.

[0004] Therefore, there is an urgent need to provide a TOPCon battery that can effectively improve the short-circuit current and open-circuit voltage of the battery, thereby improving the overall battery conversion efficiency. Summary of the Invention

[0005] The present invention mainly addresses the defects and shortcomings of the prior art TOPCon battery structure, such as the serious parasitic absorption phenomenon in the non-gate line area on the back side, which affects the short-circuit current and open-circuit voltage of the battery and leads to a reduction in the overall battery conversion efficiency. The present invention provides an N-type TOPCon battery back side structure. By adopting a new structural design on the back side of the TOPCon battery, not only is the parasitic absorption of light avoided, thereby increasing the short-circuit current of the battery, but the passivation effect and anti-reflection effect of the back side are also ensured, thereby improving the open-circuit voltage and short-circuit current, and effectively improving the conversion efficiency of the battery.

[0006] The present invention also provides a method for preparing the back structure of an N-type TOPCon battery.

[0007] The present invention also provides a TOPCon battery.

[0008] The present invention also provides a method for preparing a TOPCon battery.

[0009] The present invention provides an N-type TOPCon battery back structure, including a gate line area and a non-gate line area. The non-gate line area includes an aluminum oxide layer and a silicon nitride layer stacked in sequence on the surface of a silicon wafer, and does not contain a tunneling silicon oxide layer and a doped polysilicon layer.

[0010] According to the back structure of an N-type TOPCon battery provided by the present invention, preferably, the surface of the silicon wafer in the non-gate line area is a polished surface.

[0011] According to the back structure of an N-type TOPCon cell provided by the present invention, preferably, the light reflectivity of the silicon wafer surface in the non-gateline area is ≥45%.

[0012] According to the back structure of an N-type TOPCon cell provided by the present invention, preferably, the thickness of the aluminum oxide layer is 1.5 nm to 10 nm, and / or the thickness of the silicon nitride layer is 45 nm to 95 nm.

[0013] According to the back structure of an N-type TOPCon cell provided by the present invention, preferably, the gate line region comprises a tunneling silicon oxide layer, a phosphorus-doped polysilicon layer, an aluminum oxide layer, and a silicon nitride layer sequentially stacked on a silicon substrate. and / or the surface of the silicon wafer in the gate line area is velvet, And / or the light reflectivity of the silicon wafer surface in the gate line area is ≤15%.

[0014] The present invention also provides a method for preparing a back surface structure of an N-type TOPCon battery, comprising the following steps: S1. A tunneling silicon oxide layer and a phosphorus-doped polysilicon layer are prepared on the back of the substrate after texturing and boron diffusion; S2. Laser scanning the non-gate line area on the back of the silicon wafer to remove the tunneling silicon oxide layer and phosphorus-doped polysilicon layer in the non-gate line area; S3 backside polishing, alkaline etching polishing of the non-gate line area; S4. Wet cleaning and edge insulation treatment; S5. Backside aluminum oxide preparation; S6. Back side is made of silicon nitride.

[0015] According to a method for preparing a back structure of an N-type TOPCon battery provided by the present invention, preferably, the alkaline solution concentration for alkaline etching and polishing treatment of the non-gate line area in S3 is: 6.5%~8.5%, the etching time is: 250s~350s, and the etching temperature is 60℃~70℃.

[0016] According to the method for preparing the back structure of an N-type TOPCon battery provided by the present invention, preferably, after polishing, the height difference at the intersection of the gate line area and the non-gate line area is ≥0.1 μm.

[0017] According to a method for preparing the back structure of an N-type TOPCon battery provided by the present invention, ALD atomic layer deposition is used to prepare the back aluminum oxide in S5, the deposition temperature of the aluminum oxide layer in the non-gate line area is 300~380℃, the number of ALD atomic layer deposition cycles is 28~40 times, the aluminum source flow rate is 1200~2000ccm, and the H2O flow rate is 9000~14000sccm.

[0018] The present invention further provides a TOPCon battery, comprising a silicon wafer, wherein the back side of the silicon wafer is designed with the N-type TOPCon battery back side structure provided by the present invention.

[0019] The present invention also provides a method for preparing a TOPCon battery, wherein the back structure of the N-type TOPCon battery is prepared by the method for preparing the back structure of the N-type TOPCon battery provided by the present invention. Beneficial effects: The surface of the silicon wafer at the gate line position in the back structure of the N-type TOPCon battery provided by the present invention is velvet, and the structure is tunneling silicon oxide + doped polysilicon + AlO x + silicon nitride, the surface of the silicon wafer in the non-gate line area is polished, and the structure is AlO x + silicon nitride. The velvet design at the gate line position is more conducive to metal contact, tunneling silicon oxide + doped polysilicon + AlO x +Silicon nitride design can avoid direct contact between metal gate line and silicon substrate, velvet design and film design can reduce the loss of battery fill factor; the polishing design of non-gate line area increases the internal reflection of light and thus increases the short-circuit current of the battery. There is no tunneling silicon oxide in the non-gate line area. + doped polysilicon can avoid parasitic absorption of light and thus increase the short-circuit current of the battery. AlO x +Silicon nitride ensures the passivation and anti-reflection effects on the back side, improves the short-circuit current and open-circuit voltage of the battery, and thus improves the conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0021] Figure 1 Schematic diagram of the N-type TOPCon battery structure in the prior art.

[0022] Figure 2 Schematic diagram of the N-type TOPCon battery structure of the present invention. DETAILED DESCRIPTION

[0023] The following examples are intended to illustrate the present invention but are not intended to limit the scope of the invention. Where specific techniques or conditions are not specified in the examples, the methods were performed according to those described in the literature in the art or according to the product instructions. Where the manufacturer of the reagents or instruments is not specified, all are conventional products available through regular channels.

[0024] Among them, some terms of the present invention are explained as follows: N-type TOPCon cell: N-type tunneling oxide passivated contact cell.

[0025] Parasitic absorption: The phenomenon in which light energy is absorbed ineffectively.

[0026] The present invention provides an N-type TOPCon battery back structure, including a gate line area and a non-gate line area. The non-gate line area includes an aluminum oxide layer and a silicon nitride layer sequentially stacked on the surface of a silicon wafer, and does not contain a tunneling silicon oxide layer and a doped polysilicon layer.

[0027] Among them, it should be noted that: In N-type TOPCon cells, tunneling silicon oxide + doped polysilicon + silicon nitride are often deposited on the back of the silicon wafer for passivation and anti-reflection. However, since doped polysilicon has a serious parasitic absorption of light, it will lead to a loss of cell efficiency. The non-gateline area of ​​the back structure of the N-type TOPCon cell of the present invention does not have tunneling silicon oxide + doped polysilicon, which can avoid parasitic absorption of light and increase the short-circuit current of the cell. At the same time, the aluminum oxide AlO on the surface of the silicon wafer can effectively reduce the short-circuit current of the cell. x +The silicon nitride film layer design ensures the passivation effect and anti-reflection effect on the back side, thereby improving the open circuit voltage and short circuit current, and effectively improving the conversion efficiency of the battery.

[0028] In certain embodiments, the non-gridline area of ​​the silicon wafer is preferably polished. The polished design of the non-gridline area increases internal reflection of light, enhances absorption of long-wavelength light, improves light absorption efficiency and carrier collection capacity, thereby increasing the short-circuit current of the battery, enhancing the battery's ability to capture sunlight, and thus improving photoelectric conversion efficiency.

[0029] In certain specific embodiments, it is further preferred that the light reflectivity of the silicon wafer surface in the non-gateline region is ≥45%.

[0030] In certain embodiments, to further optimize the effect on the overall passivation performance and light absorptivity, the thickness of the aluminum oxide layer mentioned in the present invention is preferably 1.5 nm to 10 nm. For example, the thickness can be 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, or any range thereof.

[0031] In certain embodiments, to further optimize the effect on overall passivation performance and light absorption rate, the thickness of the silicon nitride layer mentioned in the present invention is preferably 45-95 nm. For example, the thickness can be 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, or any range thereof.

[0032] In a specific embodiment, the thickness of the aluminum oxide layer and the thickness of the silicon nitride layer may also be optimized simultaneously to achieve a better comprehensive improvement effect of the passivation performance and the light absorption rate.

[0033] In certain specific embodiments, the gate line region of the back structure of the N-type TOPCon cell of the present invention includes a tunneling silicon oxide layer, a phosphorus-doped polysilicon layer, an aluminum oxide layer, and a silicon nitride layer sequentially stacked on a silicon substrate.

[0034] The phosphorus-doped polysilicon layer may be a multi-layer phosphorus-doped polysilicon film, and the silicon nitride layer may include a multi-layer silicon nitride or silicon oxynitride stacked film.

[0035] In some specific embodiments, further preferably, the surface of the silicon wafer in the gate line region is a suede surface.

[0036] Among them, it should be noted that: The grid line is a metal conductive structure on the surface of the photovoltaic cell used to collect and transmit photogenerated carriers. The velvet design at the grid line position is more conducive to metal contact, increasing the contact area between the metal electrode and the silicon wafer, which can effectively reduce the contact resistance, thereby improving the cell's fill factor FF and thus improving the cell's conversion efficiency. x The silicon nitride gateline design prevents direct contact between the metal gateline and the silicon substrate, reducing both recombination losses and resistance losses, thereby improving device efficiency. Both the velvet finish and the gateline film design mentioned above can reduce the loss of cell fill factor.

[0037] In certain specific embodiments, more preferably, the light reflectivity of the silicon wafer surface in the gate line region is ≤15%.

[0038] On the other hand, the present invention provides a method for preparing a back structure of an N-type TOPCon battery, comprising the following steps: S1. A tunneling silicon oxide layer and a phosphorus-doped polysilicon layer are prepared on the back of the substrate after texturing and boron diffusion; S2. Laser scanning the non-gate line area on the back of the silicon wafer to remove the tunneling silicon oxide layer and phosphorus-doped polysilicon layer in the non-gate line area; S3 backside polishing, alkaline etching polishing of the non-gate line area; S4. Wet cleaning and edge insulation treatment; S5. Backside aluminum oxide preparation; S6. Back side is made of silicon nitride.

[0039] In some specific embodiments, in order to fully improve the light reflectivity of the silicon wafer surface in the non-gate line area and achieve better alkaline solution corrosion effect, the alkaline solution concentration of the alkaline corrosion polishing treatment in the non-gate line area in S3 is: 6.5%~8.5%, the corrosion time is: 250s~350s, and the corrosion temperature is 60℃~70℃.

[0040] The alkali solution concentration mentioned in the present invention is a mass concentration. For example, the alkali solution concentration can be 6.5%, 7%, 7.5%, 8%, 8.5%, etc., or any range value thereof. The corrosion time can be 250s, 280s, 300s, 320s, 350s, etc., or any range value thereof. The corrosion temperature can be 60°C, 65°C, 70°C, etc., or any range value thereof.

[0041] In some specific embodiments, the polishing process in S3 of the present invention also needs to control the height difference between the intersection of the gate line area and the non-gate line area after the polishing process to be ≥0.1 μm, so as to better improve the reflectivity and increase the utilization rate of light.

[0042] Furthermore, in order to improve the film deposition quality and deposition rate of the aluminum oxide layer and the silicon nitride layer in the non-gate line area, in some specific embodiments, ALD atomic layer deposition is used to prepare the back aluminum oxide in S5, the deposition temperature of the aluminum oxide layer in the non-gate line area is 300~380℃, the number of ALD atomic layer deposition cycles is 28~40 times, the aluminum source, for example, can be TMA (trimethylaluminum), the flow rate is 1200~2000ccm, and the H2O flow rate is 9000~14000sccm.

[0043] In some specific embodiments, the S6 non-gateline region silicon nitride layer process can be referred to as follows: Entering the boat: temperature 490℃, N2 flow rate 12slm; heating: temperature 490℃; vacuuming; leak detection; deposition: temperature 490℃, SiH4 flow rate 1300~1800sccm, NH3 flow rate 9000~12000sccm, time 750s; vacuuming; purging; exiting the boat.

[0044] On the other hand, the present invention further provides an N-type TOPCon battery, comprising a silicon wafer, wherein the back side of the silicon wafer is designed with the back side structure of the N-type TOPCon battery provided by the present invention.

[0045] On the other hand, the present invention also provides a method for preparing an N-type TOPCon battery, and the back structure is prepared by using the method for preparing the back structure of an N-type TOPCon battery provided by the present invention.

[0046] The preparation of the TOPCon battery structure includes texturing → high-temperature boron diffusion → wet cleaning and edge insulation treatment → SiO2+polysi preparation → high-temperature phosphorus diffusion → wet cleaning and edge insulation treatment → front aluminum oxide preparation → front silicon nitride preparation → back silicon nitride preparation → metallization process. The preparation method of the N-type TOPCon battery of the present invention is different from the existing one, especially the preparation of the back structure of the N-type TOPCon battery. The preparation method of the back structure of the N-type TOPCon battery provided by the present invention is referred to. The specific process flow can be referred to in detail as follows: (1) Texturing: Place the entire silicon wafer in a KOH or NaOH solution to obtain a pyramid velvet surface on the exposed portion of the silicon wafer. The temperature of the KOH solution is 50-70°C, and the concentration is about 2-3%. (2) High-temperature boron diffusion: High-temperature tubular boron diffusion. While the boron diffuses on the front side, boron diffusion is also achieved on the back side and edge of the silicon wafer. (3) preparing a tunneling silicon oxide layer and a phosphorus-doped polysilicon layer, for example, by using LPCVD (low pressure chemical vapor deposition) + high temperature phosphorus diffusion or PECVD (plasma enhanced chemical vapor deposition) + high temperature annealing to prepare the tunneling silicon oxide layer and the phosphorus-doped polysilicon layer; (4) Laser scanning: According to the preset scanning pattern, the laser scans the back of the silicon wafer in sections, scanning the non-gate line area to achieve the purpose of removing the tunneling silicon oxide layer and phosphorus-doped polysilicon layer in the non-gate line area. Other areas are not scanned, and the back gate line area, front and side scanning areas are retained. The phosphorus silicon glass layer (the phosphorus silicon glass layer generated in the preparation process of the tunneling silicon oxide layer and phosphorus-doped polysilicon layer in the previous step) is retained. In a specific embodiment, it is further preferred that the retained width of the phosphosilicate glass layer in the fine grid line area is 100 μm to 500 μm, and the retained width of the phosphosilicate glass layer in the main grid line area is 400 μm to 1000 μm. The retained widths of the fine grid line and main grid line areas can ensure that the metal fine grid lines and main grid lines can fall into the fine grid line area and the main grid line area in the subsequent metallization step, thereby avoiding printing errors. (5) Back polishing: Place the silicon wafer in an alkaline bath and polish the non-gate line area on the back of the silicon wafer. The front of the silicon wafer and other locations do not react due to the protection of phosphosilicate glass and borosilicate glass. After this process step, the reflectivity of the non-polished area is ≥45%, the reflectivity of the gate line area is ≤15%, and the height difference between the gate line area and the non-gate line area is ≥0.1μm (the height of the gate line area is higher than the height of the non-gate line area). The height difference control can achieve the following effects: Function 1: Before laser treatment, the back of the silicon wafer has a velvet structure. By controlling the height difference after polishing, the polishing effect and reflectivity can be improved. Function 2: The height of the back surface is designed in a gradient to increase the internal reflection of long-wave light on the back surface of the silicon wafer and increase the utilization rate of light; (6) Wet cleaning: remove the tunneling oxide passivation layer that is plated around the front of the silicon wafer and the edge of the silicon wafer adjacent to the front of the silicon wafer, and remove the borosilicate glass layer on the front of the silicon wafer and the phosphosilicate glass layer in the gate line area on the back of the silicon wafer; (7) Preparation of double-sided alumina: double-sided deposition of SiO x +ALO x At the same time, SiO is deposited on the side of the silicon wafer. x +ALO x In the battery manufacturing process, the aluminum oxide layers on the front and back can be deposited simultaneously: (8) Front SiN x Preparation: Deposition of front SiN x +N2O+SiN x At the same time, SiN is deposited on the side of the silicon wafer x +N2O+SiN x , front SiN x The thickness is preferably 70 to 100 nm.

[0047] (9) Back silicon nitride: Deposition of back SiN x At the same time, SiN is deposited on the side of the silicon wafer x .

[0048] (10) Metallization The battery preparation is completed.

[0049] Among them, if the tunneling SiO2+ doped polysilicon is prepared by LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition) method, the tunneling SiO2+ doped polysilicon that is plated around the front side needs to be removed during the subsequent cleaning.

[0050] Example 1 A TOPCon battery, comprising a silicon wafer, such as Figure 2 As shown, the back of the silicon wafer is designed with an N-type TOPCon cell back structure, and the front structure of the cell silicon wafer is: boron-doped emitter, AlO x 、SiN x The silicon wafer surface in the gate line area on the back of the battery is velvet, and the structure below the gate line is tunnel SiO x , phosphorus-doped polysilicon layer, AlO x 、SiN x The surface of the silicon wafer in the non-gate line area is polished, and the structure of the non-gate line area is AlO x 、SiN x layer.

[0051] The preparation method of the TOPCon battery of Example 1 comprises the following steps: ①Texturing: Place the entire silicon wafer in a KOH solution to obtain a pyramid velvet surface on the exposed portion of the silicon wafer. The KOH solution temperature is about 60°C and the mass concentration is 2.5%. ② High-temperature boron diffusion: High-temperature tubular boron diffusion. While the boron is diffusing on the front side, boron diffusion is also achieved on the back side and edge of the silicon wafer. ③ Using PECVD+high temperature annealing to prepare tunneling silicon oxide layer and phosphorus-doped polysilicon layer; ④Laser: The laser scans the back of the silicon wafer and the non-gate line area. The retained width of the fine grid line area is 100μm~500μm, and the retained width of the main grid line area is 400μm~1000μm; ⑤ Backside polishing: Place the silicon wafer in an alkaline bath (alkaline solution concentration: 7.5%, etching time: 300s, process temperature: 70°C) and polish the non-gate line area on the back side of the silicon wafer. The front side of the silicon wafer and other locations are protected by phosphosilicate glass and borosilicate glass and do not react. After this process step, the reflectivity of the non-polished area is ≥35%, the reflectivity of the gate line area is ≤15%, and the height difference at the intersection of the gate line area and the non-gate line area is ≥0.1μm (the height of the gate line area is higher than the height of the non-gate line area); ⑥ Wet cleaning: Remove the tunneling oxide passivation layer that is plated around the front side of the silicon wafer and the edge of the silicon wafer adjacent to the front side of the silicon wafer, and remove the borosilicate glass layer on the front side of the silicon wafer and the phosphosilicate glass layer in the gate line area on the back side of the silicon wafer; ⑦ Double-sided alumina preparation: double-sided deposition of SiOx +ALO x At the same time, SiO is deposited on the side of the silicon wafer. x +ALO x In the battery manufacturing process, the aluminum oxide layers on the front and back can be deposited simultaneously: Entering the boat: temperature 320℃, N2 flow rate 12sccm; heating: temperature 320℃; vacuum; leak detection; pretreatment: H2O flow rate 1800sccm, time 8s, AlOx deposition: TMA (trimethylaluminum) flow rate 1600sccm, H2O flow rate 11300sccm, time 6s, cycle 35 times, ALO x Thickness 5nm; ⑧Front-side SiN x Preparation: Deposition of front SiN x +N2O+SiN x At the same time, SiN is deposited on the side of the silicon wafer x +N2O+SiN x : Entering the boat: temperature 450℃, N2 flow 12slm; heating: temperature 450℃; vacuuming; leak detection Deposition: temperature 460°C, SiH4 flow rate 2000 sccm, NH3 flow rate 11000 sccm, time 800 s; vacuum; purge; exit the boat; SiN x Thickness 85nm; ⑨ Back side silicon nitride: Deposition of back side SiN x At the same time, SiN is deposited on the side of the silicon wafer x , thickness 50nm~90nm; entering the boat: temperature 490℃, N2 flow 12slm; heating: temperature 490℃; vacuuming; leak detection; deposition: temperature 490℃, SiH4 flow 1500sccm, NH3 flow 10000sccm, time 750s; vacuuming; purging; leaving the boat; SiNx3 thickness 80nm; ⑩ Metallization: Printing metal fine grid lines and main grid lines in the fine grid line area and the main grid line area to complete the preparation of the battery.

[0052] Example 2 An N-type TOPCon battery, the preparation method of which is basically the same as that of Example 1, except that the thickness of the aluminum oxide layer in the non-gate line area of ​​the back structure of the battery is 2.5 nm.

[0053] Example 3 An N-type TOPCon battery, the preparation method of which is basically the same as that of Example 1, except that the thickness of the aluminum oxide layer in the non-gate line area of ​​the back structure of the battery is 7.5 nm.

[0054] Example 4 An N-type TOPCon battery, the preparation method of which is basically the same as that of Example 1, except that the thickness of the silicon nitride layer in the non-gate line area of ​​the back structure of the battery is 70 nm.

[0055] Example 5 An N-type TOPCon battery, the preparation method of which is basically the same as that of Example 1, except that the thickness of the silicon nitride layer in the non-gate line area of ​​the back structure of the battery is 90 nm.

[0056] Example 6 An N-type TOPCon battery, the preparation method of which is basically the same as that of Example 1, except that the thickness of the silicon nitride on the front side of the battery is 75nm.

[0057] Example 7 An N-type TOPCon battery, the preparation method of which is basically the same as that of Example 1, except that the thickness of the silicon nitride on the front side of the battery is 95nm.

[0058] The performance of the N-type TOPCon cells of Examples 1 to 7 was tested, and the performance tests included: current density, open circuit voltage, fill factor, and cell conversion efficiency.

[0059] The specific detection methods are as follows: IEC60904-1:2020Photovoltaicdevices– Part1:Measurementofphotovoltaiccurrent-voltagecharacteristics The test results are shown in Table 1.

[0060] Comparative Example 1 The TOPCon battery is prepared with reference to the existing technology, which is the general technology used by existing battery manufacturers. The back of the battery is polished, and tunneling silicon oxide + doped polysilicon + silicon nitride layers are deposited on the back.

[0061] The relevant performance tests were performed with reference to the detection method of Example 1. The specific results are shown in Table 2.

[0062] Table 2

[0063] As can be seen from Table 1 above, with the TOPCon cell of prior art 1 as a reference, the current density and open circuit voltage of the TOPCon cell with a special back structure design of the present invention are both improved to a certain extent, and the fill factor and cell conversion efficiency of the N-type TOPCon cell of the present invention are also improved, indicating that the N-type TOPCon cell of the present invention not only avoids light parasitic absorption and thus increases the short-circuit current of the cell by adopting a new structural design on the back of the cell, but also ensures the passivation effect and anti-reflection effect on the back, thereby improving the open circuit voltage and short-circuit current, and effectively improving the conversion efficiency of the cell.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An N-type TOPCon battery back structure, comprising a gate line area and a non-gate line area, characterized in that: The non-gate line area includes an aluminum oxide layer and a silicon nitride layer sequentially stacked on the surface of the silicon wafer, and does not contain a tunneling silicon oxide layer and a doped polysilicon layer.

2. The back structure of the N-type TOPCon battery according to claim 1, characterized in that: The surface of the silicon wafer in the non-gate line area is a polished surface.

3. The back structure of the N-type TOPCon battery according to claim 2, characterized in that: The light reflectivity of the silicon wafer surface in the non-gate line area is ≥45%.

4. The back surface structure of an N-type TOPCon battery according to any one of claims 1 to 3, characterized in that: The thickness of the aluminum oxide layer is 1.5 nm to 10 nm, and / or the thickness of the silicon nitride layer is 45 nm to 95 nm.

5. The back surface structure of an N-type TOPCon battery according to any one of claims 1 to 3, characterized in that: The gate line region includes a tunneling silicon oxide layer, a phosphorus-doped polysilicon layer, an aluminum oxide layer, and a silicon nitride layer stacked sequentially on a silicon substrate. and / or the surface of the silicon wafer in the gate line area is velvet, And / or the light reflectivity of the silicon wafer surface in the gate line area is ≤15%.

6. A method for preparing the back surface structure of an N-type TOPCon battery according to any one of claims 1 to 5, characterized in that: The steps include: S1. A tunneling silicon oxide layer and a phosphorus-doped polysilicon layer are prepared on the back of the substrate after texturing and boron diffusion; S2. Laser scanning the non-gate line area on the back of the silicon wafer to remove the tunneling silicon oxide layer and phosphorus-doped polysilicon layer in the non-gate line area; S3 backside polishing, alkaline etching polishing of the non-gate line area; S4. Wet cleaning and edge insulation treatment; S5. Backside aluminum oxide preparation; S6. Back side is made of silicon nitride.

7. The preparation method according to claim 6, characterized in that: In S3, the alkaline solution concentration for alkaline etching and polishing of the non-gate line area is: 6.5%~8.5%, the etching time is: 250s~350s, and the etching temperature is 60℃~70℃. And / or after polishing, the height difference between the junction of the gate line area and the non-gate line area is ≥0.1 μm.

8. The preparation method according to claim 6, characterized in that: In S5, the back aluminum oxide is prepared by ALD atomic layer deposition. The deposition temperature of the aluminum oxide layer in the non-gate line area is 300~380℃, the number of ALD atomic layer deposition cycles is 28~40 times, the aluminum source flow rate is 1200~2000ccm, and the H2O flow rate is 9000~14000sccm.

9. A TOPCon battery comprising a silicon wafer, characterized in that: The back side of the silicon wafer is designed with the back side structure of the N-type TOPCon cell as claimed in any one of claims 1 to 5.

10. A method for preparing a TOPCon battery, characterized in that: The back structure is prepared using the method for preparing the back structure of an N-type TOPCon battery as described in claims 6 to 8.

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