Solar cell, photovoltaic module and manufacturing method of solar cell

Abstract

The invention discloses a solar cell, a photovoltaic module and a manufacturing method of the solar cell, relates to the technical field of solar cells, and aims to solve the problem of how to enable the photoelectric efficiency of the solar cell to reach a relatively high level. The solar cell comprises a semiconductor substrate, a first doped layer and a second doped layer. The semiconductor substrate comprises a first surface and a second surface which are opposite; the first surface comprises a first electrode region and a first non-electrode region; the surface of the first electrode area is provided with a first texture structure, and the first non-electrode area is provided with a second texture structure; the second surface comprises a second electrode region and a second non-electrode region; the second non-electrode area is provided with a third texture structure, and the size consistency of the second texture structure is larger than that of the third texture structure; the first doping layer is arranged in the first electrode region; the second doped layer is arranged in the first non-electrode region; the doping concentration of the first doping layer is larger than that of the second doping layer.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell, a photovoltaic module and a method for manufacturing a solar cell. Background Art

[0002] A solar cell is a device that utilizes solar energy and directly converts light energy into electrical energy through the photoelectric effect or photochemical effect.

[0003] Current bifacial solar cells mainly include TOPCon (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated emitter and real cell) and heterojunction cells.

[0004] Bifacial solar cells have a promising market due to their relatively simple manufacturing process and low cost. However, achieving a high level of photovoltaic efficiency remains a pressing technical challenge for the industry. Summary of the Invention

[0005] The object of the present invention is to provide a solar cell, a photovoltaic module and a method for manufacturing a solar cell, so as to improve the efficiency of the solar cell.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a solar cell. The solar cell comprises: a semiconductor substrate, a first doped layer, and a second doped layer. The semiconductor substrate comprises a first surface and a second surface opposite each other; the first surface comprises a first electrode region and a first non-electrode region; the surface of the first electrode region has a first texture structure, and the first non-electrode region has a second texture structure; the second surface comprises a second electrode region and a second non-electrode region; the second non-electrode region has a third texture structure, and the dimensional consistency of the second texture structure is greater than the dimensional consistency of the third texture structure; the first doped layer is disposed in the first electrode region; the second doped layer is disposed in the first non-electrode region; and the doping concentration of the first doped layer is greater than the doping concentration of the second doped layer.

[0007] In the solar cell provided by the present invention, the second non-electrode area has a third texture structure. Compared with the second non-electrode area without a texture structure, the reflectivity of the second non-electrode area is significantly reduced. With the optimization of the passivation process, the cell efficiency is not affected, and the cell bifaciality is improved. Furthermore, the size consistency of the second texture structure is greater than the size consistency of the third texture structure. Size consistency refers to the consistency of the one-dimensional size and / or height of the bottom surface of the texture structure. Size consistency is the difference between the size of the texture structure in a certain area and the average value of the size of the texture structure in the area. For example, the one-dimensional size of the bottom surface of the second texture structure in the unit area of ​​the first non-electrode area and the one-dimensional size of the bottom surface of the third texture structure in the second non-electrode area can be statistically analyzed respectively, and the variance or range of the size of the texture structures of these first non-electrode area and the second non-electrode area can be calculated respectively. The variance or range of the texture structures of the first non-electrode area and the second non-electrode area is used as a reference for consistency. Different texture structures can compare the size of the variance or range to compare the quality of consistency. The smaller the variance or range, the better the size consistency.

[0008] When the first surface is the light-receiving surface, the second texture structure is located on the light-receiving surface and has higher light-trapping and passivation performance requirements than the third texture structure. The texture structure has higher dimensional consistency, which can ensure that different positions of the first non-electrode area have a good light-trapping effect and reduce the probability of incident light being reflected out. At the same time, the better dimensional consistency of the texture structure can provide a surface with relatively regular undulations, which is more beneficial to the thickness uniformity of the subsequent passivation layer, thereby improving the passivation performance of the first non-electrode area surface, reducing the possibility of incident light being recombined on the first non-electrode area surface, and ensuring that the incident light has a greater probability of being incident on the semiconductor substrate at different positions of the first non-electrode area and is not recombined by surface defects. The dimensional consistency of the second texture structure is designed to be greater than that of the third texture structure. The prepared second and third texture structures can respectively meet the light-trapping and passivation requirements of the light-receiving surface of the solar cell and the requirements for improving the light-trapping performance of the backlight surface. Combined with the preparation process, the differentiated size settings of the second texture structure and the third texture structure can reduce the degree of etching of the second non-electrode area of ​​the battery while meeting the battery performance requirements, reduce the loss in the thickness direction of the semiconductor substrate, ensure the thickness of the battery cell, increase the utilization of the absorbed incident light, and ensure the mechanical strength of the battery cell.

[0009] In addition, the doping concentration of the first doped layer disposed in the first electrode region is greater than the doping concentration of the second doped layer disposed in the first non-electrode region. By reducing the doping concentration in the first non-electrode region, the high-concentration area on the first side of the solar cell is reduced, reducing the recombination problem caused by the high doping concentration on the surface of the semiconductor substrate, and increasing the open-circuit voltage of the cell. At the same time, the first doped layer in the first electrode region is retained to ensure low contact resistance between the electrode and the first doped layer, reducing the series resistance of the cell and improving the fill factor, thereby increasing the efficiency of the solar cell. Because the first non-electrode region is not obstructed by the grid lines, it focuses on the light trapping effect and passivation performance of the first side of the cell, while the first electrode region focuses on contact performance and passivation performance. Based on the aforementioned functional differences between the first electrode region and the first non-electrode region, the first non-electrode region needs to take into account both the light trapping effect and the passivation performance of the passivation layer coating.

[0010] In one implementation, the dimensional consistency of the first texture structure is greater than the dimensional consistency of the third texture structure.

[0011] In one implementation, the first texture structure, the second texture structure, or the third texture structure is a pyramid structure.

[0012] When adopting the above technical solution, it is beneficial to increase the surface area of ​​the semiconductor substrate, improve the light trapping effect of the semiconductor substrate, and help more light to be refracted into the semiconductor substrate through the area where the first texture structure, the second texture structure or the third texture structure is located and be utilized by the semiconductor substrate, so that the solar cell has a higher photoelectric conversion efficiency.

[0013] In one implementation, the first electrode region is higher than the first non-electrode region along the thickness direction of the semiconductor substrate, and the distance between the first electrode region and the first non-electrode region is greater than or equal to 2 μm and less than or equal to 7 μm along the thickness direction of the semiconductor substrate.

[0014] When the above technical solution is adopted, the first non-electrode area is recessed relative to the first electrode area, so that light can be reflected and absorbed in the groove, thereby reducing the reflectivity of the second texture structure.

[0015] In one implementation, the reflectivity of the first electrode region where the first texture structure is located is greater than the reflectivity of the first non-electrode region where the second texture structure is located.

[0016] When the above technical solution is adopted, the surface of the first non-electrode area where the second texture structure is located is not blocked by grid lines and the velvet structure with low reflectivity can better utilize the incident light, improve the light absorption utilization rate, and thus improve the photoelectric conversion rate of the solar cell.

[0017] In one implementation, the first electrode region and / or the second electrode region includes a collector electrode region and a bus electrode region, the extension direction of the collector electrode region is inconsistent with the extension direction of the bus electrode region; the width of the bus electrode region is greater than the width of the collector electrode region.

[0018] When the above technical solution is adopted, the bus electrode area includes a continuously arranged bus electrode, or an intermittently arranged bus electrode and an end line structure arranged at the edge of the battery cell, which is used for welding interconnecting parts such as welding ribbons in the component. Because the contact performance of the bus electrode with the solar cell is lower than that of the collector electrode, or because the bus electrode needs to be welded to interconnecting parts such as welding ribbons, the contact area with the solar cell surface or interconnecting parts is usually increased by increasing the width of the bus electrode to improve the contact performance and welding performance of the bus electrode. Therefore, the width of the bus electrode area in the first electrode area and the second electrode area is set to be greater than the width of the collector electrode area, while reducing the area of ​​the first electrode area and the second electrode area, ensuring the contact performance and welding performance of the bus electrode with the solar cell.

[0019] In one implementation, along the thickness direction of the semiconductor substrate, a projection of the first non-electrode region on the second surface at least partially overlaps with a projection of the second non-electrode region on the second surface.

[0020] In the case of adopting the above technical solution, when the second non-electrode area and the first non-electrode area are both recessed into the interior of the semiconductor substrate, if the second non-electrode area and the first non-electrode area completely correspond to each other along the thickness direction of the semiconductor substrate, then the thickness of the semiconductor substrate located in the second non-electrode area and the first non-electrode area is smaller than the thickness of the semiconductor substrate located in the second electrode area and the first electrode area. That is, the thickness of the semiconductor substrate in the non-electrode area is smaller than the thickness of the semiconductor substrate in the electrode area, which leads to a significant reduction in the mechanical strength of the semiconductor substrate in the non-electrode area. Therefore, compared to the complete overlap of the projection of the first non-electrode area on the second surface and the projection of the second non-electrode area on the second surface, in the present application, the projection of the first non-electrode area on the second surface and the projection of the second non-electrode area on the second surface at least partially overlap, which can meet the mechanical strength requirements of the semiconductor substrate and reduce or eliminate the probability of the semiconductor substrate breaking.

[0021] In one implementation, along the thickness direction of the semiconductor substrate, the second non-electrode region is higher than the second electrode region; along the thickness direction of the semiconductor substrate, the distance between the second electrode region and the second non-electrode region is greater than or equal to 2 μm and less than or equal to 6 μm.

[0022] When the above technical solution is adopted, if the distance between the second electrode area and the second non-electrode area along the thickness direction of the semiconductor substrate is greater than 6μm, the depth of the second non-electrode area is deep, and the second surface of the semiconductor substrate is removed more, the overall mechanical strength of the cell is reduced; and the solar cell uses light to separate electrons and holes on the semiconductor substrate to generate electricity. If the semiconductor substrate is removed too much, the transmission path of light in the semiconductor substrate will be reduced, and the light absorption rate of light in the semiconductor substrate will be reduced, resulting in the number of photogenerated carriers, i.e., holes and electrons, generated by irradiation on the semiconductor substrate. This will reduce the photoelectric conversion rate of the solar cell. The present application sets the distance between the second electrode area and the second non-electrode area along the thickness direction of the semiconductor substrate within the above value range, ensuring that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the solar cell will not be reduced, and also ensuring that the cell has sufficient mechanical strength.

[0023] In a second aspect, the present invention further provides a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string includes a plurality of interconnecting members and a plurality of solar cells as described in the above technical solution. The interconnecting members are used to connect the plurality of solar cells in series to form a cell string, and the encapsulation layer is used to cover the surface of the cell string.

[0024] The beneficial effects of the photovoltaic module provided by the present invention are the same as the beneficial effects of the solar cell described in the above technical solution, and will not be described in detail here.

[0025] In a third aspect, the present invention further provides a method for manufacturing a solar cell. The method for manufacturing a solar cell comprises: First, a semiconductor substrate is provided; the semiconductor substrate has a first surface and a second surface opposite to each other; the first surface and the second surface are subjected to a texturing process to form a first texture structure; the first surface includes a first electrode region and a first non-electrode region, and the second surface includes a second electrode region and a second non-electrode region; Next, a diffusion process is performed on the first surface of the semiconductor substrate to form a first doped layer and a first doped oxide layer formed on the first doped layer; Next, a tunneling layer and a doped conductive layer are deposited on the edge region of the first surface and the second surface; a second doped oxide layer is formed on the doped conductive layer; Next, a first laser is used to irradiate the first doped oxide layer and the first doped layer on the first non-electrode region, and the second doped oxide layer, the doped conductive layer and the tunneling layer on the edge region of the first non-electrode region; Next, a second laser is used to irradiate the second doped oxide layer, the doped conductive layer and the tunnel layer located on the second non-electrode region; Next, after the first laser and second laser irradiation processes, a secondary texturing process is performed to form a second texture structure on the first non-electrode area and a third texture structure on the second non-electrode area; the size consistency of the second texture structure is greater than the size consistency of the third texture structure.

[0026] In the method for manufacturing a solar cell provided by the present invention, since a first laser is used to irradiate the first doped oxide layer and the first doped layer located on the first non-electrode area, only the first doped layer of the first electrode area is retained, and the doping concentration at the corresponding position of the first electrode area is greater than the doping concentration at the corresponding position of the first non-electrode area. By reducing the doping concentration of the first non-electrode area, the high-concentration area on the first surface of the solar cell is reduced, the compounding problem caused by the high doping concentration on the surface of the semiconductor substrate is reduced, and the open circuit voltage of the battery is increased; at the same time, the first doped layer of the first electrode area is retained to ensure a smaller contact resistance between the electrode and the first doped layer, reduce the battery series resistance, improve the fill factor, and thus improve the efficiency of the solar cell. Since the first non-electrode area is not blocked by the grid line, the first non-electrode area focuses on the light trapping effect and passivation performance of the first surface of the battery cell, while the first electrode area focuses on contact performance and passivation performance. Based on the functional difference between the first electrode area and the first non-electrode area, the first non-electrode area needs to take into account both the light trapping effect and the passivation performance of the passivation layer coating. Furthermore, the above-mentioned "secondary texturing treatment to form a second texture structure on the first non-electrode area" is performed after the step of "depositing a tunneling layer and a doped conductive layer in the edge area of ​​the first surface and the second surface; forming a second doped oxide layer on the doped conductive layer". At this time, the surface difference between the edge area close to the semiconductor substrate and the middle area of ​​the semiconductor substrate in the first non-electrode area before texturing can be reduced, thereby reducing the difference in the second texture structure formed on the first non-electrode area after texturing. In addition, the chemical passivation of the tunneling layer and the field passivation of the doped conductive layer can significantly reduce the degree of recombination on the surface of the semiconductor substrate. At the same time, the tunneling layer can also ensure the effective tunneling of majority carriers, and the doped conductive layer can significantly improve the conduction performance of photogenerated carriers, thereby improving the open circuit voltage and fill factor of the solar cell. When the tunneling layer and the doped conductive layer are stacked on the second electrode area, the tunneling layer and the doped conductive layer form a passivation contact structure. The tunneling layer allows majority electrons to tunnel into the doped conductive layer while blocking the recombination of minority holes, thereby allowing electrons to be transported laterally in the doped conductive layer and collected by the metal, greatly reducing the metal contact recombination current, increasing the open circuit voltage and short circuit current of the battery, and thus improving the battery efficiency.

[0027] In one implementation, the power of the first laser is 1W to 50W, and the scanning speed of the first laser is 5m / s to 40m / s; the power of the second laser is 1W to 50W, and the scanning speed of the second laser is 5m / s to 40m / s; the power and scanning speed of the first laser and the second laser are different.

[0028] In one implementation, the secondary texturing treatment includes: placing the semiconductor substrate after the first laser and second laser irradiation processes into the first etching tank for secondary texturing treatment; the first etching tank contains an alkaline solution and a texturing additive, the temperature of the first etching tank is 60°C to 85°C, the concentration of the alkaline solution is 0.2% to 6%, and the time of the secondary texturing treatment is 2 minutes to 8 minutes.

[0029] In one implementation, after the first laser and second laser irradiation processes, a secondary texturing process is performed to form a second texture structure on the first non-electrode region. After the third texture structure is formed on the second non-electrode region, the method for manufacturing a solar cell further includes: forming a passivation layer on the doped conductive layer and on the first and second surfaces of the semiconductor substrate; Electrodes are formed on the passivation layer, and the electrodes are respectively located in the first electrode region and the second electrode region.

[0030] The passivation layer can passivate the surface of the semiconductor substrate, reduce surface recombination, and improve the open circuit voltage and fill factor. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 is a cross-sectional view of a solar cell according to an embodiment of the present invention; Figure 2 This is an enlarged schematic diagram of a portion of the structure on the first side of a solar cell according to an embodiment of the present invention. Figure 1 ; Figure 3 This is an enlarged schematic diagram of a portion of the structure on the first side of a solar cell according to an embodiment of the present invention. Figure 2 ; Figure 4 It is a schematic diagram of an enlarged portion of the structure of the second surface of a solar cell according to an embodiment of the present invention.

[0032] Reference numerals: 1-semiconductor substrate, 10-first surface, 100-first electrode region, 101-first non-electrode region, 102-first texture structure, 103-second texture structure; 11-second surface, 110-second electrode region, 111-second non-electrode region, 112-third texture structure; 12-side surface, 3-tunneling layer, 4-doped conductive layer, 5-passivation layer, 50-aluminum oxide passivation layer, 51-silicon nitride passivation layer; 6-first electrode, 7-second electrode. DETAILED DESCRIPTION

[0033] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0034] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0036] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0037] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0038] In a first aspect, an embodiment of the present invention provides a solar cell. Figure 1 The solar cell comprises: a semiconductor substrate 1, a first doping layer and a second doping layer ( Figures 1 to 4(not shown in the figure). The semiconductor substrate 1 includes a first surface 10 and a second surface 11 facing each other. The first surface 10 includes a first electrode region 100 and a first non-electrode region 101. Since the first non-electrode region 101 is not blocked by the gate lines, it focuses on light trapping and passivation performance on the front side of the cell, while the first electrode region 100 focuses on contact performance and passivation performance. Based on the functional differences between the first electrode region 100 and the first non-electrode region 101, the first non-electrode region 101 needs to take into account both the light trapping effect and the passivation performance of the passivation layer coating.

[0039] In terms of shape, the first surface 10 and the second surface 11 of the semiconductor substrate 1 may be the same or different. In an embodiment of the present invention, the first surface 10 and the second surface 11 are the same. For example, the shape of the first surface 10 or the second surface 11 may be square, rectangular, square with rounded corners, circular, etc.

[0040] In terms of materials, the semiconductor substrate 1 can be a substrate made of any semiconductor material, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a gallium arsenide substrate.

[0041] In terms of conductivity type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an N-type conductive substrate, or a P-type conductive substrate. Preferably, the semiconductor substrate 1 is a P-type conductive substrate or an N-type conductive substrate. Compared with the intrinsic conductive substrate, the P-type conductive substrate or the N-type conductive substrate has better conductivity, so that the final solar cell has a lower bulk resistivity, thereby improving the efficiency of the solar cell. Exemplarily, the semiconductor substrate 1 is an N-type silicon substrate. Compared with the P-type conductive substrate, the N-type silicon substrate has the advantages of a long minority carrier lifetime, no light decay, and good weak light performance.

[0042] From the perspective of light reception, when the first surface 10 is a light-receiving surface, the second surface 11 is a backlight surface.

[0043] In some embodiments, the first doping layer is disposed in the first electrode region 100 ; the second doping layer is disposed in the first non-electrode region 101 ; and the doping concentration of the first doping layer is greater than the doping concentration of the second doping layer.

[0044] See also Figures 1 to 4The doping concentration of the first doped layer disposed in the first electrode region 100 is greater than the doping concentration of the second doped layer disposed in the first non-electrode region 101. The first doped layer in the first electrode region 100 is retained to ensure low contact resistance between the electrode and the first doped layer, thereby reducing the series resistance of the cell and improving the fill factor, thereby increasing the efficiency of the solar cell. Simultaneously, by reducing the doping concentration in the first non-electrode region 101, the impact of the field effect of the doped ions in the doped layer on the passivation layer is reduced without affecting contact performance, thereby improving the passivation performance of the light-receiving surface. Furthermore, the high-concentration area on the front of the solar cell is reduced, reducing the recombination problem caused by the high doping concentration on the surface of the semiconductor substrate 1, and increasing the open-circuit voltage of the cell.

[0045] As a possible implementation manner, regarding “the doping concentration of the first doping layer is greater than the doping concentration of the second doping layer”, the doping concentration of the second doping layer is greater than or equal to zero.

[0046] See also Figures 1 to 4 When the doping concentration of the second doped layer is zero, a PN junction is formed between the semiconductor substrate 1 and the first doped layer within the first electrode region 100, while no PN junction exists in the first non-electrode region 101 of the semiconductor substrate 1. In other words, the first side 10 of the solar cell comprises both heavily doped and undoped regions. This effectively reduces the recombination level in the first non-electrode region 101 of the first side 10, increasing the cell's open-circuit voltage. Furthermore, high doping can be performed in the first electrode region 100, improving the contact resistance between the electrode and the first doped layer, reducing the cell's series resistance, and increasing the fill factor, thereby improving the efficiency of the solar cell.

[0047] Furthermore, the above “doping concentration of the first doping layer” may refer to the doping concentration on the surface of the first doping layer, or refer to the average concentration of the first doping layer at different positions along the thickness direction.

[0048] The “doping concentration of the second doping layer” may refer to the doping concentration on the surface of the second doping layer, or refer to the average doping concentration at different positions along the thickness direction of the second doping layer.

[0049] “The doping concentration of the first doping layer is greater than the doping concentration of the second doping layer” may mean that the doping concentration at the surface of the first doping layer is greater than the doping concentration at the surface of the second doping layer. Alternatively, the average concentration of the first doping layer at different locations along the thickness direction is greater than the average concentration of the second doping layer at different locations along the thickness direction.

[0050] In some embodiments, see Figures 1 to 4The above-mentioned first doped layer can be an additional film layer formed on the semiconductor substrate 1; or, the first doped layer is formed by performing a diffusion treatment on the first surface 10 of the semiconductor substrate 1, and at this time, the top surface of the first doped layer is coplanar with the first surface 10 of the semiconductor substrate 1.

[0051] In some embodiments, see Figures 1 to 4 The above-mentioned second doped layer can be an additional film layer formed on the semiconductor substrate 1; or, the second doped layer is formed by performing a diffusion treatment on the first surface 10 of the semiconductor substrate 1, and at this time, the top surface of the second doped layer is coplanar with the first surface 10 of the semiconductor substrate 1.

[0052] As a possible implementation, see Figures 1 to 4 The semiconductor substrate 1 is an N-type silicon substrate, the first doped layer is a P-type doped layer, and the second doped layer is a P-type doped layer. The first doped layer and the second doped layer are diffusion layers on the surface of the semiconductor substrate 1. In this case, the surface of the first doped layer and the second doped layer is a single crystal silicon surface. The doping concentration of the second doped layer is set to be lower than the doping concentration of the first doped layer. This improves the passivation of the semiconductor substrate 1 surface by the subsequent passivation layer, which is more important than the battery structure that provides additional doping layers.

[0053] In some embodiments, see Figures 1 to 4 The surface of the first electrode area 100 has a first texture structure 102, and the first non-electrode area 101 has a second texture structure 103; the second surface 11 includes a second electrode area 110 and a second non-electrode area 111; the second non-electrode area 111 has a third texture structure 112, and the size consistency of the second texture structure 103 is greater than the size consistency of the third texture structure 112.

[0054] See also Figures 1 to 4The first non-electrode area 101 is located on the light-receiving surface of the bifacial cell. Compared with the second non-electrode area 111, most of the incident light enters from the light-receiving surface. Therefore, better light trapping effect and passivation performance are required to ensure that the incident light enters the semiconductor substrate 1 from the light-receiving surface instead of being reflected or incident on the surface of the light-receiving surface and recombined by the recombination center on the light-receiving surface, thereby increasing the possibility of the incident light being transmitted to the laser photogenerated carriers in the semiconductor substrate 1, thereby increasing the utilization rate of the solar cell for the incident light. The second texture structure 103 located on the light-receiving surface has a higher dimensional consistency than the third texture structure 112 located on the backlight surface, which can ensure that different positions of the first non-electrode area 101 have a good light-trapping effect, reducing the probability of incident light being reflected outside the solar cell. At the same time, the better dimensional consistency of the texture structure can provide a surface with relatively regular undulations, which is more beneficial to the thickness uniformity of the subsequent passivation layer, thereby improving the passivation performance of the surface of the first non-electrode area 101, reducing the possibility of incident light being recombined on the surface of the first non-electrode area 101, and ensuring that the incident light has a greater probability of being incident on the semiconductor substrate 1 at different positions of the first non-electrode area 101 and is not recombined by surface defects. The dimensional consistency of the second texture structure 103 is designed to be greater than the dimensional consistency of the third texture structure 112. The prepared second texture structure 103 and third texture structure 112 can respectively meet the light trapping and passivation requirements of the light-receiving surface of the solar cell, and the requirements for improving the light trapping performance of the backlight surface. Combined with the preparation process, the differentiated size settings of the second texture structure 103 and the third texture structure 112 can reduce the degree of etching of the second non-electrode area 111 of the battery while meeting the battery performance requirements, reduce the loss in the thickness direction of the semiconductor substrate 1, ensure the thickness of the battery cell, increase the utilization of the absorbed incident light, and ensure the mechanical strength of the battery cell.

[0055] As a possible implementation, see Figures 1 to 4 The dimensional consistency of the first texture structure 102 in the first electrode region 100 is greater than the dimensional consistency of the third texture structure 112 in the second non-electrode region 111. The dimensional consistency of the texture structure on the light-receiving surface needs to be greater than that on the backlight surface to meet the reflectivity consistency and passivation performance requirements of the texture structure on the light-receiving surface of the cell.

[0056] The third texture structure 112 of the second non-electrode area 111 has better size consistency, which can improve the light trapping effect on the surface of the second non-electrode area 111. It can not only improve the light trapping effect of the back of the solar cell on the incident light, but also reduce the probability of light transmitted from the inside of the solar cell to the back to be reflected out of the solar cell. At the same time, the first texture structure 102 in the first electrode area 100 and the second texture structure 103 in the first non-electrode area 101 have better size consistency. While enhancing the reflection of the front of the solar cell and improving the light trapping effect of the front of the solar cell, it also enhances the uniformity of the thickness of the passivation layer at different positions when the passivation layer is coated on the front of the solar cell, improves the passivation performance of the front of the solar cell, and reduces the probability of incident light being recombined on the light-receiving surface. By matching the structure of the electrode area and the non-electrode area on the light-receiving surface and the texture structure in different areas, the light utilization rate is improved from the two aspects of improving the light trapping effect and reducing the probability of incident light being recombined, thereby improving the efficiency of the solar cell.

[0057] Size consistency refers to the consistency of the one-dimensional size and / or height of the bottom surface of the texture structure. Size consistency is the difference between the size of the texture structure in a certain area and the average value of the size of the texture structure in the area. For example, the one-dimensional size of the bottom surface of the second texture structure 103 in the unit area of ​​the first non-electrode area 101 and the one-dimensional size of the bottom surface of the third texture structure 112 in the second non-electrode area 111 can be statistically analyzed respectively, and the variance or range of the size of the texture structures of the first non-electrode area 101 and the second non-electrode area 111 can be calculated respectively. The variance or range of the texture structure of the first non-electrode area 101 and the second non-electrode area 111 is used as a reference for consistency. Different texture structures can compare the size of the variance or range to compare the quality of consistency. The smaller the variance or range, the better the size consistency.

[0058] As a possible implementation, see Figure 1 The first texture structure 102, the second texture structure 103, or the third texture structure 112 is a pyramid-shaped structure. This helps increase the surface area of ​​the semiconductor substrate 1, improves the light trapping effect of the semiconductor substrate 1, and helps more light be refracted into the semiconductor substrate 1 through the area where the first texture structure 102, the second texture structure 103, or the third texture structure 112 is located and utilized by the semiconductor substrate 1, thereby achieving a higher photoelectric conversion efficiency for the solar cell.

[0059] In an alternative approach, see Figure 1When the first texture structure 102 is a pyramid-shaped structure, the tower height of the first texture structure 102 is greater than or equal to 1 μm and less than or equal to 4 μm; the base size of the first texture structure 102 is greater than or equal to 1 μm and less than or equal to 5 μm. The base of the first texture structure 102 is square, rhombus, rectangle, parallelogram, approximately rhombus, or approximately rectangle. The base size of the first texture structure 102 can be the longest side, short side, diagonal, or the longest distance between the two endpoints of the base shape. The tower height and base size of the first texture structure 102 can be the tower height or base size of a single texture structure, or can be the average tower height or base size of the first texture structure 102 within a certain area. For example, in the range of 1 μm×1 μm, the tower height of the first texture structure 102 can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm, etc. The bottom surface size of the first texture structure 102 may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm.

[0060] In an alternative approach, see Figure 1 When the second texture structure 103 is a pyramid structure, the tower height of the second texture structure 103 is greater than or equal to 1 μm and less than or equal to 4 μm; the bottom surface size of the second texture structure 103 is greater than or equal to 1 μm and less than or equal to 5 μm. The bottom surface of the second texture structure 103 is square, rhombus, rectangle, parallelogram, approximately rhombus or approximately rectangle. The bottom surface size of the second texture structure 103 can be the long side, short side, diagonal or the longest distance between the two end points of the bottom surface shape. The tower height and bottom surface size of the second texture structure 103 can be the tower height or bottom surface size of a single texture structure, or the average value of the tower height or bottom surface size of the second texture structure 103 within a certain area. For example, in the range of 1 μm×1 μm, the tower height of the second texture structure 103 can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm or 4 μm, etc. The bottom surface size of the second texture structure 103 may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm.

[0061] See also Figure 1 The tower heights or bottom dimensions of the first texture structure 102 and the second texture structure 103 may be equal or unequal.

[0062] As a possible implementation, see Figure 1 、 Figure 2 and Figure 3Along the thickness direction A of the semiconductor substrate 1, the first electrode region 100 is higher than the first non-electrode region 101. Along the thickness direction of the semiconductor substrate 1, the distance between the first electrode region 100 and the first non-electrode region 101 is greater than or equal to 2 μm and less than or equal to 7 μm. In this case, the first non-electrode region 101 is recessed relative to the first electrode region 100, allowing light to be reflected and absorbed within the recess, thereby reducing the reflectivity of the second texture structure 103.

[0063] See also Figures 1 to 3 The distance L1 between the first electrode region 100 and the first non-electrode region 101 may be the distance between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the top surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101. Exemplarily, the distance L1 between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101 may be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, or 7 μm, etc.

[0064] It is worth noting that see Figures 1 to 3 The top surface of the first electrode region 100 is formed by the vertices of multiple first texture structures 102. Due to the different sizes of different first texture structures 102, the top surface here is the plane formed by the vertices of the majority of the first texture structures 102 on the first electrode region 100. The proportion of the majority of the first texture structures 102 in the first electrode region 100 can be flexibly selected according to actual conditions. Similarly, the top surface of the first non-electrode region 101 is formed by the vertices of multiple second texture structures 103.

[0065] As a possible implementation, see Figures 1 to 3 The reflectivity of the first electrode region 100 where the first texture structure 102 is located is greater than the reflectivity of the first non-electrode region 101 where the second texture structure 103 is located. The absence of grid lines on the surface of the first non-electrode region 101 where the second texture structure 103 is located, combined with the suede structure with lower reflectivity, allows for better utilization of incident light, improving light absorption and utilization, thereby increasing the photoelectric conversion efficiency of the solar cell.

[0066] As a possible implementation, see Figures 1 to 3 The first electrode region 100 and / or the second electrode region 110 includes a collector electrode region and a bus electrode region, and the extension direction of the collector electrode region is inconsistent with the extension direction of the bus electrode region; the width of the bus electrode region is greater than the width of the collector electrode region.

[0067] The busbar electrode area includes continuously arranged busbar electrodes, or intermittently arranged busbar electrodes and terminal line structures arranged at the edge of the cell, which are used for welding interconnects such as welding ribbons in the module. Because the contact performance of the busbar electrode with the solar cell is lower than that of the collector electrode, or because the busbar electrode needs to be welded to interconnects such as welding ribbons, the contact area with the solar cell surface or interconnects is usually increased by increasing the width of the busbar electrode to improve the contact performance and welding performance of the busbar electrode. Therefore, the width of the busbar electrode area in the first electrode area and the second electrode area is set to be greater than the width of the collector electrode area. While reducing the area of ​​the first electrode area and the second electrode area, the contact performance and welding performance of the busbar electrode with the solar cell are guaranteed.

[0068] As a possible implementation, see Figure 1 Along the thickness direction of the semiconductor substrate 1 , a projection of the first non-electrode region 101 on the second surface 11 at least partially overlaps with a projection of the second non-electrode region 111 on the second surface 11 .

[0069] As a possible implementation, see Figure 1 The overlap range of the projection width of the first non-electrode area 101 on the second surface 11 and the projection width of the second non-electrode area 111 on the second surface 11 accounts for 50% to 95% of the projection width of the first non-electrode area 101 on the second surface 11 or the projection width of the second non-electrode area 111 on the second surface 11. For example, the overlap range may be 50%, 55%, 60%, 65%, 70%, 75%, 80%, 86%, 90%, or 95%.

[0070] See also Figure 1In the actual production of solar cells, the second non-electrode region 111 is the laser action area. When the laser acts on the second surface 11 of the semiconductor substrate 1, it will affect the first surface 10 of the semiconductor substrate 1, causing changes in the surface of the first surface 10 corresponding to the laser action area. Based on this, when the second non-electrode region 111 and the first non-electrode region 101 are completely overlapped along the thickness direction of the semiconductor substrate 1, the laser-affected area (i.e., the first non-electrode region 101) on the other side affected by the laser action area (i.e., the second non-electrode region 111) can be etched away during the process, reducing the area affected by the laser on the first and second surfaces 10, 11 of the semiconductor substrate 1, providing a good surface foundation for subsequent coating and electrode printing; and can also reduce the transmission path of carriers to the positive and negative electrode regions to a certain extent. When both the second non-electrode region 111 and the first non-electrode region 101 are recessed into the interior of the semiconductor substrate 1, if the second non-electrode region 111 and the first non-electrode region 101 completely correspond along the thickness direction of the semiconductor substrate 1, the thickness of the semiconductor substrate 1 located in the second non-electrode region 111 and the first non-electrode region 101 is smaller than the thickness of the semiconductor substrate 1 located in the second electrode region 110 and the first electrode region 100. In other words, the thickness of the semiconductor substrate 1 in the non-electrode region is smaller than the thickness of the semiconductor substrate 1 in the electrode region, resulting in a significant reduction in the mechanical strength of the semiconductor substrate 1 in the non-electrode region. Therefore, compared to completely overlapping the projection of the first non-electrode region 101 on the second surface 11 and the projection of the second non-electrode region 111 on the second surface 11, in the present application, the projection of the first non-electrode region 101 on the second surface 11 and the projection of the second non-electrode region 111 on the second surface 11 at least partially overlap, which can meet the mechanical strength requirements of the semiconductor substrate 1 and reduce or eliminate the probability of fracture of the semiconductor substrate 1.

[0071] As a possible implementation, see Figure 1 The second electrode regions 110 and the second non-electrode regions 111 are alternately arranged on the second surface 11. The tunneling layer 3 is disposed on the surface of the second electrode region 110, and the doped conductive layer 4 is disposed on the second electrode region 110 and is located on the side of the tunneling layer 3 away from the semiconductor substrate 1. The surface of the second electrode region 110 includes a tower base structure. The tower base structure has a smaller undulation than the pyramid structure, and the surface reflectivity of the tower base structure area is greater than the surface reflectivity of the pyramid structure area.

[0072] See also Figure 1The second non-electrode region 111 is not provided with a tunneling layer 3 and a doped conductive layer 4, which can reduce the area of ​​the tunneling layer 3 and the doped conductive layer 4 on the second surface 11, reduce parasitic absorption on the second surface 11, and improve the utilization rate of the incident light on the second surface 11 of the solar cell. In the process of preparing the tunneling layer 3 and the doped conductive layer 4, the tunneling layer 3 and the doped conductive layer 4 are usually first deposited as a whole layer on the second surface 11, and then the tunneling layer 3 and the doped conductive layer 4 on the second non-electrode region 111 are removed by laser, wet etching, etc. Therefore, setting the second electrode region 110 higher than the second non-electrode region 111 can ensure that while removing the tunneling layer 3 and the doped conductive layer 4 in the second non-electrode region 111, the inner expansion layer on the surface of the semiconductor substrate 1 in the second non-electrode region 111 is also removed, reducing the Auger recombination caused by the doping elements in the second non-electrode region 111, reducing the probability of carriers being recombined in the second non-electrode region 111, and improving the battery efficiency.

[0073] In some embodiments, see Figure 1 The doping types of the doped conductive layer 4 and the first doped layer are opposite.

[0074] See also Figure 1 As for the material and thickness of the tunneling layer 3, they can be set according to actual conditions and are not specifically limited here. For example, the material of the tunneling layer 3 may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbide. The thickness of the tunneling layer 3 is greater than or equal to 1 nm and less than or equal to 2 nm. For example, the thickness of the tunneling layer 3 may be 1 nm, 1.2 nm, 1.5 nm, 1.7 nm, 1.8 nm or 2 nm. Furthermore, the doped conductive layer 4 may be a doped polysilicon layer, and the doped polysilicon layer may be a phosphorus-doped polysilicon layer. Of course, it may also be doped with other substances and is not specifically limited here.

[0075] In some embodiments, see Figure 1 and Figure 4 Along the thickness direction A of the semiconductor substrate 1, the second non-electrode region 111 is higher than the second electrode region 110. Along the thickness direction A of the semiconductor substrate 1, a distance L2 between the second electrode region 110 and the second non-electrode region 111 is greater than or equal to 2 μm and less than or equal to 6 μm.

[0076] See also Figure 1 and Figure 4The distance L2 between the second electrode region 110 and the second non-electrode region 111 may be the distance between the top surface of the second electrode region 110 and the top surface of the second non-electrode region 111, or the distance between the bottom surface of the second electrode region 110 and the bottom surface of the second non-electrode region 111, or the distance between the bottom surface of the second electrode region 110 and the top surface of the second non-electrode region 111, or the distance between the top surface of the second electrode region 110 and the bottom surface of the second non-electrode region 111. Exemplarily, the distance L2 between the second electrode region 110 and the second non-electrode region 111 may be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, or 6 μm, etc.

[0077] See also Figures 1 to 4 If the distance between the second electrode region 110 and the second non-electrode region 111 along the thickness direction of the semiconductor substrate 1 is greater than 6μm, and the depth of the second non-electrode region 111 is deeper, then more of the second surface 11 of the semiconductor substrate 1 is removed, which will reduce the overall mechanical strength of the cell. In addition, solar cells use light to separate electrons and holes on the semiconductor substrate 1 to generate electricity. If too much of the semiconductor substrate 1 is removed, the transmission path of light in the semiconductor substrate 1 will be reduced, and the light absorption rate of the semiconductor substrate 1 will be reduced, resulting in a decrease in the number of photogenerated carriers, i.e., holes and electrons, generated by irradiation on the semiconductor substrate 1, which will in turn reduce the photoelectric conversion rate of the solar cell. This application sets the distance between the second electrode region 110 and the second non-electrode region 111 along the thickness direction of the semiconductor substrate 1 within the above-mentioned value range, ensuring that the light absorption rate of the semiconductor substrate 1 is high, the photoelectric conversion rate of the solar cell will not be reduced, and also ensuring that the cell has sufficient mechanical strength.

[0078] In some embodiments, see Figure 1 In the process of texturing the second non-electrode area 111 of the second surface 11 to form the third texture structure 112, a portion of the semiconductor substrate 1 located in the second non-electrode area 111 is corroded and removed, so along the thickness direction A of the semiconductor substrate 1, the top surface of the second non-electrode area 111 is higher than the top surface of the second electrode area 110.

[0079] At this time, the top surface of the second non-electrode area 111 is composed of the vertices of multiple third texture structures 112. Based on the different sizes of different third texture structures 112, the top surface of the second non-electrode area 111 here is a plane formed by the vertices of most third texture structures 112 on the second non-electrode area 111. The proportion of most third texture structures 112 in the second non-electrode area 111 can be flexibly selected according to actual conditions.

[0080] In a second aspect, embodiments of the present invention further provide a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string includes a plurality of interconnecting members and a plurality of solar cells as described in the above technical solution. The interconnecting members are used to connect the plurality of solar cells in series to form a cell string, and the encapsulation layer is used to cover the surface of the cell string.

[0081] The beneficial effects of the photovoltaic module provided by the embodiment of the present invention are the same as the beneficial effects of the solar cell described in the above technical solution, and will not be described in detail here.

[0082] In some embodiments, the solar cell is a TOPCon cell.

[0083] In a third aspect, the present invention also provides a method for manufacturing a solar cell. Figures 1 to 4 , the manufacturing method of the solar cell includes: First, a semiconductor substrate 1 is provided; the semiconductor substrate 1 has a first surface 10 and a second surface 11 opposite to each other, and a plurality of side surfaces 12 located between the first surface 10 and the second surface 11; the first surface 10 and the second surface 11 are subjected to a texturing process to form a first texture structure 102; the first surface 10 includes a first electrode region 100 and a first non-electrode region 101, and the second surface 11 includes a second electrode region 110 and a second non-electrode region 111; The first texture structure 102 can trap light, reduce the reflection of sunlight by the solar cell, and thus improve the performance of the solar cell.

[0084] For example, when the first surface 10 is the light-receiving surface, the second surface 11 is the backlight surface. Alternatively, when the first surface 10 is the front surface, the second surface 11 is the back surface.

[0085] For example, the semiconductor substrate 1 is cleaned, and then the first surface 10 and the second surface 11 are textured using an alkaline texturing solution. The specific cleaning steps and texturing methods can be found in the prior art and are not specifically limited here. The shape, material, conductivity type, and light-receiving characteristics of the semiconductor substrate 1 are described above and are not further elaborated here.

[0086] Next, the first surface 10 of the semiconductor substrate 1 is diffused to form a first doped layer and a first doped oxide layer formed on the first doped layer; wherein the semiconductor substrate 1 and the first doped layer located in the first electrode region 100 have opposite conductivity types. At this time, the semiconductor substrate 1 and the first doped layer located in the first electrode region 100 form a PN junction.

[0087] Exemplarily, the doping source used in the diffusion process includes a Group III source. For example, the Group III source may be a boron source, a gallium source, an indium source, or the like.

[0088] In an optional embodiment, the Group III source is a boron source and the first doped oxide layer is a borosilicate glass layer. The borosilicate glass layer can protect the solar cell during subsequent processing, reducing the risk of etching the first electrode region 100 and ensuring the quality of the solar cell.

[0089] In some embodiments, the first surface 10 of the semiconductor substrate 1 is subjected to a diffusion treatment to form a first doped layer and a first doped oxide layer formed on the first doped layer. The method can be: the semiconductor substrate 1 is placed in a tubular diffusion furnace and a boron source BCl3 or BBr3 is diffused in a nitrogen and oxygen atmosphere. The diffusion time and temperature can be set according to actual needs. At this time, a first doped layer (e.g., a doped P+ layer) and a first doped oxide layer (e.g., a borosilicate glass layer) are formed. It should be noted that when the first surface 10 of the semiconductor substrate 1 is subjected to a diffusion treatment, the first doped layer and the first doped oxide layer are inevitably formed on at least a portion of the side surface 12 and the second surface 11. The at least portion of the second surface 11 can be understood as: the edge region of the second surface 11 near the side surface 12, or the entire second surface 11.

[0090] As a possible implementation, the above-mentioned method for manufacturing a solar cell further includes the following steps: removing the first doping layer formed on the second surface 11 and the side surface 12 to remove the PN junction on the second surface 11 and the side surface 12 .

[0091] Exemplarily, a chain machine and a slot machine are used to polish the second surface 11 (backlight surface) and side surface 12 formed with the first doped layer to remove the PN junction on the second surface 11 and side surface 12 of the semiconductor substrate 1, thereby eliminating leakage caused by the PN junction on the side. The specific processing process and the reagents used can refer to the existing technology and are not specifically limited here. It should be noted that the first doped oxide layer formed on the second surface 11 and side surface 12 is also removed at this time. While cleaning the PN junction on the second surface 11 and side surface 12, the borosilicate glass layer remaining in the first non-electrode area 101 of the first surface 10 is also cleaned to facilitate the subsequent secondary texturing process.

[0092] Next, a tunneling layer 3 and a doped conductive layer 4 are deposited on the edge region of the first surface 10 and the second surface 11. A second doped oxide layer is formed on the doped conductive layer 4. The semiconductor substrate 1 and the doped conductive layer 4 located within the first electrode region 100 have the same conductivity type. For the first surface 10 of the semiconductor substrate 1, the tunneling layer 3 and the doped conductive layer 4 are disposed on the first doped layer located in the edge region or the first non-electrode region 101.

[0093] For example, a tunneling layer 3 and a doped conductive layer 4 are sequentially grown on the second surface 11, and the tunneling layer 3 and the doped conductive layer 4 are plated around the edge region of the first surface 10. Alternatively, a tunneling layer 3 and a doped conductive layer 4 are sequentially grown on the edge region of the first surface 10 and on the second surface 11. Simultaneously, a second doped oxide layer is grown on the doped conductive layer 4. During subsequent processing of the solar cell, the second doped oxide layer can provide protection, reducing the risk of etching the second electrode region 110, thereby ensuring the quality of the solar cell.

[0094] As a possible implementation method, there are three possible implementation methods for depositing the doped conductive layer 4: LPCVD (Low Pressure Chemical Vapor Deposition) double-sided deposition of the doped conductive layer, LPCVD single-sided deposition of the doped conductive layer, and PECVD (Plasma Enhanced Chemical Vapor Deposition) deposition of the doped conductive layer 4. Among them, LPCVD double-sided deposition of the doped conductive layer 4 and PECVD deposition of the doped conductive layer 4 can ensure that the doped conductive layer 4 formed on the first surface 10 and the second surface 11 are consistent, and a uniform texture structure can be formed in the first non-electrode area 101 and the second non-electrode area 111 during subsequent texturing. When LPCVD is used to deposit the doped conductive layer 4 on the second surface 11, there is wrap-around plating on the first surface 10, resulting in wrap-around plating areas and non-wrapped plating areas on the first surface 10, which in turn leads to inconsistent reaction times for subsequent secondary texturing in the wrap-around plating areas and non-wrapped plating areas on the first surface 10. By optimizing additives and formulas, it can be ensured that both the wrap-around plating areas and the non-wrapped plating areas can form a good texture structure, thereby achieving the expected light trapping and passivation effects.

[0095] As for the material and thickness of the tunneling layer 3, they can be set according to actual conditions and are not specifically limited here. For example, the material of the tunneling layer 3 can include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbide. The doped conductive layer 4 can be a doped polysilicon layer, and the doped polysilicon layer can be a phosphorus-doped polysilicon layer. Of course, other substances can also be doped, and are not specifically limited here. The second doped oxide layer is a phosphosilicate glass layer.

[0096] At this time, the above-mentioned solar cell manufacturing method can be used to manufacture a tunneling oxide layer passivation contact cell to meet actual needs. Furthermore, the chemical passivation of the tunneling layer 3 and the field passivation of the doped conductive layer 4 can significantly reduce the degree of recombination on the surface of the semiconductor substrate 1. At the same time, the tunneling layer 3 can also ensure the effective tunneling of majority carriers, and the doped conductive layer 4 can significantly improve the conductivity of photogenerated carriers, thereby improving the open circuit voltage and fill factor of the solar cell. When the second surface 11 is stacked with a tunneling layer 3 and a doped conductive layer 4, the tunneling layer 3 and the doped conductive layer 4 form a passivation contact structure. The tunneling layer 3 allows the majority electrons to tunnel into the doped conductive layer 4 while blocking the recombination of the minority carrier holes, thereby allowing the electrons to be transported laterally in the doped conductive layer 4 and collected by the metal, greatly reducing the metal contact recombination current, improving the open circuit voltage and short circuit current of the battery, and thus improving the battery efficiency. When the tunneling layer 3 and the doped conductive layer 4 are stacked on the edge region of the first surface 10 , the tunneling layer 3 and the doped conductive layer 4 can further passivate the edge region of the first surface 10 , thereby improving the passivation performance of the cell edge.

[0097] Next, the first doped oxide layer and the first doped layer on the first non-electrode region 101 are irradiated with a first laser, and the second doped oxide layer, the doped conductive layer 4 and the tunneling layer 3 on the edge region of the first non-electrode region 101 are irradiated with a first laser. Specifically, when the first non-electrode region 101 includes an edge region and a middle region, using a first laser to irradiate the first doped oxide layer and the first doped layer located on the first non-electrode region 101 includes: using a first laser to irradiate the first doped oxide layer and the first doped layer located on the edge region and the middle region of the first non-electrode region 101.

[0098] The following describes a possible method in which a first laser is used to irradiate the first doped oxide layer and the first doped layer located on the first non-electrode area 101, and a first laser is used to irradiate the second doped oxide layer, the doped conductive layer 4 and the tunneling layer 3 located on the edge area of ​​the first non-electrode area 101. It should be noted that the following description is for understanding only and is not used for specific limitation.

[0099] The first doped oxide layer located in the first non-electrode region 101 is irradiated using a first laser process, and the second doped oxide layer located on the edge region of the first non-electrode region 101 is irradiated using the first laser process. The depth of the first laser treatment is relatively deep to ensure that the first doped oxide layer and the first doped layer in the middle region of the first non-electrode region 101, as well as the second doped oxide layer, the doped conductive layer, the tunneling layer, the first doped oxide layer and the first doped layer in the edge region of the first non-electrode region 101 can all be removed during the subsequent cleaning process. Exemplarily, the first laser irradiation destroys the doped silicon glass layer located in the first non-electrode region 101, including the borosilicate glass layer and / or the phosphosilicate glass layer, thereby reducing the protective effect of the doped silicon glass layer on the first non-electrode region 101. The laser in the first laser process can be any one of red, green or purple light. The high-energy laser beam of a specific wavelength emitted by the laser acts on the doped silica glass layer. The doped silica glass layer absorbs the high-energy laser, causing the atoms in the doped silica glass layer to gain energy and produce vibration, migration and other movements, thereby destroying the chemical bonds between the atoms, thereby destroying the internal structure of the doped silica glass layer and making the doped silica glass layer structure loose. Alternatively, when the laser energy is very high, the doped silica glass layer will melt and vaporize in a short time, and eventually volatilize and remove. Regardless of whether the doped silica glass layer is removed or loosened, its protective effect on the first non-electrode area 101 is significantly reduced. During subsequent alkali cleaning, the alkali can corrode the semiconductor substrate 1 due to insufficient protection of the doped silica glass layer.

[0100] Exemplarily, after using a first laser to irradiate the first doped oxide layer located on the first non-electrode area 101 and the second doped oxide layer located on the edge area of ​​the first non-electrode area 101, an alkaline texturing formula is used to remove the first doped layer located on the first non-electrode area 101. At this time, only the first doped layer of the first electrode area 100 is retained, and the doping concentration at the corresponding position of the first electrode area 100 is greater than the doping concentration at the corresponding position of the first non-electrode area 101. At this time, since the second doped oxide layer in the edge area of ​​the first non-electrode area 101 and the first doped oxide layer in the middle area are both irradiated by the first laser, they can be removed during the cleaning process, and after processing, the surface of the semiconductor substrate 1 corresponding to the first non-electrode area 101 is exposed, thereby increasing the dimensional consistency of the texture structure in the edge area and the middle area of ​​the first non-electrode area 101 in the subsequent texturing process.

[0101] By reducing the doping concentration of the first non-electrode region 101, the high-concentration area on the front of the solar cell is reduced, reducing the recombination problem caused by the high doping concentration on the surface of the semiconductor substrate 1, and increasing the open-circuit voltage of the cell. At the same time, the first doped layer of the first electrode region 100 is retained, ensuring low contact resistance between the electrode and the first doped layer, reducing the cell's series resistance, improving the fill factor, and thus enhancing the efficiency of the solar cell. Because the first non-electrode region 101 is not obstructed by the grid lines, it focuses on light trapping and passivation performance on the front of the cell, while the first electrode region 100 focuses on contact performance and passivation performance. Given the functional differences between the first electrode region 100 and the first non-electrode region 101, the first non-electrode region 101 must balance light trapping and the passivation performance of the passivation layer. In other words, after removing the first doped oxide layer on the first non-electrode region 101, the doping concentration within the first non-electrode region 101 is now zero. That is, the PN junction in the first non-electrode area 101 is removed, which effectively reduces the recombination level of the first non-electrode area 101 in the first surface 10 on the one hand, thereby improving the open circuit voltage of the battery. At the same time, high doping can be performed in the first electrode area 100 to improve the contact resistance between the electrode and the first doping layer in the first electrode area 100, reduce the battery series resistance, and improve the fill factor. On the other hand, the surface of the first non-electrode area 101 with a lower doping concentration can reduce the impact on the field effect passivation of the passivation layer, improve the passivation performance of the solar cell surface, and comprehensively improve the efficiency of the solar cell.

[0102] In some embodiments, see Figure 1 The width W1 of the first non-electrode region 101 is greater than or equal to 200 μm and less than or equal to 800 μm. For example, the width W1 of the first non-electrode region 101 may be 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm, or 800 μm.

[0103] In some embodiments, the first non-electrode region 101 is etched to a depth greater than or equal to 1 μm and less than or equal to 5 μm. For example, the depth may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, or 5 μm.

[0104] It should be noted that since the film layer structures in the edge area and the middle area of ​​the first non-electrode area 101 are different, the film layer in the edge area can be loosened to a greater depth by making the laser action time different in the edge area and the middle area, thereby ensuring that the film layer on the surface of the first non-electrode area 101 can be completely removed at the same time in the subsequent wet process.

[0105] Next, a second laser is used to irradiate the second doped oxide layer, the doped conductive layer 4 and the tunneling layer 3 located on the second non-electrode region 111 ; Exemplarily, a second laser process is used to irradiate the second doped oxide layer within the second non-electrode region 111, i.e., the second doped oxide layer is subjected to laser patterning. The second laser irradiation area is the second non-electrode region 111. High-energy laser irradiation acts on the phosphosilicate glass layer in a short period of time, causing the phosphosilicate glass layer to be modified, loosened, or vaporized, reducing the protective capability of the phosphosilicate glass layer within the second non-electrode region 111. This ensures that a reaction rate gradient is formed during the subsequent alkaline etching process, allowing the second non-electrode region 111 to be etched as required, while the second electrode region 110 is unaffected due to the protection of the phosphosilicate glass layer. During the subsequent etching process, the doped conductive layer 4 within the second electrode region 110 is protected by the phosphosilicate glass layer and is not corroded by the alkaline agent. However, due to the destruction of the phosphosilicate glass layer within the second non-electrode region 111, the doped conductive layer 4 within the second non-electrode region 111 is corroded by the alkaline agent, and the alkaline agent further corrodes the tunneling layer 3 and the semiconductor substrate 1. At this point, the tunneling layer 3 and doped conductive layer 4 located in the second electrode region 110 form a conductive contact layer, which corresponds one-to-one with the electrodes. The doped conductive layer 4 located in the second non-electrode region 111 on the second surface 11 is removed, effectively reducing parasitic absorption and increasing the battery current. The doped conductive layer 4 in the second electrode region 110 is retained, preventing corrosion of the semiconductor substrate 1 by the slurry during metallization and improving the battery's fill factor.

[0106] Illustratively, the laser wavelength in the first laser process and the second laser process is greater than or equal to 300 nm and less than or equal to 1200 nm. For example, the laser wavelength may be 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, or 1200 nm. The wavelength of the first laser in the first laser process and the wavelength of the second laser in the second laser process may be the same or different.

[0107] The width W2 of the second non-electrode area 111 is greater than or equal to 250μm and less than or equal to 800μm. For example, the width W2 of the second non-electrode area 111 can be 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm, 650μm, 700μm, 750μm or 800μm, etc.

[0108] In some embodiments, the laser power of the first laser and the second laser ranges from 1 W to 50 W. Exemplarily, the laser power can be 1 W, 5 W, 10 W, 15 W, 20 W, 25 W, 30 W, 35 W, 40 W, 45 W, or 50 W. The scanning speed of the first laser and the second laser ranges from 5 m / s to 40 m / s. Exemplarily, the scanning speed of the first laser and the second laser ranges from 5 m / s, 10 m / s, 15 m / s, 20 m / s, 25 m / s, 30 m / s, 35 m / s, or 40 m / s. The first laser and the second laser constitute two process steps. The specific laser power and scanning speed can be the same or different and should be adjusted according to the actual process conditions. No special limitation is made here.

[0109] Next, see Figure 1 After the first laser and second laser irradiation processes, a secondary texturing process is performed to form a second texture structure 103 on the first non-electrode area 101, and at the same time form a third texture structure 112 in the second non-electrode area 111; the size consistency of the second texture structure 103 is greater than the size consistency of the third texture structure 112.

[0110] Combined with the above description, see Figure 1 Since the first doped oxide layer and the first doped layer in the middle area of ​​the first non-electrode area 101, and the first doped oxide layer, the first doped layer, the second doped oxide layer, the doped conductive layer 4 and the tunneling layer 3 in the edge area are removed, a texturing solution (such as a mixed solution of a sodium hydroxide solution and a texturing additive) is used to treat the semiconductor substrate 1 located in the first non-electrode area 101 to form a second texture structure 103 on the first non-electrode area 101.

[0111] See also Figure 1 , combined with the above description, since the phosphosilicate glass layer located in the second non-electrode area 111 is destroyed, the doped conductive layer 4 located in the second non-electrode area 111 is corroded by the alkaline agent, and the alkaline agent further corrodes the tunneling layer 3 and the semiconductor substrate 1 downward. When the alkaline agent corrodes downward the semiconductor substrate 1 located in the second non-electrode area 111, a third texture structure 112 is formed in the second non-electrode area 111. Compared with the second non-electrode area 111 without a texture structure, the reflectivity of the second non-electrode area 111 is significantly reduced. Combined with the optimization of the passivation process, the battery efficiency is not affected, and the battery bifaciality is improved.

[0112] In the process of achieving a doping concentration of the first doping layer that is lower than the doping concentration of the second doping layer, a velvet structure is first prepared, and then the doping concentration of part of the first non-electrode area 101 is reduced by etching the first doping layer of the first non-electrode area 101. This process will destroy the texture structure of the first non-electrode area 101, but for the light trapping requirements of the solar cell, the first non-electrode area 101 on the light-receiving surface still needs to prepare a velvet structure that meets the structural requirements. Therefore, the second texture structure 103 and the third texture structure 112 are prepared in the secondary velveting process. The second texture structure 103 and the third texture structure 112 can be prepared in the same process step, simplifying the battery process steps, increasing production capacity, and saving production costs. In addition, the differentiated setting of the above-mentioned texture structure can reduce the degree of etching of the second non-electrode area 111 during the preparation process, reduce the weight loss of the solar cell due to etching during the preparation process, and ensure the mechanical strength of the solar cell.

[0113] The above-mentioned "secondary texturing treatment to form a second texture structure 103 on the first non-electrode area 101" is carried out after the step of "depositing a tunneling layer 3 and a doped conductive layer 4 on the edge area of ​​the first surface 10 and the second surface 11; forming a second doped oxide layer on the doped conductive layer 4". At this time, the surface difference between the edge area close to the semiconductor substrate 1 and the middle area of ​​the semiconductor substrate 1 in the first non-electrode area 101 before texturing can be reduced, thereby reducing the difference in the second texture structure 103 formed on the first non-electrode area 101 after texturing.

[0114] As a possible implementation, see Figure 1 Since the alkaline agent corrodes downward the semiconductor substrate 1 located in the second non-electrode area 111, a portion of the semiconductor substrate 1 located in the second non-electrode area 111 is corroded and removed. At this time, along the thickness direction A of the semiconductor substrate, the top surface of the second non-electrode area 111 is higher than the top surface of the second electrode area 110.

[0115] In some embodiments, along the thickness direction of the semiconductor substrate 1, a distance L2 between the top surface of the second electrode region 110 and the top surface of the second non-electrode region 111 is greater than or equal to 2 μm and less than or equal to 6 μm. For example, the distance L2 between the top surface of the second electrode region 110 and the top surface of the second non-electrode region 111 can be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, or 6 μm, etc.

[0116] It should be noted that the top surface of the second non-electrode area 111 is composed of the vertices of multiple third texture structures 112. Based on the different sizes of different third texture structures 112, the top surface of the second non-electrode area 111 here is a plane formed by the vertices of most third texture structures 112 on the second non-electrode area 111. The proportion of most third texture structures 112 in the second non-electrode area 111 can be flexibly selected according to actual conditions.

[0117] As a possible implementation method, the secondary texturing treatment includes: placing the semiconductor substrate 1 after the first laser and second laser irradiation processes into the first etching groove for secondary texturing treatment. The first etching groove contains an alkaline solution and a texturing additive, the temperature of the first etching groove is 60°C to 85°C, the concentration of the alkaline solution is 0.2% to 6%, and the time of the secondary texturing treatment is 2 minutes to 8 minutes. Exemplarily, the temperature of the first etching groove can be 60°C, 65°C, 70°C, 75°C, 80°C, 82°C or 85°C. The concentration of the alkaline solution can be 0.2%, 1%, 1.2%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, 5.5% or 6%. The time of the secondary texturing treatment can be 2 minutes, 2.5 minutes, 3 minutes, 3.5 minutes, 4 minutes, 4.5 minutes, 5 minutes, 5.5 minutes, 6 minutes, 6.5 minutes, 7 minutes, 7.5 minutes or 8 minutes. It should be noted that the time for the above-mentioned secondary texturing treatment includes the time for cleaning the semiconductor substrate 1 and the time for etching the semiconductor substrate 1 .

[0118] In an alternative approach, see Figure 1 The first texture structure 102, the second texture structure 103 or the third texture structure 112 is a pyramid structure. The size description of the first texture structure 102 and the second texture structure 103 can be found in the first aspect and will not be repeated here.

[0119] As a possible implementation, see Figure 1 When forming the second texture structure 103 , the alkaline texturing formula etches downward the semiconductor substrate 1 located in the first non-electrode area 101 . At this time, along the thickness direction A of the semiconductor substrate 1 , the first electrode area 100 is higher than the first non-electrode area 101 .

[0120] In some embodiments, along the thickness direction of the semiconductor substrate 1 , the distance between the first electrode region 100 and the first non-electrode region 101 is greater than or equal to 2 μm and less than or equal to 7 μm. Figure 1The distance L1 between the first electrode region 100 and the first non-electrode region 101 may be the distance between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the top surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101. Exemplarily, the distance L1 between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101 may be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, or 7 μm, etc.

[0121] It is worth noting that the top surface of the first electrode region 100 is composed of the vertices of multiple first texture structures 102. Due to the different sizes of different first texture structures 102, the top surface here is the plane formed by the vertices of the majority of the first texture structures 102 on the first electrode region 100. The proportion of the majority of the first texture structures 102 in the first electrode region 100 can be flexibly selected according to actual conditions. Similarly, the top surface of the first non-electrode region 101 is composed of the vertices of multiple second texture structures 103.

[0122] Next, see Figure 1 A passivation layer 5 is formed on the doped conductive layer 4 and the first surface 10 and the second surface 11 of the semiconductor substrate 1 .

[0123] The material and thickness of the passivation layer 5 can be set according to actual conditions and are not specifically limited here. For example, the material of the passivation layer 5 can include one or more of silicon nitride, hydrogenated silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, zinc oxide, and hafnium dioxide.

[0124] As a possible implementation, the passivation layer 5 may be a stack of multiple films, for example, a stack of an aluminum oxide layer and a silicon nitride layer.

[0125] In some embodiments, an aluminum oxide passivation layer 50 is grown on the doped conductive layer 4 and on the first and second surfaces 10 and 11 of the semiconductor substrate 1 using atomic layer deposition, and then a silicon nitride passivation layer 51 is deposited on the aluminum oxide passivation layer 50 located on the doped conductive layer 4 and on the first and second surfaces 10 and 11 using plasma enhanced chemical vapor deposition (PECVD) equipment.

[0126] The passivation layer 5 can passivate the surface of the semiconductor substrate 1, reduce surface recombination, and improve the open circuit voltage and fill factor. At the same time, the silicon nitride passivation layer 51 can protect the semiconductor substrate 1 and reduce pollution and mechanical damage.

[0127] Next, electrodes are formed on the passivation layer 5, with the electrodes being located in the first electrode region 100 and the second electrode region 110. Specifically, a first electrode 6 is formed in the first electrode region 100 of the first side 10 of the semiconductor substrate 1, and a second electrode 7 is formed in the second electrode region 110 of the second side 11 of the semiconductor substrate 1, using a printing device.

[0128] For example, the semiconductor substrate 1 is metallized, and electrodes are formed using methods such as screen printing or electroplating. The paste used to make the first electrode 6 and the second electrode 7 can be a silver alloy, a silver-copper alloy, a copper alloy, a nickel alloy, or the like. The paste is solidified through a low-temperature sintering process, and then light injection is used to enhance hydrogen passivation. Finally, laser-assisted contact formation (LECO) is used to form a good ohmic contact, completing the production of the solar cell.

[0129] In summary, compared with the prior art, the solar cell manufacturing method provided by the present application has a shorter process flow, achieves the same effect, and improves the feasibility of mass production.

[0130] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0131] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A solar cell, characterized in that: include: The semiconductor substrate comprises a first surface and a second surface opposite to each other; the first surface comprises a first electrode region and a first non-electrode region; a first doping layer, disposed in the first electrode region; a second doping layer, disposed in the first non-electrode region; the doping concentration of the first doping layer is greater than the doping concentration of the second doping layer; The surface of the first electrode area has a first texture structure, and the first non-electrode area has a second texture structure; the second surface includes a second electrode area and a second non-electrode area; the second non-electrode area has a third texture structure, and the dimensional consistency of the second texture structure is greater than the dimensional consistency of the third texture structure.

2. The solar cell according to claim 1, wherein The size consistency of the first texture structure is greater than the size consistency of the third texture structure.

3. The solar cell according to claim 1, wherein The first texture structure, the second texture structure or the third texture structure is a pyramid structure.

4. The solar cell according to claim 1, wherein Along the thickness direction of the semiconductor substrate, the first electrode region is higher than the first non-electrode region; The distance between the first electrode area and the first non-electrode area is greater than or equal to 2 μm and less than or equal to 7 μm.

5. The solar cell according to claim 1, wherein The reflectivity of the first electrode region where the first texture structure is located is greater than the reflectivity of the first non-electrode region where the second texture structure is located.

6. The solar cell according to claim 1, wherein The first electrode region and / or the second electrode region includes a collector electrode region and a bus electrode region, the extension direction of the collector electrode region is inconsistent with the extension direction of the bus electrode region; the width of the bus electrode region is greater than the width of the collector electrode region.

7. The solar cell according to claim 1, wherein Along the thickness direction of the semiconductor substrate, a projection of the first non-electrode area on the second surface and a projection of the second non-electrode area on the second surface at least partially overlap.

8. The solar cell according to claim 1, wherein Along the thickness direction of the semiconductor substrate, the second non-electrode area is higher than the second electrode area; A distance between the second electrode region and the second non-electrode region is greater than or equal to 2 μm and less than or equal to 6 μm.

9. A photovoltaic module, characterized in that: The photovoltaic module comprises: A battery string, comprising a plurality of interconnecting members and a plurality of solar cells according to any one of claims 1 to 8; the interconnecting members are used to connect the plurality of solar cells in series to form the battery string; The encapsulation layer is used to cover the surface of the battery string.

10. A method for manufacturing a solar cell, characterized in that: include: providing a semiconductor substrate; The semiconductor substrate has a first surface and a second surface opposite to each other; the first surface and the second surface are subjected to a texturing process to form a first texture structure; the first surface includes a first electrode area and a first non-electrode area, and the second surface includes a second electrode area and a second non-electrode area; Performing a diffusion process on the first surface of the semiconductor substrate to form a first doped layer and a first doped oxide layer formed on the first doped layer; Depositing a tunneling layer and a doped conductive layer on the edge region of the first surface and the second surface; forming a second doped oxide layer on the doped conductive layer; Using a first laser to irradiate the first doped oxide layer and the first doped layer located on the first non-electrode region, and irradiate the second doped oxide layer, the doped conductive layer, and the tunneling layer located on the edge region of the first non-electrode region; irradiating the second doped oxide layer, the doped conductive layer and the tunneling layer on the second non-electrode region with a second laser; After the first laser and second laser irradiation processes, a secondary texturing process is performed to form a second texture structure on the first non-electrode area and a third texture structure on the second non-electrode area; the size consistency of the second texture structure is greater than the size consistency of the third texture structure.

11. The method for manufacturing a solar cell according to claim 10, wherein: The power of the first laser is 1W to 50W, and the scanning speed of the first laser is 5m / s to 40m / s; The power of the second laser is 1W to 50W, and the scanning speed of the second laser is 5m / s to 40m / s; The first laser and the second laser have different powers and scanning speeds.

12. The method for manufacturing a solar cell according to claim 10, wherein: The secondary texturing process includes: placing the semiconductor substrate after the first laser and second laser irradiation processes into a first etching groove for secondary texturing treatment; The first etching tank contains an alkaline solution and a texturing additive. The temperature of the first etching tank is 60° C. to 85° C., the concentration of the alkaline solution is 0.2% to 6%, and the time of the secondary texturing treatment is 2 minutes to 8 minutes.

13. The method for manufacturing a solar cell according to claim 10, wherein: After the first laser and second laser irradiation processes, a secondary texturing process is performed to form a second texture structure on the first non-electrode area, and after a third texture structure is formed on the second non-electrode area, the method for manufacturing a solar cell further includes: forming a passivation layer on the doped conductive layer and on the first and second surfaces of the semiconductor substrate; Electrodes are formed on the passivation layer, and the electrodes are respectively located in the first electrode region and the second electrode region.

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