Epitaxial structure, manufacturing method, thickness design method, LED chip and display device

Abstract

The invention provides an epitaxial structure, a manufacturing method, a thickness design method, an LED chip and a display device. The epitaxial structure comprises a substrate, a stress compensation layer and an epitaxial lamination layer, the substrate comprises one of a sapphire substrate, a silicon substrate and a silicon carbide substrate, the stress compensation layer is arranged on the surface of one side of the substrate, the epitaxial lamination layer comprises a GaN material layer and an I nGaN material layer, the epitaxial lamination layer and the stress compensation layer are located on the same side of the substrate, and the I nGaN material layer is arranged on the surface of the other side of the substrate. Or the epitaxial lamination layer and the stress compensation layer are respectively positioned on two opposite sides of the substrate. According to the epitaxial structure, stress compensation layers with different thermal expansion coefficients are correspondingly arranged aiming at the three conditions that the substrate is a sapphire substrate, a silicon substrate and a silicon carbide substrate, so that huge thermal stress generated in different temperature states due to huge thermal mismatch between the substrate and a GaN epitaxial layer can be effectively reduced; and the conditions of epitaxial wafer cracks, deformation, non-uniform in-layer temperature and poor photoelectric property uniformity caused by thermal stress are reduced, the stability and yield of the device are improved, and the service life of the device is prolonged.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more specifically, to an epitaxial structure and a manufacturing method, a thickness design method, an LED chip, and a display device. Background Art

[0002] Light-emitting diode chip (LED chip) is a PN junction electroluminescent light-emitting device. As a new generation of solid cold light source, it has the advantages of high electro-optical conversion efficiency, low energy consumption, long life, energy saving and environmental protection, and high reliability. It is widely used in indoor lighting, outdoor lighting, display technology, automobile lights, plant growth and other aspects.

[0003] GaN-based materials, due to their direct bandgap characteristics and efficient radiative recombination capabilities, have become the core light-emitting layer material for high-brightness light-emitting diodes (LEDs). Silicon, silicon carbide, and sapphire substrates, due to their respective advantages, have become the mainstream substrates for epitaxial growth of GaN-based materials. For epitaxial stacks comprising GaN and InGaN layers, the applicable process temperatures for the GaN and InGaN layers differ significantly, resulting in significant temperature fluctuations during epitaxial growth. However, the thermal expansion coefficients of silicon, silicon carbide, and sapphire substrates differ from those of the GaN-based epitaxial stack, resulting in a significant thermal mismatch between the substrate and the GaN-based epitaxial stack during epitaxial growth temperature fluctuations. This thermal mismatch can induce compressive stress in the GaN-based epitaxial stack. For thicker GaN-based films, the compressive stress can increase to the point where cracks form in the GaN-based epitaxial stack and the substrate, seriously affecting device stability. Furthermore, the substrate and epitaxial stack undergo varying degrees of deformation, generating thermal stress. The presence of thermal stress in multilayer films not only affects the robustness of the connection between the epitaxial stack and the substrate, but also severely impacts the stability and lifespan of the device. Furthermore, this thermal stress can lead to significant warping during epitaxial growth, causing significant temperature variations within the epitaxial layers during growth, resulting in poor uniformity in optoelectronic performance within the layers. This can also complicate subsequent chip fabrication and reduce yield. Summary of the Invention

[0004] In view of this, the present invention provides an extension structure and a manufacturing method, a thickness design method, an LED chip and a display device, which can reduce the influence of thermal stress and improve the stability and yield of the device.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] Epitaxial structure comprising

[0007] a substrate comprising one of a sapphire substrate, a silicon substrate, and a silicon carbide substrate;

[0008] A stress compensation layer is provided on one side surface of the substrate; the thermal expansion coefficient of the stress compensation layer is D;

[0009] When the substrate is the sapphire substrate, D>A; the thermal expansion coefficient of the sapphire substrate is A;

[0010] When the substrate is the silicon substrate, D<B; the thermal expansion coefficient of the silicon substrate is B;

[0011] When the substrate is the silicon carbide substrate, D<C; the thermal expansion coefficient of the silicon carbide substrate is C;

[0012] an epitaxial stack comprising a GaN material layer and an InGaN material layer;

[0013] The epitaxial stack and the stress compensation layer are located on the same side of the substrate, or the epitaxial stack and the stress compensation layer are located on opposite sides of the substrate respectively;

[0014] When the epitaxial stack and the stress compensation layer are located on the same side of the substrate, the stress compensation layer is arranged between the epitaxial stack and the substrate, and the stress compensation layer is provided with a plurality of hollow regions.

[0015] Furthermore, when the substrate is a sapphire substrate, the material of the stress compensation layer includes one of a nickel-based alloy and a titanium-based alloy;

[0016] When the substrate is one of a silicon substrate and a silicon carbide substrate, the material of the stress compensation layer includes one of silicon dioxide, lithium ceramics, cordierite ceramics, and aluminum titanate ceramics.

[0017] Furthermore, when the stress compensation layer is provided with the hollow area, the hollow area divides the stress compensation layer into a plurality of stress compensation units;

[0018] The sidewall of each stress compensation unit is an inclined surface;

[0019] The angle formed by the sidewall of each stress compensation unit and the substrate is in the range of 30°-60°, including the end points.

[0020] Furthermore, the epitaxial stack includes an undoped gallium nitride layer, a first-type semiconductor layer, an active layer, and a second-type semiconductor layer sequentially arranged in a direction away from the substrate; the active layer includes an InGaN layer and a GaN layer.

[0021] Furthermore, the thermal stress σ of the substrate s Satisfies the following formula:

[0022]

[0023] σGaN is the stress exerted by the epitaxial stack on the substrate, σ scl the stress applied to the substrate by the stress compensation layer;

[0024] α GaN is the thermal expansion coefficient of GaN material, α s is the thermal expansion coefficient of the substrate, α scl is the thermal expansion coefficient of the stress compensation layer;

[0025] M GaN is the biaxial modulus of GaN material, M s is the biaxial modulus of the substrate, M scl is the biaxial modulus of the stress compensation layer; wherein the biaxial moduli of the GaN material, the substrate and the stress compensation layer all satisfy M=E / (1-υ), E is the elastic modulus of the corresponding material, and υ is the Poisson's ratio of the corresponding material;

[0026] h GaN is the thickness of the epitaxial stack, h s is the substrate thickness, h scl is the thickness of the stress compensation layer;

[0027] ΔT=T1-T2; T1 is the growth temperature of the undoped gallium nitride layer, and T2 is the growth temperature of InGaN in the active layer.

[0028] The present invention also provides a thickness design method for designing the thickness of a stress compensation layer in an epitaxial structure;

[0029] The epitaxial structure is any of the epitaxial structures described above, and the epitaxial stack comprises an undoped gallium nitride layer, a first-type semiconductor layer, an active layer, and a second-type semiconductor layer sequentially arranged in a direction away from the substrate; the active layer comprises an InGaN layer and a GaN layer;

[0030] The thermal stress σ of the substrate s Satisfies the following formula:

[0031]

[0032] σ GaN is the stress exerted by the epitaxial stack on the substrate, σ scl the stress applied to the substrate by the stress compensation layer;

[0033] α GaN is the thermal expansion coefficient of GaN material, α s is the thermal expansion coefficient of the substrate, α scl is the thermal expansion coefficient of the stress compensation layer;

[0034] M GaN is the biaxial modulus of GaN material, Ms is the biaxial modulus of the substrate, M scl is the biaxial modulus of the stress compensation layer; wherein the biaxial moduli of the GaN material, the substrate and the stress compensation layer all satisfy M=E / (1-υ), E is the elastic modulus of the corresponding material, and υ is the Poisson's ratio of the corresponding material;

[0035] h GaN is the thickness of the epitaxial stack, h s is the substrate thickness, h scl is the thickness of the stress compensation layer;

[0036] ΔT = T1 - T2; T1 is the growth temperature of the undoped GaN layer, and T2 is the growth temperature of InGaN in the active layer;

[0037] Get the biaxial modulus M of the substrate s , thickness h s and thermal expansion coefficient α s ;

[0038] Obtain the biaxial modulus M of GaN material GaN and thermal expansion coefficient α GaN ;

[0039] Get the thickness h of the epitaxial stack GaN ;

[0040] Get ΔT;

[0041] Obtain the biaxial modulus M of the stress compensation layer scl , thermal expansion coefficient α scl ;

[0042] The sum of the stresses on the substrate σ s is zero, and the thickness h of the stress compensation layer is obtained by the thermal stress relationship of the substrate scl .

[0043] The present invention also provides a method for manufacturing an epitaxial structure, comprising:

[0044] Providing a substrate; the substrate is one of a sapphire substrate, a silicon substrate and a silicon carbide substrate;

[0045] A stress compensation layer is grown on one surface of the substrate; the thermal expansion coefficient of the stress compensation layer is D;

[0046] When the substrate is the sapphire substrate, D>A; the thermal expansion coefficient of the sapphire substrate is A;

[0047] When the substrate is the silicon substrate, D<B; the thermal expansion coefficient of the silicon substrate is B;

[0048] When the substrate is the silicon carbide substrate, D<C; the thermal expansion coefficient of the silicon carbide substrate is C;

[0049] growing an epitaxial stack including a GaN material layer and an InGaN material layer; the epitaxial stack and the stress compensation layer are located on the same side of the substrate, or the epitaxial stack and the stress compensation layer are located on opposite sides of the substrate;

[0050] When the epitaxial stack and the stress compensation layer are located on the same side of the substrate, growing the stress compensation layer includes first growing a layer of stress compensation layer material and then patterning the stress compensation layer material so that the stress compensation layer forms a plurality of hollow areas; the stress compensation layer is arranged between the epitaxial stack and the substrate.

[0051] Furthermore, when the substrate is a sapphire substrate, the material of the stress compensation layer includes one of a nickel-based alloy and a titanium-based alloy;

[0052] When the substrate is one of a silicon substrate and a silicon carbide substrate, the material of the stress compensation layer includes one of silicon dioxide, lithium ceramics, cordierite ceramics, and aluminum titanate ceramics.

[0053] Furthermore, the epitaxial stack includes an undoped gallium nitride layer, a first-type semiconductor layer, an active layer, and a second-type semiconductor layer sequentially arranged in a direction away from the substrate; the active layer includes an InGaN layer and a GaN layer;

[0054] The thermal stress σ of the substrate s Satisfies the following formula:

[0055]

[0056] σ GaN is the stress exerted by the epitaxial stack on the substrate, σ scl the stress applied to the substrate by the stress compensation layer;

[0057] α GaN is the thermal expansion coefficient of GaN material, α s is the thermal expansion coefficient of the substrate, α scl is the thermal expansion coefficient of the stress compensation layer;

[0058] M GaN is the biaxial modulus of GaN material, M s is the biaxial modulus of the substrate, M scl is the biaxial modulus of the stress compensation layer; wherein the biaxial moduli of the GaN material, the substrate and the stress compensation layer all satisfy M=E / (1-υ), E is the elastic modulus of the corresponding material, and υ is the Poisson's ratio of the corresponding material;

[0059] h GaN is the thickness of the epitaxial stack, h s is the substrate thickness, h scl is the thickness of the stress compensation layer;

[0060] ΔT=T1-T2; T1 is the growth temperature of the undoped gallium nitride layer, and T2 is the growth temperature of InGaN in the active layer.

[0061] The present invention also provides an LED chip, which includes any of the above-mentioned epitaxial structures, a first electrode, and a second electrode.

[0062] The present invention also provides a display device, which includes the above-mentioned LED chip.

[0063] Compared with the existing technology, the technical solution provided by the present invention has at least the following advantages:

[0064] 1. The epitaxial structure includes a substrate, a stress-compensating layer, and an epitaxial stack. The substrate includes one of a sapphire substrate, a silicon substrate, and a silicon carbide substrate. The stress-compensating layer is provided on one surface of the substrate; the thermal expansion coefficient of the stress-compensating layer is D. When the substrate is a sapphire substrate, D>A; the thermal expansion coefficient of the sapphire substrate is A; when the substrate is a silicon substrate, D<B; the thermal expansion coefficient of the silicon substrate is B; when the substrate is a silicon carbide substrate, D<C; the thermal expansion coefficient of the silicon carbide substrate is C. The epitaxial stack includes a GaN material layer and an InGaN material layer. The epitaxial stack and the stress-compensating layer are located on the same side of the substrate, or the epitaxial stack and the stress-compensating layer are located on opposite sides of the substrate respectively; when the epitaxial stack and the stress-compensating layer are located on the same side of the substrate, the stress-compensating layer is provided between the epitaxial stack and the substrate, and the stress-compensating layer has a plurality of hollow regions.

[0065] Since the process temperatures applicable to the epitaxial GaN material layer and the InGaN material layer are quite different, the temperature changes greatly during the epitaxial growth process. However, the thermal expansion coefficients of silicon substrates, silicon carbide substrates, and sapphire substrates are different from those of the GaN-based epitaxial stack, which will cause the thermal mismatch between the substrate and the GaN-based epitaxial stack to be particularly prominent during the temperature change of epitaxial growth. This thermal mismatch will cause compressive stress in the GaN-based epitaxial stack. For thicker GaN-based films, the compressive stress will increase to the extent that cracks will appear in the GaN-based epitaxial stack and the substrate, seriously affecting the stability of the device. In addition, the substrate and the epitaxial stack will produce different degrees of deformation, thereby generating thermal stress. The presence of thermal stress in the multilayer film not only affects the firmness of the connection between the epitaxial stack and the substrate, but also seriously affects the stability and life of the device. In addition, due to the existence of this thermal stress, there will be very large warping during the epitaxial growth process, which will cause excessive temperature differences within the epitaxial layer during the growth period, resulting in poor uniformity of optoelectronic performance within the layer. It will also increase the difficulty of subsequent chip end manufacturing and reduce the manufacturing yield.

[0066] This epitaxial structure is designed for three substrates: sapphire substrate, silicon substrate and silicon carbide substrate. Corresponding stress compensation layers with different thermal expansion coefficients are set up respectively. This can effectively reduce the huge thermal stress generated under different temperature conditions due to the huge thermal mismatch between the substrate and the GaN epitaxial layer, as well as reduce the cracks, deformation, uneven temperature within the layer and poor uniformity of optoelectronic performance of the epitaxial wafer caused by thermal stress, thereby improving the stability, yield and life of the device.

[0067] When the epitaxial stack and the stress compensation layer are located on the same side of the substrate, the stress compensation layer is provided with a plurality of hollow regions, so that the epitaxial stack can grow from the hollow regions.

[0068] 2. When the substrate is a sapphire substrate, the material of the stress compensation layer includes one of a nickel-based alloy and a titanium-based alloy; it has good high temperature resistance and corrosion resistance, and does not react with the reaction chamber gas.

[0069] When the substrate is one of a silicon substrate and a silicon carbide substrate, the material of the stress compensation layer includes one of silicon dioxide, lithium ceramics, cordierite ceramics, and aluminum titanate ceramics; it has good high temperature resistance and corrosion resistance, and will not react with the reaction chamber gas.

[0070] 3. When the epitaxial structure is used as a light-emitting diode, the sidewalls of each stress-compensating unit are inclined, which can enhance total internal reflection and improve the device's light extraction efficiency. Setting the angle between the sidewalls of each stress-compensating layer and the substrate within a range of 30°-60° improves stress transfer, stress compensation, and improved light extraction efficiency. An angle less than 30° results in insufficient thickness on the inclined surface, impairing the stress compensation effect. An angle greater than 60° results in insufficient reflective surface, resulting in a poor improvement in device light extraction efficiency.

[0071] 4. According to the thermal stress σ of the substrate s The calculation formula can accurately adjust the thickness of the stress compensation layer according to the actual product size, material and growth temperature difference during the actual production of the epitaxial structure, thereby minimizing the thermal stress on the substrate and minimizing the impact of thermal stress. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0073] Figure 1 A schematic structural diagram of an embodiment of the epitaxial structure of the present application;

[0074] Figure 2 A schematic structural diagram of another embodiment of the epitaxial structure of the present application;

[0075] Figure 3 This is a schematic top view of the structure in which a stress compensation layer is provided on the substrate of the present application;

[0076] Figure 4 A schematic structural diagram of another embodiment of the epitaxial structure of the present application;

[0077] Figure 5 A schematic structural diagram of another embodiment of the epitaxial structure of the present application;

[0078] Figure 6 A schematic structural diagram of another embodiment of the epitaxial structure of the present application;

[0079] Figure 7 This is a schematic diagram of the structure of the LED chip of this application.

[0080] Reference numerals:

[0081] Substrate 1; stress compensation layer 2; hollow region 3; epitaxial stack 4; undoped gallium nitride layer 5; first-type semiconductor layer 6; active layer 7; second-type semiconductor layer 8; buffer layer 9; first superlattice layer 10; second superlattice layer 11; electron blocking layer 12; ohmic contact layer 13; first electrode 14; second electrode 15. DETAILED DESCRIPTION

[0082] To make the content of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0083] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0084] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, the three-dimensional dimensions of length, width, and depth should be included.

[0085] like Figure 1 、 2 As shown in FIG4 , the present application provides an epitaxial structure comprising a substrate 1 , a stress compensation layer 2 and an epitaxial stack 4 .

[0086] The substrate 1 includes one of a sapphire substrate, a silicon substrate and a silicon carbide substrate. The substrate 1 can be a planar substrate or a patterned substrate. Figure 1 The epitaxial structure of the substrate is shown as a planar substrate. Figure 2 The epitaxial structure in which the substrate is a patterned substrate is shown.

[0087] Stress compensation layer 2 is provided on one side surface of substrate 1. The thermal expansion coefficient of stress compensation layer 2 is D. When substrate 1 is a sapphire substrate, D>A; the thermal expansion coefficient of the sapphire substrate is A. When substrate 1 is a silicon substrate, D<B; the thermal expansion coefficient of the silicon substrate is B. When substrate 1 is a silicon carbide substrate, D<C; the thermal expansion coefficient of the silicon carbide substrate is C.

[0088] The epitaxial stack 4 includes a GaN material layer and an InGaN material layer. The epitaxial stack 4 and the stress compensation layer 2 are located on the same side of the substrate 1 (e.g. Figure 1 、 2 As shown), or the epitaxial stack 4 and the stress compensation layer 2 are respectively located on opposite sides of the substrate 1 (as shown Figure 4 When the epitaxial stack 4 and the stress compensation layer 2 are located on the same side of the substrate 1, the stress compensation layer 2 is provided between the epitaxial stack 4 and the substrate 1, and the stress compensation layer 2 is provided with a plurality of hollow regions 3, as shown in FIG. Figure 3 As shown. Since the process temperatures applicable to the GaN material layer and the InGaN material layer of the epitaxial stack 4 are quite different, the temperature changes greatly during the epitaxial growth process. However, the silicon substrate, silicon carbide substrate and sapphire substrate all have different thermal expansion coefficients from the GaN-based epitaxial stack 4, which will cause the thermal mismatch between the substrate 1 and the GaN-based epitaxial stack 4 to be particularly prominent during the temperature change of epitaxial growth. This thermal mismatch will cause compressive stress in the GaN-based epitaxial stack 4. For thicker GaN-based films, the compressive stress will increase to the extent that cracks will appear in the GaN-based epitaxial stack 4 and the substrate 1, seriously affecting the stability of the device; in addition, the substrate 1 and the epitaxial stack 4 will produce different degrees of deformation, thereby generating thermal stress. The presence of thermal stress in the multilayer film not only affects the firmness of the connection between the epitaxial stack 4 and the substrate 1, but also seriously affects the stability and life of the device. In addition, due to the existence of this thermal stress, there will be very large warping during the epitaxial growth process, which will cause excessive temperature differences within the epitaxial layer during the growth period, resulting in poor uniformity of optoelectronic performance within the layer. It will also increase the difficulty of subsequent chip end manufacturing and reduce the manufacturing yield.

[0089] This epitaxial structure is designed for three situations where the substrate 1 is a sapphire substrate, a silicon substrate, and a silicon carbide substrate, and stress compensation layers 2 with different thermal expansion coefficients are respectively provided. This can effectively reduce the huge thermal stress generated under different temperature conditions due to the huge thermal mismatch between the substrate 1 and the GaN epitaxial layer, as well as reduce the cracks, deformation, uneven temperature within the layer, and poor uniformity of the optoelectronic performance of the epitaxial wafer caused by thermal stress, thereby improving the stability, yield, and life of the device.

[0090] When the epitaxial stack 4 and the stress-compensating layer 2 are located on the same side of the substrate 1, the stress-compensating layer 2 is provided with a plurality of hollow regions 3, considering that the epitaxial stack 4 cannot be grown directly on the stress-compensating layer 2. This allows the epitaxial stack 4 to grow from the hollow regions 3. When the epitaxial stack 4 and the stress-compensating layer are located on opposite sides of the substrate 1, the stress-compensating layer 2 may not be provided with the hollow regions 3.

[0091] Based on any of the above embodiments, in a preferred embodiment, when substrate 1 is a sapphire substrate, the material of stress-compensating layer 2 includes one of a nickel-based alloy and a titanium-based alloy, which exhibits excellent high-temperature and corrosion resistance and is non-reactive with reaction chamber gases. When substrate 1 is a silicon substrate or a silicon carbide substrate, the material of stress-compensating layer 2 includes one of silicon dioxide, lithium ceramic, cordierite ceramic, and aluminum titanate ceramic, which exhibits excellent high-temperature and corrosion resistance and is non-reactive with reaction chamber gases.

[0092] Based on any of the above embodiments, in a preferred embodiment, when the stress compensation layer 2 is provided with a hollow region 3, the hollow region 3 divides the stress compensation layer 2 into a plurality of stress compensation units. The longitudinal cross-section of the stress compensation unit can be trapezoidal, rectangular, or triangular, etc., and this application does not impose any limitation.

[0093] Preferably, the sidewall of each stress compensation unit is an inclined surface. The angle formed between the sidewall of each stress compensation unit and the substrate 1 is in the range of 30° to 60°, including the end values; Figure 1 It shows that the longitudinal section of the stress compensation unit is a triangle, and the angle formed between the sidewall of the stress compensation unit and the substrate 1 is a, and the range of the angle a is 30°-60°.

[0094] When the epitaxial structure is used as a light-emitting diode, the sidewalls of each stress-compensating unit are inclined, which can enhance total internal reflection and improve the device's light extraction efficiency. Setting the angle between the sidewalls of each stress-compensating layer 2 and the substrate 1 within a range of 30°-60° improves stress transfer, stress compensation, and improved light extraction efficiency. An angle less than 30° results in insufficient thickness on the inclined surface, impairing the stress compensation effect. An angle greater than 60° results in insufficient reflective surface, resulting in a poor improvement in device light extraction efficiency.

[0095] Based on any of the above embodiments, in a preferred embodiment, if Figure 5 As shown, the epitaxial stack 4 includes an undoped gallium nitride layer 5, a first-type semiconductor layer 6, an active layer 7, and a second-type semiconductor layer 8, arranged in sequence along a direction away from the substrate 1. The active layer 7 includes an InGaN layer and a GaN layer. One of the first-type semiconductor layer 6 and the second-type semiconductor layer 8 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. This application uses the example of the first-type semiconductor layer 6 being an N-type semiconductor layer and the second-type semiconductor layer 8 being a P-type semiconductor layer. N-type semiconductor layers include, but are not limited to, N-GaN, and P-type semiconductor layers include, but are not limited to, P-GaN.

[0096] Optionally, the thickness of the undoped gallium nitride layer 5 is 1 μm-4 μm, including the end value; the thickness of the first type semiconductor layer 6 is 1 μm-3 μm (including the end value), and the N-type doping concentration is 1E18 / cm 3 -1E20 / cm3 (including endpoint values); the thickness of the second semiconductor layer 8 is 10nm-300nm including endpoint values, and the P-type doping concentration is 5E18 / cm 3 -1E20 / cm 3 , including endpoint values. The thickness of the InGaN layer in the active layer 7 is 1nm-5nm (including endpoint values), the In composition is 0.1-0.25 (including endpoint values), the thickness of the GaN layer is 5nm-15nm (including endpoint values), and the N-type doping concentration is 0-5E17 / cm 3 (Inclusive of endpoint values).

[0097] Based on any of the above embodiments, in a preferred embodiment, the thermal stress σ of the substrate 1 is s Satisfies the following formula:

[0098]

[0099] σ GaN is the stress applied by the epitaxial stack 4 to the substrate 1, σ scl The stress applied to the substrate 1 by the stress compensation layer 2;

[0100] α GaN is the thermal expansion coefficient of GaN material, α s is the thermal expansion coefficient of substrate 1, α scl is the thermal expansion coefficient of the stress compensation layer 2;

[0101] M GaN is the biaxial modulus of GaN material, M s is the biaxial modulus of substrate 1, M scl is the biaxial modulus of the stress compensation layer 2; wherein the biaxial moduli of the GaN material, the substrate 1 and the stress compensation layer 2 all satisfy M=E / (1-υ), E is the elastic modulus of the corresponding material, and υ is the Poisson's ratio of the corresponding material;

[0102] h GaN is the thickness of the epitaxial stack 4, h s is the thickness of substrate 1, h scl is the thickness of the stress compensation layer 2;

[0103] ΔT=T1−T2; T1 is the growth temperature of the undoped gallium nitride layer 5 , and T2 is the growth temperature of InGaN in the active layer 7 .

[0104] It should be understood that since the thickness of the GaN material accounts for a large proportion of the total thickness of the epitaxial stack 4, the thermal expansion coefficient and biaxial modulus of the GaN material are included in the above thermal stress formula for the epitaxial stack 4.

[0105] According to the thermal stress σ of the substrate 1s The calculation formula can accurately adjust the thickness of the stress compensation layer 2 according to the size, material and growth temperature difference of the actual product during the actual production of the epitaxial structure, thereby minimizing the thermal stress on the substrate 1 and minimizing the impact of the thermal stress.

[0106] Based on the above embodiments, in a preferred embodiment, as Figure 6 As shown, the epitaxial stack 4 further includes a buffer layer 9. The buffer layer 9 is disposed between the substrate 1 and the undoped gallium nitride layer 5. Optionally, the buffer layer 9 has a thickness of 10 nm to 100 nm, inclusive. The buffer layer 9 may be made of, but is not limited to, AlN. Suitable materials may be selected based on specific needs.

[0107] Based on any of the above embodiments, in a preferred embodiment, if Figure 6 As shown, the epitaxial stack 4 also includes a first superlattice layer 10, and the first superlattice layer 10 is located between the first-type semiconductor layer 6 and the active layer 7. Optionally, the first superlattice layer 10 includes a narrow-well wide-barrier InGaN / GaN superlattice layer, but is not limited thereto. Suitable materials can be selected as needed. Optionally, in the narrow-well wide-barrier InGaN / GaN superlattice layer, the InGaN layer has a thickness of 1nm-10nm (including endpoint values), an In component value of 0.01-0.2, including endpoint values, a GaN layer thickness of 5nm-100nm, including endpoint values, and an N-type doping concentration of 0-5E17 / cm 3 (Inclusive of endpoint values).

[0108] Based on any of the above embodiments, in a preferred embodiment, if Figure 6 As shown, the epitaxial stack 4 also includes a second superlattice layer 11. The second superlattice layer 11 is located between the first superlattice layer 10 and the active layer 7. Optionally, the second superlattice layer 11 includes a narrow-well narrow-barrier InGaN / GaN superlattice layer but is not limited thereto, and a suitable material can be selected according to requirements. Optionally, the thickness of the InGaN layer in the narrow-well narrow-barrier InGaN / GaN superlattice layer is 1nm-5nm (including endpoint values), the In component is 0.05-0.1 (including endpoint values), the thickness of the GaN layer is 1nm-20nm (including endpoint values), and the N-type doping concentration is 0-5E17 / cm 3 (Inclusive of endpoint values).

[0109] Based on any of the above embodiments, in a preferred embodiment, if Figure 6As shown, the epitaxial stack 4 further includes an electron blocking layer 12, which is located between the active layer 7 and the second-type semiconductor layer 8. Optionally, the material of the electron blocking layer 12 includes AlGaN, but is not limited thereto, and a suitable material can be selected according to requirements. Optionally, the Al component of the AlGaN electron blocking layer 12 is 0.05-0.3 (including endpoint values), the thickness is 5nm-100nm including endpoint values, and the P-type doping concentration is 1E18 / cm 3 -1E20 / cm 3 (Inclusive of endpoint values).

[0110] Based on any of the above embodiments, in a preferred embodiment, if Figure 6 As shown, the epitaxial stack 4 further includes an ohmic contact layer 13, which is located on the surface of the second-type semiconductor layer 8 facing away from the substrate 1. Optionally, the material of the ohmic contact layer 13 includes P-GaN, but is not limited thereto, and a suitable material can be selected according to requirements. Optionally, the P-type doping concentration of the ohmic contact layer 13 is 1E19 / cm 3 -1E20 / cm 3 (Inclusive of endpoint values).

[0111] When the substrate 1 is a sapphire substrate 1, the thermal stress principle of the epitaxial structure is explained by taking the epitaxial structure and the stress compensation layer 2 being arranged on the same side of the substrate 1 as an example:

[0112] During the growth process, when the temperature of the graphite disk carrier rises to 1100°C, conventional substrates experience compressive stress due to the temperature difference between the upper and lower surfaces, resulting in a concave warpage of -50 to -200 μm. In this embodiment, due to the presence of stress-compensating layer 2, the upper stress-compensating layer 2 has a greater thermal expansion coefficient than the underlying sapphire substrate 1. Therefore, the sapphire substrate 1 is also subjected to tensile stress from the stress-compensating layer 2. This allows the entire epitaxial layer to remain flat even at 1100°C, thereby ensuring temperature uniformity within the wafer. When the underlying GaN epitaxial layer is grown and the temperature is lowered by 400-500°C to grow InGaN, the conventional substrate experiences a decrease in compressive stress due to the temperature difference between the upper and lower surfaces. Simultaneously, the GaN epitaxial layer exerts significant tensile stress on the substrate, resulting in a balanced or tensile stress on the substrate. This process causes the substrate 1 to warp from concave to flat, or even convex. This high-temperature-temperature transition, resulting in epitaxial wafer warpage, is difficult to overcome using conventional MOCVD technology. Because of the presence of stress-compensating layer 2, which has a higher coefficient of thermal expansion, the upper surface of the stress-compensating layer 2 contracts faster than the lower surface of the sapphire substrate 1 during cooling, thereby imparting a compressive stress to the sapphire substrate 1. When these three stresses reach equilibrium, the overall stress of the epitaxial layer remains constant at zero during transitions between high and low temperatures, resulting in no warping throughout the epitaxial growth process. Specifically, the thickness of the stress-compensating layer can be precisely adjusted using the aforementioned substrate thermal stress formula to achieve no noticeable warping throughout the entire epitaxial growth process.

[0113] When the substrate 1 is a silicon substrate or a silicon carbide substrate, the thermal stress principle of the epitaxial structure is explained by taking the example of the epitaxial structure and the stress compensation layer 2 being arranged on the same side of the substrate 1:

[0114] During the growth process, when the temperature of the graphite disk carrier rises to 1100°C, the bottom layer GaN growth is completed, and then the temperature is lowered by 400-500°C to grow InGaN. Since the thermal expansion coefficient of the silicon substrate 1 is smaller, the GaN epitaxial layer will exert huge compressive stress on the substrate 1, causing the substrate 1 to warp and become concave significantly. However, in order to ensure the uniformity of the wavelength within the plane of the InGaN growth stage, the substrate 1 needs to remain in a basically warp-free state during the growth process. Therefore, during the bottom layer growth stage, the substrate 1 needs to show a significant convex state. This convex state will lead to poor temperature uniformity within the wafer, resulting in differences in the epitaxial quality of different areas, which in turn affects the reliability and life of the material. Traditional MOCVD technology cannot overcome this problem of epitaxial wafer warping caused by high and low temperature transitions.

[0115] In this embodiment, due to the presence of the stress-compensating layer 2, which has a smaller coefficient of thermal expansion, the upper surface of the stress-compensating layer 2 contracts more slowly than the lower surface of the silicon substrate 1 during cooling, thereby imparting a tensile stress to the silicon substrate 1. When the compressive and tensile stresses reach equilibrium, the overall stress in the epitaxial layer remains constant at zero, and no noticeable warping occurs during the entire epitaxial growth process. Specifically, the thickness of the stress-compensating layer can be precisely adjusted using the aforementioned substrate thermal stress formula to achieve a warpage-free state throughout the entire epitaxial growth process.

[0116] The present application also provides a thickness design method for designing the thickness of a stress-compensating layer 2 in an epitaxial structure. The epitaxial structure is the epitaxial structure of any of the above embodiments, and the epitaxial stack 4 includes an undoped gallium nitride layer 5, a first-type semiconductor layer 6, an active layer 7, and a second-type semiconductor layer 8, sequentially arranged in a direction away from the substrate 1; the active layer 7 includes an InGaN layer and a GaN layer.

[0117] Thermal stress σ of substrate 1 s Satisfies the following formula:

[0118]

[0119] σ GaN is the stress applied by the epitaxial stack 4 to the substrate 1, σ scl The stress applied to the substrate 1 by the stress compensation layer 2;

[0120] α GaN is the thermal expansion coefficient of GaN material, α s is the thermal expansion coefficient of substrate 1, α scl is the thermal expansion coefficient of the stress compensation layer 2;

[0121] M GaN is the biaxial modulus of GaN material, M s is the biaxial modulus of substrate 1, M scl is the biaxial modulus of the stress compensation layer 2; wherein the biaxial moduli of the GaN material, the substrate 1 and the stress compensation layer 2 all satisfy M=E / (1-υ), E is the elastic modulus of the corresponding material, and υ is the Poisson's ratio of the corresponding material;

[0122] h GaN is the thickness of the epitaxial stack 4, h s is the thickness of substrate 1, h scl is the thickness of the stress compensation layer 2;

[0123] ΔT=T1-T2; T1 is the growth temperature of the undoped gallium nitride layer 5, and T2 is the growth temperature of InGaN in the active layer 7;

[0124] Obtain the biaxial modulus M of substrate 1 s, thickness h s and thermal expansion coefficient α s ;

[0125] Obtain the biaxial modulus M of GaN material GaN and thermal expansion coefficient α GaN ;

[0126] Get the thickness h of the epitaxial stack 4 GaN ;

[0127] Get ΔT;

[0128] Obtain the biaxial modulus M of the stress compensation layer 2 scl , thermal expansion coefficient α scl ;

[0129] The sum of the stresses on substrate 1 is σ s is zero, and the thickness h of the stress compensation layer 2 is obtained by the thermal stress relationship of the substrate scl .

[0130] Among them, h GaN 、h s 、h scl and ΔT can be obtained based on the growth process parameters of the actual product.

[0131] Through this thickness design method, in the actual process of manufacturing the epitaxial structure, the thickness of the stress compensation layer 2 can be accurately adjusted according to the size, material and growth temperature difference of the actual product, so as to minimize the thermal stress on the substrate 1 and minimize the impact of thermal stress.

[0132] This application also provides a method for manufacturing an epitaxial structure, comprising the following steps:

[0133] S01: providing a substrate 1; the substrate 1 is one of a sapphire substrate 1, a silicon substrate 1 and a silicon carbide substrate 1.

[0134] S02: A stress-compensating layer is grown on one surface of substrate 1. The thermal expansion coefficient of stress-compensating layer 2 is D. When substrate 1 is a sapphire substrate, D>A; the thermal expansion coefficient of sapphire substrate 1 is A. When substrate 1 is a silicon substrate, D<B; the thermal expansion coefficient of silicon substrate is B. When substrate 1 is a silicon carbide substrate, D<C; the thermal expansion coefficient of silicon carbide substrate 1 is C. Alternatively, the stress-compensating layer can be grown using methods such as physical evaporation or chemical vapor deposition. After the stress-compensating layer is grown, post-processing steps such as cleaning and passivation can be performed to ensure the stability and reliability of stress-compensating layer 2.

[0135] S03: growing an epitaxial stack 4 including a GaN material layer and an InGaN material layer; the epitaxial stack 4 and the stress compensation layer 2 are located on the same side of the substrate 1 (eg Figure 1 、2 As shown), or the epitaxial stack 4 and the stress compensation layer 2 are respectively located on opposite sides of the substrate 1 (as shown Figure 4 shown).

[0136] like Figure 1-3 As shown, when the epitaxial stack 4 and the stress compensation layer 2 are located on the same side of the substrate 1, growing the stress compensation layer 2 includes first growing a layer of stress compensation layer 2 material, and then patterning the stress compensation layer 2 so that the stress compensation layer 2 forms a plurality of hollow regions 3; the stress compensation layer 2 is arranged between the epitaxial stack 4 and the substrate 1.

[0137] Based on the above embodiment, in a preferred embodiment, when substrate 1 is a sapphire substrate, the material of stress-compensating layer 2 includes one of a nickel-based alloy and a titanium-based alloy. When substrate 1 is one of a silicon substrate and a silicon carbide substrate, the material of stress-compensating layer 2 includes one of silicon dioxide, lithium ceramic, cordierite ceramic, and aluminum titanate ceramic.

[0138] Based on any of the above embodiments, in a preferred embodiment, Figure 5 As shown, the epitaxial stack 4 includes an undoped gallium nitride layer 5, a first-type semiconductor layer 6, an active layer 7, and a second-type semiconductor layer 8, arranged in sequence along a direction away from the substrate 1. The active layer 7 includes an InGaN layer and a GaN layer. One of the first-type semiconductor layer 6 and the second-type semiconductor layer 8 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. This application uses the example of the first-type semiconductor layer 6 being an N-type semiconductor layer and the second-type semiconductor layer 8 being a P-type semiconductor layer. N-type semiconductor layers include, but are not limited to, N-GaN, and P-type semiconductor layers include, but are not limited to, P-GaN.

[0139] Optionally, the thickness of the undoped gallium nitride layer 5 is 1 μm-4 μm, including the end value; the growth temperature is 1000° C.-1150° C., including the end value. The thickness of the first type semiconductor layer 6 is 1 μm-3 μm, including the end value, and the N-type doping concentration is 1E18 / cm 3 -1E20 / cm 3 , including the endpoint value; the growth temperature is 1000℃-1150℃, including the endpoint value. The thickness of the second type semiconductor layer 8 is 10nm-300nm including the endpoint value, and the P-type doping concentration is 5E18 / cm 3 -1E20 / cm 3 , including the endpoint values; the growth temperature is 900°C-100°C, including the endpoint values. The thickness of the InGaN layer in the active layer 7 is 1nm-5nm (including the endpoint values), the In composition is 0.1-0.25 (including the endpoint values), and the growth temperature is 700°C-800°C (including the endpoint values); the thickness of the GaN layer is 5nm-15nm (including the endpoint values), and the N-type doping concentration is 0-5E17 / cm3 (including endpoint values), and the growth temperature is 800° C.-900° C. (including endpoint values).

[0140] Based on the above embodiment, in a preferred embodiment, the thermal stress σ of the substrate 1 s Satisfies the following formula:

[0141]

[0142] σ GaN is the stress applied by the epitaxial stack 4 to the substrate 1, σ scl The stress applied to the substrate 1 by the stress compensation layer 2;

[0143] α GaN is the thermal expansion coefficient of GaN material, α s is the thermal expansion coefficient of substrate 1, α scl is the thermal expansion coefficient of the stress compensation layer 2;

[0144] M GaN is the biaxial modulus of GaN material, M s is the biaxial modulus of substrate 1, M scl is the biaxial modulus of the stress compensation layer 2; wherein the biaxial moduli of the GaN material, the substrate 1 and the stress compensation layer 2 all satisfy M=E / (1-υ), E is the elastic modulus of the corresponding material, and υ is the Poisson's ratio of the corresponding material;

[0145] h GaN is the thickness of the epitaxial stack 4, h s is the thickness of substrate 1, h scl is the thickness of the stress compensation layer 2;

[0146] ΔT=T1−T2; T1 is the growth temperature of the undoped gallium nitride layer 5 , and T2 is the growth temperature of InGaN in the active layer 7 .

[0147] In a preferred embodiment based on any of the above embodiments, when the stress compensation layer 2 is provided with a hollow region 3, the hollow region 3 divides the stress compensation layer 2 into a plurality of stress compensation units. The longitudinal cross-section of the stress compensation unit can be trapezoidal, rectangular, or triangular, etc., which is not limited in this application.

[0148] Preferably, the sidewall of each stress compensation unit is an inclined surface, and the angle formed between the sidewall of each stress compensation unit and the substrate 1 is in the range of 30° to 60°, including the end values.

[0149] Based on the above embodiment, in a preferred embodiment, Figure 6As shown, the epitaxial stack 4 further includes a buffer layer 9. The buffer layer 9 is disposed between the substrate 1 and the undoped gallium nitride layer 5. Optionally, the buffer layer 9 has a thickness of 10 nm to 100 nm, inclusive, and a growth temperature of 400°C to 700°C, inclusive. The buffer layer can be made of, but is not limited to, AlN. Suitable materials can be selected based on requirements.

[0150] Based on any of the above embodiments, in a preferred embodiment, Figure 6 As shown, the epitaxial stack 4 also includes a first superlattice layer 10, and the first superlattice layer 10 is located between the first-type semiconductor layer 6 and the active layer 7. Optionally, the first superlattice layer 10 includes a narrow-well wide-barrier InGaN / GaN superlattice layer, but is not limited thereto. Suitable materials can be selected as needed. Optionally, the growth temperature of the narrow-well wide-barrier InGaN / GaN superlattice layer is 850°C-950°C (including endpoint values), the thickness of the InGaN layer is 1nm-10nm (including endpoint values), and the In component is 0.01-0.2 (including endpoint values); the thickness of the GaN layer is 5nm-100nm (including endpoint values), and the N-type doping concentration is 0-5E17 / cm 3 (Inclusive of endpoint values).

[0151] Based on any of the above embodiments, in a preferred embodiment, Figure 6 As shown, the epitaxial stack 4 also includes a second superlattice layer 11. The second superlattice layer 11 is located between the first superlattice layer 10 and the active layer 7. Optionally, the second superlattice layer 11 includes a narrow-well narrow-barrier InGaN / GaN superlattice layer but is not limited thereto, and a suitable material can be selected according to requirements. Optionally, the growth temperature of the narrow-well narrow-barrier InGaN / GaN superlattice layer is 800°C-900°C (including endpoint values), the thickness of the InGaN layer is 1nm-5nm (including endpoint values), the In component is 0.05-0.1 (including endpoint values), the thickness of the GaN layer is 1nm-20nm (including endpoint values), and the N-type doping concentration is 0-5E17 / cm 3 (Inclusive of endpoint values).

[0152] Based on any of the above embodiments, in a preferred embodiment, Figure 6 As shown, the epitaxial stack 4 further includes an electron blocking layer 12, which is located between the active layer 7 and the second-type semiconductor layer 8. Optionally, the material of the electron blocking layer 12 includes AlGaN, but is not limited thereto, and a suitable material can be selected according to requirements. Optionally, the AlGaN electron blocking layer 12 has an Al component of 0.05-0.3 (including endpoint values), a thickness of 5nm-100nm (including endpoint values), and a P-type doping concentration of 1E18 / cm 3 -1E20 / cm 3(including endpoint values), and the growth temperature is 900-1000° C. (including endpoint values).

[0153] Based on any of the above embodiments, in a preferred embodiment, Figure 6 As shown, the epitaxial stack 4 further includes an ohmic contact layer 13, which is located on the surface of the second-type semiconductor layer 8 facing away from the substrate 1. Optionally, the material of the ohmic contact layer 13 includes P-GaN, but is not limited thereto, and a suitable material can be selected according to requirements. Optionally, the P-type doping concentration of the ohmic contact layer 13 is 1E19 / cm 3 -1E20 / cm 3 (including endpoint values), and the growth temperature is 900° C.-1000° C. (including endpoint values).

[0154] The method for fabricating an epitaxial structure provided in this application can be used to fabricate the epitaxial structure of any of the above-mentioned embodiments, and thus has all the beneficial effects of the epitaxial structure of any of the above-mentioned embodiments, which will not be described in detail here. Any portion not mentioned in the method for fabricating an epitaxial structure can be configured with reference to the epitaxial structure of any of the above-mentioned embodiments.

[0155] This application also provides LED chips, such as Figure 7 As shown, it includes the epitaxial structure of any of the above-mentioned embodiments, the first electrode 14, and the second electrode 15. Optionally, the epitaxial structure is provided with a groove and a mesa. The groove exposes a portion of the surface of the first-type semiconductor layer 6. The first electrode 14 is provided in the groove and electrically connected to the first-type semiconductor layer 6. The second electrode 15 is provided on the mesa and electrically connected to the second-type semiconductor layer 8. It should be understood that this embodiment is only described as an example of a horizontal LED chip structure. In other embodiments, the LED chip can also have a vertical structure, a face-up structure, or a flip-chip structure.

[0156] The present application also provides a display device, which includes the above-mentioned LED chip.

[0157] It should be understood by those skilled in the art that, in the disclosure of the present invention, the terms "horizontal", "vertical", "upper", "lower", etc. indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms cannot be understood as limiting the present invention.

[0158] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0159] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. Epitaxial structure, characterized in that include a substrate comprising one of a sapphire substrate, a silicon substrate, and a silicon carbide substrate; A stress compensation layer is provided on one side surface of the substrate; the thermal expansion coefficient of the stress compensation layer is D; When the substrate is the sapphire substrate, D>A; the thermal expansion coefficient of the sapphire substrate is A; When the substrate is the silicon substrate, D<B; the thermal expansion coefficient of the silicon substrate is B; When the substrate is the silicon carbide substrate, D<C; The thermal expansion coefficient of the silicon carbide substrate is C; an epitaxial stack comprising a GaN material layer and an InGaN material layer; The epitaxial stack and the stress compensation layer are located on the same side of the substrate, or the epitaxial stack and the stress compensation layer are located on opposite sides of the substrate respectively; When the epitaxial stack and the stress compensation layer are located on the same side of the substrate, the stress compensation layer is arranged between the epitaxial stack and the substrate, and the stress compensation layer is provided with a plurality of hollow regions.

2. The epitaxial structure according to claim 1, wherein: When the substrate is a sapphire substrate, the material of the stress compensation layer includes one of a nickel-based alloy and a titanium-based alloy; When the substrate is one of a silicon substrate and a silicon carbide substrate, the material of the stress compensation layer includes one of silicon dioxide, lithium ceramics, cordierite ceramics, and aluminum titanate ceramics.

3. The epitaxial structure according to claim 1, wherein When the stress compensation layer is provided with the hollow area, the hollow area divides the stress compensation layer into a plurality of stress compensation units; The sidewall of each stress compensation unit is an inclined surface; The angle formed by the sidewall of each stress compensation unit and the substrate is in the range of 30°-60°, including the end points.

4. The epitaxial structure according to claim 1, wherein: The epitaxial stack includes an undoped gallium nitride layer, a first-type semiconductor layer, an active layer, and a second-type semiconductor layer, which are sequentially arranged in a direction away from the substrate; the active layer includes an InGaN layer and a GaN layer.

5. The epitaxial structure according to claim 4, wherein: The thermal stress σ of the substrate s Satisfies the following formula: σ GaN is the stress exerted by the epitaxial stack on the substrate, σ scl the stress applied to the substrate by the stress compensation layer; α GaN is the thermal expansion coefficient of GaN material, α s is the thermal expansion coefficient of the substrate, α scl is the thermal expansion coefficient of the stress compensation layer; M GaN is the biaxial modulus of GaN material, M s is the biaxial modulus of the substrate, M scl is the biaxial modulus of the stress compensation layer; wherein the biaxial moduli of the GaN material, the substrate and the stress compensation layer all satisfy M=E / (1-υ), E is the elastic modulus of the corresponding material, and υ is the Poisson's ratio of the corresponding material; h GaN is the thickness of the epitaxial stack, h s is the substrate thickness, h scl is the thickness of the stress compensation layer; ΔT=T1-T2; T1 is the growth temperature of the undoped gallium nitride layer, and T2 is the growth temperature of InGaN in the active layer.

6. Thickness design method, characterized in that, It is used to design the thickness of stress compensation layers in epitaxial structures; The epitaxial structure is the epitaxial structure according to any one of claims 1 to 5, and the epitaxial stack comprises an undoped gallium nitride layer, a first-type semiconductor layer, an active layer, and a second-type semiconductor layer sequentially arranged in a direction away from the substrate; the active layer comprises an InGaN layer and a GaN layer; The thermal stress σ of the substrate s Satisfies the following formula: σ GaN is the stress exerted by the epitaxial stack on the substrate, σ scl the stress applied to the substrate by the stress compensation layer; α GaN is the thermal expansion coefficient of GaN material, α s is the thermal expansion coefficient of the substrate, α scl is the thermal expansion coefficient of the stress compensation layer; M GaN is the biaxial modulus of GaN material, M s is the biaxial modulus of the substrate, M scl is the biaxial modulus of the stress compensation layer; wherein the biaxial moduli of the GaN material, the substrate and the stress compensation layer all satisfy M=E / (1-υ), E is the elastic modulus of the corresponding material, and υ is the Poisson's ratio of the corresponding material; h GaN is the thickness of the epitaxial stack, h s is the substrate thickness, h scl is the thickness of the stress compensation layer; ΔT = T1 - T2; T1 is the growth temperature of the undoped GaN layer, and T2 is the growth temperature of InGaN in the active layer; Get the biaxial modulus M of the substrate s , thickness h s and thermal expansion coefficient α s ; Obtain the biaxial modulus M of GaN material GaN and thermal expansion coefficient α GaN ; Get the thickness h of the epitaxial stack GaN ; Get ΔT; Obtain the biaxial modulus M of the stress compensation layer scl , thermal expansion coefficient α scl ; The sum of the stresses on the substrate σ s is zero, and the thickness h of the stress compensation layer is obtained by the thermal stress relationship of the substrate scl .

7. A method for producing an epitaxial structure, characterized in that: Providing a substrate; the substrate is one of a sapphire substrate, a silicon substrate and a silicon carbide substrate; A stress compensation layer is grown on one surface of the substrate; the thermal expansion coefficient of the stress compensation layer is D; When the substrate is the sapphire substrate, D>A; the thermal expansion coefficient of the sapphire substrate is A; When the substrate is the silicon substrate, D<B; the thermal expansion coefficient of the silicon substrate is B; When the substrate is the silicon carbide substrate, D<C; the thermal expansion coefficient of the silicon carbide substrate is C; growing an epitaxial stack including a GaN material layer and an InGaN material layer; the epitaxial stack and the stress compensation layer are located on the same side of the substrate, or the epitaxial stack and the stress compensation layer are located on opposite sides of the substrate; When the epitaxial stack and the stress compensation layer are located on the same side of the substrate, growing the stress compensation layer includes first growing a layer of stress compensation layer material, and then patterning the stress compensation layer material so that the stress compensation layer forms a plurality of hollow regions; The stress compensation layer is arranged between the epitaxial stack and the substrate.

8. The method for manufacturing an epitaxial structure according to claim 7, wherein: When the substrate is a sapphire substrate, the material of the stress compensation layer includes one of a nickel-based alloy and a titanium-based alloy; When the substrate is one of a silicon substrate and a silicon carbide substrate, the material of the stress compensation layer includes one of silicon dioxide, lithium ceramics, cordierite ceramics, and aluminum titanate ceramics.

9. The method for manufacturing an epitaxial structure according to claim 7, wherein: The epitaxial stack includes an undoped gallium nitride layer, a first-type semiconductor layer, an active layer, and a second-type semiconductor layer sequentially arranged in a direction away from the substrate; the active layer includes an InGaN layer and a GaN layer; The thermal stress σ of the substrate s Satisfies the following formula: σ GaN is the stress exerted by the epitaxial stack on the substrate, σ scl the stress applied to the substrate by the stress compensation layer; α GaN is the thermal expansion coefficient of GaN material, α s is the thermal expansion coefficient of the substrate, α scl is the thermal expansion coefficient of the stress compensation layer; M GaN is the biaxial modulus of GaN material, M s is the biaxial modulus of the substrate, M scl is the biaxial modulus of the stress compensation layer; wherein the biaxial moduli of the GaN material, the substrate and the stress compensation layer all satisfy M=E / (1-υ), E is the elastic modulus of the corresponding material, and υ is the Poisson's ratio of the corresponding material; h GaN is the thickness of the epitaxial stack, h s is the substrate thickness, h scl is the thickness of the stress compensation layer; ΔT=T1-T2; T1 is the growth temperature of the undoped gallium nitride layer, and T2 is the growth temperature of InGaN in the active layer.

10. LED chip, characterized in that The method comprises the epitaxial structure according to any one of claims 1 to 5, a first electrode and a second electrode.

11. A display device, characterized in that The LED chip according to claim 10 is included.

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