Energy saving Vmin architecture for shared power rail

Abstract

Various embodiments include a method performed by a processor for managing a voltage drop margin for a power distribution network (PDN). Various embodiments may include receiving, by a processor, a performance corner of a first request from a first client powered by a shared power rail within a PDN; receiving, by the processor, a second requested performance corner from a second client powered by the shared power rail; determining, by the processor, a first peak current value based on a performance corner of the first request; determining, by the processor, a second peak current value based on a performance corner of the second request; determining, by a processor, a system voltage drop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN; and adjusting the voltage of the shared power rail based on the system voltage drop margin.

Description

[0001] Related applications

[0002] This application claims the benefit of priority to U.S. non-provisional application No. 18 / 166,381, filed on February 8, 2023; the entire contents of that patent application are incorporated herein by reference. Background Art

[0003] A power manager, or power management integrated circuit (PMIC), is used to manage the power requirements of the host system. The power manager manages the rail voltage provided to the system-on-chip (SoC). The rail voltage is provided to the clients (e.g., processors, loads) of the SoC so that the clients can operate. The clients can request voltage changes to the shared power rail voltage from the power manager to accommodate various performance modes, during which the clients can perform functions at a higher operating frequency. Voltage sags can occur during various processes and during transitions between performance modes. The power manager can output voltage on the shared power rail to accommodate any voltage sags, so that the clients receive sufficient voltage during any voltage sag event. Summary of the Invention

[0004] Various aspects include a method for managing a power distribution network (PDN) executable by a processor of a computing device. The various aspects may include: determining, by the processor, a first peak current value based on a performance margin of a first request received from a first client powered by a shared power rail within the PDN; determining, by the processor, a second peak current value based on a performance margin of a second request received from a second client powered by the shared power rail; determining, by the processor, a system voltage droop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN; and adjusting a voltage of the shared power rail based on the system voltage droop margin.

[0005] In some aspects, determining, by the processor, the first peak current value based on the first requested performance corner may include: the processor identifying, in a lookup table, the first peak current value associated with the first requested performance corner, and determining, by the processor, the second peak current value based on the second requested performance corner may include: the processor identifying, in the lookup table, the second peak current value associated with the second requested performance corner.

[0006] In some aspects, determining, by the processor, the system voltage drop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN may include: aggregating the first peak current value and the second peak current value to determine, by the processor, a cumulative peak current value, and determining, by the processor, the system voltage drop margin based on the cumulative peak current value and the impedance value of the PDN.

[0007] In some aspects, the impedance value of the PDN can be based on a maximum operating frequency, which can be equal to a higher of a first operating frequency of the first requested performance margin and a second operating frequency of the second requested performance margin.

[0008] Some aspects may also include determining, by the processor, a first impedance value associated with the first requested performance corner, wherein the first impedance value may be associated with a first operating frequency of the first requested performance corner; and determining, by the processor, a second impedance value associated with the second requested performance corner, wherein the second impedance value may be associated with a second operating frequency of the second requested performance corner.

[0009] In some aspects, determining, by the processor, the system voltage drop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN may include: determining, by the processor, a first voltage drop margin based on the first peak current value and the first impedance value; determining, by the processor, a second voltage drop margin based on the second peak current value and the second impedance value; and aggregating the first voltage drop margin and the second voltage drop margin to determine, by the processor, the system voltage drop margin.

[0010] Some aspects may also include reducing the system voltage droop margin based on the instantaneous load current rise time of the PDN.

[0011] In some aspects, the first requested performance margin may be included as part of a first voting request received by the processor from the first client, and the second requested performance margin may be included as part of a second voting request received by the processor from the second client.

[0012] In some aspects, the first requested performance margin and the second requested performance margin can be one of a high frequency mode, a low frequency mode, or a lowest frequency mode.

[0013] Further aspects include: a computing device (e.g., a UE) comprising a processor configured to perform the operations of any of the methods outlined above. Further aspects include: a computing device comprising means for performing the functions of any of the methods outlined above. Further aspects include: a non-transitory processor-readable medium having stored thereon processor-executable instructions configured to cause a processor of the UE to perform the operations of any of the methods outlined above. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated herein and constitute a part of this specification, illustrate example embodiments among the various embodiments and, together with the general description given above and the detailed description given below, serve to explain features of the claims.

[0015] Figure 1 is a component block diagram illustrating an example computing device suitable for implementing various embodiments.

[0016] Figure 2 Systems including computing devices suitable for use with various embodiments are illustrated.

[0017] Figure 3A Illustrated is a graph representing impedance values ​​within a power distribution network (PDN) as a function of frequency, according to some embodiments.

[0018] Figure 3B A graph representing current values ​​within a PDN as a function of time is illustrated, according to some embodiments.

[0019] Figure 4 A diagram 400 including voltage margining for a shared power rail within a PDN is illustrated.

[0020] Figure 5 is a component block diagram illustrating an example system for managing voltage droop margin of a PDN according to some embodiments.

[0021] Figure 6 An example peak current value table is illustrated for a client voting scheme for a PDN.

[0022] Figure 7 Illustrated includes a diagram illustrating reduced voltage margin for shared power rails within a PDN according to some embodiments.

[0023] Figures 8A to 8C is a process flow diagram illustrating a method for managing voltage droop margin of a PDN according to some embodiments.

[0024] Figure 9 is a component block diagram illustrating an example mobile computing device suitable for implementing various embodiments.

[0025] Figure 10 is a component block diagram illustrating an example mobile computing device suitable for implementing various embodiments.

[0026] Figure 11 is a component block diagram illustrating an example server suitable for implementing various embodiments. DETAILED DESCRIPTION

[0027] Various embodiments will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Reference to specific examples and specific implementations is for illustrative purposes and is not intended to limit the scope of the claims.

[0028] Various embodiments include methods for managing voltage droop margins of a power distribution network (PDN) of a computing device and computing devices implementing such methods. Some embodiments include reducing voltage margins of a voltage output from a power manager / power management integrated circuit to a shared power rail that powers multiple clients (e.g., processors, processing units, loads, etc.). Some embodiments reduce voltage margins and thereby save power by determining the voltage droop margin based on the performance margin requested by each client on the shared power rail.

[0029] The terms "computing device" and "mobile device" are used interchangeably herein to refer to any or all of the following: a cellular telephone, a smartphone, a personal or mobile multimedia player, a personal data assistant (PDA), a laptop computer, a tablet computer, a convertible laptop / tablet computer (2-in-1 computer), a smartbook, an ultrabook, a netbook, a handheld computer, a wireless email receiver, an Internet-enabled multimedia cellular telephone, a mobile game console, a wireless game controller, and similar personal electronic devices that include memory and a programmable processor. The term "computing device" may further refer to a fixed computing device, including a personal computer, a desktop computer, a stand-alone computer, a workstation, a supercomputer, a mainframe computer, an embedded computer, a server, a home theater computer, and a game console.

[0030] Figure 1 A system 100 is illustrated that includes a computing device 10 suitable for use with various embodiments. The computing device 10 may include a system on a chip (SoC) 12 having a processor 14, a memory 16, a memory interface 34, a communication interface 18, a storage memory interface 20, a clock controller 30, and an interconnect 32. The computing device 10 may also include a communication component 22 (such as a wired or wireless modem), storage memory 24, an antenna 26 for establishing a wireless communication link, a power manager 28, and a memory 36. The processor 14 may include any of a variety of processing devices, such as multiple processor cores.

[0031] The term "system on a chip" (SoC) is used herein to refer to a collection of interconnected electronic circuits, typically but not exclusively including a processing device, memory, and a communication interface. The processing device can include a variety of different types of processors 14 and processor cores, such as general-purpose processors, central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), accelerated processing units (APUs), security processing units (SPUs), neural network processing units (NPUs), subsystem processors for specific components of the computing device (such as an image processor for a camera subsystem or a display processor for a display), auxiliary processors, single-core processors, multi-core processors, controllers, and microcontrollers. The processing device can further embody other hardware and hardware combinations, such as field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), other programmable logic devices, discrete gate logic components, transistor logic components, performance monitoring hardware, watchdog hardware, and time references. The integrated circuit can be configured so that the components of the integrated circuit reside on a single piece of semiconductor material (such as silicon).

[0032] SoC 12 may include one or more processors 14. Computing device 10 may include more than one SoC 12, thereby increasing the number of processors 14 and processor cores. Computing device 10 may also include processors 14 that are not associated with SoC 12. Processors 14 may each be configured for a specific purpose that may be the same as or different from other processors 14 of computing device 10. One or more processors 14 and processor cores of the same or different configurations may be grouped together. A group of processors 14 or processor cores may be referred to as a multi-processor cluster.

[0033] The computing device 10 may include any number and combination of memories, such as a memory 16 integral to the SoC 12 and a memory 36 separate from the SoC 12. Any of the memories 16, 36 may be volatile or non-volatile memory configured to store data and processor-executable code for access by the processor 14. The computing device 10 and / or the SoC 12 may include one or more memories 16, 36 configured for various purposes. The one or more memories 16, 36 may include volatile memory, such as random access memory (RAM) or main memory, including static RAM (SRAM) (such as memory 16), dynamic RAM (DRAM) (such as memory 36), or cache memory.

[0034] The memory 16, 36 may be configured to temporarily store a limited amount of data received from a data sensor or subsystem, data and / or processor-executable code instructions requested from the non-volatile memory 16, 24, 36 and loaded into the memory 16, 36 in anticipation of future access based on a variety of factors, and / or intermediate processing data and / or processor-executable code instructions generated by the processor 14 and temporarily stored for future quick access without being stored in the non-volatile memory 16, 24, 36. The memory 16, 36 may be configured to store data and processor-executable code in a portion of the memory 16, 36 configured to store data and processor-executable code for secure computing operations (referred to herein as a secure portion). The memory 16, 36 may be configured to store data and processor-executable code in a portion of the memory 16, 36 configured to store data and processor-executable code for non-secure computing operations (referred to herein as a non-secure portion).

[0035] The memory interface 34 may operate in concert with the memory 36 to enable the computing device 10 to store data and processor-executable code on and retrieve data and processor-executable code from the memory 36. The memory interface 34 may control access to the storage memory 36 and allow the processor 14 to read data from and write data to the memory 36.

[0036] The storage memory interface 20 and storage memory 24 can work in concert to allow the computing device 10 to store data and processor-executable code on a non-volatile storage medium. The storage memory 24 can be configured much like the embodiment of the memory 16, where the storage memory 24 can store data or processor-executable code for access by one or more of the processors 14. The non-volatile storage memory 24 can retain information after the computing device 10 has been powered off. When power is restored and the computing device 10 restarts, the information stored on the storage memory 24 is available to the computing device 10. The storage memory interface 20 can control access to the storage memory 24 and allow the processor 14 to read data from and write data to the storage memory 24.

[0037] The power manager 28 can be configured to control the power state of one or more power rails (not shown) for power delivery to components of the SoC 12. In some embodiments, the power manager 28 can be configured to generate a notification signal that indicates the power state and / or power event of the power rail to the components of the SoC 12 to prompt the components of the SoC 12 to respond to the signaled power state and / or event. For example, the notification signal generated and transmitted by the power manager 28 can be configured as an interrupt signal associated with the power state and / or power event of the power rail, such as a power state and / or power event associated with a voltage drop margin based on a requested performance margin of a component powered by a shared power rail. In some embodiments, the power manager 28 can be configured to control the amount of power provided to the components of the SoC 12. For example, the power manager 28 can be configured to control the connection between the components of the SoC 12 and the power rail. As another example, the power manager 28 can be configured to control the amount of power on the power rail connected to the components of the SoC 12. As another example, the power manager 28 or a processor coupled to the power manager 28 may be configured to calculate a voltage droop margin based on the PDN impedance and the peak current for each performance corner requested by each component on the shared power rail, and may supply voltage to the shared power rail based on the calculated voltage droop margin.

[0038] The clock controller 30 can be configured to control the clock signals sent to the components of the SoC 12. In some embodiments, the clock controller 30 can be configured to signal a clock state (such as gated or non-gated) to the components of the SoC 12 to prompt the components of the SoC 12 to transition to that clock state. For example, the components of the SoC 12 can transition to a gated clock state in response to receiving a gated clock state signal from the clock controller 30 by disconnecting from the clock signal, and can transition to a non-gated clock state in response to receiving a non-gated clock state signal from the clock controller 30 by connecting to the clock signal. In some embodiments, the clock controller 30 can be configured to control the clock signals to the components of the SoC 12. For example, the clock controller 30 can disconnect the components of the SoC 12 from the clock signal to transition the components of the SoC 12 to a gated clock state, and can connect the components of the SoC 12 to the clock signal to transition the components of the SoC 12 to a non-gated clock state.

[0039] Interconnect 32 may be a communication fabric, such as a communication or interface bus, configured to communicatively connect components of SoC 12. Interconnect 32 may route signals between components of SoC 12. In some embodiments, interconnect 32 may be configured to control signals between components of SoC 12 by controlling the timing and / or routing of the signals.

[0040] Some or all of the components of computing device 10 and / or SoC 12 may be arranged differently and / or may be combined while still providing the functionality of various embodiments. Computing device 10 may not be limited to one of each of these components, and various configurations of computing device 10 may include multiple instances of each component.

[0041] Figure 2 Illustrated is a system 200 including a computing device 10 suitable for use with the various embodiments. Figure 2 illustrates a shared rail scenario where a single source provides power to multiple clients, see Figures 1 to 2 , computing device 10 may include a power manager 28, a shared power rail 201 (e.g., a core logic power rail (CX), an embedded memory power rail (MX) (not shown)), and clients 202 (i.e., client 1, client 2, client 3). Power manager 28 may control the power supplied across shared power rail 201. Client 202 may be connected to shared power rail 201 and thus may be supplied with a power level managed by power manager 28.

[0042] Client 202 can be any type of load component or device that requires power to operate and is capable of communicating with power manager 28 (i.e., requesting performance margins, providing voltage voting messages for adjusting the power supplied to shared power rail 201, etc.), such as a processor, sub-processor, core, or other IC. For example, client 202 can be a processor (e.g., processor 14) or processor core of SoC 12 as illustrated. As another example, client 202 can be a component located external to SoC 12, such as other board-level components communicatively coupled to SoC 12. As another example, client 202 can be located external to computing device 10 but communicatively connected to the computing device. Client 202 is illustrated as having a first client (client 1), a second client (client 2), and a third client (client 3). However, client 202 is not limited to three clients and may include fewer or more clients connected to shared power rail 201 implemented in various configurations of system 200.

[0043] In some embodiments, the power manager 28 can be configured as a power management integrated circuit (PMIC). For example, the power manager 28 can be a PMIC that communicates with the resource manager, and the PMIC can transmit a request message to the resource manager requesting approval to adjust the voltage across the shared power rail 201, wherein the request message is based on and / or includes the performance corner requested by the client 202. The resource manager can send a response message to the PMIC that approves or denies the request to adjust the voltage across the shared power rail. Upon receiving approval from the resource manager, the PMIC can adjust the voltage across the shared power rail 201 and send an acknowledgment (ACK) message to the resource manager indicating that the voltage adjustment has been performed. The client 202 can then be configured according to the requested performance corner.

[0044] Shared power rail 201 may include any number of components positioned between power manager 28 and client 202 for providing power to client 202, and is not limited to the components illustrated in the example circuit of system 200. Depending on the device type of client 202 and the expected load of client 202, the components of shared power rail 201 may include any number and any type of components suitable for supplying power to client 202. For example, client 202 may be a processor or processor core located within SoC 12, power manager 28 may be located on the same printed circuit board (PCB) as SoC 12, and shared power rail 201 may include any active and passive components along the power supply path and ground return path between power manager 28 and client 202. Thus, shared power rail 201 may include any components along the path that traverses on and / or within the PCB and within the package of SoC 12. For example, the shared power rail 201 may include PCB-level components such as transistors (Q1, Q2), a voltage controller switch (VSW), an inductor (L), PCB-level resistors (pcb1, pcb2, pcb3) (or wiring resistance values), and capacitors (pcb_cap) for passing the supply voltage (e.g., Vph) to the shared power rail 201 components, as well as components at the SoC 12 package level such as package resistors (pkg1, pkg2) and package capacitors (pkg_cap) located between a ball grid array (BGA) connected to the PCB and the client 202 (i.e., connected at solder bumps (“bumps”)).

[0045] A sense line may be coupled to a point along the path of shared power rail 201, such as sense point D. The sense line may be connected to power manager 28 so that power manager 28 can observe the power value and changes in supply voltage Vph after it has passed through a portion of the components of shared power rail 201. Power manager 28 may make adjustments (e.g., voltage fine-tuning) to the voltage supplied to shared power rail 201 based on the power value observed at sense point D. Power manager 28 may have any number of additional sense points along shared power rail 201 and is not limited to the single sense point as illustrated.

[0046] The shared power rail 201 may exhibit voltage droop due to various frequency-based / frequency-affected components (L, pcb_caps, pkg_caps, etc.) along the shared power rail 201. For example, the voltage supplied along the shared power rail 201 may experience a voltage droop (V droop 1) due to PCB-level transient responses (i.e., transient responses of the power manager 28 and PCB-level capacitors (pcb_caps)), and a voltage droop (V droop 2) due to package and die-level transient responses (i.e., transient responses of the client 202 and package and die-level capacitors (pkg_caps)).

[0047] Figure 3A and Figure 3B Graphs representing example PDN impedance values ​​and instantaneous load current values ​​that may be measured within some embodiments are illustrated. Figure 3A A graph representing impedance values ​​within a PDN as a function of frequency is illustrated, according to some embodiments. Figure 3B A graph representing current values ​​within a PDN as a function of time is illustrated, according to some embodiments. Figure 3A and Figure 3B The example in FIG is for illustrative purposes and does not represent all potential situations and responses of impedance and current values ​​that can be measured or experienced within a PDN, and does not limit the scope of the claims and specification to this example. Other descriptions of situations and responses of impedance and current of a shared power rail can be similarly graphed.

[0048] refer to Figures 1 to 3B The voltage drop (e.g., V droop 1, V droop 2) is the result of the frequency-dependent impedance multiplied by the instantaneous load current (e.g., V droop = Z(f)*di / dt). For any given PDN circuit design, the impedance value along the path of the shared power rail (e.g., 201) is fixed. For example, Figure 3AAs illustrated, for the shared power rail 201 of the system 200, the magnitude of the impedance (Ohm) may be fixed or static according to the frequency (Hz), wherein the impedance is a specific value that depends on the phase of the voltage provided to the shared power rail 201 by the power manager 28. For any given PDN circuit design, the current value, i.e., the instantaneous current magnitude (I step ) and step load bandwidth (i.e., the rise time of a dynamic load (t r )) is dynamic and depends on use case activity (voltage voting by clients 202 to request more / less voltage and / or faster / slower operating modes). For example, the instantaneous current magnitude (Amp) and the step load bandwidth (time) may vary depending on whether one or more loads of client 202 request a change in performance margin (i.e., a change in voltage and / or phase) from power manager 28.

[0049] Figure 4 1. A diagram 400 is illustrated that includes voltage margins for shared power rails within a PDN. The absolute percentages of these voltage margins may vary based on the system design and may differ from the percentages illustrated. For example, the percentages may vary but may overall follow the general division of voltage margins as shown. Diagram 400 illustrates conventional voltage margins designed into the power output settings of a PMIC (PMIC settings) so that the voltage level provided to the load at the endpoint of the shared power rail does not drop below the minimum system load requirement (i.e., SYS Vmin at the junction) due to voltage drops caused by transient responses of components of the shared power rail. In other words, the conventional voltage margins illustrated add a voltage buffer or voltage margin to ensure that the actual client-side voltage remains above the client-side voltage requirement throughout any power adjustments made to the shared power rail. The percentage of each voltage margin may be a percentage of (i.e., SYS Vmin at the junction).

[0050] Applying the concepts of diagram 400 to system 200, PMIC settings (e.g., power manager 28 settings) can be offset by multiple voltage margins from the SYS Vmin voltage value at the junction (e.g., the voltage at client 202). The percentages of voltage margin are merely illustrative and not intended to be exhaustive, and can vary depending on at least the client load and shared power rail circuit design.

[0051] Voltage margins can include dynamic margins such as test margins, aging margins, power manager / PMIC direct current (DC) margins, and any other margins that account for manufacturing process variations, PCB and component aging, and environmental, board-level, and internal IC temperature. For example, automated test equipment (ATE) can be used to determine process corner voltage margins to provide open-loop core power reduction margins. As another example, aging voltage margins can be dynamically adjusted in situ. As another example, voltage fine-tuning can be dynamically adjusted for temperature changes in closed-loop core power reduction methods.

[0052] Voltage margins can include static, non-dynamic margins designed to accommodate worst-case voltage droop scenarios. For example, a customer PDN margin can be a static voltage droop margin designed to account for voltage droops (e.g., V droop 1) due to transient responses of the PMIC (e.g., power manager 28) and PCB capacitors (e.g., pcb_cap). A customer PDN margin can be a percentage margin above SYS Vmin at the PMIC (e.g., the voltage value measured by power manager 28 at sense point D via a sense line). As another example, a PDN design budget margin can be a static voltage droop margin designed to account for voltage droops (e.g., V droop 2) due to transient responses of capacitors (e.g., pkg_cap) on the package and die (e.g., SoC 12), other voltage droops on the package and die, and package and die PDN noise margins. A PDN design budget margin can be a percentage margin above SYS Vmin at the junction (e.g., the voltage at client 202).

[0053] The static customer PDN margin and the PDN design budget margin can be combined and / or referred to as a total Vmin noise margin, where the source (e.g., PMIC) voltage is a specific percentage above or at the SYS Vmin at the junction. The total Vmin noise margin can be a worst-case voltage margin to account for the concurrent peak current values ​​from all loads (e.g., client 202) on a shared power rail (e.g., 201). In other words, the total Vmin noise margin can account for the worst-case voltage drop so that when the loads (e.g., client 202) are simultaneously operating at maximum capability (e.g., high-frequency operation), the load voltage (i.e., the voltage observed / measured at client 202) still exceeds the minimum operating voltage of the load at the lowest point of the PCB-side and / or package-side voltage drop.

[0054] By designing for worst-case voltage droop with a static total voltage margin, conventional PMIC configurations often provide more voltage to the shared power rail than necessary because the load is not always operating at full capacity. For example, a sample rail voltage signal with a voltage level set as "lower limit voltage at PMIC" is illustrated as experiencing a voltage droop that extends below the SYS Vmin threshold at the PMIC. However, the total margin overcompensates for the worst-case voltage droop, and the voltage margin provided below a large portion of the rail voltage remains unutilized. Various embodiments optimize and reduce static PDN margins (customer PDN margin for Vdroop 1, PDN design budget margin for Vdroop 2) by determining the actual worst-case voltage droop based on the requested performance margin of each client in clients 202 and lowering the lower limit voltage set by power manager 28.

[0055] Figure 5 is a component block diagram illustrating an example system 500 for managing voltage droop margin of a PDN according to some embodiments. Figures 1 to 5 , the system 500 may include one or more computing devices 502 (e.g., computing device 10) and external resources 518, which may communicate via a wireless communication link 524. The external resources 518 may include information sources external to the system 500, external entities that interact with the system 500, or other resources. For example, the external resource 518 may be a paired BT device, such as the second BT device 106. In some implementations, some or all of the functionality attributed herein to the external resources 518 may be provided by resources included in the system 500. The system 500 may include multiple hardware, software, and / or firmware components that operate together to provide the functionality attributed herein to the processor 522.

[0056] Computing device 502 may include electronic storage 520 that may be configured to store information related to the functionality implemented by interface module 530 , transmit-receive module 550 , memory access module 552 , voltage margining module 554 , and any other instruction modules.

[0057] Electronic storage 320 may include non-transitory storage media that electronically stores information. Electronic storage 320 may include one or both of system storage that is provided integrally with system 200 (i.e., is substantially non-removable) and / or removable storage that is removably connectable to system 200 via, for example, a port (e.g., a Universal Serial Bus (USB) port, a FireWire port, etc.) or a drive (e.g., a disk drive, etc.).

[0058] In various embodiments, electronic storage 520 may include one or more of charge-based storage media (e.g., EEPROM, RAM, etc.), solid-state storage media (e.g., flash drives, etc.), optically readable storage media (e.g., optical disks, etc.), magnetically readable storage media (e.g., magnetic tape, magnetic hard drives, floppy disk drives, etc.), and / or other electronically readable storage media. Electronic storage 520 may include one or more virtual storage resources (e.g., cloud storage, virtual private networks, and / or other virtual storage resources). Electronic storage 520 may store software algorithms, information determined by processor 522, and / or other information that enables system 500 to function as described herein.

[0059] Computing device 502 may be configured via machine-readable instructions 506. Machine-readable instructions 506 may include one or more instruction modules. Instruction modules may include computer program modules. Instruction modules may include one or more of a transmit-receive module 550, a memory access module 552, a voltage margin module 554, and other instruction modules (not illustrated). Computing device 502 may include a processor 522 configured to implement machine-readable instructions 506 and corresponding modules.

[0060] Processor 522 may include one of a plurality of local processors that may be configured to provide information processing capabilities in system 500. Thus, processor 522 may include one or more of the following: a digital processor, an analog processor, a digital circuit designed to process information, an analog circuit designed to process information, a state machine, and / or other mechanisms for electronically processing information. Although processor 522 may be configured to provide information processing capabilities in system 500, processor 522 may include one or more of the following: a digital processor, an analog processor, a digital circuit designed to process information, an analog circuit designed to process information, a state machine, and / or other mechanisms for electronically processing information. Figure 5 500. In some embodiments, processor 522 may include multiple processing units. These processing units may be physically located within the same device, or processor 522 may represent processing functionality distributed across multiple devices in system 500.

[0061] In some embodiments, the processor 522 executing the transmit-receive module 550 may be configured to receive a first requested performance margin from a processor of a first client powered by a shared power rail within the PDN. In some embodiments, the processor 522 executing the transmit-receive module 550 may be configured to receive a second requested performance margin from a processor of a second client powered by the shared power rail.

[0062] In some embodiments, the processor 522 executing the memory access module 552 may be configured to determine, by the processor, a first peak current value based on the first requested performance corner. In some embodiments, the processor 522 executing the memory access module 552 may be configured to determine, by the processor, a second peak current value based on the second requested performance corner. In some embodiments, the processor 522 executing the memory access module 552 may be configured to determine, by the processor, a first impedance value associated with the first requested performance corner, wherein the first impedance value is associated with a first operating frequency of the first requested performance corner. In some embodiments, the processor 522 executing the memory access module 552 may be configured to determine, by the processor, a second impedance value associated with the second requested performance corner, wherein the second impedance value is associated with a second operating frequency of the second requested performance corner.

[0063] In some embodiments, the processor 522 executing the voltage margin module 554 may be configured to determine, via the processor, a system voltage droop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN. In some embodiments, the processor 522 executing the voltage margin module 554 may be configured to adjust the voltage of the shared power rail based on the system voltage droop margin. In some embodiments, the processor 522 executing the voltage margin module 554 may be configured to reduce the system voltage droop margin based on the instantaneous load current rise time of the PDN.

[0064] Processor 522 may execute modules 550 - 554 and / or other modules via software, hardware, firmware, some combination of software, hardware, and / or firmware, and / or other mechanisms for configuring processing capabilities on processor 522 .

[0065] The description of the functionality provided by the different modules 550-554 is for illustrative purposes and is not intended to be limiting, as any of the modules 550-554 may provide more or less functionality than described. For example, one or more of the modules 550-554 may be eliminated, and some or all of their functionality may be provided by other modules in the modules 550-554. As another example, the processor 522 may execute one or more additional modules that may perform some or all of the functionality attributed below to one of the modules 550-554.

[0066] Figure 6A table of example peak current values ​​for a client voting scheme for a PDN is shown. The number of clients (e.g., 202), the requested performance margins, and the current values ​​are merely illustrative and not intended to be exhaustive. A PDN (e.g., system 200) may be implemented with fewer or more clients, other operating modes may be implemented, and other current values ​​may be utilized depending on the design of the PDN.

[0067] refer to Figures 1 to 6 Peak current value table 600 illustrates clients 202 (client 1, client 2, client 3), requested performance corners, and peak current values. According to some embodiments, peak current value table 600 includes peak current values ​​used when determining a normal static PDN voltage margin (i.e., a total voltage noise margin) and peak current values ​​used when determining a minimized PDN voltage margin.

[0068] Existing PDN voltage margins are static, taking into account the concurrent worst-case di / dt transient response experienced by all clients on a shared rail. As previously described, this can cause the power manager to overcompensate and supply more voltage to the shared power rail than necessary to ensure that voltage drops do not cause the voltage supplied to the clients to drop below the minimum required operating voltage for the client loads. For example, Client 1, Client 2, and Client 3 may each request a different performance margin from the power manager 28—Client 1 may request a turbo performance margin (i.e., a high voltage and / or high frequency performance margin), Client 2 may request a static voltage scaling (SVS) performance margin (i.e., a performance margin with a lower operating voltage and / or frequency than the turbo performance margin), and Client 3 may request a low SVS (LSVS) performance margin (i.e., a performance margin with a lower operating voltage and / or frequency than the SVS performance margin). Conventionally, the PMIC or power manager would aggregate the shared power rail performance margins to determine the highest level of operation requested by the clients. Here, the highest level of operation requested by Clients 1, 2, and 3 would be the high-frequency turbo mode. The worst-case total di / dt will be the sum of the peak currents of each client during the turbo performance corner, even though two of the clients did not request turbo mode (e.g., client 1 turbo voltage and frequency = 10A; client 2 turbo voltage and frequency = 6A; client 3 turbo voltage and frequency = 5A; total di / dt at the aggregate performance corner = 21A). The static PDN voltage margin will be set to at least be greater than the voltage drop for a load attack with a worst-case di / dt of 21A on the shared power rail. However, the voltage margin calculated using conventional aggregate performance methods will supply more voltage to the clients than necessary because clients 2 and 3 actually only requested SVS and LSVS, which provide less voltage drop than turbo mode at transient response.

[0069] Various embodiments minimize static PDN voltage margins and reduce overcompensation of the voltage supplied to shared power rail 201 by power manager 28 by accumulating peak current values ​​corresponding to the actual performance corners requested by each of clients 202 (rather than the aggregate performance corners). For example, client 1 may request a turbo performance corner from power manager 28, client 2 may request an SVS performance corner from the power manager, and client 3 may request an LSVS performance corner from the power manager. Power manager 28 may be configured to determine a peak current associated with each requested performance corner. For example, upon receiving one or more messages or signals from client 202 including the requested performance corners, power manager 28 may determine or otherwise request a predefined / designed peak current value associated with each requested performance corner from a lookup table. The cumulative peak current value di / dt (i.e., Ipeak load attack) can then be determined by aggregating the peak current at each requested performance corner (e.g., client 1 turbo voltage and frequency = 10A; client 2 turbo voltage and SVS frequency = 2A; client 3 turbo voltage and LSVS frequency = 1A; total di / dt at the requested performance corner = 13A). The power manager 28 can calculate the voltage droop based on the known impedance of the PDN (i.e., Z(f)) and the cumulative peak current value of 13A. The power manager 28 can then safely reduce the static PDN voltage margin and, therefore, lower the voltage floor at the power manager 28 (i.e., SYSVmin at the PMIC) to reduce overall power waste across the shared power rail 201 while maintaining sufficient voltage to ensure that any potential voltage droop does not fall below the minimum required voltage of the client 202 (i.e., SYS Vmin at the junction). In other words, power manager 28 may estimate rail (uS) and on-die (nS) level peak currents based on client 202 performance voting requests and known PDN impedance specifications, and may calculate voltage droop margins to optimize voltage for any voting request configuration for client 202 .

[0070] As another example calculation (not shown), client 1 may request an LSVS performance corner, client 2 may request an SVS performance corner, and client 3 may request an SVS performance corner. Thus, the cumulative peak current value used in determining voltage droop may be calculated as follows: client 1 SVS voltage and LSVS frequency = 1A; client 2 SVS voltage and SVS frequency = 2A; client 3 SVS voltage and SVS frequency = 2A; total di / dt at requested performance corner = 5A. Power manager 28 may then further reduce the PDN voltage margin and, therefore, lower the voltage supplied to shared power rail 201.

[0071] In some embodiments, power manager 28 may determine the voltage drop across the PCB (i.e., V droop 1) and the voltage drop across the package die (e.g., SoC 12) (i.e., V droop 2) based on the peak current value associated with each performance corner requested by client 202.

[0072] For example, the customer PDN margin can be a static voltage droop margin that can be designed to account for the voltage droop (e.g., Vdroop 1) of the transient response of the PMIC (e.g., power manager 28) and PCB capacitors (e.g., pcb_cap). Vdroop 1 can be determined by multiplying the known impedance Z(f) of the shared power rail 201 from the power manager 28 to the board-side components by the total di / dt at the requested performance corner (e.g., 13A, 5A according to the previous example). The customer PDN margin can then be reduced based on the calculated voltage droop 1 for the cumulative peak current value at the requested performance corner.

[0073] The PDN design budget margin can be a static voltage droop margin, which can be designed to account for the voltage droop (e.g., V droop 2) of the package (e.g., SoC 12) capacitor (e.g., pkg_cap) transient response, other package and die voltage droops, and package and die PDN noise margins. V droop 2 can be determined by multiplying the known impedance Z(f) of the shared power rail 201 from the package-side components by the total di / dt at the requested performance corner (e.g., 13A, 5A according to the previous example). The PDN design budget margin can then be reduced based on the calculated voltage droop 2 for the cumulative peak current value at the requested performance corner.

[0074] Therefore, the power manager 28 may reduce the customer PDN margin and the PDN design budget margin independently.

[0075] In some embodiments, the reduced total Vmin noise margin can be based on the transient load rise time (t r Some embodiments can proactively manage transient load rise times and further reduce customer PDN margins (i.e., to account for voltage droop 1) by understanding the managed di / dt load profile. For example, based on previous data simulations, the worst-case on-die Ipeak (e.g., rise time of a few ns) and the worst-case on-board Ipeak (i.e., averaged over 1 us) can be determined. These worst-case values ​​can be used in conjunction with known impedance data algorithms to determine PDN voltage margin reduction relative to V droop 1 and V droop 2.

[0076] Figure 7Graph 700 illustrates reduced voltage margins for a shared power rail within a PDN, according to some embodiments. Graph 700 illustrates reduced voltage margins designed into the power output settings of the power manager 28 or PMIC (PMIC settings) so that the voltage level provided to the loads at the endpoints of the shared power rail does not drop below the minimum system load requirement (i.e., SYSVmin at the junction) due to voltage drops caused by transient responses of components of the shared power rail 201. The illustrated reduced voltage margin is based on the requested performance corners of the client 202 (i.e., and therefore based on the cumulative peak current), rather than on, for example, Figure 4 and Figure 6 The reduced voltage margin reduces the overall power usage of the system 200 by keeping the lower limit voltage as close as possible to the SYS Vmin voltage at the junction without risking the rail voltage to drop below the SYS Vmin value at the junction. Figure 7 The reduced client PDN margin illustrated may be less than Figure 4 The margin of the conventional customer PDN margin is shown. Figure 7 The reduced PDN design budget margin illustrated may be less than Figure 4 The conventional PDN design budget margin is shown as follows. Figure 7 The reduced total voltage margin illustrated may be less than Figure 4 The margin for the conventional total voltage margin is illustrated.

[0077] Figure 8A is a process flow diagram of an example method 800a for managing voltage droop margin of a PDN, according to various embodiments. Figure 8B and Figure 8C is a process flow diagram of example operations 800b and 800c that may be performed as part of the method 800a for managing voltage droop margin of a PDN as described, according to some embodiments. Figures 1 to 8C , method 800a and operations 800b and 800c may be performed by a computing device (e.g., 10, 502). In some embodiments, the computing device may be configured to perform operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., 16, 24, 36, 520). The components for performing the operations of method 800a and each of operations 800b and 800c may be a processor (e.g., 14, 522, power manager 28) of system 100, 200, and 500 and / or as described in reference Figures 1 to 8C Similar to what is described.

[0078] In block 802, a computing device may perform operations including receiving, via a processor, a first requested performance margin (e.g., turbo, SVS, LSVS) from a first client (e.g., client 1, client 2, client 3) powered by a shared power rail 201 within a PDN. In some embodiments, the first requested performance margin may be included as part of a first voting request received by the processor from the first client, wherein the voting request includes a request for a voltage adjustment on the shared power rail 201. Means for performing the operations of block 802 may include a computing device (e.g., 10, 502) executing a transmit-receive module 550.

[0079] In block 804, the computing device may perform operations including receiving, by a processor, a second requested performance margin from a second client (e.g., client 1, client 2, client 3) powered by the shared power rail 201. In some embodiments, the second requested performance margin may be included as part of a second voting request received by the processor from the second client, wherein the voting request includes a request for a voltage adjustment to the shared power rail 201. In some embodiments, the first requested performance margin and the second requested performance margin may be one of a high frequency mode (e.g., turbo mode), a low frequency mode (SVS), or a lowest frequency mode (LSVS). Means for performing the operations of block 804 may include a computing device (e.g., 10, 502) executing the transmit-receive module 550.

[0080] In block 806, the computing device may perform operations including determining, by the processor, a first peak current value based on the first requested performance corner. In some embodiments, determining, by the processor, the first peak current value based on the first requested performance corner may include the processor identifying, in a lookup table, the first peak current value associated with the first requested performance corner. Means for performing the operations of block 806 may include the computing device (e.g., 10, 502) executing the memory access module 552.

[0081] In block 808, the computing device may perform operations including determining, by the processor, a second peak current value based on the second requested performance corner. In some embodiments, determining, by the processor, the second peak current value based on the second requested performance corner may include the processor identifying, in a lookup table, the second peak current value associated with the second requested performance corner. Means for performing the operations of block 806 may include a computing device (e.g., 10, 502) executing the memory access module 552.

[0082] In block 810, the computing device may perform operations including determining, by a processor, a system voltage droop margin (e.g., a reduced total Vmin noise margin) based on a first peak current value, a second peak current value, and an impedance value of a PDN (e.g., Z(f)). In some embodiments, determining, by the processor, a voltage droop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN may include aggregating the first peak current value and the second peak current value to determine, by the processor, a cumulative peak current value (i.e., total di / dt at the requested performance corner = client 1 di / dt + client 2 di / dt), and determining, by the processor, a voltage droop margin based on the cumulative peak current value and the impedance value of the PDN (i.e., total di / dt at the requested performance corner * Z(f)). In some embodiments, the impedance value of the PDN may be based on a maximum operating frequency, the maximum operating frequency being equal to the higher of a first operating frequency of the first requested performance corner and a second operating frequency of the second requested performance corner. For example, a client requesting a turbo performance margin and a client requesting an SVS performance margin will have V droop calculated using Z(f) for turbo mode rather than Z(f) for the lower frequency SVS mode. Means for performing the operations of block 810 may include a computing device (e.g., 10, 502) executing the voltage margin module 554.

[0083] In block 812 , the computing device may perform operations including adjusting the voltage of the shared power rail based on the system voltage droop margin. Components for performing the operations of block 812 may include the computing device (eg, 10 , 502 ) executing the voltage margin module 554 .

[0084] Figure 8B Operations 800b that may be performed as part of method 800a for managing voltage droop margin of a PDN according to some embodiments are illustrated. Figures 1 to 8B After the operation in block 804, the computing device may perform operations including determining, by a processor, a first impedance value associated with the first requested performance corner in block 812, wherein the first impedance value is associated with a first operating frequency of the first requested performance corner. Means for performing the operations in block 812 may include a computing device (e.g., 10, 502) executing the memory access module 552.

[0085] In block 816, the computing device may perform operations including determining, by the processor, a second impedance value associated with the second requested performance corner, wherein the second impedance value is associated with a second operating frequency of the second requested performance corner. Means for performing the operations of block 812 may include a computing device (e.g., 10, 502) executing the memory access module 552.

[0086] After the operations in block 816, the computing device may perform operations as described with reference to block 806. In some embodiments, after the operations in block 816, the operations in block 810 for determining, by the processor, a system voltage droop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN may include: determining, by the processor, a first voltage droop margin based on the first peak current value and the first impedance value, determining, by the processor, a second voltage droop margin based on the second peak current value and the second impedance value, and aggregating the first voltage droop margin and the second voltage droop margin to determine, by the processor, the system voltage droop margin.

[0087] Each requested performance corner (eg, turbo, SVS, LSVS) may result in a full shared power rail 201 (see Figure 3A ) in a different impedance value Z(f) in the SVS or LSVS performance corner. For example, the impedance of the shared power rail 201 may be a different value when the client 202 is operating in the turbo performance corner than when the client 202 is operating in the SVS or LSVS performance corner. In some embodiments, V droop may be calculated separately for each client and for each operating frequency of the requested performance corner. For example, a client requesting the turbo performance corner will have V droop calculated using Z(f) for turbo mode, and a client requesting the LSVS performance corner will have V droop calculated using Z(f) for LSVS mode instead of Z(f) for the higher frequency SVS mode (e.g., reduced total Vmin noise margin = V droop1 margin + V droop2 margin = (client 1 Ipeak * PDN Z high frequency) + (client 2 Ipeak * PDN Z lower frequency)).

[0088] In some embodiments, the operations of blocks 814 and 816 may be performed between the operations in blocks 806 and 808 .

[0089] Figure 8C Operations 800c that may be performed as part of method 800a for managing voltage droop margin of a PDN according to some embodiments are illustrated. Figures 1 to 8C After the operation in block 810, the computing device may perform operations including reducing the system voltage droop margin based on the instantaneous load current rise time of the PDN in block 818. The means for performing the operation in block 812 may include a computing device (e.g., 10, 502) executing the voltage margin module 554.

[0090] Following the operations in block 818 , the computing device may perform operations as described with reference to block 812 .

[0091] Various embodiments (including but not limited to the above reference Figures 1 to 8CThe described embodiments) can be implemented in a wide variety of computing systems including mobile computing devices, an example of which is Figure 9 . The mobile computing device 900 may include a processor 902 coupled to a touch screen controller 904 and internal memory 906. The processor 902 may be one or more multi-core integrated circuits designated for general or specific processing tasks. The internal memory 906 may be volatile or non-volatile memory, and may also be secure and / or encrypted memory, or unsecure and / or unencrypted memory, or any combination thereof. Examples of memory types that may be utilized include, but are not limited to, DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, and embedded DRAM. The touch screen controller 904 and processor 902 may also be coupled to a touch screen panel 912, such as a resistive sensing touch screen, a capacitive sensing touch screen, an infrared sensing touch screen, or the like. Additionally, the display of the mobile computing device 900 need not have touch screen capabilities.

[0092] The mobile computing device 900 may have one or more radio signal transceivers 908 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radios) and antennas 910 coupled to each other and / or to the processor 902 for transmitting and receiving communications. The transceiver 908 and antenna 910 may be used with the circuits mentioned above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 900 may include a cellular network wireless modem chip 916 that enables communication via a cellular network and is coupled to the processor.

[0093] The mobile computing device 900 may include a peripheral device connection interface 918 coupled to the processor 902. The peripheral device connection interface 918 may be configured solely to accept one type of connection, or may be configured to accept various types of physical and communication connections, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe, whether shared or proprietary. The peripheral device connection interface 918 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0094] The mobile computing device 900 may also include a speaker 914 for providing audio output. The mobile computing device 900 may also include a housing 920 for housing all or some of the components described herein, which may be constructed of plastic, metal, or a combination of materials. The mobile computing device 900 may include a power source 922, such as a disposable or rechargeable battery, coupled to the processor 902. The rechargeable battery may also be coupled to a peripheral device connection port to receive charging current from a source external to the mobile computing device 900. The mobile computing device 900 may also include a physical button 924 for receiving user input. The mobile computing device 900 may also include a power button 926 for turning the mobile computing device 900 on and off.

[0095] Various embodiments (including but not limited to the above reference Figures 1 to 8C The described embodiments) can be implemented in a wide variety of computing systems including a laptop computer 1000, an example of which is shown in FIG. Figure 10 10. Many laptop computers include a trackpad touch surface 1017 that serves as a pointing device for the computer and, therefore, can receive gestures similar to those implemented on computing devices equipped with a touch screen display and as described above, such as drag, scroll, and tap gestures. The laptop computer 1000 will typically include a processor 1002 coupled to volatile memory 1012 and a disk drive 1013 of large-capacity non-volatile memory, such as flash memory. Additionally, the computer 1000 may have one or more antennas 1008 for transmitting and receiving electromagnetic radiation, connectable to a wireless data link, and / or a cellular telephone transceiver 1016 coupled to the processor 1002. The computer 1000 may also include a floppy disk drive 1014 and a compact disk (CD) drive 1015 coupled to the processor 1002. In a notebook configuration, the computer housing includes a trackpad 1017, a keyboard 1018, and a display 1019, all coupled to the processor 1002. Other configurations of computing devices may include a computer mouse or trackball coupled to the processor (eg, via USB input) as is well known, which may also be used in conjunction with various embodiments.

[0096] Various embodiments (including but not limited to the above reference Figures 1 to 8C The described embodiments may also be implemented in a fixed computing system, such as any of a variety of commercially available servers. Figure 11 An example server 1100 is illustrated in FIG. Such a server 1100 typically includes one or more multi-core processor assemblies 1101 coupled to volatile memory 1102 and large-capacity non-volatile storage (such as disk drives 1104). Figure 11As illustrated, multi-core processor assemblies 1101 can be added to the server 1100 by inserting them into the assembly's chassis. The server 1100 may also include a floppy disk drive, compact disk (CD), or digital versatile disk (DVD) disk drive 1106 coupled to the processor 1101. The server 1100 may also include network access ports 1103 coupled to the multi-core processor assembly 1101 for establishing a network interface connection with a network 1105, such as a local area network coupled to other broadcast system computers and servers, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, 5G, LTE, or any other type of cellular data network).

[0097] Computer program code or "program code" for executing on a programmable processor to perform the operations of the various embodiments can be written in a high-level programming language (such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic), a structured query language (e.g., Transact-SQL), Perl, or in various other programming languages. Program code or program stored on a computer-readable storage medium as used in this application can refer to machine language code (such as object code) in a format that can be understood by a processor.

[0098] The following paragraphs describe specific implementations. While some of the following implementations are described in terms of example computing device memory systems, other example implementations may include: the example functionality of a computing device memory system discussed in the following paragraphs implemented as a method of the following implementations; and the example computing device memory system implemented by a computing device memory system discussed in the following paragraphs, the computing device memory system including components for performing the functionality of the computing device memory system of the following implementations.

[0099] Embodiment 1. A method for managing a power distribution network (PDN), the method comprising: determining, by a processor, a first peak current value based on a performance corner of a first request received from a first client powered by a shared power rail within the PDN; determining, by the processor, a second peak current value based on a performance corner of a second request received from a second client powered by the shared power rail within the PDN; determining, by the processor, a system voltage drop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN; and adjusting the voltage of the shared power rail based on the system voltage drop margin.

[0100] Embodiment 2. A method according to embodiment 1, wherein: determining the first peak current value based on the performance corner of the first request by the processor includes: the processor identifying the first peak current value associated with the performance corner of the first request in a lookup table, and determining the second peak current value based on the performance corner of the second request by the processor includes: the processor identifying the second peak current value associated with the performance corner of the second request in the lookup table.

[0101] Example 3. A method according to any one of Examples 1 to 2, wherein determining the system voltage drop margin by the processor based on the first peak current value, the second peak current value and the impedance value of the PDN includes: aggregating the first peak current value and the second peak current value to determine a cumulative peak current value by the processor; and determining the system voltage drop margin by the processor based on the cumulative peak current value and the impedance value of the PDN.

[0102] Embodiment 4. A method according to any one of embodiments 1 to 3, wherein the impedance value of the PDN is based on a maximum operating frequency, the maximum operating frequency being equal to the higher of a first operating frequency of the first requested performance corner and a second operating frequency of the second requested performance corner.

[0103] Example 5. A method according to any one of Examples 1 to 4, the method further comprising: determining, by the processor, a first impedance value associated with the performance corner of the first request, wherein the first impedance value is associated with a first operating frequency of the performance corner of the first request; and determining, by the processor, a second impedance value associated with the performance corner of the second request, wherein the second impedance value is associated with a second operating frequency of the performance corner of the second request.

[0104] Example 6. A method according to Example 5, wherein determining the system voltage drop margin based on the first peak current value, the second peak current value and the impedance value of the PDN by the processor includes: determining a first voltage drop margin based on the first peak current value and the first impedance value by the processor; determining a second voltage drop margin based on the second peak current value and the second impedance value by the processor; and aggregating the first voltage drop margin and the second voltage drop margin to determine the system voltage drop margin by the processor.

[0105] Embodiment 7. The method according to any one of embodiments 1 to 6 further comprising: reducing the system voltage drop margin based on the instantaneous load current rise time of the PDN.

[0106] Embodiment 8. A method according to any one of embodiments 1 to 7, wherein: the performance edge of the first request is included as part of a first voting request received by the processor from the first client, and the performance edge of the second request is included as part of a second voting request received by the processor from the second client.

[0107] Embodiment 9. The method of any one of embodiments 1 to 8, wherein the first requested performance margin and the second requested performance margin are one of a high frequency mode, a low frequency mode, or a lowest frequency mode.

[0108] Embodiment 10. The method according to any one of embodiments 1 to 9 further comprises: receiving, by a processor, a first requested performance corner from a first client powered by a shared power rail within the PDN; and receiving, by the processor, a second requested performance corner from a second client powered by the shared power rail.

[0109] The foregoing method descriptions and process flow charts are provided as illustrative examples only and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As will be appreciated by those skilled in the art, the order of operations in the foregoing embodiments may be performed in any order. Words such as "thereafter," "then," "next," etc. are not intended to limit the order of operations; these words are only used to guide the reader through the description of the method. In addition, any reference to a claim element in the singular (e.g., a reference using the article "a," "an," or "the") should not be construed as limiting the element to the singular.

[0110] The various illustrative logical blocks, modules, circuits, and algorithmic operations described in conjunction with the various embodiments can be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and operations have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Although a skilled person may implement the described functionality in different ways for each specific application, such specific implementation decisions should not be interpreted as causing a departure from the scope of the claims.

[0111] The hardware for implementing the various exemplary logics, logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed with a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof designed to perform the functions described herein. Although a general-purpose processor can be a microprocessor, in an alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Alternatively, some operations or methods can be performed by circuits specific to a given function.

[0112] In one or more embodiments, the functions described can be implemented in hardware, software, firmware or any combination thereof. If implemented in software, each function can be stored as one or more instructions or codes on a non-transient computer-readable medium or a non-transient processor-readable medium. The operation of the method or algorithm disclosed herein can be implemented in a processor-executable software module, which can reside on a non-transient computer-readable or processor-readable storage medium. A non-transient computer-readable or processor-readable storage medium can be any storage medium that can be accessed by a computer or processor. By way of example and not limitation, such non-transient computer-readable or processor-readable media can include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or can be used to store desired program codes in the form of instructions or data structures and any other medium that can be accessed by a computer. Disks and optical disks as used herein include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks and blue discs, wherein disks typically reproduce data magnetically, and optical discs reproduce data optically with lasers. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Additionally, the operations of a method or algorithm may reside as a code and / or instruction or any combination or set of codes and / or instructions on a non-transitory processor-readable medium and / or computer-readable medium that may be incorporated into a computer program product.

[0113] The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the claims. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations described herein, but should be accorded the broadest scope consistent with the appended claims and the principles and novel features disclosed herein.

Claims

1. A method for managing a power distribution network (PDN), the method comprising: determining, by a processor, a first peak current value based on a performance margin of a first request received from a first client powered by a shared power rail within the PDN; determining, by the processor, a second peak current value based on a performance margin of a second request received from a second client powered by the shared power rail; determining, by the processor, a system voltage drop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN; as well as The voltage of the shared power rail is adjusted based on the system voltage droop margin.

2. The method according to claim 1, wherein: determining, by the processor, the first peak current value based on the first requested performance corner includes: the processor identifying, in a lookup table, the first peak current value associated with the first requested performance corner, and Determining, by the processor, the second peak current value based on the second requested performance corner includes identifying, by the processor, in the lookup table, the second peak current value associated with the second requested performance corner.

3. The method according to claim 1 , wherein determining, by the processor, the system voltage drop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN comprises: aggregating the first peak current value and the second peak current value to determine a cumulative peak current value by the processor; as well as The system voltage drop margin is determined by the processor based on the accumulated peak current value and the impedance value of the PDN. 4 . The method of claim 1 , wherein the impedance value of the PDN is based on a maximum operating frequency, the maximum operating frequency being equal to a higher of a first operating frequency of the first requested performance margin and a second operating frequency of the second requested performance margin.

5. The method according to claim 1, further comprising: determining, by the processor, a first impedance value associated with the first requested performance corner, wherein the first impedance value is associated with a first operating frequency of the first requested performance corner; as well as A second impedance value associated with the second requested performance corner is determined by the processor, wherein the second impedance value is associated with a second operating frequency of the second requested performance corner.

6. The method according to claim 5, wherein determining, by the processor, the system voltage drop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN comprises: determining, by the processor, a first voltage drop margin based on the first peak current value and the first impedance value; determining, by the processor, a second voltage drop margin based on the second peak current value and the second impedance value; as well as The first voltage droop margin and the second voltage droop margin are aggregated to determine the system voltage droop margin by the processor.

7. The method according to claim 1, further comprising: The system voltage drop margin is reduced based on an instantaneous load current rise time of the PDN.

8. The method according to claim 1, wherein: The first requested performance corner is included as part of a first voting request received by the processor from the first client, and The second requested performance corner is included as part of a second voting request received by the processor from the second client.

9. The method of claim 1, wherein the first requested performance margin and the second requested performance margin are one of a high frequency mode, a low frequency mode, or a lowest frequency mode.

10. A computing device, comprising: Shared power rails within the power distribution network (PDN); and A processor configured to: determining a first peak current value based on a performance margin of a first request received from a first client powered by the shared power rail; determining a second peak current value based on a performance margin of a second request from a second client powered by the shared power rail; determining a system voltage drop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN; as well as The voltage of the shared power rail is adjusted based on the system voltage droop margin.

11. The computing device of claim 10, wherein the processor is further configured to: determining the first peak current value based on the first requested performance corner by identifying the first peak current value associated with the first requested performance corner in a lookup table, and The second peak current value is determined based on the second requested performance corner by identifying in the lookup table the second peak current value associated with the second requested performance corner.

12. The computing device of claim 10 , wherein the processor is further configured to determine the system voltage droop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN by: aggregating the first peak current value and the second peak current value to determine a cumulative peak current value; and The system voltage drop margin is determined based on the accumulated peak current value and the impedance value of the PDN.

13. The computing device of claim 10, wherein the impedance value of the PDN is based on a maximum operating frequency, the maximum operating frequency being equal to a higher of a first operating frequency of the first requested performance corner and a second operating frequency of the second requested performance corner.

14. The computing device of claim 10, wherein the processor is further configured to: determining a first impedance value associated with the first requested performance corner, wherein the first impedance value is associated with a first operating frequency of the first requested performance corner; and A second impedance value associated with the second requested performance corner is determined, wherein the second impedance value is associated with a second operating frequency of the second requested performance corner.

15. The computing device of claim 14, wherein the processor is further configured to determine the system voltage droop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN by: determining a first voltage drop margin based on the first peak current value and the first impedance value; determining a second voltage drop margin based on the second peak current value and the second impedance value; as well as The first voltage droop margin and the second voltage droop margin are aggregated to determine the system voltage droop margin.

16. The computing device of claim 10, wherein the processor is further configured to: The system voltage drop margin is reduced based on an instantaneous load current rise time of the PDN.

17. The computing device of claim 10, wherein: The first requested performance corner is included as part of a first voting request received by the processor from the first client, and The second requested performance corner is included as part of a second voting request received by the processor from the second client.

18. The computing device of claim 10, wherein the first requested performance margin and the second requested performance margin are one of a high frequency mode, a low frequency mode, or a lowest frequency mode.

19. A computing device, comprising: Shared power rails within the power distribution network (PDN); means for determining a first peak current value based on a performance margin of a first request received from a first client powered by the shared power rail; means for determining a second peak current value based on a second requested performance corner received from a second client powered by the shared power rail; means for determining a system voltage drop margin based on the first peak current value, the second peak current value and an impedance value of the PDN; and Means for adjusting a voltage of the shared power rail based on the system voltage droop margin.

20. The computing device of claim 19, wherein: The means for determining the first peak current value based on the first requested performance corner comprises: means for identifying the first peak current value associated with the first requested performance corner in a lookup table, and The means for determining the second peak current value based on the second requested performance corner includes means for identifying, in the lookup table, the second peak current value associated with the second requested performance corner.

21. The computing device of claim 19, wherein the means for determining the system voltage drop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN comprises: means for aggregating the first peak current value and the second peak current value to determine a cumulative peak current value; and means for determining the system voltage drop margin based on the accumulated peak current value and the impedance value of the PDN.

22. A non-transitory processor-readable medium having stored thereon processor-executable instructions configured to cause a processor of a computing device to perform operations comprising: determining a first peak current value based on a performance margin of a first request received from a first client powered by the shared power rail; determining a second peak current value based on a second requested performance margin received from a second client powered by the shared power rail; determining a system voltage drop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN; as well as The voltage of the shared power rail is adjusted based on the system voltage droop margin.

23. The non-transitory processor-readable medium of claim 22, wherein the stored processor-executable instructions are configured to cause the processor to perform operations such that: Determining the first peak current value based on the performance margin of the first request includes: identifying in a lookup table the first peak current value associated with the first requested performance corner, and Determining the second peak current value based on the second requested performance corner includes identifying the second peak current value associated with the second requested performance corner in the lookup table.

24. The non-transitory processor-readable medium of claim 22, wherein the stored processor-executable instructions are configured to cause the processor to perform operations such that determining the system voltage droop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN comprises: aggregating the first peak current value and the second peak current value to determine a cumulative peak current value; as well as The system voltage drop margin is determined based on the accumulated peak current value and the impedance value of the PDN.

25. The non-transitory processor-readable medium of claim 22, wherein the impedance value of the PDN is based on a maximum operating frequency, the maximum operating frequency being equal to a higher of a first operating frequency of the first requested performance corner and a second operating frequency of the second requested performance corner.

26. The non-transitory processor-readable medium of claim 22, wherein the stored processor-executable instructions are configured to cause the processor to perform operations further comprising: determining a first impedance value associated with the first requested performance corner, wherein the first impedance value is associated with a first operating frequency of the first requested performance corner; as well as A second impedance value associated with the second requested performance corner is determined, wherein the second impedance value is associated with a second operating frequency of the second requested performance corner.

27. The non-transitory processor-readable medium of claim 26 , wherein the stored processor-executable instructions are configured to cause the processor to perform operations such that determining the system voltage droop margin based on the first peak current value, the second peak current value, and the impedance value of the PDN comprises: determining a first voltage drop margin based on the first peak current value and the first impedance value; determining a second voltage drop margin based on the second peak current value and the second impedance value; as well as The first voltage droop margin and the second voltage droop margin are aggregated to determine the system voltage droop margin.

28. The non-transitory processor-readable medium of claim 22, wherein the stored processor-executable instructions are configured to cause the processor to perform operations further comprising: The system voltage drop margin is reduced based on an instantaneous load current rise time of the PDN.

29. The non-transitory processor-readable medium of claim 22, wherein: The first requested performance corner is included as part of a first voting request received by the processor from the first client, and The second requested performance corner is included as part of a second voting request received by the processor from the second client.

30. The non-transitory processor-readable medium of claim 22, wherein the first requested performance margin and the second requested performance margin are one of a high frequency mode, a low frequency mode, or a lowest frequency mode.

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