Providing content-aware cache replacement and insertion policies in processor-based devices

Abstract

Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device includes a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value based on the plurality of content costs. The cache controller circuit is further configured to evict the target cached data value from the cache memory device.

Description

[0001] Priority Application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 163,446, entitled “PROVIDING CONTENT-AWARE CACHE REPLACEMENT AND INSERTION POLICIES IN PROCESSOR-BASED DEVICES,” filed February 2, 2023, which is incorporated by reference herein in its entirety. BACKGROUND

[0003] I. TECHNICAL FIELD

[0004] The technology of this disclosure relates generally to the use of cache memory devices in processor-based devices, and specifically to cache replacement and insertion policies.

[0005] II. BACKGROUND

[0006] Processor-based devices are subject to a phenomenon known as memory access latency, which is the time interval between the time a processor initiates a memory access request for data (i.e., by executing a memory load instruction) and the time the processor actually receives the requested data. If the memory access latency for a memory access request is large enough, the processor can be forced to stop further execution of instructions while waiting for the memory access request to complete. One method of minimizing the impact of memory access latency is to use a cache memory device (also simply referred to as a “cache”). A cache is a memory device that has a smaller capacity than system memory, but can be accessed more quickly by the processor due to the type of memory used and / or the physical location of the cache relative to the processor. Caches can be used to store copies of data that are frequently accessed from system memory (or retrieved from higher level caches such as a last level cache (LLC)), thereby reducing memory access latency.

[0007] Because of the limited capacity of a cache, the cache can quickly fill up with copies of recently retrieved data. In such cases, the processor-based device can need to select a cache entry within the cache to evict and replace with newly retrieved data, and / or determine whether to fully cache the results of a particular memory access request. To select a cache entry to evict, the processor-based device can employ any of a variety of cache replacement policies, including as non-limiting examples, a round robin, least recently used (LRU), and most recently used (MRU) cache replacement policy. However, for some caches, such as an LLC, the miss rate associated with the cache can be less sensitive to different cache replacement policies, such that selection of a given cache replacement policy can have little effect on the number of misses in cache usage. Moreover, conventional cache replacement and insertion policies can have limited impact on other costs associated with memory access requests, such as increased energy consumption associated with data movement of particular data values within the processor and / or between the processor and system memory. SUMMARY

[0008] Aspects disclosed in the detailed description include providing content-aware cache replacement and insertion policies in a processor-based device. Related apparatus and methods are also disclosed. In this regard, in some example aspects disclosed herein, a processor-based device provides a cache memory device and a cache controller circuit associated with the cache memory device. The cache controller circuit is configured to select a cached data value for eviction from the cache memory device based on a content cost of the cached data value, such that cached data values having a lower content cost are evicted earlier. As used herein, the "content cost" of a data value refers to a numerical value corresponding to the energy consumption of the processor-based device based on the bit values of the multiple bits of the data value, such as the energy consumption in storing and / or transmitting the data value.

[0009] Accordingly, when the cache controller circuit determines that eviction from the cache memory device is required, the cache controller circuit determines a content cost for each of a plurality of cached data values (e.g., cached data values stored in a bank of the cache memory device) in the cache memory device. Each content cost is determined based on bit values of a plurality of bits of each corresponding cached data value. For example, in some aspects, each content cost can include a count of occurrences of a specified bit value (e.g., a value of one (1) or a value of zero (0)) in the plurality of bit values of the corresponding cached data value. Some aspects can provide that each content cost can include a count of changes of each bit value in the plurality of bit values of the most recently evicted data value compared to the bit values of the corresponding cached data value. The cache controller circuit uses the content costs to identify a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit then evicts the target cached data value from the cache memory device. In this way, the cache controller circuit implements a content-aware cache replacement policy that ensures that subsequent transmission and / or re-storing of the evicted data value will incur a lower energy cost, while preserving cached data values that would incur a greater energy cost if transmitted and / or stored.

[0010] Some aspects can provide that the cache controller circuit can receive a data value to be cached and can also determine a content cost for the data value. In some such aspects, prior to identifying a target cached data value, the cache controller circuit can determine whether all of the plurality of content costs for the cached data values have the same value (i.e., whether there is no particular cached data value that can be transmitted from and / or stored in system memory at a lower energy cost than any other cached data value). If so, the cache controller circuit can identify the target cached data value using an alternative cache replacement policy (e.g., using a "least recently used" cache replacement policy, as a non-limiting example). According to some such examples, if the cache controller circuit determines that not all of the plurality of content costs have the same value, the cache controller circuit can further determine whether the content cost for the data value to be cached is lower than all of the plurality of content costs (i.e., whether the data value to be cached has a lower energy cost than any of the cached data values). If so, the cache controller circuit can bypass caching of the data value.

[0011] In some aspects, the cache controller circuitry can receive a cache hint based on a plurality of bit values of a data value to be cached (e.g., received from a client device such as a neural signal processor (NSP), by way of non-limiting example). The cache hint can include, for example, an indication that the data value is associated with a relatively higher content cost or memory access latency, or a relatively lower content cost or memory access latency, such that the data value should or should not be cached by the cache controller circuitry, respectively. In such aspects, the cache controller circuitry can then determine whether to cache the data value based on the cache hint or bypass caching of the data value based on the cache hint.

[0012] In another aspect, a processor-based device is provided. The processor-based device includes a cache memory device and cache controller circuitry of the cache memory device. The cache controller circuitry is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuitry is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuitry is further configured to evict the target cached data value from the cache memory device.

[0013] In another aspect, a processor-based device is provided. The processor-based device includes means for determining a plurality of content costs for each of a plurality of cached data values in a cache memory device based on a plurality of bit values of each of the plurality of cached data values. The processor-based device further includes means for identifying, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The processor-based device further includes means for evicting the target cached data value from the cache memory device.

[0014] In another aspect, a method for providing content-aware cache replacement and insertion policies in a processor-based device is provided. The method includes determining, by cache controller circuitry, a plurality of content costs for each of a plurality of cached data values in a cache memory device based on a plurality of bit values of each of the plurality of cached data values. The method also includes identifying, by cache controller circuitry, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value based on the plurality of content costs. The method also includes evicting, by cache controller circuitry, the target cached data value from the cache memory device.

[0015] In another aspect, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium stores computer-executable instructions thereon that, when executed, cause a processor to determine a plurality of content costs for each of a plurality of cached data values in a cache memory device based on a plurality of bit values of each of the plurality of cached data values. The computer-executable instructions also cause the processor to identify a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value based on the plurality of content costs. The computer-executable instructions also cause the processor to evict the target cached data value from the cache memory device. BRIEF DESCRIPTION OF DRAWINGS

[0016] FIG. 1 is a block diagram illustrating an exemplary processor-based device including a cache memory device and associated cache controller circuitry configured to provide content-aware cache replacement and insertion policies in accordance with some aspects;

[0017] FIG. 2A-2B is a block diagram illustrating cache controller circuitry of FIG. 1 using a content-aware cache replacement policy under which content costs are computed based on a number of occurrences of bit values of one (1) in a cached data value;

[0018] FIG. 3A-3B is a block diagram illustrating cache controller circuitry of FIG. 1 using a content-aware cache replacement policy under which content costs are computed based on a number of occurrences of bit values of zero (0) in a cached data value;

[0019] FIG. 4A-4B is a block diagram illustrating cache controller circuitry of FIG. 1a cache controller circuit that uses a content-aware cache replacement policy under which a content cost is calculated based on a number of changes in bit values of recently evicted data values compared to bit values of cached data values;

[0020] FIG. 5A-5D is an example of a cache controller circuit that provides content-aware cache replacement and insertion policies in accordance with some aspects; FIG. 1 is a flowchart of exemplary operations of a cache controller circuit that provides content-aware cache replacement and insertion policies; and

[0021] FIG. 6 is an example of a processor-based device that can include FIG. 1 is a block diagram of an example processor-based device based on the processor-based device of DETAILED DESCRIPTION

[0022] Referring now to the drawings, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0023] Aspects disclosed in the detailed description include providing content-aware cache replacement and insertion policies in a processor-based device. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a processor-based device provides a cache memory device and a cache controller circuit associated with the cache memory device. The cache controller circuit is configured to select a cached data value for eviction from the cache memory device based on a content cost of the cached data value such that cached data values having lower content costs are evicted earlier. As used herein, the “content cost” of a data value refers to a numerical value corresponding to processor-based device energy consumption resulting from bit values of a plurality of bits of the data value, such as energy consumption in storing and / or transmitting the data value.

[0024] Accordingly, when the cache controller circuit determines that eviction from the cache memory device is required, the cache controller circuit determines a content cost for each of a plurality of cached data values (e.g., cached data values stored in a bank of the cache memory device) in the cache memory device. Each content cost is determined based on bit values of a plurality of bits of each corresponding cached data value. For example, in some aspects, each content cost can include a count of occurrences of a specified bit value (e.g., a value of one (1) or a value of zero (0)) in the plurality of bit values of the corresponding cached data value. Some aspects can provide that each content cost can include a count of changes of each bit value in the plurality of bit values of the most recently evicted data value compared to the bit values of the corresponding cached data value. The cache controller circuit uses the content costs to identify a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit then evicts the target cached data value from the cache memory device. In this way, the cache controller circuit implements a content-aware cache replacement policy that ensures that subsequent transmission and / or re-storing of the evicted data value will incur a lower energy cost, while preserving cached data values that would incur a greater energy cost if transmitted and / or stored.

[0025] Some aspects can provide that the cache controller circuit can receive a data value to be cached, and can also determine a content cost for the data value. In some such aspects, prior to identifying a target cached data value, the cache controller circuit can determine whether all of the plurality of content costs for the cached data values have the same value (i.e., whether there is no particular cached data value that can be transmitted from and / or stored in system memory at a lower energy cost than any other cached data value). If so, the cache controller circuit can identify the target cached data value using an alternative cache replacement policy (e.g., using a "least recently used" cache replacement policy, as a non-limiting example). According to some such examples, if the cache controller circuit determines that not all of the plurality of content costs have the same value, the cache controller circuit can further determine whether the content cost for the data value to be cached is lower than all of the plurality of content costs (i.e., whether the data value to be cached has a lower energy cost than any of the cached data values). If so, the cache controller circuit can bypass caching of the data value.

[0026] In some aspects, the cache controller circuit can receive a cache hint based on a plurality of bit values of a data value to be cached (e.g., received from a client device such as a neural signal processor (NSP), among other examples). The cache hint can include, for example, an indication that the data value is associated with a relatively higher content cost or memory access latency, or a relatively lower content cost or memory access latency, and thus should or should not be cached by the cache controller circuit, respectively. In such aspects, the cache controller circuit can then determine whether to cache the data value based on the cache hint or bypass caching of the data value based on the cache hint.

[0027] In this regard, FIG. 1 An exemplary processor-based device 100 is illustrated that provides a processor 102 for providing content-aware cache replacement and insertion policies. In some aspects, the processor 102 can include a central processing unit (CPU) having one or more processor cores, and in some exemplary aspects, can be one of a plurality of similarly configured processors (not shown) of the processor-based device 100. The processor 102 is communicatively coupled to an interconnect bus 104, which in some embodiments can include additional constituent elements (e.g., bus controller circuitry and / or arbitration circuitry, among other examples) not shown in FIG. 1 for the sake of clarity. FIG. 1

[0028] The processor 102 is also communicatively coupled to a memory controller 106 via the interconnect bus 104, which controls access to a system memory device 108 and manages data flow to and from the system memory device 108. The system memory device 108 provides addressable memory for data storage by the processor-based device 100, and thus can include, by way of non-limiting example, dynamic random access memory (DRAM). FIG. 1 The processor 102 of FIG. 1 also includes a cache memory device 110, which can be used to cache local copies of frequently accessed data within the processor 102 for faster access. In some aspects, the cache memory device 110 can include, for example, a level 1 (LI) cache. FIG. 1 The processor 102 of the example of FIG. 1 is also communicatively coupled to a cache memory device (in this example, the cache memory device 110) via the interconnect bus 104. FIG. 1 ​The cache memory device 112 (labeled as "cache") may include, for example, a Level 2 (L2) cache, a Level 3 (L3) cache, or a Last Level (LLC) cache. The cache memory devices 110 and 112 together constitute a hierarchical cache structure used by the processor-based device 100 to cache frequently accessed data for faster retrieval (compared to retrieving data from the system memory device 108).

[0029] like FIG. 1 As shown, the cache memory device 110 is divided into multiple groups (in FIG. 1 The groups are labeled "groups" 114(0)-114(S), each group including multiple paths, such as paths (in... FIG. 1 The cache memory device 110 is configured to support corresponding levels of associativity, with each of the multiple paths 116(0)-116(W) and 116'(0)-116'(W) in the group 114(0)-114(S) configured to store cached data values, such as cached data values ​​118(0)-118(W) of path 116(0)-116(W), representing data previously retrieved from system memory device 108 or from a higher-level cache such as cache memory device 112. Each cached data value 118(0)-118(W) may each include, for example, a cache line and may be associated with a tag (not shown) storing information that enables the corresponding cache line to be mapped to a unique memory address. It will be understood that the cached data values ​​118(0)-118(W) of the cache memory device 110 may also be associated with other data elements, such as validity indicators and / or dirty data indicators, which are not included for clarity. FIG. 1 As shown in the image.

[0030] FIG. 1 The processor-based device 100 may encompass any of known digital logic elements, semiconductor circuits, processing cores and / or memory structures, as well as other elements or combinations thereof. The embodiments described herein are not limited to any particular arrangement of elements, and the disclosed techniques can be readily extended to various structures and layouts on semiconductor sockets or packages. It will be understood that some embodiments of the processor-based device 100 may include more than FIG. 1 The processor 102 may include more or fewer components as shown. For example, it may also include more or fewer memory devices, execution pipeline stages, controller circuitry, registers, and / or caches, which are omitted for clarity. FIG. 1 Omit.

[0031] As mentioned above, caches such as cache memory devices 110 and 112 can be used to minimize the impact of memory access latency encountered by processor 102 when performing memory access operations on system memory device 108 or a higher-level cache such as cache memory device 112. However, for some caches, the choice of cache replacement strategy may have little impact on the miss rate of processor-based device 100 when using the cache. Furthermore, conventional cache replacement and insertion strategies do not take into account other costs that may be associated with memory access requests. In some respects, one such cost is the energy cost associated with data movement within processor 102 or between processor 102 and system memory device 108 and / or data storage in system memory device 108. For example, when transferring data, a device such as a DRAM module using off-chip termination interconnects may consume energy only when transferring bit value one (1) and not when transferring bit value zero (0). In contrast, devices such as System-on-Chip (SoC) that employ unterminated on-chip interconnects consume energy only when bit values ​​are transitioned from one value to another (i.e., from value zero (0) to value one (1) and vice versa). Similarly, some memory devices may consume more refresh energy when storing data values ​​that include more bit values ​​one (1) than bit values ​​zero (0).

[0032] Therefore, in this respect, processor 102 provides cache controller circuitry 120 to provide content-aware cache replacement and insertion strategies. FIG. 1 In the example shown, cache controller circuitry 120 is depicted as a separate element from cache memory device 110. However, it will be understood that in some respects, cache controller circuitry 120 may be provided as an integral part of cache memory device 110, or vice versa. Cache controller circuitry 120 is configured to employ content-based costing (CBC)... FIG. 1 The content-aware cache replacement strategy is labeled as “Cached Data Value Content Cost” 122(0)-122(W). These content costs are calculated based on cached data values ​​such as cached data values ​​118(0)-118(W) and are used to select one of the cached data values ​​118(0)-118(W) with the lowest content cost 122(0)-122(W) as the target cached data value to be evicted.

[0033] The content costs 122(0)-122(W) are determined by the cache controller circuit 120 based on bit values of a plurality of bits (not shown) of each cached data value. The calculation of the content costs 122(0)-122(W) varies from implementation to implementation, depending on how the processor-based device 100 consumes energy in transferring and / or storing each bit value. For example, in some aspects, each of the content costs 122(0)-122(W) can include a count of occurrences of a specified bit value (e.g., a value of one (1) or a value of zero (0)) among the plurality of bit values of the corresponding cached data value 118(0)-118(W). In some such aspects, the content costs 122(0)-122(W) can be compared to a content cost (annotated as "data value content cost" in FIG. 2A-2B FIG. 2) 124 of the data value 126 received by the cache controller circuit 120 to be cached. Examples of determining the content costs 122(0)-122(W) according to these aspects are discussed in more detail below with respect to FIG. 3A-3B and FIG. 4A-4B

[0034] Some aspects can provide that the cache controller circuit 120 is configured to track a recently evicted data value 128 that represents a value of a recently evicted cached data value from the cache memory device 110. In such aspects, the content costs 122(0)-122(W) can include a count of changes of each bit value of a plurality of bit values (not shown) of the recently evicted data value 128 compared to a corresponding bit value among a plurality of bit values of each of the cached data values 118(0)-118(W). Examples of determining the content costs 122(0)-122(W) according to these aspects are discussed in more detail below with respect to FIG. 1

[0035] ​​The cache controller circuit 120 identifies a target cached data value 118(0) as the cached data value 118(0) associated with the lowest content cost of the plurality of cached data values 118(0)-118(W) using the content costs 122(0)-122(W) as a non-limiting example. The cache controller circuit 120 then evicts the target cached data value 118(0) from the cache memory device 110. By evicting the target cached data value 118(0) having the lowest content cost of the content costs 122(0)-122(W), the cache controller circuit 120 can ensure that the processor-based device 100 will produce a lower energy consumption when the target cached data value 118(0) is subsequently re-transmitted and / or re-stored, while preserving the cached data values 118(1)-118(W) that would produce a greater energy cost if re-transmitted and / or re-stored.

[0036] As mentioned above, in some aspects, the cache controller circuit 120 can receive a data value 126 to be cached and can determine a content cost 124 of the data value 126. In some such aspects, prior to identifying the target cached data value 118(0), the cache controller circuit 120 can determine whether all of the plurality of content costs 122(0)-122(W) of the cached data values 118(0)-118(W) have the same value. If so, this indicates that none of the cached data values 118(0)-118(W) can be retrieved or transmitted at a lower energy cost than any of the other cached data values 118(0)-118(W). Accordingly, in such aspects, the cache controller circuit 120 can identify the target cached data value using an alternative cache replacement policy, such as a least recently used cache replacement policy as a non-limiting example. Some such examples can further provide that if the cache controller circuit 120 determines that not all of the content costs 122(0)-122(W) have the same value, the cache controller circuit 120 can determine whether the content cost 124 of the data value 126 to be cached is lower than all of the plurality of content costs 122(0)-122(W). This indicates that the data value 126 to be cached can be retrieved or transmitted at a lower energy cost than any of the cached data values 118(0)-118(W). In this case, the cache controller circuit 120 can bypass caching of the data value 126.

[0037] According to some aspects, a client device (not shown) that is the source of the data value 126 received by cache controller circuitry 120 may provide cache hints 130 based on multiple bit values ​​of the data value 126. For example, in the aspect where the client device is an NSP, the NSP may determine that the content of the data value 126 (e.g., lookup table, neural network weights, or similar content) is biased towards containing more of a particular data value (e.g., more zeros (0) than ones (1), or vice versa). Thus, the client device may provide cache hints 130 to cache controller circuitry 120 to indicate that the data value 126 is associated with a relatively high content cost or memory access latency, or with a relatively low content cost or memory access latency (and thus the data value 126 should or should not be cached by cache controller circuitry 120, respectively). Based on cache hints 130, in these aspects, cache controller circuitry 120 may subsequently determine whether to cache the data value 126 based on cache hints 130 or to bypass caching of the data value 126.

[0038] As mentioned above, the content cost 122(0)-122(W) is determined based on multiple bit values ​​of the cached data values ​​118(0)-118(W), and in some respects, can be compared with the content cost 124 of data value 126 when providing a content-aware cache replacement strategy. For illustration... FIG. 2A-2B In the case where the cache controller circuit 120 uses a content-aware cache replacement strategy, under which the content cost 122(0)-122(W) is calculated based on the number of occurrences of the bit value 1 (1) in the cached data values ​​118(0)-118(W), this paper provides FIG. 2A .exist FIG. 1 In the middle, the data value 126 will be... FIG. 1 The cache controller circuit 120 caches data in group 114(0) of the cache memory device 110, thus caching one of the cached data values ​​118(0)-118(3) (i.e., FIG. 2A-2B The cached data values ​​118(0)-118(W), where for illustration purposes, W=3), will be identified as the target cached data values ​​to be evicted. For the simplicity of the example shown, data value 126 and cached data values ​​118(0)-118(3) are each shown as comprising four (4) bits; however, it will be understood that some aspects may specify that data value 126 and cached data values ​​118(0)-118(3) comprise more than four (4) bits. Additionally, for clarity, from FIG. 2A The path 116(0)-116(W) that stores the cached data value 118(0)-118(W) is omitted.

[0039] existFIG. 2B In the example of FIG. 1, cache controller circuit 120 determines content cost 124 of data value 126 based on bit values 200(0)-200(3) of data value 126. Cache controller circuit 120 also determines content costs 122(0)-122(3) of corresponding cached data values 118(0)-118(3) based on respective bit values 202(0)-202(3), 204(0)-204(3), 206(0)-206(3), and 208(0)-208(3). Since the content-aware cache replacement policy applied in this example is based on the number of occurrences of bit value one (1), content cost 124 of data value 126 is determined to have a value of three (3), while content costs 122(0)-122(3) of cached data values 118(0)-118(3) are determined to have values of two (2), one (1), four (4), and two (2), respectively. Cached data value 118(1) is thus identified as having the lowest content cost 122(1), and cache controller circuit 120 thus identifies cached data value 118(1) as target cached data value 118(1). As shown in FIG. 1, cache controller circuit 120 evicts target cached data value 118(1), and installs data value 126 as new cached data value 118(1). FIG. 3A-3B

[0040] FIG. 1 Example FIG. 2A-2B Cache controller circuit 120 uses a content-aware cache replacement policy in the example of FIG. 2 that is similar to that of FIG. 1, but differs in that content costs 122(0)-122(W) are computed based on the number of occurrences of bit value zero (0) in cached data values 118(0)-118(W). As shown in FIG. 2, bit values 200(0)-200(3) of data value 126 to be cached, and bit values 202(0)-202(3), 204(0)-204(3), 206(0)-206(3), and 208(0)-208(3) of corresponding cached data values 118(0)-118(3) have FIG. 3A-3B FIG. 2A FIG. 3B ​​​The same values ​​are shown in the example. Since the content-aware cache replacement strategy applied in this example is based on the number of occurrences of the bit value zero (0), the content cost 124 of data value 126 is determined to have a value of one (1), while the content costs 122(0)-122(3) of cached data values ​​118(0)-118(3) are determined to have values ​​of two (2), three (3), zero (0), and two (2), respectively. Therefore, the cache controller circuit 120 in this example identifies the cached data value 118(2) as having the lowest content cost 122(2), and the cache controller circuit 120 thus identifies the cached data value 118(2) as the target cached data value 118(2). FIG. 4A-4B As shown, the cache controller circuit 120 evicts the target cached data value 118(2) and installs the data value 126 as the new cached data value 118(2).

[0041] FIG. 1 Example FIG. 1 In the case where the cache controller circuit 120 uses a content-aware cache replacement strategy, each content cost in content costs 122(0)-122(W) includes FIG. 4A-4B The count of the number of changes in the bit values ​​of the most recently evicted data value 128 in the multiple bit values ​​400(0)-400(3) compared to the corresponding bit values ​​202(0)-202(3), 204(0)-204(3), 206(0)-206(3), and 208(0)-208(3) of the corresponding cached data values ​​118(0)-118(3). FIG. 2A In the data value 126 to be cached, the bit values ​​200(0)-200(3) and the corresponding cached data values ​​118(0)-118(3), the bit values ​​202(0)-202(3), 204(0)-204(3), 206(0)-206(3) and 208(0)-208(3), have FIG. 4BThe same value is shown in the figure. In order to calculate the content cost 122(0) of cached data value 118(0), for example, the bit values ​​400(0)-400(3) of the most recently evicted data value 128 are compared with the bit values ​​202(0)-202(3), and the number of bit value changes between the corresponding bits is counted. Although bit value 400(0) is the same as bit value 202(0) (i.e., zero (0)) and bit value 400(1) is the same as bit value 202(1) (i.e., one (1)), bit values ​​400(2) and 202(2) and bit values ​​400(3) and 202(3) each represent the bit value changes (from one (1) to zero (0) and from zero (0) to one (1) respectively). Therefore, the content cost 122(0) of cached data value 118(0) is determined to be two (2). Similarly, content costs 122(1)-122(3) are determined to have values ​​one (1), two (2), and two (2), respectively. Therefore, the cache controller circuit 120 in this example identifies the cached data value 118(1) as having the lowest content cost 122(1), and the cache controller circuit 120 thus identifies the cached data value 118(1) as the target cached data value 118(1). FIG. 1 As shown, the cache controller circuit 120 evicts the target cached data value 118(1) and installs the data value 126 as the new cached data value 118(1).

[0042] To further describe FIG. 5A-5D The cache controller circuit 120 is used to provide operation of content-aware cache replacement and insertion strategies. FIG. 5A-5D A flowchart illustrating exemplary operation 500 is provided. For clarity, in the description... FIG. 1 When quoted FIG. 2A-2B , FIG. 3A-3B , FIG. 4A-4B and FIG. 5A-5D The components. It will be understood that some aspects can be specified, FIG. 5A Some of the operations shown may be performed in a different order than those illustrated in this document and / or may be omitted. FIG. 1 In some aspects, exemplary operation 500 is from FIG. 1 The processor 102 (e.g., using) FIG. 1 The cache controller circuit 120) identifies multiple groups of cache memory devices used to store data values ​​(e.g., FIG. 2A-2B , FIG. 3A-3B and FIG. 1 The data value 126) is cached in one of the sets (e.g., FIG. 1The multiple sets of 114(0)-114(S) cache memory devices 110 begin with set 114(0) (box 502). In this respect, cache controller circuitry 120 may subsequently identify the corresponding multiplexer stored in set 114(0) (e.g., FIG. 2A-2B Multiple cached data values ​​in multiple paths 116(0)-116(W)) (e.g., FIG. 3A-3B , FIG. 4A-4B and FIG. 1 Multiple cached data values ​​118(0)-118(3) (Box 504).

[0043] Based on factors such as calculating content cost (e.g., the number of changes in the bit value of the most recently evicted data value compared to the bit value of a cached data value), the cache controller circuit 120 can determine the most recently evicted data value, such as... FIG. 4A-4B and FIG. 1 The most recently evicted data value is 128 (box 506). Some aspects may specify that the cache controller circuit 120 receives data values ​​to be cached, such as... FIG. 2A-2B , FIG. 3A-3B , FIG. 4A-4B and FIG. 2A-2B The data value 126 (box 508). In some aspects, the cache controller circuit 120 may be based on multiple bit values ​​of the data value 126 (e.g., FIG. 3A-3B , FIG. 4A-4B and FIG. 1 The bit value 200(0)-200(3)) receives cache hints (e.g., FIG. 5B The cache hint 130 (box 510). In this respect, the cache controller circuit 120 may then determine, based on the cache hint 130, whether to cache the data value 126 (box 512). If not, the cache controller circuit 120 will bypass caching of the data value 126 (box 514). However, if the cache controller circuit 120 determines at decision box 512 that the data value 126 should be cached (or if the cache controller circuit 120 embodies the aspect of not using the cache hint 130), then exemplary operation 500 in FIG. 5B Continue at frame 516.

[0044] See now FIG. 1 In some respects, exemplary operation 500 continues, and cache controller circuitry 120 determines the content cost of data value 126 (e.g., FIG. 2A-2B , FIG. 3A-3B , FIG. 4A-4B and FIG. 2A-2BContent cost 124 (box 516). Cache controller circuit 120 is based on multiple bit values ​​(e.g., ...) of each cached data value in a plurality of cached data values ​​118(0)-118(W) in cache memory device 110. FIG. 3A-3B , FIG. 4A-4B and FIG. 1 The multiple bit values ​​202(0)-202(3)) determine the multiple content costs (e.g., for each cached data value in the multiple cached data values ​​118(0)-118(W)) FIG. 2A-2B , FIG. 3A-3B , FIG. 4A-4B and FIG. 4A-4B The multiple content costs 122(0)-122(W) (box 518). In some aspects, the operation of box 518 for determining the multiple content costs 122(0)-122(W) may include: each of the multiple content costs 122(0)-122(W) includes a count of the occurrence of a specified bit value among multiple bit values ​​202(0)-202(3) of cached data values ​​in multiple cached data values ​​118(0)-118(W) (box 520). In some aspects, the operation of box 518 for determining the multiple content costs 122(0)-122(W) may include: each of the multiple content costs 122(0)-122(W) includes multiple bit values ​​of the most recently evicted data value 128 (e.g., FIG. 5C The count of the number of changes of each bit value in the plurality of bit values ​​400(0)-400(3) compared with the corresponding bit value in the plurality of cached data values ​​202(0)-202(3) of the plurality of cached data values ​​118(0)-118(W) (box 522). In some aspects, exemplary operation 500 then in FIG. 5C Continue at frame 524.

[0045] Now go to FIG. 1 Continuing with exemplary operation 500: Cache controller circuitry 120 determines whether all content costs in a plurality of content costs 122(0)-122(W) have the same value (box 524). If so, cache controller circuitry 120 uses an alternative cache replacement strategy to replace cached data values ​​in a plurality of cached data values ​​118(0)-118(W) (e.g., ...). FIG. 2A-2B , FIG. 3A-3B , FIG. 4A-4B and FIG. 5Dthe cache controller circuit 120 determines that the content cost 124 of the data value 126 is not lower than all of the plurality of content costs 122(0)-122(W), the example operations 500 continue at block 532. FIG. 5D

[0046] Now continuing to refer to FIG. 1 , the example operations 500 continue: the cache controller circuit identifies, based on the plurality of content costs 122(0)-122(W), a target cached data value among the plurality of cached data values 118(0)-118(W) associated with a lowest content cost (e.g., the cached data value 118(0) associated with the content cost 122(0) of the plurality of content costs 122(0)-122(W)), as the target cached data value (block 532). The cache controller circuit 120 then evicts the target cached data value 118(0) from the cache memory device 110 (block 534). FIG. 2A-2B , FIG. 3A-3B , FIG. 4A-4B and FIG. 2A-2B the content cost 122(0) of the plurality of content costs 122(0)-122(W)), as the target cached data value 118(0) (block 532). The cache controller circuit 120 then evicts the target cached data value 118(0) from the cache memory device 110 (block 534). FIG. 3A-3B , FIG. 4A-4B and FIG. 6 the content cost 122(0) of the plurality of content costs 122(0)-122(W)), as the target cached data value 118(0) (block 532). The cache controller circuit 120 then evicts the target cached data value 118(0) from the cache memory device 110 (block 534).

[0047] ​Providing content-aware cache replacement and insertion policies in a processor-based device as disclosed in aspects described herein can be provided in or integrated into any processor-based device. Non-limiting examples include a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a laptop computer, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a transportation ballast, an avionics system, a drone, and a multicopter.

[0048] In this regard, FIG. 1 An example of a processor-based device 600 is illustrated that can include FIG. 6 The processor-based device 100 is shown. In this example, the processor-based device 600 includes a processor 602 that includes one or more central processing units (annotated as "CPU" in FIG. 6 ) 604, which can also be referred to as CPU cores or processor cores. The processor 602 can have cache memory 606 coupled to the processor 602 for rapid access to temporarily stored data. The processor 602 is coupled to a system bus 608 and can intercouple master and slave devices included in the processor-based device 600. As is well known, the processor 602 communicates with these other devices by exchanging address, control, and data information over the system bus 608. For example, the processor 602 can communicate bus transaction requests to an example of a master device, the memory controller 610. Although not shown, multiple system buses 608 could be provided, wherein each system bus 608 constitutes a different fabric. FIG. 6 Multiple system buses 608 could be provided, wherein each system bus 608 constitutes a different fabric.

[0049] Other master and slave devices can be connected to the system bus 608. As FIG. 6As illustrated in the example of FIG. 6, the devices can include, as examples, a memory system 612 (including a memory controller 610 and a memory array 614), one or more input devices 616, one or more output devices 618, one or more network interface devices 620, and one or more display controllers 622. The input devices 616 can include any type of input devices, including, but not limited to, input keys, switches, voice processors, etc. The output devices 618 can include any type of output devices, including, but not limited to, audio, video, other visual indicators, etc. The network interface devices 620 can be any devices configured to allow exchange of data to and from a network 624. The network 624 can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH® network, and the Internet. The network interface devices 620 can be configured to support any type of communications protocol desired. ™

[0050] The processor 602 can also be configured to access the display controller(s) 622 over the system bus 608 to control the information sent to the one or more displays 626. The display controller(s) 622, in turn, can control the information sent to the displays 626. The display controller(s) 622 and / or the video processor(s) 628 can include a GPU or be integrated into a GPU. The displays 626 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma, etc.

[0051] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such

[0052] ​The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0053] The aspects disclosed herein can be embodied in hardware and in instructions stored in hardware, and can reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. In the alternative, the processor and the storage medium can reside as discrete components in a remote station, a base station, or a server.

[0054] Note also that the operational steps described in any of the example aspects herein are described to provide examples and discussion. The operations described can be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step can actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the example aspects can be combined. It is understood that all the functions described herein can be performed by hardware, software, or any combination of hardware and software. It is also understood that the various figures can not be drawn to scale and that any reference to a dimension is not intended to be a critical dimension. It is further understood that the various figures can be used to represent one or more elements and do not limit the examples described herein to a single representational dimension. It will be apparent to those skilled in the art that substantial variations can be made in form, detail, and implementation of the example aspects without departing from the spirit and scope of the application. One skilled in the art will also appreciate that the application can be practiced with a variety of computer-system configurations, including single-processor or multiprocessor computer systems, mini-computing devices, mainframe computers, as well as computer-system configurations that are widely varied and that are well known to those skilled in the art. It will further be appreciated that the example aspects can be practiced using any number of languages, libraries, frameworks, modules, systems, or other applications, including one or more languages and libraries designed for the Internet; for the world wide web; and / or for the Internet protocol suite discussed above. The example aspects described herein can be implemented as a method, apparatus, or article of manufacture using programming and / or engineering techniques to produce software, firmware, hardware, or any combination thereof.

[0055] The foregoing description of the present disclosure has been provided in order to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations. Thus, the present disclosure is not intended to be limited to the examples described herein and the designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0056] Various implementation examples are described in the following numbered clauses:

[0057] 1. A processor-based device, comprising:

[0058] a cache memory device; and

[0059] a cache controller circuit of the cache memory device, the cache controller circuit configured to:

[0060] determine, based on a plurality of bit values of each of a plurality of cached data values in the cache memory device, a plurality of content costs for each of the plurality of cached data values;

[0061] identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value; and

[0062] evict the target cached data value from the cache memory device.

[0063] 2. The processor-based device of clause 1, wherein:

[0064] the cache memory device comprises a plurality of banks, each bank comprising a plurality of ways;

[0065] the cache controller circuit is further configured to:

[0066] identify a bank of the cache memory device for caching a data value therein; and

[0067] identify the plurality of cached data values stored in corresponding ways of the bank.

[0068] 3. The processor-based device of any of clauses 1-2, wherein the plurality of content costs each comprise a count of occurrences of a specified bit value of the plurality of bit values of a cached data value of the plurality of cached data values.

[0069] 4. The processor-based device of any of clauses 1-2, wherein:

[0070] the cache memory device is further configured to determine a most recently evicted data value; and

[0071] the plurality of content costs each comprise a count of a number of changes in each bit value of a plurality of bit values of the most recently evicted data value compared to a corresponding bit value of the plurality of bit values of a cached data value of the plurality of cached data values.

[0072] 5. The processor-based device of any of clauses 1-4, wherein:

[0073] the cache controller circuitry is further configured to:

[0074] determine whether all of the plurality of content costs have a same value; and

[0075] in response to determining that all of the plurality of content costs have the same value, identify the cached data value of the plurality of cached data values as the target cached data value using an alternative cache replacement policy; and

[0076] the cache controller circuitry is configured to, in response to determining that all of the plurality of content costs do not have the same value, identify the cached data value of the plurality of cached data values associated with the lowest content cost as the target cached data value.

[0077] 6. The processor-based device of any of clauses 1-5, wherein:

[0078] the cache controller circuitry is further configured to:

[0079] receive a data value to be cached;

[0080] determine a content cost of the data value;

[0081] determine whether the content cost of the data value is lower than all of the plurality of content costs; and

[0082] in response to determining that the content cost of the data value is lower than all of the plurality of content costs, bypass caching of the data value; and

[0083] the cache controller circuitry is configured to, in response to determining that the content cost of the data value is not lower than all of the plurality of content costs, identify the cached data value of the plurality of cached data values associated with the lowest content cost as the target cached data value.

[0084] 7. The processor-based device of any one of clauses 1-6, wherein:

[0085] the cache controller circuit is further configured to:

[0086] receive a data value to be cached;

[0087] receive a cache hint based on a plurality of bit values of the data value;

[0088] determine, based on the cache hint, whether the data value is to be cached; and

[0089] in response to determining that the data value is not to be cached, bypass caching of the data value; and

[0090] the cache controller circuit is configured to, in response to determining that the data value is to be cached, identify the cached data value of the plurality of cached data values associated with the lowest content cost as the target cached data value.

[0091] 8. The processor-based device of any one of clauses 1-7 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a transportation hub component; avionics; a drone; and a multicopter.

[0092] 9. A processor-based device comprising:

[0093] means for determining, based on a plurality of bit values of each cached data value of a plurality of cached data values in a cache memory device, a plurality of content costs for each cached data value of the plurality of cached data values;

[0094] means for identifying, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value; and

[0095] a component to evict the target cached data value from the cache memory device.

[0096] 10. A method for providing content-aware cache replacement and insertion policies, the method comprising:

[0097] determining, by cache controller circuitry, a plurality of content costs for each of a plurality of cached data values in a cache memory device based on a plurality of bit values of each of the plurality of cached data values;

[0098] identifying, by the cache controller circuitry, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value based on the plurality of content costs; and

[0099] evicting, by the cache controller circuitry, the target cached data value from the cache memory device.

[0100] 11. The method of clause 10, further comprising:

[0101] identifying, by the cache controller circuitry, a way of the plurality of ways of the cache memory device for caching a data value therein; and

[0102] identifying, by the cache controller circuitry, the plurality of cached data values stored in a corresponding way of the way.

[0103] 12. The method of any of clauses 10-11, wherein the plurality of content costs each comprise a count of occurrences of a specified bit value of the plurality of bit values of a cached data value of the plurality of cached data values.

[0104] 13. The method of any of clauses 10-11, further comprising determining, by the cache controller circuitry, a most recently evicted data value;

[0105] wherein the plurality of content costs each comprise a count of changes of each bit value of a plurality of bit values of the most recently evicted data value compared to a corresponding bit value of the plurality of bit values of a cached data value of the plurality of cached data values.

[0106] 14. The method of any of clauses 10-13, further comprising determining, by the cache controller circuitry, that all of the plurality of content costs do not have a same value;

[0107] wherein, in response to determining that all of the plurality of content costs do not have the same value, the cached data value of the plurality of cached data values associated with the lowest content cost is identified as the target cached data value.

[0108] 15. The method of any of clauses 10-14, further comprising:

[0109] receiving, by the cache controller circuit, a data value to be cached;

[0110] determining, by the cache controller circuit, a content cost of the data value; and

[0111] determining, by the cache controller circuit, that the content cost of the data value is not lower than all of the plurality of content costs; and

[0112] wherein, in response to determining that the content cost of the data value is not lower than all of the plurality of content costs, the cached data value of the plurality of cached data values associated with the lowest content cost is identified as the target cached data value.

[0113] 16. The method of any of clauses 10-15, wherein:

[0114] receiving, by the cache controller circuit from a client device, a data value to be cached;

[0115] receiving, by the cache controller circuit from the client device, a cache hint based on a plurality of bit values of the data value; and

[0116] determining, by the cache controller circuit based on the cache hint, that the data value is to be cached;

[0117] wherein, in response to determining that the data value is to be cached, the cached data value of the plurality of cached data values associated with the lowest content cost is identified as the target cached data value.

[0118] 17. A non-transitory computer-readable medium having stored thereon computer- executable instructions that, when executed, cause a processor to:

[0119] determine, based on a plurality of bit values of each cached data value of a plurality of cached data values in a cache memory device, a plurality of content costs for each cached data value of the plurality of cached data values;

[0120] identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value; and

[0121] evict the target cached data value from the cache memory device.

[0122] 18. The non-transitory computer-readable medium of clause 17, wherein the plurality of content costs each comprise a count of occurrences of a specified bit value of the plurality of bit values of a cached data value of the plurality of cached data values.

[0123] 19. The non-transitory computer-readable medium of clause 17, wherein:

[0124] the computer-executable instructions further cause the processor to determine a most recently evicted data value; and

[0125] the plurality of content costs each comprise a count of changes of each bit value of a plurality of bit values of the most recently evicted data value compared to a corresponding bit value of the plurality of bit values of a cached data value of the plurality of cached data values.

[0126] 20. The non-transitory computer-readable medium of any of clauses 17-19, wherein the computer-executable instructions further cause the processor to:

[0127] determine whether all of the plurality of content costs have a same value; and

[0128] in response to determining that all of the plurality of content costs have the same value, identify a cached data value of the plurality of cached data values as a target cached data value using an alternative cache replacement policy.

Claims

1. A processor-based device, the processor-based device comprising: Cache memory devices; and The cache controller circuit of the cache memory device is configured to: Multiple content costs for each cached data value are determined based on multiple bit values ​​of each cached data value among a plurality of cached data values ​​in the cache memory device; Based on the multiple content costs, the cached data value associated with the lowest content cost among the multiple cached data values ​​is identified as the target cached data value; and Evict the target cached data value from the cache memory device; Each of the plurality of content costs includes a count of the occurrences of a specified bit value among the plurality of bit values ​​of the cached data values.

2. The processor-based device according to claim 1, wherein: The cache memory device comprises multiple groups, each group comprising multiple paths; and The cache controller circuit is further configured as follows: A set of identifiers for caching data values ​​in the cache memory device; as well as The identifiers are the multiple cached data values ​​stored in the corresponding multiplexes of the set.

3. The processor-based device according to claim 1, wherein: The cache controller circuit is further configured as follows: Determine whether all content costs among the plurality of content costs have the same value; and In response to determining that all content costs among the plurality of content costs have the same value, an alternative cache replacement strategy is used to identify the cached data value among the plurality of cached data values ​​as the target cached data value; and The cache controller circuit is configured to, in response to determining that all content costs among the plurality of content costs do not have the same value, identify the cached data value among the plurality of cached data values ​​associated with the lowest content cost as the target cached data value.

4. The processor-based device according to claim 1, wherein: The cache controller circuit is further configured as follows: Receive the data value to be cached; Determine the content cost of the data value; Determine whether the content cost of the data value is lower than the total content cost of the plurality of content costs; and In response to determining that the content cost of the data value is lower than the total content cost of the plurality of content costs, the caching of the data value is bypassed; and The cache controller circuit is configured to, in response to determining that the content cost of the data value is not less than the total content cost of the plurality of content costs, identify the cached data value associated with the lowest content cost among the plurality of cached data values ​​as the target cached data value.

5. The processor-based device according to claim 1, wherein: The cache controller circuit is further configured as follows: Receive the data value to be cached; Receive cache hints based on multiple bit values ​​of the data value; Based on the cache suggestion, determine whether the data value should be cached; as well as In response to determining that the data value is not cached, the caching of the data value is bypassed; and The cache controller circuit is configured to, in response to determining that the data value needs to be cached, identify the cached data value associated with the lowest content cost among the plurality of cached data values ​​as the target cached data value.

6. The processor-based device of claim 1, wherein the processor-based device is integrated into a device selected from the group consisting of: set-top box; entertainment unit; navigation device; communication device; fixed location data unit; mobile location data unit; Global Positioning System (GPS) device; mobile phone; cellular phone; smartphone; Session Initiation Protocol (SIP) phone; tablet computer; tablet phone; server; computer; portable computer; mobile computing device; wearable computing device; desktop computer; personal digital assistant (PDA); monitor; computer monitor; television set; tuner; radio; Satellite radio; music player; digital music player; portable music player; digital video player; video player; digital video disc (DVD) player; portable digital video player; automobile; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

7. A processor-based device, the processor-based device comprising: A component for determining multiple content costs of each of the multiple cached data values ​​based on multiple bit values ​​of each of the multiple cached data values ​​in a cache memory device; A component for identifying, based on the plurality of content costs, the cached data value associated with the lowest content cost among the plurality of cached data values ​​as the target cached data value; and Components for evicting the target cached data value from the cache memory device; Each of the plurality of content costs includes a count of the occurrences of a specified bit value among the plurality of bit values ​​of the cached data values.

8. A method for providing a content-aware cache replacement and insertion strategy, the method comprising: The cache controller circuit determines multiple content costs for each of the multiple cached data values ​​based on multiple bit values ​​of each of the multiple cached data values ​​in the cache memory device; The cache controller circuit identifies the cached data value associated with the lowest content cost among the plurality of cached data values ​​as the target cached data value based on the plurality of content costs; and The cache controller circuit evicts the target cached data value from the cache memory device. Each of the plurality of content costs includes a count of the occurrences of a specified bit value among the plurality of bit values ​​of the cached data values.

9. The method according to claim 8, further comprising: The cache controller circuit identifies one of the multiple groups of the cache memory device for caching data values. as well as The cache controller circuit identifies the plurality of cached data values ​​stored in the corresponding multiplexes of the set.

10. The method of claim 8, further comprising determining by the cache controller circuit that all content costs among the plurality of content costs do not have the same value; in, In response to determining that all content costs among the plurality of content costs do not have the same value, the cached data value among the plurality of cached data values ​​associated with the lowest content cost is identified as the target cached data value.

11. The method according to claim 10, further comprising: The cache controller circuit receives the data value to be cached. The content cost of the data value is determined by the cache controller circuit. as well as The cache controller circuit determines that the content cost of the data value is not less than the total content cost of the plurality of content costs; and In response to determining that the content cost of the data value is not lower than the total content cost among the plurality of content costs, the cached data value associated with the lowest content cost among the plurality of cached data values ​​is identified as the target cached data value.

12. The method according to claim 8, further comprising: The cache controller circuit receives the data value to be cached from the client device; The cache controller circuit receives cache hints from the client device based on multiple bit values ​​of the data value; as well as The cache controller circuit determines, based on the cache hint, that the data value should be cached; In response to determining that the data value should be cached, the cached data value associated with the lowest content cost among the plurality of cached data values ​​is identified as the target cached data value.

13. A non-transitory computer-readable medium having stored thereon computer-executable instructions, which, when executed, cause a processor to: Multiple content costs for each cached data value are determined based on multiple bit values ​​of each cached data value among a plurality of cached data values ​​in a cache memory device; Based on the multiple content costs, the cached data value associated with the lowest content cost among the multiple cached data values ​​is identified as the target cached data value; and Evict the target cached data value from the cache memory device; Each of the plurality of content costs includes a count of the occurrences of a specified bit value among the plurality of bit values ​​of the cached data values.

14. The non-transitory computer-readable medium of claim 13, wherein the computer-executable instructions further cause the processor to: Determine whether all content costs among the plurality of content costs have the same value; and In response to determining that all content costs among the plurality of content costs have the same value, an alternative cache replacement strategy is used to identify the cached data value among the plurality of cached data values ​​as the target cached data value.

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