Self-aligned small contact structure

Abstract

Techniques for semiconductor structures are disclosed. In one aspect, a semiconductor structure includes: a gate structure disposed on a substrate; a gate spacer adjacent to the gate structure; a source / drain structure adjacent to the gate spacer; a first dielectric layer disposed on the substrate and the source / drain structure; an etch stop spacer over the first dielectric layer and adjacent to the gate spacer; and an etch stop layer over the gate structure, the gate spacer, and the etch stop spacer. The semiconductor structure further includes a source / drain contact extending through the etch stop layer and the first dielectric layer and in contact with the source / drain structure, a sidewall of the source / drain contact abutting a sidewall of the etch stop layer and a sidewall of the etch stop spacer.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor structures and, more particularly, to semiconductor structures having self-aligned small contact structures. Background Art

[0002] Integrated circuits (ICs) are becoming increasingly common in electronic devices. An IC can be implemented in the form of an IC die (or IC chip, or simply die or chip) having a set of electronic circuits integrated thereon. In some implementations, the IC die includes a semiconductor substrate, various electrical components on the substrate (e.g., transistors, resistors, capacitors, and / or inductors), and various conductive structures connecting the electrical components to form the set of electronic circuits. The manufacturing processes used to manufacture the electrical components can be collectively referred to as front-end-of-line (FEOL) processes. The manufacturing processes used to form a portion of the conductive structure in the form of a layer of conductive lines and via plugs can be collectively referred to as back-end-of-line (BEOL) processes. In some applications, the processes used to form another portion of the conductive structure connecting the electrical components and the layer of conductive lines and via plugs (including, for example, contact plugs or sometimes simply contacts) can be collectively referred to as middle-of-line (MOL) processes.

[0003] As manufacturing technology advances, the size of the MOL contacts shrinks as component sizes decrease. MOL contacts with reduced size can reduce parasitic effects, such as contact-to-gate capacitance, for improved performance, including reduced dynamic power consumption and improved DOU. In some applications, to form smaller contacts (e.g., for critical dimensions (CDs) of 15 nanometers (nm) or less), precise overlay and / or high exposure dose (e.g., high-dose extreme ultraviolet (EUV) lithography) are often used to avoid contact overlay misalignment or contact-to-gate shorts, but at the expense of complex processes, wafer rework, and / or reduced wafer throughput.

[0004] Therefore, there is a need for an improved MOL process for forming smaller contacts that can be properly aligned to effectively avoid contact-to-gate shorts without significantly increasing processing complexity and / or reducing wafer throughput. Summary of the Invention

[0005] The following is a brief overview of one or more aspects disclosed herein. Therefore, the following summary should not be considered an extensive overview of all contemplated aspects, nor should it be considered to identify key or important elements related to all contemplated aspects or to outline the scope associated with any particular aspect. Therefore, the sole purpose of the following summary is to provide some concepts related to one or more aspects of the mechanisms disclosed herein in a brief form before the detailed description given below.

[0006] In one aspect, a semiconductor structure includes: a gate structure disposed on a substrate; a gate spacer adjacent to a sidewall of the gate structure; a source / drain structure adjacent to the gate spacer; a first dielectric layer disposed on the substrate and the source / drain structure; an etch stop spacer over the first dielectric layer and adjacent to the gate spacer; an etch stop layer over and adjacent to an upper surface of the gate structure, an upper surface of the gate spacer, and an upper surface of the etch stop spacer; and source / drain contacts extending through the etch stop layer and the first dielectric layer and in contact with the source / drain structure, with sidewalls of the source / drain contacts adjacent to sidewalls of the etch stop layer and sidewalls of the etch stop spacer.

[0007] In one aspect, a method of fabricating a semiconductor structure includes forming an opening in an intermediate structure, wherein the intermediate structure includes a substrate; a gate structure disposed on the substrate; a gate spacer adjacent to a sidewall of the gate structure; a source / drain structure adjacent to the gate spacer; a first dielectric layer disposed on the substrate and the source / drain structure; an etch stop spacer over the first dielectric layer and adjacent to the gate spacer; and an etch stop layer over an upper surface of the gate structure, an upper surface of the gate spacer, and an upper surface of the etch stop spacer and adjacent to the gate spacer. and forming a first dielectric layer and a second dielectric layer disposed on the top of the gate electrode structure, a gate spacer and an etch stop spacer, wherein the opening extends through at least the etch stop layer and the first dielectric layer and exposes the source / drain structure, and wherein sidewalls of the etch stop layer and the etch stop spacer define at least a portion of the sidewalls of the opening; and forming a source / drain contact in the opening, the source / drain contact extending through the etch stop layer and the first dielectric layer and contacting the source / drain structure, and the sidewalls of the source / drain contact abutting the sidewalls of the etch stop layer and the sidewalls of the etch stop spacer.

[0008] Other objects and advantages associated with the various aspects disclosed herein will be apparent to those skilled in the art based on the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are presented to aid in describing various aspects of the present disclosure and are provided solely for illustration of the aspects and not limitation thereof.

[0010] Figure 1 is an example semiconductor structure illustrating aspects according to the present disclosure.

[0011] Figure 2A-2C Example semiconductor structures fabricated under various tolerable conditions according to aspects of the present disclosure are shown.

[0012] Figure 3A-3J An example portion of a method for fabricating a semiconductor structure according to aspects of the present disclosure is shown.

[0013] Figure 4 A method for fabricating a semiconductor structure according to aspects of the present disclosure is shown.

[0014] Figure 5 An example of a mobile device in accordance with aspects of the present disclosure is shown.

[0015] Figure 6 Various electronic devices are shown that may be integrated with an IC according to aspects of the present disclosure. DETAILED DESCRIPTION

[0016] Aspects of the present disclosure are provided in the following description and related drawings for each example provided for illustrative purposes. Without departing from the scope of the present disclosure, alternative aspects can be designed. In addition, the well-known elements of the present disclosure will not be described in detail or will be omitted to avoid blurring the relevant details of the present disclosure.

[0017] The words "exemplary" and / or "example" are used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" and / or "example" is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term "aspects of the disclosure" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation.

[0018] Those skilled in the art will recognize that the information and signals described below may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the following description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof, depending in part on the specific application, in part on the desired design, in part on the corresponding technology, etc.

[0019] Further, many aspects are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be appreciated that the various actions described herein may be performed by specific circuitry (e.g., an application specific integrated circuit (ASIC)), by program instructions executed by one or more processors, or by a combination of the two. Furthermore, the sequence(s) of actions described herein may be considered to be fully embodied in any form of non-transitory computer-readable storage medium having stored therein a set of corresponding computer instructions that, when executed, will cause or instruct an associated processor of a device to perform the functions described herein. Accordingly, various aspects of the present disclosure may be embodied in a number of different forms, all of which are contemplated to be within the scope of the claimed subject matter. Furthermore, for each of the various aspects described herein, the corresponding form of any such aspect may be described herein as, for example, "logic configured to (perform the described actions)."

[0020] According to the present application, the MOL process may include forming an etch stop spacer adjacent to a gate spacer. The etch stop spacer may limit the etching process used to form the opening for the plug contact. The etch stop spacer allows the formation of the plug contact to be "self-aligned" so that the plug contact can reach a desired critical dimension (CD) and can be kept sufficiently away from nearby gate structures for lower parasitic capacitance and to avoid contact-to-gate shorting. As a result, the precision requirements for the patterning process for the opening and / or the complexity of the MOL process may be relaxed.

[0021] Figure 1 An example semiconductor structure 100 is shown in accordance with aspects of the present disclosure. In some aspects, semiconductor structure 100 corresponds to a portion of a die at an intermediate stage during a MOL process.

[0022] like Figure 1As shown, semiconductor structure 100 includes substrate 102, gate structure 110a and gate structure 110b disposed on substrate 102, gate spacer 122a disposed on substrate 102 and adjacent to a sidewall of gate structure 110a, gate spacer 124a disposed on substrate 102 and adjacent to another sidewall of gate structure 110a, gate spacer 122b disposed on substrate 102 and adjacent to a sidewall of gate structure 110b, and gate spacer 124b disposed on substrate 102 and adjacent to another sidewall of gate structure 110b. Semiconductor structure 100 includes source / drain structures 130 disposed on the substrate and adjacent to gate spacers 122a and 122b. Furthermore, semiconductor structure 100 includes a first dielectric layer 142 disposed on the substrate and source / drain structures 130.

[0023] In some aspects, the substrate can be an undoped silicon substrate (e.g., having a silicon purity of at least 99.9999999 weight percent, nine-nine, or 9N), a doped silicon substrate, a III-V substrate (e.g., based on gallium arsenide (GaAs) or indium phosphide (InP)), a sapphire substrate, or any substrate on which a semiconductor component can be formed. In some aspects, the first dielectric layer 142 can have a relative dielectric constant no greater than the relative dielectric constant of silicon dioxide (SiO2). In some aspects, the first dielectric layer 142 can include SiCOH or SiO2. In some aspects, the gate spacers 122a, 122b, 124a, and 124b can have a relative dielectric constant no greater than the relative dielectric constant of SiO2. In some aspects, the gate spacers 122a, 122b, 124a, and 124b can include SiBCN. In some aspects, the source / drain structure 130 can include epitaxial silicon or epitaxial polysilicon.

[0024] In some aspects, gate structure 110a is the gate of a first transistor, and source / drain structure 130 can form a source or drain terminal of the first transistor. In some aspects, gate structure 110b is the gate of a second transistor, and source / drain structure 130 can form a source or drain terminal of the second transistor. In some aspects, height H (measurable along vertical direction 183) of gate structures 110a and 110b is G It can range from 10nm to 20nm.

[0025] In some aspects, the gate structure 110a can be a high-k metal gate. In some aspects, the gate structure 110a can include a conductive structure 112a, a gate metal layer 114a adjacent to the sidewalls and bottom surface of the conductive structure 112a, and a gate dielectric layer 116a adjacent to the sidewalls and bottom surface of the gate metal layer 114a. The gate metal layer 114a can be sandwiched between the gate dielectric layer 116a and the conductive structure 112a. In some aspects, the gate dielectric layer 116a can have a relative dielectric constant greater than the relative dielectric constant of SiO2. In some aspects, the conductive structure 112a can include tungsten, copper, or silicide. In some aspects, the gate metal layer 114a can include TiAlN, TiAl, TiN, or any material for a suitable work function setting. In some aspects, the gate dielectric layer 116a can include HfO2.

[0026] In some aspects, the gate structure 110b may be a high-k metal gate. In some aspects, the gate structure 110b may include a conductive structure 112b, a gate metal layer 114b adjacent to the sidewalls and bottom surface of the conductive structure 112b, and a gate dielectric layer 116b adjacent to the sidewalls and bottom surface of the gate metal layer 114b. The gate metal layer 114b may be sandwiched between the gate dielectric layer 116b and the conductive structure 112b. In some aspects, the gate dielectric layer 116b may have a relative dielectric constant greater than the relative dielectric constant of SiO2. In some aspects, the conductive structure 112b may include tungsten, copper, or silicide. In some aspects, the gate metal layer 114b may include TiAlN, TiAl, TiN, or any material for a suitable work function setting. In some aspects, the gate dielectric layer 116b may include HfO2.

[0027] like Figure 1 As shown, gate structure 110a and gate structure 110b can be gate-last high-k metal gates. In some aspects, either gate structure 110a or gate structure 110b can be gate-first high-k metal gates, polysilicon gates, or metal gates.

[0028] The semiconductor structure 100 also includes etch stop spacers 152a, 154a, 152b, and 154b overlying the first dielectric layer 142. The etch stop spacer 152a is adjacent to the gate spacer 122a; the etch stop spacer 154a is adjacent to the gate spacer 124a; the etch stop spacer 152b is adjacent to the gate spacer 122b; and the etch stop spacer 154b is adjacent to the gate spacer 124b. The semiconductor structure 100 includes an etch stop layer 162 that is disposed above and adjacent to the upper surfaces of the gate structure 110 a, the gate structure 110 b, the gate spacers 122 a, 122 b, 124 a, and 124 b, and the etch stop spacers 152 a, 152 b, 154 a, and 154 b. Furthermore, the semiconductor structure 100 includes source / drain contacts 170 that extend through the etch stop layer 162 and the first dielectric layer 142. Source / drain contact 170 contacts source / drain structure 130, wherein a sidewall of source / drain contact 170 can abut a sidewall of etch stop layer 162 and a sidewall of etch stop spacer 152a, and another sidewall of source / drain contact 170 can abut another sidewall of etch stop layer 162 and a sidewall of etch stop spacer 152b. In some aspects, a portion of first dielectric layer 142 between a lower portion of source / drain contact 170 and gate spacers 122a and 122b has a width (measurable along horizontal direction 184) greater than zero.

[0029] In some aspects, the etch stop spacers 152a, 152b, 154a, and 154b can include a material that is sufficiently selective to the first dielectric layer 142 during the etching process (e.g., the first dielectric layer 142 is removed faster than the etch stop spacers 152a, 152b, 154a, and 154b). In some aspects, the etch stop spacers 152a, 152b, 154a, and 154b can include silicon nitride, aluminum oxide, aluminum nitride, or a combination thereof. In some aspects, the source / drain contacts 170 can include cobalt, tungsten, or both. In some aspects, the height H (measurable along the vertical direction 183) of the etch stop spacers 152a, 152b, 154a, and 154b can be greater than or equal to 0. E In some aspects, the width W of the etch stop spacer 152a or 152b (measurable along the horizontal direction 184) may range from 1 nm to 5 nm. EIn some aspects, the width W (measurable along horizontal direction 184 ) of the lower portion of source / drain contact 170 beneath etch stop spacers 152 a , 152 b , 154 a , and 154 b is 1 nm to 5 nm. L It can range from 5nm to 15nm.

[0030] In some aspects, semiconductor structure 100 can include a second dielectric layer 182 overlying first dielectric layer 142, wherein etch stop layer 162 can be overlying and adjacent to an upper surface of second dielectric layer 182. In some aspects, semiconductor structure 100 can include a third dielectric layer 166 overlying etch stop layer 162, wherein source / drain contacts 170 can extend through third dielectric layer 166.

[0031] In some aspects, second dielectric layer 182 can include SiCOH or SiO2. In some aspects, third dielectric layer 166 can include SiO2. In some aspects, etch stop layer 162 can include a material that is sufficiently selective to at least third dielectric layer 166 during one or more etching processes (e.g., third dielectric layer 166 is removed faster than etch stop layer 162 in one etching process and / or etch stop layer 162 is removed faster than third dielectric layer 166 in another etching process). In some aspects, etch stop layer 162 can include silicon nitride, silicon carbide, or a combination thereof.

[0032] In view of the above, the location and size of the source / drain contacts 170 can be primarily determined by the etch stop spacers 152a and 152b rather than the mask(s) used to form the contact openings (in which the source / drain contacts 170 are formed) in the MOL process or the alignment of the masks used in the MOL process. Therefore, in some aspects, the source / drain contacts 170 can also be referred to as "self-aligned contacts". In some aspects, where the source / drain contacts and the corresponding gate spacers are separated by a piece of dielectric material (e.g., a portion of the first dielectric layer 142), the source / drain contacts can be referred to as "small contacts". Therefore, in some aspects, the source / drain contacts 170 can also be referred to as "self-aligned small contacts". In some aspects, a smaller contact size can result in lower contact-to-gate capacitance.

[0033] In some aspects, the etch stop spacers 152a and 152b can have the same width (measurable along the horizontal direction 184) due to the conformal deposition and anisotropic etching used to form the etch stop spacers 152a and 152b. In some aspects, the gate spacers 122a and 122b can also have the same width (measurable along the horizontal direction 184) due to the conformal deposition and anisotropic etching used to form the gate spacers 122a and 122b. Thus, in some aspects, the source / drain contacts 170 can have exactly the same distance to the gate structures 110a and 110b. In some aspects, the self-aligned features of the source / drain contacts 170 can minimize contact-to-gate capacitance and mitigate contact-to-gate shorts from misalignment.

[0034] In some aspects, even under possible process variations or a certain degree of misalignment of the mask used for the photolithography process, the one or more etching processes used to form the openings for the source / drain contacts 170 can be limited by the etch stop spacers 152a and 152b, and thus the lower portion of the source / drain contacts 170 can be kept sufficiently small (e.g., CD < 15nm) and sufficiently far away from the gate structures 110a and 110b. Thus, the chance of a contact-to-gate short forming between the source / drain contacts 170 and the gate structures 110a and 110b can be reduced. Furthermore, the parasitic capacitance between the source / drain contacts 170 and the gate structures 110a and 110b can be within a predetermined range because the distance between the source / drain contacts 170 and the gate structures 110a and 110b can be limited by the etch stop spacers 152a and 152b.

[0035] In some aspects, because the location and size of the source / drain contacts 170 can be primarily determined by the etch stop spacers 152 a and 152 b, the size of the opening above the etch stop spacers 152 a and 152 b for the source / drain contacts 170 can be set to be larger than the desired width of the source / drain contacts 170 below the etch stop spacers 152 a and 152 b. Furthermore, in some aspects, the accuracy of the mask alignment for the opening above the etch stop spacers 152 a and 152 b for the source / drain contacts 170 can be relaxed (e.g., more tolerant to mask misalignment). Thus, the performance of the resulting IC can be achieved while reducing the complexity of the manufacturing process, reducing the number of masks required, increasing production throughput, increasing yield, and / or reducing manufacturing costs.

[0036] Figure 2AAn example semiconductor structure 200A fabricated under a first tolerable condition according to aspects of the present disclosure is shown. Components of the semiconductor structure 200A that are the same or similar to those of the semiconductor structure 100 are given the same reference numerals, and detailed descriptions thereof may be omitted.

[0037] like Figure 2A As shown, the source / drain contact 170 can include an upper portion 170a above the etch stop spacers 152a and 152b and a lower portion 170b below the etch stop spacers 152a and 152b. In some aspects, a first tolerable condition corresponding to a patterning process for forming an opening for the source / drain contact 170 can be performed based on a mask corresponding to a width of the opening being greater than a desired width of the lower portion 170b of the source / drain contact 170. The position and width of the lower portion of the opening for the lower portion 170b of the source / drain contact 170 can be further limited by the etch stop spacers 152a and 152b.

[0038] For example, in some aspects, where such a mask is properly aligned with the predetermined opening locations 210, the resulting source / drain contact 170 can have a T-shape. In some aspects, the width W of the lower portion 170b of the source / drain contact 170b is L may be no greater than the width W of the upper portion 170 a of the source / drain contact 170 U In some aspects, the width W of the lower portion 170b of the source / drain contact 170 is L The width W of the upper portion 170 a of the source / drain contact 170 may range from 5 nm to 15 nm. U It can range from 10nm to 20nm.

[0039] according to Figure 2A In some aspects, the use of a mask with a wider pattern for the opening (i.e., the first tolerable condition) can save costs in various aspects including mask preparation, photolithography tools and processes, and / or precise control of the etching process. In some aspects, the etch stop spacers 152a and 152b can ensure the position and size of the lower portion 170b of the source / drain contact 170, regardless of the size of the pattern in the mask used to form the opening (as reflected in the width of the upper portion 170a of the source / drain contact 170) being wider.

[0040] Figure 2B An example semiconductor structure 200B fabricated under a second tolerable condition according to aspects of the present disclosure is shown. Components of the semiconductor structure 200B that are the same or similar to those of the semiconductor structure 100 or 200A are given the same reference numerals, and detailed descriptions thereof may be omitted.

[0041] In some aspects, a second tolerable condition corresponding to a patterning process for forming openings for source / drain contacts 170 can be performed based on a mask having a pattern corresponding to a width of the opening being greater than a desired width of a lower portion 170 b of the source / drain contact 170 , and an alignment of the mask being offset in a direction toward gate structure 110 a (e.g., along horizontal direction 184 ).

[0042] Figure 2C An example semiconductor structure 200C fabricated under a third tolerable condition according to aspects of the present disclosure is shown. Components of the semiconductor structure 200C that are the same or similar to those of the semiconductor structure 100 or 200A are given the same reference numerals, and detailed descriptions thereof may be omitted.

[0043] In some aspects, a third tolerable condition corresponding to a patterning process for forming openings for source / drain contacts 170 can be performed based on a mask having a pattern corresponding to a width of the opening being greater than a desired width of a lower portion 170 b of the source / drain contact 170, and an alignment of the mask being offset in a direction toward gate structure 110 b (e.g., along horizontal direction 184).

[0044] like Figure 2B and Figure 2C As shown, in some aspects, the resulting source / drain contact 170 can have an inverted L shape when the mask for the opening is misaligned with the predetermined opening location 210. The location and width of the lower portion of the opening for the lower portion 170b of the source / drain contact 170 can still be limited by the etch stop spacers 152a and 152b.

[0045] according to Figure 2B and 2C In some aspects, the etch stop spacers 152a and 152b can ensure the position and size of the lower portion 170b of the source / drain contact 170 regardless of the shifted alignment of the mask used to form the opening.

[0046] Figure 3A-3J A method for fabricating a semiconductor structure such as Figure 1 An example portion of a method for a semiconductor structure 100 in FIG. Figure 3A-3J Components shown in FIG. 1 that are the same as or similar to those of the semiconductor structure 100 are given the same reference numerals, and detailed descriptions thereof may be omitted.

[0047] like Figure 3AAs shown, a semiconductor structure 300A is formed. The semiconductor structure 300A includes a substrate 102, a first dielectric material layer 302 formed on the substrate 102, and an intermediate gate structure 310a and an intermediate gate structure 310b formed on the substrate 102. First spacer material layers 322a, 322b, 324a, and 324b are formed on the sidewalls of the intermediate gate structure 310a and the intermediate gate structure 310b. The first spacer material layers 322a and 324a and the intermediate gate structure 310a are surrounded by the first dielectric material layer 302; and the first spacer material layers 322b and 324b and the intermediate gate structure 310b are surrounded by the first dielectric material layer 302.

[0048] In some aspects, the intermediate gate structure 310a may include a polysilicon gate 312a and a hard mask 314a above the polysilicon gate 312a. In some aspects, the intermediate gate structure 310b may include a polysilicon gate 312b and a hard mask 314b above the polysilicon gate 312b. In some aspects, the first spacer material layers 322a, 322b, 324a, and 324b may be formed by deposition using chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some aspects, the first spacer material layers 322a, 322b, 324a, and 324b may have a relative dielectric constant no greater than that of SiO2. In some aspects, the first spacer material layers 322a, 322b, 324a, and 324b may include SiBCN.

[0049] In some aspects, source / drain structure 130 can be formed on substrate 102 and adjacent to first spacer material layers 322a and 322b. In some aspects, source / drain structure 130 can be formed based on an epitaxial growth process and can include epitaxial silicon or epitaxial polysilicon.

[0050] In some aspects, the first dielectric material layer 302 may be formed by filling the dielectric material after forming the intermediate gate structures 310a and 310b, the first spacer material layers 322a, 322b, 324a, and 324b, and the source / drain structures. In some aspects, the first dielectric material layer 302 may be formed by CVD or PVD. In some aspects, the first dielectric material layer 302 may have a relative dielectric constant no greater than that of SiO2. In some aspects, the first dielectric material layer 302 may include SiCOH or SiO2.

[0051] like Figure 3BAs shown, semiconductor structure 300B is formed based on semiconductor structure 300A by removing an upper portion of first dielectric material layer 302 to form first dielectric layer 142. In some aspects, the removal of the upper portion of first dielectric material layer 302 is performed by a recessing process based on a wet etching process.

[0052] like Figure 3C As shown, semiconductor structure 300C is based on semiconductor structure 300B and is formed by forming second spacer material layers 332a, 332b, 334a and 334b ​​on at least a portion of the respective sidewalls of first spacer material layers 322a, 322b, 324a and 324b. The second spacer material layers 332a, 332b, 334a and 334b ​​are above the first dielectric layer 142. In some aspects, the second spacer material layers 332a, 332b, 334a and 334b ​​can be formed by deposition using CVD or PVD. In some aspects, the second spacer material layers 332a, 332b, 334a and 334b ​​can include silicon nitride, aluminum oxide, aluminum nitride or a combination thereof. In some aspects, the width of any layer of the second spacer material 332a, 332b, 334a and 334b ​​can range from 1nm to 5nm.

[0053] like Figure 3D As shown, semiconductor structure 300D is formed based on semiconductor structure 300C by forming a second dielectric material layer 304 above first dielectric layer 142. In some aspects, second dielectric material layer 304 is an intermediate dielectric layer that will be at least partially removed in a later processing stage.

[0054] In some aspects, the second spacer material layers 332a and 332b can be directly overlying the first portion of the source / drain structure 130. In some aspects, a portion of the second dielectric material layer 304 can be adjacent to sidewalls of the second spacer material layers 332a and 332b and directly overlying the second portion of the source / drain structure 130.

[0055] In some aspects, the second dielectric material layer 304 can be formed by filling the recess shown in the semiconductor structure 300C with a dielectric material. In some aspects, the second dielectric material layer 304 can be formed by CVD or PVD. In some aspects, the second dielectric material layer 304 can include SiCOH or SiO2.

[0056] like Figure 3EAs shown, semiconductor structure 300E is formed based on semiconductor structure 300D by removing the top of semiconductor structure 300D so as to remove hard mask 314a and hard mask 314b. Although the intermediate gate structure 310a, the intermediate gate structure 310b, the first spacer material layers 322a, 322b, 324a and 324b, and the top of the second dielectric material layer may also be removed, for the sake of clarity, these remaining parts are still named and labeled as they are before the top of the parts are removed.

[0057] In some aspects, the top portion of semiconductor structure 300D (including hard mask 314a and hard mask 314b) can be removed using a chemical mechanical polishing (CMP) process. In some aspects, other removal or planarization processes can be used to remove hard mask 314a and hard mask 314b.

[0058] like Figure 3F As shown, semiconductor structure 300F is formed based on semiconductor structure 300E by replacing intermediate gate structures 310a and 310b with different intermediate gate structures 340a and 340b, respectively. In some aspects, polysilicon gates 312a and 312b are removed by an etching process such as a wet etching process. In some aspects, a material layer is formed in the opening where polysilicon gates 312a and 312b are located. In some aspects, intermediate gate structures 340a and 340b can have different structures and different materials.

[0059] In some aspects, the intermediate gate structure 340a can be formed by depositing a gate dielectric material layer 346a by CVD or PVD, followed by depositing a gate metal material layer 344a by CVD or PVD, and then forming a conductive filler 342a by CVD or PVD. In some aspects, one or more polishing processes can be performed after the one or more deposition processes to remove excess material on the first spacer material layers 322a, 322b, 324a, and 324b and the second dielectric material layer 304.

[0060] In some aspects, the gate dielectric material layer 346a can have a relative dielectric constant greater than that of SiO2. In some aspects, the conductive filler 342a can include tungsten, copper, or silicide. In some aspects, the gate metal material layer 344a can include TiAlN, TiAl, TiN, or any material for a suitable work function setting. In some aspects, the gate dielectric material layer 346a can include HfO2.

[0061] In some aspects, the intermediate gate structure 340b can be formed by depositing a gate dielectric material layer 346b by CVD or PVD, followed by depositing a gate metal material layer 344b by CVD or PVD, and then forming a conductive filler 342b by CVD or PVD. In some aspects, one or more polishing processes can be performed after the one or more deposition processes to remove excess material on the first spacer material layers 322a, 322b, 324a, and 324b and the second dielectric material layer 304.

[0062] In some aspects, the gate dielectric material layer 346b can have a relative dielectric constant greater than that of SiO2. In some aspects, the conductive filler 342b can include tungsten, copper, or silicide. In some aspects, the gate metal material layer 344b can include TiAlN, TiAl, TiN, or any material for a suitable work function setting. In some aspects, the gate dielectric material layer 346b can include HfO2.

[0063] In some aspects, forming the intermediate gate structures 340 a and 340 b may include temporarily covering one of the gate structures so that the intermediate gate structures 340 a and 340 b may be formed with different materials and / or structures.

[0064] like Figure 3G As shown, semiconductor structure 300G is formed based on semiconductor structure 300F by removing upper portions of semiconductor structure 300F. For example, upper portions of first spacer material layers 322a, 322b, 324a, and 324b are removed to form gate spacers 122a, 122b, 124a, and 124b, respectively. Upper portions of second spacer material layers 332a, 332b, 334a, and 334b ​​are removed to form etch stop spacers 152a, 152b, 154a, and 154b, respectively. An upper portion of second dielectric material layer 304 is removed to form second dielectric layer 182. Furthermore, upper portions of intermediate gate structures 340a and 340b are removed to form gate structures 110a and 110b, respectively. For gate structure 110a, conductive filler 342a, gate metal layer 344a, and gate dielectric layer 346a become its conductive structure 112a, gate metal layer 114a, and gate dielectric layer 116a. For gate structure 110b, conductive filler 342b, gate metal layer 344b, and gate dielectric layer 346b become its conductive structure 112b, gate metal layer 114b, and gate dielectric layer 116b.

[0065] In some aspects, the upper portion of the semiconductor structure 300F can be removed based on a CMP process. In some aspects, other removal or planarization processes can be used to remove the upper portion of the semiconductor structure 300F. In some aspects, the height of the etch stop spacers 152a, 152b, 154a, and 154b can range from 1 nm to 5 nm.

[0066] like Figure 3H As shown, semiconductor structure 300H is formed based on semiconductor structure 300G by forming an etch stop layer 162 on semiconductor structure 300G and forming a third dielectric layer 166 on etch stop layer 162. In some aspects, etch stop layer 162 can be above and adjacent to upper surfaces of gate structures 110a and 110b, upper surfaces of gate spacers 122a, 122b, 124a, and 124b, upper surfaces of etch stop spacers 152a, 152b, 154a, and 154b, and an upper surface of the second dielectric layer.

[0067] In some aspects, etch stop layer 162 can be formed by CVD or PVD. In some aspects, etch stop layer 162 can include silicon nitride, silicon carbide, or a combination thereof. In some aspects, third dielectric layer 166 can be formed by CVD or PVD. In some aspects, third dielectric layer 166 can include SiO2.

[0068] like Figure 3I As shown, semiconductor structure 300I can be formed based on semiconductor structure 300H by forming an opening 350 in semiconductor structure 300H. In some aspects, opening 350 extends at least through etch stop layer 162 and first dielectric layer 142, exposing source / drain structure 130. In some aspects, opening 350 also extends through second dielectric layer 182 and third dielectric layer 166. In some aspects, a sidewall of etch stop layer 162 and a sidewall of etch stop spacer 152a define a portion of a sidewall of opening 350. In some aspects, another sidewall of etch stop layer 162 and a sidewall of etch stop spacer 152b define a portion of another sidewall of opening 350.

[0069] In some aspects, opening 350 can be formed by first forming another mask layer over third dielectric layer 166 and patterning the other mask layer, on which a first etching process can be performed to remove a portion of third dielectric layer 166 and a portion of etch stop layer 162 to form an upper portion of opening 350. In some aspects, after forming the upper portion of opening 350, a second etching process can be performed to extend opening 350 to reach source / drain structure 130. In some aspects, a portion of source / drain structure 130 can be removed during the second etching process.

[0070] In some aspects, the first etching process can be a wet etching process or a dry etching process. In some aspects, the second etching process can be a wet etching process or a dry etching process. In some aspects, the etch stop spacers 152a and 152b can include a material that is sufficiently selective to the first dielectric layer 142 during the second etching process. Therefore, in some aspects, the size and position of the lower portion of the opening 350 below the etch stop spacers 152a and 152b can be limited by the etch stop spacers 152a and 152b.

[0071] like Figure 3J As shown, the semiconductor structure 300J is formed based on the semiconductor structure 300I by filling the opening 350 with a conductive material to form the source / drain contact 170. In some aspects, the semiconductor structure 300J may correspond to Figure 1 In some aspects, the source / drain contacts 170 can include cobalt, tungsten, or both. In some aspects, the source / drain contacts 170 can be formed by CVD or PVD, followed by a polishing process (e.g., a CMP process) to remove excess material above the third dielectric layer 166.

[0072] Figure 4 A method 400 for fabricating a semiconductor structure, such as semiconductor structure 100 or semiconductor structure 300J, is shown in accordance with aspects of the present disclosure.

[0073] In operation 410, an opening (eg, opening 350) is formed in an intermediate structure (eg, semiconductor structure 300H). In some aspects, the opening can be formed based on one or more etching processes.

[0074] In some aspects, the intermediate structure can include: a substrate (e.g., substrate 102); a gate structure (e.g., gate structures 110a, 110b) disposed on the substrate; a gate spacer (e.g., gate spacer 122a) disposed on the substrate and adjacent to a sidewall of the gate structure; a source / drain structure (e.g., source / drain structure 130) disposed on the substrate and adjacent to the first spacer; a first dielectric layer (e.g., first dielectric layer 142) disposed on the substrate and the source / drain structure; an etch stop spacer (e.g., etch stop spacer 152a) disposed on the first dielectric layer and adjacent to the first spacer; and an etch stop layer (e.g., etch stop layer 162) disposed on and adjacent to an upper surface of the gate structure, an upper surface of the first spacer, and an upper surface of the etch stop spacer. In some aspects, the opening can extend through at least the etch stop layer and the first dielectric layer, exposing the source / drain structure. In some aspects, sidewalls of the etch stop layer and sidewalls of the etch stop spacers can define at least a portion of a sidewall of the opening.

[0075] In some aspects, the etch stop spacers include silicon nitride, aluminum oxide, aluminum nitride, or a combination thereof. In some aspects, the etch stop spacers have a width ranging from 1 nm to 5 nm.

[0076] In operation 420, source / drain contacts (e.g., source / drain contacts 170) are formed in openings (e.g., opening 350). In some aspects, the source / drain contacts can be formed based on a CVD process or a PVD process. In some aspects, the source / drain contacts can include cobalt, tungsten, or both.

[0077] In some aspects, the source / drain contacts extend through the etch stop layer and the first dielectric layer and contact the source / drain structure, and sidewalls of the source / drain contacts abut sidewalls of the etch stop layer and sidewalls of the etch stop spacers.

[0078] As will be appreciated, a technical advantage of method 400 is that the location and size of the source / drain contacts are limited based on the etch stop spacers adjacent to the gate spacers. The etch stop spacers allow the formation of the openings (in which the source / drain contacts are to be formed) to be "self-aligned," so that the source / drain contacts can achieve a desired CD and can be kept sufficiently away from nearby gate structures for low parasitic capacitance and to avoid contact-to-gate shorting. Consequently, the precision requirements for the patterning process for the openings and / or the complexity of their fabrication process can be relaxed.

[0079] Figure 5A mobile device 500 is shown in accordance with aspects of the present disclosure. In some aspects, the mobile device 500 can be implemented by including one or more ICs including semiconductor structures fabricated based on examples described in this disclosure.

[0080] In some aspects, the mobile device 500 can be configured as a wireless communication device. As shown, the mobile device 500 includes a processor 501. The processor 501 can be communicatively coupled to a memory 532 via a link, which can be a die-to-die link or a chip-to-chip link. The mobile device 500 also includes a display 528 and a display controller 526, wherein the display controller 526 is coupled to the processor 501 and the display 528. The mobile device 500 may include an input device 530 (e.g., a physical or virtual keyboard), a power supply 544 (e.g., a battery), a speaker 536, a microphone 538, and a wireless antenna 542. In some aspects, the power supply 544 can directly or indirectly provide a supply voltage for operating some or all of the components of the mobile device 500.

[0081] In some respects, Figure 5 It may include a coder / decoder (CODEC) 534 (e.g., an audio and / or voice CODEC) coupled to the processor 501; a speaker 536 and a microphone 538 coupled to the CODEC 534; and a wireless circuit 540 (which may include a modem, RF circuitry, filters, etc.) coupled to a wireless antenna 542 and the processor 501.

[0082] In some aspects, one or more of processor 501, display controller 526, memory 532, CODEC 534, and wireless circuitry 540 may comprise one or more ICs including semiconductor structures fabricated according to examples described in this disclosure.

[0083] It should be noted that although Figure 5 Mobile device 500 is depicted, but similar architecture may be used to implement apparatus including set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed location data units, computers, laptop computers, tablet computers, communication devices, mobile phones, or other similar devices.

[0084] Figure 6Various electronic devices 610, 620, and 630 are shown that may be integrated with ICs 612, 622, and 632 according to aspects of the present disclosure. For example, mobile phone device 610, laptop device 620, and fixed location terminal device 630 may each be generally considered to be user equipment (UE) and may include one or more ICs (such as ICs 612, 622, and 632) and a power supply for providing a supply voltage to power the ICs. ICs 612, 622, and 632 may, for example, correspond to devices including a plurality of ICs based on the above reference. Figure 1 、 Figures 2A-2C and Figures 3A-3J An example of fabricating a semiconductor structure for an IC is described.

[0085] Figure 6 The devices 610, 620, and 630 shown are non-limiting examples only. Other electronic devices may also feature an IC that includes a semiconductor structure as described in the present disclosure, including but not limited to a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablets, computers, wearable devices, servers, routers, electronic devices implemented in automobiles (e.g., self-driving cars), Internet of Things (IoT) devices, access points, base stations, or any other device that stores or retrieves data or computer instructions or any combination thereof.

[0086] It will be appreciated that various aspects disclosed herein may be described as functional equivalents to structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one aspect, an apparatus may include units for performing the various functions discussed above. It will be appreciated that the foregoing aspects are provided by way of example only, and that the claimed aspects are not limited to the specific references and / or illustrations cited as examples.

[0087] Figures 1-6 One or more of the components, steps, features, and / or functions shown in the can be rearranged and / or combined into a single component, process, feature, or function, or integrated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. In some implementations, Figures 1-6The present invention and corresponding descriptions can be used to manufacture, create, provide, and / or produce an integrated device. In some implementations, the device can include a die, an integrated device, a die package, an IC, a device package, an IC package, a wafer, a semiconductor device, a system-in-package (SiP), a system-on-chip (SoC), a package-on-package (PoP) device, etc.

[0088] As used herein, the terms "user equipment" (or "UE"), "user device," "user terminal," "client device," "communication device," "wireless device," "wireless communication device," "handheld device," "mobile device," "mobile terminal," "mobile station," "handset," "access terminal," "subscriber device," "subscriber terminal," "subscriber station," "terminal," and variations thereof, may interchangeably refer to any suitable mobile or stationary device that can receive wireless communications and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in motor vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate (such as via short-range wireless, infrared, wired connection, or other connection) with another device that can receive wireless communications and / or navigation signals, regardless of whether satellite signal reception, assistance data reception, and / or location-related processing occurs at the device or at the other device. A UE may be embodied by any of a number of types of devices including, but not limited to, a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wired phone, a smartphone, a tablet, a consumer tracking device, an asset tag, etc.

[0089] Wireless communication between electronic devices may be based on different technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread), or other protocols that may be used in wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart)

[0090] Nothing stated or shown in this application is intended to confer any component, act, feature, benefit, advantage, or equivalent to the public regardless of whether the component, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0091] Further, those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the examples disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate such interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and actions have been generally described in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Technicians can implement the described functionality in an alternative manner for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of this disclosure.

[0092] Although some aspects have been described in conjunction with equipment, it is self-evident that these aspects also constitute the description of the corresponding method, and therefore, the block or assembly of equipment should also be understood as the feature of the corresponding method action or method action. Similarly, the various aspects described in conjunction with or as method action also constitute the description of the corresponding block or details or features of the corresponding equipment. Some method actions or all method actions in the method action can be performed by hardware devices (or using hardware devices) (such as, for example, microprocessors, programmable computers or electronic circuits). In some examples, some method actions or multiple method actions in the most important method actions can be performed by such devices.

[0093] As can be seen in the detailed description above, different features are grouped together in the examples. Such a disclosure should not be understood as an intention that the example clauses have more features than those explicitly mentioned in each clause. Instead, various aspects of the present disclosure may include less than all the features of the disclosed individual example clauses. Therefore, the following clauses should be considered to be incorporated into the description accordingly, wherein each clause itself may exist as a separate example. Although each dependent clause can refer to a specific combination with one of the other clauses in the clause, the (multiple) aspects of the dependent clause are not limited to specific combinations. It will be appreciated that other example clauses may also include a combination of (multiple) dependent clause aspects with the subject matter of any other dependent clause or independent clause, or a combination of any feature with other dependent clauses and independent clauses. Various aspects disclosed herein explicitly include these combinations, unless it is explicitly stated or it can be easily inferred that a specific combination is not intended (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). In addition, it is also intended to include various aspects of a clause in any other independent clause, even if the clause is not directly dependent on the independent clause.

[0094] Implementation examples are described in the following numbered clauses:

[0095] Item 1. A device comprising: a gate structure disposed on a substrate; a gate spacer adjacent to a sidewall of the gate structure; a source / drain structure adjacent to the gate spacer; a first dielectric layer disposed on the substrate and the source / drain structure; an etch stop spacer over the first dielectric layer and adjacent to the gate spacer; an etch stop layer over and adjacent to an upper surface of the gate structure, an upper surface of the gate spacer, and an upper surface of the etch stop spacer; and source / drain contacts extending through the etch stop layer and the first dielectric layer and contacting the source / drain structure, with sidewalls of the source / drain contacts adjacent to sidewalls of the etch stop layer and sidewalls of the etch stop spacer.

[0096] Item 2. The semiconductor structure of Item 1, wherein the etch stop spacer comprises silicon nitride, aluminum oxide, aluminum nitride, or a combination thereof.

[0097] Item 3. The semiconductor structure of any one of Items 1 to 2, wherein the etch stop spacer has a width ranging from 1 nm to 5 nm.

[0098] Item 4. A semiconductor structure according to any one of items 1 to 3, further comprising: a second gate structure disposed on the substrate; a second gate spacer adjacent to a sidewall of the second gate structure; and a second etch stop spacer above the first dielectric layer and adjacent to the second gate spacer, wherein: the source / drain contact is disposed between the etch stop spacer and the second etch stop spacer, and the second sidewall of the source / drain contact is adjacent to a sidewall of the second etch stop spacer.

[0099] Item 5. The semiconductor structure of Item 4, wherein a width of the etch stop spacer is the same as a width of the second etch stop spacer.

[0100] Item 6. The semiconductor structure of any one of Items 1 to 5, further comprising: a second dielectric layer overlying the first dielectric layer, the etch stop layer overlying and abutting an upper surface of the second dielectric layer.

[0101] Item 7. The semiconductor structure of Item 6, wherein the second dielectric layer comprises SiO 2 .

[0102] Item 8. The semiconductor structure of any one of Items 1 to 7, further comprising: a third dielectric layer overlying the etch stop layer, wherein the source / drain contacts extend through the third dielectric layer.

[0103] Item 9. The semiconductor structure of Item 8, wherein a width of a portion of the source / drain contact below the etch stop spacer is no greater than a width of a portion of the source / drain contact above the etch stop spacer.

[0104] Item 10. The semiconductor structure of Item 9, wherein: a width of a portion of the source / drain contact below the etch stop spacer ranges from 5 nm to 15 nm, and a width of a portion of the source / drain contact above the etch stop spacer ranges from 10 nm to 20 nm.

[0105] Item 11. The semiconductor structure of any one of Items 1 to 10, wherein the gate spacer has a relative permittivity no greater than a relative permittivity of SiO 2 .

[0106] Item 12. The semiconductor structure of any one of Items 1 to 11, wherein the first dielectric layer has a relative permittivity no greater than a relative permittivity of SiO 2 .

[0107] Item 13. The semiconductor structure of any one of Items 1 to 12, wherein the gate spacer comprises SiBCN.

[0108] Item 14. The semiconductor structure of any one of Items 1 to 13, wherein the first dielectric layer comprises SiCOH or SiO 2 .

[0109] Item 15. The semiconductor structure of any one of Items 1 to 14, wherein the source / drain contacts comprise cobalt, tungsten, or both.

[0110] Clause 16. A method of fabricating a semiconductor structure, comprising: forming an opening in an intermediate structure, wherein the intermediate structure comprises: a substrate; a gate structure disposed on the substrate; a gate spacer adjacent to a sidewall of the gate structure; a source / drain structure adjacent to the gate spacer; a first dielectric layer disposed on the substrate and the source / drain structure; an etch stop spacer over the first dielectric layer and adjacent to the gate spacer; and an etch stop layer over an upper surface of the gate structure, an upper surface of the gate spacer, and an upper surface of the etch stop spacer and adjacent to the gate structure. and forming a first dielectric layer and a second dielectric layer disposed on the top of the etch stop layer and the second dielectric layer so as to expose the source / drain structure and the drain structure; ...

[0111] Item 17. The method according to Item 16 further includes: forming an intermediate structure, which includes: forming a first spacer material layer on the sidewall of the first intermediate gate structure, the first intermediate gate structure being above the substrate; forming a second spacer material layer on at least a portion of the sidewall of the first spacer material layer; replacing the first intermediate gate structure with the second intermediate gate structure; and removing an upper portion of the first spacer material layer, an upper portion of the second spacer material layer, and an upper portion of the second intermediate gate structure to form a gate spacer, an etch stop spacer, and a gate structure, respectively.

[0112] Item 18. The method of Item 17, wherein the removing is performed based on a chemical mechanical polishing (CMP) process.

[0113] Item 19. A method according to any one of Items 17 to 18, wherein forming the intermediate structure further comprises: forming a source / drain structure on the substrate and adjacent to the first spacer material layer before forming the second spacer material layer, the second spacer material layer being directly on a first portion of the source / drain structure; forming a first dielectric layer on the substrate and the source / drain structure before forming the second spacer material layer; and forming a dielectric material layer on the first dielectric layer, a portion of the dielectric material layer being adjacent to a sidewall of the second spacer material layer and directly on a second portion of the source / drain structure.

[0114] Item 20. A method according to Item 19, wherein forming the intermediate structure further comprises: removing an upper portion of the dielectric material layer to form a second dielectric layer; and forming an etch stop layer above and adjacent to an upper surface of the gate structure, an upper surface of the gate spacer, an upper surface of the etch stop spacer, and an upper surface of the second dielectric layer.

[0115] Item 21. The method of any one of Items 16 to 20, wherein forming source / drain contacts in the openings comprises: filling the openings with a material comprising cobalt, tungsten, or both; and performing a chemical mechanical polishing (CMP) process to remove excess material.

[0116] Item 22. The method of Item 21, wherein a width of a portion of the source / drain contact below the etch stop spacer is no greater than a width of a portion of the source / drain contact above the etch stop spacer.

[0117] Item 23. The method of Item 22, wherein: a width of a portion of the source / drain contact below the etch stop spacer ranges from 5 nm to 15 nm, and a width of a portion of the source / drain contact above the etch stop spacer ranges from 10 nm to 20 nm.

[0118] Item 24. The method of any one of Items 16 to 23, wherein the etch stop spacer comprises silicon nitride, aluminum oxide, aluminum nitride, or a combination thereof.

[0119] Clause 25. The method of any one of clauses 16 to 24, wherein the etch stop spacer has a width ranging from 1 nm to 5 nm.

[0120] Item 26. The method of any one of Items 16 to 25, wherein the gate spacer has a relative permittivity no greater than the relative permittivity of SiO 2 .

[0121] Clause 27. The method of any one of clauses 16 to 26, wherein the first dielectric layer has a relative permittivity no greater than the relative permittivity of SiO 2 .

[0122] Item 28. The method of any one of Items 16 to 27, wherein the gate spacer comprises SiBCN.

[0123] Item 29. The method of any one of Items 16 to 28, wherein the first dielectric layer comprises SiCOH or SiO 2 .

[0124] Item 30. A method according to any one of items 16 to 29, wherein: the intermediate structure further comprises: a second gate structure disposed on the substrate; a second gate spacer adjacent to a sidewall of the second gate structure; and a second etch stop spacer above the first dielectric layer and adjacent to the second gate spacer, the source / drain contact disposed between the etch stop spacer and the second etch stop spacer, and the second sidewall of the source / drain contact abutting a sidewall of the second etch stop spacer.

[0125] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0126] Further, it will be understood by those skilled in the art that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate such interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been generally described in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The technician can implement the described functionality in an alternative manner for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of this disclosure.

[0127] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0128] The methods, sequences and / or algorithms described in conjunction with the various aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An example storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative embodiment, the storage medium may be an integral part of the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., UE). In an alternative embodiment, the processor and storage medium may exist as discrete components in a user device.

[0129] In one or more example aspects, the functions described can be implemented with hardware, software, firmware or any combination thereof. If implemented with software, the functions can be stored on a computer-readable medium or transmitted as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, and the communication media include any media that facilitates the transfer of a computer program from one place to another. Storage media can be any available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or can be used to carry or store desired program code and any other media that can be accessed by a computer in the form of an instruction or data structure. In addition, any connection is appropriately referred to as a computer-readable medium. For example, if software is sent from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves, then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0130] Although the foregoing disclosure illustrates the illustrative aspects of the present disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of the disclosure defined by the appended claims. The steps and / or actions of the method claims according to the various aspects of the disclosure described herein do not need to be performed in any particular order. In addition, although each element of the present disclosure may be described or claimed in the singular, the plural form is contemplated unless expressly stated to be limited to the singular.

Claims

1. A semiconductor structure comprising: a gate structure disposed on the substrate; a gate spacer adjacent to a sidewall of the gate structure; a source / drain structure adjacent to the gate spacer; a first dielectric layer disposed on the substrate and the source / drain structure; an etch stop spacer overlying the first dielectric layer and adjacent to the gate spacer; an etch stop layer over and adjacent to an upper surface of the gate structure, an upper surface of the gate spacer, and an upper surface of the etch stop spacer; as well as A source / drain contact extends through the etch stop layer and the first dielectric layer and contacts the source / drain structure, with sidewalls of the source / drain contact abutting sidewalls of the etch stop layer and sidewalls of the etch stop spacer.

2. The semiconductor structure according to claim 1, wherein The etch stop spacer includes silicon nitride, aluminum oxide, aluminum nitride, or a combination thereof.

3. The semiconductor structure according to claim 1, wherein The width of the etch stop spacers ranges from 1 nm to 5 nm.

4. The semiconductor structure according to claim 1 , further comprising: a second gate structure disposed on the substrate; a second gate spacer adjacent to a sidewall of the second gate structure; as well as a second etch stop spacer overlying the first dielectric layer and adjacent to the second gate spacer, in: the source / drain contacts are positioned between the etch stop spacer and the second etch stop spacer, and Second sidewalls of the source / drain contacts abut sidewalls of the second etch stop spacers.

5. The semiconductor structure according to claim 4, wherein The width of the etch stop spacer is the same as the width of the second etch stop spacer. 6 . The semiconductor structure of claim 1 , further comprising a second dielectric layer overlying the first dielectric layer, the etch stop layer overlying and abutting an upper surface of the second dielectric layer.

7. The semiconductor structure according to claim 6, wherein: The second dielectric layer includes SiO2.

8. The semiconductor structure according to claim 1, further comprising a third dielectric layer above the etch stop layer, wherein The source / drain contacts extend through the third dielectric layer.

9. The semiconductor structure according to claim 8, wherein A width of a portion of the source / drain contact below the etch stop spacer is no greater than a width of a portion of the source / drain contact above the etch stop spacer.

10. The semiconductor structure of claim 9, wherein: The width of the portion of the source / drain contact below the etch stop spacer ranges from 5 nm to 15 nm, and The width of the portion of the source / drain contact above the etch stop spacer ranges from 10 nm to 20 nm.

11. The semiconductor structure according to claim 1, wherein The gate spacer has a relative dielectric constant no greater than a relative dielectric constant of SiO 2 .

12. The semiconductor structure according to claim 1, wherein The first dielectric layer has a relative dielectric constant not greater than that of SiO 2 .

13. The semiconductor structure according to claim 1, wherein The gate spacer includes SiBCN.

14. The semiconductor structure according to claim 1, wherein The first dielectric layer includes SiCOH or SiO2.

15. The semiconductor structure according to claim 1, wherein The source / drain contacts include cobalt, tungsten, or both.

16. A method of manufacturing a semiconductor structure, comprising: forming an opening in the intermediate structure, Wherein, the intermediate structure includes: substrate; a gate structure disposed on the substrate; a gate spacer adjacent to a sidewall of the gate structure; a source / drain structure adjacent to the gate spacer; a first dielectric layer disposed on the substrate and the source / drain structure; an etch stop spacer overlying the first dielectric layer and adjacent to the gate spacer; and an etch stop layer over and adjacent to an upper surface of the gate structure, an upper surface of the gate spacer, and an upper surface of the etch stop spacer, wherein the opening at least extends through the etch stop layer and the first dielectric layer and exposes the source / drain structure, and wherein a sidewall of the etch stop layer and a sidewall of the etch stop spacer define at least a portion of a sidewall of the opening; and A source / drain contact is formed in the opening, extending through the etch stop layer and the first dielectric layer and contacting the source / drain structure, with sidewalls of the source / drain contact abutting sidewalls of the etch stop layer and sidewalls of the etch stop spacer.

17. The method of claim 16, further comprising forming the intermediate structure, the intermediate structure comprising: forming a first spacer material layer on sidewalls of a first intermediate gate structure, the first intermediate gate structure being above the substrate; forming a second spacer material layer on at least a portion of a sidewall of the first spacer material layer; replacing the first intermediate gate structure with a second intermediate gate structure; as well as An upper portion of the first spacer material layer, an upper portion of the second spacer material layer, and an upper portion of the second intermediate gate structure are removed to form the gate spacer, the etch stop spacer, and the gate structure, respectively.

18. The method according to claim 17, wherein The removal is performed based on a chemical mechanical polishing (CMP) process.

19. The method according to claim 17, wherein The forming of the intermediate structure further comprises: forming the source / drain structure over the substrate and adjacent to the first spacer material layer before forming the second spacer material layer, the second spacer material layer directly overlying a first portion of the source / drain structure; Before forming the second spacer material layer, forming the first dielectric layer on the substrate and the source / drain structure; and A dielectric material layer is formed over the first dielectric layer, with a portion of the dielectric material layer adjacent to a sidewall of the second spacer material layer and directly over the second portion of the source / drain structure.

20. The method according to claim 19, wherein The forming of the intermediate structure further comprises: removing an upper portion of the dielectric material layer to form a second dielectric layer; and The etch stop layer is formed above and adjacent to the upper surface of the gate structure, the upper surface of the gate spacer, the upper surface of the etch stop spacer and the upper surface of the second dielectric layer.

21. The method according to claim 16, wherein The forming the source / drain contact in the opening comprises: filling the opening with a material comprising cobalt, tungsten, or both; and A chemical mechanical polishing (CMP) process is performed to remove excess portions of the material.

22. The method according to claim 21, wherein A width of a portion of the source / drain contact below the etch stop spacer is no greater than a width of a portion of the source / drain contact above the etch stop spacer.

23. The method of claim 22, wherein: The width of the portion of the source / drain contact below the etch stop spacer ranges from 5 nm to 15 nm, and The width of the portion of the source / drain contact above the etch stop spacer ranges from 10 nm to 20 nm.

24. The method according to claim 16, wherein The etch stop spacer includes silicon nitride, aluminum oxide, aluminum nitride, or a combination thereof.

25. The method according to claim 16, wherein The width of the etch stop spacers ranges from 1 nm to 5 nm.

26. The method according to claim 16, wherein The gate spacer has a relative dielectric constant no greater than a relative dielectric constant of SiO 2 .

27. The method according to claim 16, wherein The first dielectric layer has a relative dielectric constant not greater than that of SiO 2 .

28. The method according to claim 16, wherein The gate spacer includes SiBCN.

29. The method according to claim 16, wherein The first dielectric layer includes SiCOH or SiO2.

30. The method of claim 16, wherein: The intermediate structure further comprises: a second gate structure disposed on the substrate; a second gate spacer adjacent to a sidewall of the second gate structure; a second etch stop spacer overlying the first dielectric layer and adjacent to the second gate spacer, The source / drain contacts are placed between the etch stop spacer and the second etch stop spacer, and Second sidewalls of the source / drain contacts abut sidewalls of the second etch stop spacers.

Images