Calibration of imaging IWR digital pixels

Abstract

The invention relates to an imaging pixel consisting of a photodetector (102) connected to a readout circuit (110), comprising an integrating capacitor (CINT), a reset transistor (Mr1) for the integrating capacitor (CINT), a coupling transistor between the photodetector (102) and the integrating capacitor (CINT), a storage capacitor (CMEM), a second reset transistor (Mr2) for the storage capacitor (CMEM), and a storage switch (121) located between the integration capacitor (CINT) and the storage capacitor (CMEM) to enable different configurations corresponding to different phases of a parameter for estimating the pixel, in particular a ratio R = Cint / Cmem.

Description

Technical Field

[0001] The invention relates to the field of imaging devices, in particular imaging devices provided with IWR type ("Integrate While Read") pixels, for which the integration phase and the phase of reading the previously integrated phase can occur simultaneously.

[0002] More specifically, the present invention relates to pixels provided with an architecture for charge packet counting and utilizing the residual voltage on an integrating capacitor, and to an improved device capable of measuring specific parameters of an IWR pixel to estimate its dispersion relative to other pixels of the same imager and to perform calibration for the majority of the fixed spatial noise present on the imager. Background Art

[0003] Typically, an imager or image sensor is formed by an array of pixels, each of which is provided with a photodetector, such as a photodiode or a phototransistor, designed to convert electromagnetic radiation into an electrical signal. The photodetector is associated with a readout circuit.

[0004] Some imagers are designed to detect a specific range of wavelengths, and operate, for example, in the infrared region. Regardless of the wavelength range for which the imager is designed, the intention is to faithfully present a digital image across the entire surface of the imager that is within the widest possible operating range (from lowest intensity to highest intensity) that the imager should be able to measure. The goal is to be able to convert and measure the captured electromagnetic radiation with the highest possible resolution.

[0005] The principle for reading the measured value consists in integrating the current Id obtained from the photodetector by charging and discharging an integration capacitor which may have been previously charged or discharged to a predetermined value, over a predetermined period of time called integration time Tint.

[0006] Depending on the value of the current Id, which is proportional to the captured light energy, the integrating capacitor is discharged more or less quickly.

[0007] However, it can prove difficult to provide the integrating capacitor with sufficient value to enable the desired operating range in terms of minimum and maximum measurable light energy.

[0008] A circuit whose block diagram is shown in FIG1 can overcome this difficulty.

[0009] Since it is impossible to have a capacitor of sufficient value in each pixel, the integrating capacitor is charged or discharged multiple times, and the number of charges or discharges varies according to the light energy captured by the diode 2, and generally becomes larger as the discharge current Id becomes higher.

[0010] In this circuit, the voltage Vc at the terminals of the integrating capacitor Cpix is ​​caused to evolve between a fixed first reset voltage (in this example, equal to the supply voltage VDD of the capacitor Cpix) and a fixed second threshold voltage (in this example, denoted as Vref). When the voltage Vc at the terminals of the integrating capacitor Cpix reaches the voltage Vref, this voltage is detected by the comparator circuit 30, and the pulse generator stage 35 automatically generates a reset pulse 32 in the form of a charge injection Q0, which causes the charging of the integrating capacitor Cpix through the switch 20. Thus, a loop is formed.

[0011] When the switch 20 becomes conductive for the duration of the reset pulse, a rapid charge of the integration capacitor Cpix is ​​obtained. The charge and discharge cycle is automatically repeated over the entire duration of the integration Tint via the above loop. In each pixel, the number of completed charge and discharge cycles is counted by a counter 40.

[0012] This quantity therefore provides a measure of the amount of light energy captured by the photodiode 2 over the integration time Tint.

[0013] The value of the current Id, which is proportional to the captured light energy, depends on the number of completed charge (or discharge) cycles.

[0014] In order to improve the accuracy of the measured values, that is, to obtain the smallest possible difference between the two measurable signals, it is possible to consider performing an integration of the residual voltage v remaining at the terminals of the integration capacitor during the last charging or discharging interrupted by the lapse of the integration time Tint. residu measurement.

[0015] This voltage is Figure 2 , it is schematically shown in a specific case where the integrated voltage varies between the reset voltage Vreset and the threshold voltage Vref, where the threshold voltage Vref is higher than the reset voltage.

[0016] The number of times the integration capacitor Cint charges Q0 over the integration time Tint is counted, and the quantization resolution is Q0. Q0 should be small, so the number of bits should be high to obtain suitable resolution and low quantization noise.

[0017] At the end of the integration, digital information is obtained originating from the counter of each pixel, as well as information related to the residual voltage at the bottom of the column digitized by the analog-to-digital converter 50 .

[0018] Nevertheless, the information of the counter 40 only indicates the number of charge packets. Therefore, the value of the charge packet Q0 should be known. This result can be obtained because Cpix, Vreset and Vref are known. One difficulty is that each pixel is affected by the parameter dispersion of the components that make up the pixel, in particular the parameter dispersion of the transistors of the comparator 30, which detects the period when the voltage of the integrating capacitor exceeds the threshold voltage Vref. This results in that the voltage used to trigger the reset can vary from one pixel to another. This voltage for the i-th pixel of the array can be equal to Vref+Voffset(i). Similarly, due to the different voltage drops in the connections that distribute the reset voltage Vreset in the pixel array, the reset voltage Vreset may not be exactly the same for each pixel.

[0019] Document EP 2 687 020 B1 presents an architecture and a method for accurately measuring such information Vseuil+Voffset(i) and Vreset(i) for each pixel.

[0020] In the above devices, the reading circuits capable of counting charge packets and using the residual voltage all operate according to the ITR (“Integrate Then Read”) mode, ie for the ITR mode the integration phase and the reading phase occur successively.

[0021] However, for some applications, it may be desirable to maximize the integration time in order to capture as much signal (photons) as possible while limiting the time during which no scene is observed. For this purpose, there are pixels whose readout circuitry operates according to the so-called "IWR" ("IntegrateWhile Read") mode, in which the integration phase and the readout phase occur simultaneously.

[0022] Compared to ITR pixels, IWR pixels usually also include additional so-called "storage" capacitors.

[0023] The calibration implemented in the aforementioned document EP 2 687 020 B1 is valid in the context of pixels operating in ITR mode, but may prove to be insufficient in the case of IWR pixels. Summary of the Invention

[0024] According to one aspect, the invention relates to an imaging device comprising a plurality of pixels, each pixel being formed by a photodetector associated with and connected to a reading circuit, the imaging device comprising:

[0025] an integrating capacitor connected to the first node and intended to store the charge originating from the photodetector,

[0026] - a first reset transistor configured to reset the integration capacitor when the first reset transistor is turned on,

[0027] at least one so-called "coupling" transistor, which is arranged between the photodetector and the integrating capacitor and is capable of alternately coupling the photodetector to the first node when the at least one so-called "coupling" transistor is conducting and decoupling the photodetector from the first node when the at least one so-called "coupling" transistor is non-conducting,

[0028] - a storage capacitor connected to the second node,

[0029] - a second reset transistor configured to reset the storage capacitor when the second reset transistor is turned on,

[0030] a so-called “storage” switch located between the integrating capacitor and the storage capacitor, which connects the integrating capacitor and the storage capacitor when the “storage” switch is conducting and disconnects the integrating capacitor from the storage capacitor when the “storage” switch is not conducting.

[0031] Thus, by introducing a storage switch and a coupling transistor, an IWR type pixel is realized, which can adopt different configurations depending on whether we are in normal operation mode or in an operation mode in which one or more measurements are performed to perform calibration.

[0032] Advantageously, the device further comprises a circuit for controlling the reading circuit, the circuit being configured to, during a measurement cycle comprising a phase of estimating the ratio R=Cint / Cmem between the value of the integrating capacitance and the value of the storage capacitance:

[0033] - according to a first part of the phase of estimating the ratio R, rendering the first reset transistor and the second reset transistor conductive to reset the integration capacitor and the storage capacitor, respectively, and rendering the storage switch non-conductive to disconnect the integration capacitor from the storage capacitor, and decoupling the photodetector from the first node during the first phase and during the first part, and then,

[0034] - according to a second part of the estimation phase, the first and second reset transistors are rendered non-conductive and the storage switch is rendered conductive in order to connect the first node and the second node and thus enable estimation of a potential at the second node representative of the ratio R=Cint / Cmem.

[0035] When estimating this ratio R, the compression effect that occurs when connecting the integrating and storage capacitors is taken into account. This compression depends on the ratio Cint / Cmem, where Cint represents the value of the integrating capacitor, but also all parasitic capacitances added at this node, in particular the input capacitance of the compressor. Similarly, Cmem represents the value of the storage capacitor and the parasitic capacitances added at this node. Therefore, the dispersion associated with these values ​​from one pixel to another causes the capacitance ratio to vary from one pixel to another. By estimating this ratio R, correction data is added, making it possible to perform improved calibration for each pixel.

[0036] Advantageously, the reading circuit further comprises:

[0037] a comparator connected to the integrating capacitor, a first input of the comparator coupled to the first node, a second input of the comparator set to a reference voltage,

[0038] a pulse generator block located at the output of the comparator and configured to continuously emit pulses for triggering a reset of the integration capacitor through the first reset transistor when the pulse generator block is coupled to the first reset transistor and when the first input reaches a reference voltage.

[0039] The read circuit may further include:

[0040] - a pulse counter, which is located at the output of the pulse generator,

[0041] - an element for storing the count digital data obtained from the pulse counter.

[0042] According to a possible implementation, the control circuit may be configured to generate, during said phase of estimating said ratio, an operating mode control signal to:

[0043] During the first portion: setting the operating mode control signal to a first state to set the pulse generator block to a first operating mode in which the pulse generator block maintains a signal at the output for triggering a reset of the integrating capacitor regardless of the first input, and then

[0044] During the second portion: the control signal is set to a second state to set the pulse generator block to a second mode corresponding to the normal operating mode.

[0045] According to an advantageous embodiment, the device may further comprise a switching circuit provided with at least one first switch arranged between the output of the comparator and the first reset transistor and a second switch arranged between the output terminals of the pulse generator.

[0046] The first reset transistor and the second reset transistor can be controlled by the control circuit and are intended to connect the output of the comparator directly to the reset transistor during at least one phase of the reference voltage estimation measurement cycle and to connect the output of the pulse generator to the first reset transistor during a so-called "normal operation" period or at least one other phase of the measurement cycle.

[0047] The control circuit of the read circuit may further be configured to, during the phase of estimating the reference voltage Vref at the input of the comparator:

[0048] - rendering the first switch conductive while rendering the second switch non-conductive, while connecting the first node to the second node, to enable estimation of the value of the reference voltage from the potential at said second node.

[0049] According to a possible implementation, the resetting of the storage capacitor is completed at a first reset voltage, and the control circuit can be configured to: reset the integration capacitor and simultaneously turn on the storage switch to connect the integration capacitor to the storage capacitor during the phase of estimating the first reset voltage in the measurement cycle.

[0050] According to a possible implementation, the resetting of the storage capacitor is completed at a second reset voltage, and the control circuit can be configured to: reset the storage capacitor while making the storage switch non-conductive during the phase of estimating the second reset voltage in the measurement cycle to disconnect the integration capacitor from the storage capacitor.

[0051] Advantageously, the coupling transistor may be arranged in series with a bias stage of the photodetector, in particular a direct injection (DI) or buffered direct injection (BDI) bias stage.

[0052] The coupling transistor typically includes one electrode of its source or drain connected to the electrode of the photodetector and the other electrode of its drain or source connected to the integration capacitor, and the control circuit of the reading circuit is configured to apply a signal to the gate of the coupling transistor for triggering the decoupling of the photodetector from the first node during the first step of the phase of estimating the ratio R.

[0053] According to certain embodiments, the coupling transistor may be a direct injection (DI) bias transistor of the photodetector.

[0054] Advantageously, the read circuit may further be provided with a follower transistor and a line selection transistor coupled to the second node.

[0055] According to a possible implementation, the first reset transistor includes an electrode set to a first reset voltage, and the second reset transistor includes an electrode set to a second reset voltage different from the first reset voltage.

[0056] This can better adapt to the dynamic voltage range of the output and can provide different reset voltages to the storage capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The present invention will be better understood from the following description and accompanying drawings, in which:

[0058] FIG. 1 is intended to illustrate a method according to the related art. A readout circuit for an imaging pixel of the type;

[0059] Figure 2 The aim is to show the evolution of the voltage at the terminals of the integration capacitor during an integration time and the residual voltage which it is hoped to be able to determine at the end of this integration time;

[0060] Figure 3 It is intended to illustrate an embodiment of a circuit for reading an IWR type imaging pixel implemented according to the present invention;

[0061] Figure 4 Intended to illustrate examples of control signal sequences for different elements of a readout circuit, which may be performed during different evaluation phases implemented during a measurement cycle performed on an IWR imaging pixel according to the present invention;

[0062] Figure 5 Intended to illustrate a variant of a readout circuit provided with a direct injection transistor for biasing a photodetector and a coupling transistor arranged between the photodetector and an integrating capacitor and enabling the photodetector to be isolated from the rest of the readout circuit;

[0063] Figure 6 Intended to illustrate a variation in which the coupling transistors and the direct injection transistors between the photodetector and the integrating capacitor are arranged in the same order as in Figure 6 The order is reversed;

[0064] Figure 7 Intended to illustrate a variant of a readout circuit having a biasing stage, other than biasing by direct injection, arranged in series with a coupling transistor arranged between the photodetector and the integrating capacitor;

[0065] Figure 8 Intended to illustrate a variant in which the bias stages and coupling transistors are distributed in the same order as Figure 7 The order is reversed;

[0066] Figure 9 Intended to illustrate a variant of a readout circuit having a direct injection transistor serving as a coupling transistor arranged between a photodetector and an integrating capacitor;

[0067] Figure 10 Intended to illustrate a variant of the readout circuit with a coupling transistor but without a stage for biasing the photodetector;

[0068] Figure 11 Intended to illustrate a variant arrangement of a readout circuit, which is suitable for connecting the readout circuit to a region P of a P-on-N type photodiode;

[0069] Figure 12A and Figure 12B The linear simulation results of one pixel are given for arbitrary values ​​of the integration capacitor and the storage capacitor and the values ​​obtained by means of the calibration method implemented according to the present invention;

[0070] Figure 13A and Figure 13B It is intended to illustrate a variation of the arrangement of the read circuit;

[0071] Identical, similar or equivalent parts of the various figures have the same reference numerals to facilitate moving from one figure to another.

[0072] To make the drawings easier to read, the various parts shown in the drawings are not necessarily based on a uniform scale. DETAILED DESCRIPTION

[0073] exist Figure 3 An example of the structure of the imaging reading circuit 110 implemented according to an embodiment of the present invention is given in FIG.

[0074] Readout circuit 110 is connected to a photodetector, such as photodiode 102, that converts electromagnetic radiation into a current Id. The associated photodiode 102 and readout circuit 110 form a detection element, also referred to as a "pixel." An imager typically includes a plurality of pixels P(i, j), which may also be arranged in an array having i rows and j columns (i, j being integers equal to or greater than 1).

[0075] According to certain embodiments, the photodiode 102 may be designed to operate in the infrared domain, and then the photodiode 102 is typically reverse polarized and delivers a current Id representative of the observed scene to the readout circuit 110 .

[0076] Herein, the read circuit 110 has an IWR type (standing for “Integrate While Read”) structure that is capable of performing integration and simultaneously performing readout of the value of a signal resulting from a previous integration due to the presence of a memory stage.

[0077] Therefore, in addition to the integration capacitor C connected to the first node N1 INTIn addition, the read circuit 110 is further provided with a storage capacitor C connected to the second node N2. MEM .

[0078] Herein, the read circuit 110 is special in that: the read circuit 110 is further provided with a so-called “storage” switch 121 between the first node N1 and the second node N2 .

[0079] The switch 121, which is typically formed of one or more transistors, is configured to connect the integrating capacitor C to the integrator capacitor C when the switch 121 is turned on (ie, closed). INT and storage capacitor C MEM When the switch 121 is not conducting (ie, open), the integral capacitor C INT With the storage capacitor C MEM Disconnect. Thus, such a switch 121 enables the reading circuit 110 to adopt different configurations, in particular different configurations according to the different phases of the measurement cycle that the reading circuit 110 may adopt, so as to be able to perform calibration of the pixel. The storage switch 121 enables the coupling of the reading circuit 110 to the first node N1 and the integration capacitor C INT A portion of the read circuit is coupled to the second node N2 and the storage capacitor C MEM The other parts can be alternately spaced apart from each other or connected together.

[0080] The integrating capacitor C can be connected to the INT and storage capacitor C MEM In this structure where two capacitors C are connected to store residual voltage, it should be considered that INT and C MEM The compression effect that may occur when the two terminals are connected is determined by the ratio R = Cint / Cmem, which may be specific to each pixel and should be estimated in this context. Cint represents the value of the integrating capacitor, taking into account the parasitic capacitance added at the first node N1, in particular the input capacitance of the comparator 130. Similarly, Cmem represents the value of the storage capacitor, taking into account the parasitic capacitance added at the second node N2. Therefore, the dispersion associated with these values ​​from one pixel to another leads to differences from one pixel to another in relation to this ratio R to be estimated.

[0081] The measurement of this ratio R should be performed without introducing a large number of additional components, in particular without introducing a large number of additional transistors in the pixel.

[0082] A specific estimation phase of the measurement cycle is implemented to estimate this ratio R.

[0083] The first part of the phase is based on the estimated ratio R, by adding capacitors C INT 、CMEM Each capacitor C is independently reset at its own reset voltage Vresetmem and VresetInt. INT 、C MEM Advantageously, these reset voltages Vresetmem, VresetInt can be different from each other. In particular, different respective reset voltages Vresetmem, VresetInt can enable the detection dynamics to be extended.

[0084] Integrating capacitor C INT The resetting of is achieved by means of the first reset transistor Mr1 coupled to the first node N1.

[0085] When the first reset transistor Mr1 is turned on, the first reset transistor Mr1 enables the first reset voltage VresetInt to be applied to the integration capacitor C INT . Storage capacitor C MEM The resetting of the storage capacitor C is achieved by means of a second reset transistor Mr2 coupled to the node N2. When the second reset transistor Mr2 is turned on, the second reset transistor Mr2 enables the second reset voltage Vresetmem to be applied to the storage capacitor C. MEM .

[0086] Then, according to the second part of the phase of the estimated ratio R, the reset transistors Mr1 and Mr2 are deactivated, in other words, by blocking or not conducting the reset transistors Mr1 and Mr2, and by switching the capacitor C INT 、C MEM Connect together to disable reset.

[0087] Before the second stage, an integrating capacitor C INT The coupling transistor Mc between the photodiode and the photodetector cuts off the photodiode current 102.

[0088] To enable the phase of estimating the ratio R, a circuit 199 is provided for controlling the reading circuit 110 and enables the application of various control signals. The control circuit 199 is typically a circuit external to the pixel array and, in particular, includes logic blocks. The control circuit 199 can also be implemented by a microprocessor or a programmable logic circuit (FPGA).

[0089] exist Figure 4 An example of a time diagram of the evolution of the control signal is given in FIG. In this context, the phase of estimating the ratio R is marked Φ4 in the diagram and belongs to the measurement period during which the different parameters can be estimated. Figure 4In the embodiment, the signals Sresetmem and Srap are signals applied to the gate of the second reset transistor Mr2 and the gate of the coupling transistor Mc respectively and enable the second reset transistor Mr2 and the coupling transistor Mc to be alternately turned on or off, and the signal S 121 is the control signal of the switch 121. Therefore, the signal S obtained from the control circuit 199 can be used to 121 To control the open or closed (ie, non-conducting or conducting, respectively) state of the storage switch 121.

[0090] Signal S INT is a control signal applied to the pulse generator block 135 and is based on the signal S INT state, so that the pulse generator block 135 can be alternately set to be in the first operating mode or the second operating mode.

[0091] By applying a signal S at this position of the device INT , it is advantageous to be able to use the same reset transistor Mr1 to reset the integration capacitor C each time the threshold voltage Vref is exceeded. INT The first node N1 is discharged and can be kept at the voltage VresetInt when the operation is closed in the integration phase.

[0092] When no integration is performed, the signal S INT It can be set to be in the first state, for example, so that S INT =0 to force the pulse generator block 135 into a first operating mode in which the pulse generator block 135 continuously outputs a reset signal on the gate of the reset transistor Mr1 and enables the reset transistor Mr1 to turn on, regardless of the value on its input E1.

[0093] During the integration phase, the signal S INT Usually set to different states, such as making S INT =1, in which case the pulse generator block 135 operates in a second so-called "normal" mode, during which the pulse generator block 135 only generates a reset pulse each time a threshold value is exceeded, in other words, the pulse generator block 135 generates a reset pulse when a signal at its input indicates that the voltage Vref is exceeded.

[0094] Therefore, the control circuit 199 is configured to estimate the ratio R according to the first part of the phase ( Figure 4 The first part of the stage Φ4 41 ) turns on the first reset transistor Mr1 and the second reset transistor Mr2 to pass the integrated capacitor C INT Applying the reset voltage VresetInt makes the integration capacitor C INTreset and pass to the storage capacitor C MEM Applying the reset voltage Vresetmem causes the storage capacitor C MEM Reset and make the storage switch 121 non-conductive so that the integral capacitor C INT With the storage capacitor C MEM Disconnect.

[0095] exist Figure 3 and Figure 4 In the particular embodiment shown, the reset transistor Mr2 is a transistor of the NMOS type, with a gate (in the first part of phase Φ4) 41 During the period) the signal Sresetmem is set to a high state so that the storage capacitor C MEM Can be reset.

[0096] exist Figure 3 and Figure 4 In the particular embodiment shown, the coupling transistor 121 is an NMOS type transistor, on its gate (in the portion Φ 41 During the period) set to the signal S in the low state 121 The integrating capacitor C INT Capable of storing capacitor C MEM Separate.

[0097] In the first part of the phase of estimating the ratio R (part Φ of phase Φ4) 41 ) during which the signal Srap applied to the gate of the decoupling transistor Mc is modified (in a specific embodiment where Mc is a PMOS type transistor, Srap is applied to the gate of the decoupling transistor Mc during which the signal ... 41 is set to be in a high state) so that the photodetector 102 and the integration capacitor C INT Decoupling.

[0098] Furthermore, the signal S INT It is typically arranged to be in a state where the pulse generator block 135 is placed in its above-mentioned first mode of operation.

[0099] According to the second part of the phase of the estimated ratio R in the measurement period (part Φ of phase Φ4) 42 ), the control circuit 199 makes the first reset transistor Mr1 and the second reset transistor Mr2 non-conductive and turns on the storage switch 121 to connect the first node N1 and the second node N2. Figure 4 The time diagram of the part Φ 42 medium signal S INT 、S resetmem and S 121 Then, the signal S INTThe state is set to set the pulse generator block 135 to be in its second operating mode (in other words, the above-mentioned normal operating mode of the pulse generator block 135).

[0100] Thus, during the phase Φ4 of estimating the ratio R, the block 135 is alternately placed in its first operating mode and then in its second operating mode.

[0101] The ratio R can be estimated by estimating the potential at the second node N2.

[0102] Therefore, the voltage Vf on the second node N2 can be read by means of a follower. Therefore, in the example shown, the read circuit 110 is further provided with a follower transistor M coupled to the second node N2. 11 and line selection transistor M 21 In this paper, by applying the selection transistor M 21 The selection is performed by a signal sel on the gate of the pixel. The voltage Vf can be read at the root of the column of pixels to which the pixel Pi,j whose ratio R is to be estimated is connected. The read voltage is usually converted into a piece of data, which is digitized by means of an analog-to-digital converter 150 arranged at the root of the column.

[0103] This final voltage Vf read across the follower satisfies the following equation:

[0104] V f (C int +C mem )=C mem V resetMem +C int V resetInt ,

[0105] Wherein, VresetInt and Vresetmem correspond to the first reset voltage and the second reset voltage respectively.

[0106] This equation can also be expressed as follows:

[0107]

[0108] Each pixel of the imager can have a ratio specific to each pixel:

[0109]

[0110] Advantageously, this ratio is estimated for each pixel of the imager:

[0111]

[0112] Typically, the read circuit 110 further includes a comparator 130 located upstream of the pulse generator 135, and the comparator 130 is provided with a capacitor coupled to the integration capacitor C INT The first input terminal E1 and the second input terminal E2 set to the reference voltage Vref may also be desired for each pixel of the array, in particular for Figure 3 The pixel Pi,j shown measures or estimates a reference voltage Vref.

[0113] A pulse generator block 135 is provided at the output of the comparator 130. This pulse generator block 135, provided for example with a monostable latch and a switching element, is configured to emit a pulse for triggering the integration capacitor C via the first reset transistor Mr1 in its second so-called "operation" operating mode when the first input E1 reaches the reference voltage Vref. INT When the reference voltage Vref is reached, the output of the comparator 130 switches, which causes a pulse to be emitted at the output of the generator block 135. The pulse is applied to the gate of the first reset transistor Mr1, and then the reset voltage VresetInt is applied to the integration capacitor C through the loopback on the first node N1. INT superior.

[0114] Here, at the output of the pulse generator block 135 , the read circuit 110 generally includes an integrating pulse counter 140 and an element 144 for storing count digital data at the output of the pulse counter 140 .

[0115] The read circuit 110 is further provided with a switch circuit including a first switch 132 arranged between the output of the comparator 130 and the first reset transistor Mr1 and a second switch 134 arranged between the output of the pulse generator block 135 and the first reset transistor Mr1 .

[0116] Depending on the state of the signal Scalib emitted by the control circuit 199 , the first switch 132 is intended to alternately connect the output of the comparator 130 directly to the first reset transistor Mr1 or to disconnect the output of said comparator 130 from the first reset transistor Mr1 .

[0117] Depending on the state of the signal Scalib emitted by the control circuit 199 , the second switch 134 is intended to alternately connect the output of the pulse generator block 135 to the first reset transistor Mr1 or disconnect it from the reset transistor Mr1 .

[0118] Herein, both the first switch 132 and the second switch 134 are controlled by the signal Scalib.

[0119] During the calibration phase Φ1, signal Scalib is in a first logic state, for example, such that Scalib=1, to position first switch 132 in a conductive (i.e., closed) state and second switch 134 in a non-conductive (i.e., open) state. Feedback is then performed by the output of comparator 130 to control first reset transistor Mr1. ​​In this configuration, first node N1 can be set to a voltage of Vref+Voffset.

[0120] The change in the state of signal Scalib causes the corresponding states of switches 132 and 134 to change. Thus, when signal Scalib is in a second logic state, such as Scalib = 0, first switch 132 is set to a non-conductive (i.e., open) state, and second switch 134 is set to a conductive (i.e., closed) state. Feedback is then performed by the output of pulse generator block 135.

[0121] Thus, the switching circuit provided with the switches 132, 134 can realize different configurations. In particular, the output of the comparator 130 is directly connected to the reset transistor Mr1 during at least one phase of the measurement cycle, while the output of the pulse generator block 135 is connected to the first reset transistor Mr1 during the so-called "normal operation" period or at least one other phase of the measurement cycle.

[0122] Preferably, as a complement to being able to perform an effective calibration of the pixels Pi,j, further information of the above-mentioned ratio R is estimated.

[0123] Therefore, the measurement cycle implemented on the pixel Pi,j may also include a phase of estimating the value of the reference voltage Vref at the input E1 of the comparator 130. Such a phase of estimating the reference voltage Vref may be performed before the phase of estimating the ratio R in the measurement cycle.

[0124] Therefore, in Figure 4 In the embodiment shown, the stage ( Figure 4 The portion Φ1) of the time diagram of corresponds to the first phase of the measurement cycle, during which the ratio R is estimated as also described before.

[0125] During this estimation phase, the control circuit 199 turns on the first switch 132 and turns off the second switch 134, and the first node is connected to the second node through the turned-on switch 121 to enable the value of the reference voltage Vref to be estimated based on the potential at the second node.

[0126] The measurement cycle implemented on the pixel Pi,j may also include the estimation of the storage capacitor C MEMThe value of the reset voltage Vresetmem is set at this stage.

[0127] Such a phase of estimating the second reset voltage Vresetmem may be performed before the phase of estimating the ratio R in the measurement cycle.

[0128] exist Figure 4 In the embodiment shown, such an estimation phase ( Figure 4 The portion Φ2 of the time diagram of FIG. 1 is performed after the phase of estimating the voltage Vref (corresponding to the portion Φ1 ) and before the phase of estimating the ratio R (portion Φ4 ), in particular corresponding to the second phase of the measurement cycle.

[0129] To perform this phase, the control circuit 199 is configured to cause the storage capacitor C MEM Reset, and make the storage switch 121 non-conductive. Therefore, the integration capacitor C INT With the storage capacitor C MEM Disconnect.

[0130] Then, after this reset, by means of the follower M 11 Estimation of the potential at the second node N2 enables obtaining a measured value of the second reset voltage Vresetmem of the pixel Pi,j.

[0131] The measurement cycle implemented on the pixel Pi,j may also include the estimation of the integration capacitor C INT The reset voltage Vresetint is the voltage value of the stage.

[0132] Such a phase of estimating the first reset voltage Vresetint may be performed before the phase of estimating the ratio R in the measurement cycle.

[0133] exist Figure 4 In the embodiment shown, such that the integrating capacitor C INT The phase of reset (part Φ3 of the time diagram) corresponds in particular to the third phase of the measurement cycle. To perform this phase, the control circuit 199 is configured to modify the signal S sent to the pulse generator block 135. INT , so that the block 135 is set to its first operating mode. In the first operating mode, regardless of the input value of the block 135, the block 135 continuously generates a reset signal on the gate of the reset transistor Mr1 and enables the reset transistor Mr1 to be turned on to make the integration capacitor C INT Reset. The control circuit 199 is reset by the signal S 121 The storage switch 121 is turned on. Therefore, the integration capacitor C INT and storage capacitor C MEM are connected.

[0134] The evaluation of the potential at the second node N2 by means of a follower, carried out continuously with this resetting, then makes it possible to obtain a measured value of the first reset voltage Vresetint of the pixel Pi,j.

[0135] Thanks to these values ​​obtained for each pixel during the measurement period, it is possible to calculate the integrated signal for each pixel independently.As indicated before, the accurate readout of the current uses two values: the one in the counter 140 and the residual voltage.

[0136] These two values ​​can be expressed by the following expressions (in units of charge):

[0137] Q com pteur =N com pteur *C int *(V ref -V resetInt )

[0138] and

[0139] Q residu =(C mem +C int )*V f -C mem *V resetMem -C int *V resetInt

[0140] where Vf is the residual voltage read at the end of integration on the storage capacitor.

[0141] Measuring the period enables us to obtain the values ​​Vref, VresetInt, VresetMem and the ratio R=Cint / Cmem.

[0142] Therefore, Qresidu can be rewritten so as not to rely on C mem .

[0143]

[0144] Therefore, of the total charge, which includes Qcompteur and Qresidu, only Cint remains, which is not estimated for each pixel. If Cint varies between pixels, this will produce a gain error related to the total charge between pixels. Such gain variations can be measured and corrected by taking measurements while subjecting the photodetector to at least two different light fluxes.

[0145] To illustrate the interest in the measured value of the ratio R = Cint / Cmem, a Figure 12A The simulation of the linearity of the pixel is shown in FIG.

[0146] In this figure, Vmem is the signal measured at the pixel's output that varies according to flux. Vreg is the line obtained from linear regression. The small error between the two means they overlap. C_Ecart represents the difference between these two values, thus indicating nonlinearity.

[0147] In order to calculate the integrated total charge corresponding to each flux, the values ​​of the injected integration capacitor and the storage capacitor are set.

[0148] It should be noted that the ratio R is different from the ratio found when considering the ratio of the values ​​of the injected capacitances.

[0149] When using the capacitance values ​​obtained using the measurement cycle as described previously, we obtain Figure 12B The new nonlinear curve is shown.

[0150] In this example, the ideal ratio of R considering only the capacitance value is 6, but the calibration results in an actual R of 5.706.

[0151] exist Figure 5 In the variant of the pixel Pi,j shown, the current emitted by the photodiode 102 passes through a so-called direct injection (DI stands for "direct injection") structure, which is used to appropriately bias the photodiode 102. In this context, the biasing structure is in the direct injection transistor M DI The form of, and makes the integration capacitor C INT During the current integration, the polarization of the photodiode 102 can be kept fixed, and the photodiode 102 and the integration capacitor C INT The voltage change at the terminal of the direct injection transistor M is isolated. DI is arranged between one electrode of the photodiode 102 and one electrode of the coupling transistor Mc. Furthermore, the coupling transistor is arranged between the transistor Mc DI One electrode of the integrating capacitor C INT between.

[0152] Direct injection transistor M DI and the reverse distribution between the coupling transistor Mc. Therefore, Figure 7 In the embodiment shown, the coupling transistor Mc is arranged between one electrode of the photodiode 102 and the direct injection transistor M DI Furthermore, the direct injection transistor M DI Arranged between one electrode of the coupling transistor Mc and the integrating capacitor C INT between.

[0153] Biasing configurations other than direct injection (DI) mounting are also available.

[0154] Therefore, in Figure 7 In the embodiment shown, a bias block 120 for the photodiode 120 is arranged between the photodiode 102 and the coupling transistor Mc. According to a particular embodiment, this bias block 120 can, for example, follow a BDI type (standing for "buffered direct injection") installation. In this type of installation, an amplifier is provided, in particular a gain differential amplifier A, which generally comprises an input terminal set to a fixed voltage and another input terminal coupled to the drain or source of a direct injection transistor, the other source or drain of the DI type transistor being connected to the photodiode. The output terminal of the amplifier A controls the gate voltage of the direct injection transistor. Thus, feedback is established on the signal used to bias the photodiode 102. Such a biasing architecture solves the need to reduce the input impedance of the reading circuit 110 while limiting the number of additional transistors required.

[0155] Here again, an inverse distribution between the bias block 120 and the coupling transistor Mc may be provided. Figure 8 In the embodiment shown, the coupling transistor Mc is arranged between one electrode of the photodiode 102 and the bias block 120. Furthermore, the bias block 120 is arranged between one electrode of the coupling transistor Mc and the integration capacitor C INT between.

[0156] exist Figure 9 In another variation shown, a direct injection transistor M is used to bias the photodiode 102. DI It also serves as a coupling transistor to alternately couple the photodiode 102 to capacitors in the rest of the readout circuit 110, particularly to the integrating capacitor C INT , and decoupling (ie, isolating) the photodiode 102 from the rest of the readout circuit 110, particularly from the integrating capacitor C INT Thus, as previously indicated, during the phase of the measurement cycle where the ratio R is estimated (at which phase the photodiode 102 is first coupled to the readout circuit 110), a voltage applied to the coupling transistor (herein corresponding to the direct injection transistor M) is applied. DI ) enables the current from the photodiode 102 toward the reading circuit 110 to be cut off. During the measurement cycle, when it is desired to measure the capacitance ratio R, the gate voltage is modified so that it places the transistor in an open circuit instead of in cascade.

[0157] There are also possible embodiments without a bias stage, where as in Figure 10 In the embodiment, the coupling transistor Mc is connected to one electrode of the photodiode 102 and directly connected to the first node N1.

[0158] As an alternative to any of the previously described embodiments, a P-on-N photodiode can be provided instead of the N-on-P diode 102 .

[0159] In this case, the reset transistors Mr1 and Mr2 can be composed of PMOS transistors. DI In this case, it can be composed of NMOS transistors. Follower transistor M 11 and line selection transistor M 12 It may also be an NMOS transistor.

[0160] Examples of such variations are for example Figure 11 , where the N-on-P type photodiode 102 includes an anode set to a fixed potential VSUPV and a cathode connected to a coupling transistor Mc.

[0161] exist Figure 13A and Figure 13B An alternative embodiment of the readout circuit described above is given in .

[0162] For this variant, in normal operating mode ( Figure 13A ), the switch 134′, called the second switch, disposed between the output terminal of the pulse generator block 135 and the first reset transistor Mr1 is closed (ie, turned on), and transmits a reset pulse on the gate of the reset transistor Mr1. Figure 13B ), one or more measurements are performed to perform calibration. A switch 132′, referred to as a first switch and located between the input E1 and the output of the comparator 130, is closed to connect the output of the comparator 130 to the input E1. The comparator 130 then operates as a follower while evaluating the reference voltage Vref at the second input E2. The switch 134′ is then opened (i.e., non-conductive), and an additional switch 136, located between the second switch 134′ and the reset transistor Mr1, is closed (conductive).

[0163] This additional switch 136, arranged between the gate of transistor Mr1 and a given potential (in this example, a reference potential corresponding to ground), ensures that reset transistor Mr1 is indeed blocked or disconnected, so that in this mode of reading voltage Vref, reset transistor Mr1 does not intervene. This variant of measuring voltage Vref can be used independently of the other calibration and measurement methods described above. In particular, this variant of measuring Vref can be used in other readout circuits of the photodiode, for example in the presence of a single integrating capacitor.

Claims

1. An imaging device comprising a plurality of pixels, each pixel (Pi,j) being formed by a photodetector (102) associated with and connected to a reading circuit (110), the imaging device comprising: -Integrating capacitor (C INT ), said integrating capacitor being connected to a first node (N1) and intended to store the charge originating from said photodetector, a first reset transistor (Mr1) configured to cause the integration capacitor (C INT ) reset, - at least one so-called "coupling" transistor (Mc) arranged between the photodetector (102) and the integrating capacitor (C INT ), and capable of alternately coupling the photodetector (102) to the first node (N1) when the at least one so-called "coupling" transistor is conducting and decoupling the photodetector (102) from the first node (N1) when the at least one so-called "coupling" transistor is non-conducting, - Storage capacitor (C MEM ), the storage capacitor is connected to a second node (N2), a second reset transistor (Mr2) configured to enable the storage capacitor (C MEM ) reset, - Located at the integrating capacitor (C INT ) and the storage capacitor (C MEM ) between the so-called "storage" switch (121), when the "storage" switch is turned on, the "storage" switch will INT ) and the storage capacitor (C MEM ) are connected, and when the "storage" switch is not conducting, the "storage" switch causes the integration capacitor (C INT ) and the storage capacitor (C MEM ) to disconnect, The device further comprises: a circuit (199) for controlling the reading circuit (110), the circuit (199) being configured to, during a measurement cycle comprising a phase of estimating a ratio (R=Cint / Cmem) between an estimated value of the integrating capacitance and an estimated value Cmem of the storage capacitance: - according to a first part of the phase of estimating the ratio (R), turning on the first reset transistor (Mr1) and the second reset transistor (Mr2) to respectively turn on the integration capacitor (C INT ) and the storage capacitor (C MEM ) is reset and the storage switch (121) is non-conductive so that the integration capacitor (C INT ) and the storage capacitor (C MEM ) is disconnected, and during the first phase and during the first portion, the photodetector (102) is decoupled from the first node (N1), and then, - According to a second part of the estimation phase, the first reset transistor (Mr1) and the second reset transistor (Mr2) are rendered non-conductive and the storage switch (121) is rendered conductive, so as to connect the first node (N1) and the second node (N2) and thereby enable estimation of a potential (Vf) at the second node (N2) representing the ratio (R=Cint / Cmem).

2. The imaging device according to claim 1, wherein The reading circuit (110) further includes: - a comparator (130) connected to the integrating capacitor (C INT ), the first input terminal (E1) of the comparator is coupled to the first node (N1), the second input terminal (E2) of the comparator (130) is set to be at a reference voltage (Vref), a pulse generator block (135) located at the output of the comparator (130) and configured to, in a normal operating mode, continuously emit a pulse for triggering the integration capacitor (C) via the first reset transistor (Mr1) when the pulse generator block is coupled to the first reset transistor (Mr1) and when the first input terminal (E1) reaches the reference voltage; INT ) reset pulse.

3. The imaging device according to claim 2, wherein The control circuit (199) is configured to generate an operating mode control signal (S) during the phase of estimating the ratio INT ), During the first part: the operation mode control signal (S INT ) is set to a first state to set the pulse generator block (135) to a first operating mode in which the pulse generator block (135) maintains a current at the output terminal for triggering the integrating capacitor (C INT ) of the reset signal, regardless of the first input terminal (E1), then During the second part: the control signal (S INT ) is set to a second state to set the pulse generator block (135) to a second mode corresponding to the normal operating mode.

4. The imaging device according to claim 2 , wherein: The reading circuit (110) further includes: a pulse counter (140) located at the output of the pulse generator (135), - an element (144) for storing the count digital data obtained from the pulse counter (140).

5. The device according to claim 2 , further comprising a switching circuit provided with at least one first switch ( 132 ) and one second switch ( 134 ), the at least one first switch being arranged between the output of the comparator ( 130 ) and the first reset transistor ( Mr1 ), the at least one second switch being arranged between the output of the pulse generator ( 135 ) and the first reset transistor ( Mr1 ), the second switch ( 134 ) being controlled by the control circuit ( 199 ), the first switch ( 132 ) and the second switch ( 134 ) being intended to connect the output of the comparator ( 130 ) directly to the reset transistor ( Mr1 ) during at least one phase of the measurement cycle for estimating the reference voltage ( Vref ) and to connect the output of the pulse generator ( 135 ) to the first reset transistor ( Mr1 ) during a so-called “normal operation” period or at least one other phase of the measurement cycle, the control circuit ( 199 ) of the reading circuit being further configured to, during the phase of estimating the reference voltage ( Vref ): - rendering the first switch (132) conductive while rendering the second switch (134) non-conductive, while connecting the first node to the second node, to enable estimation of the value of the reference voltage (Vref) from the potential at the second node (N2).

6. An imaging device according to any one of the preceding claims, wherein The second reset transistor (Mr2) is capable of enabling the storage capacitor (C MEM ) is reset, and wherein the control circuit (199) is configured to, during a phase of the measurement cycle in which the second reset voltage (Vresetmem) is estimated: cause the storage capacitor (C MEM ) is reset and the storage switch (121) is turned off, so that the integration capacitor (C INT ) and the storage capacitor (C MEM ) is disconnected, and thus the potential generated by the reset at the second node (N2) and representing the second reset voltage (Vresetmem) can be estimated.

7. An imaging device according to any one of the preceding claims, wherein The first reset transistor (Mr1) is capable of switching the integration capacitor (C INT ) reset, and wherein the control circuit (199) is configured to, during a phase of the measurement cycle in which the first reset voltage (Vresetint) is estimated: trigger the integration capacitor (C INT ) is reset and the storage switch (121) is turned on to turn the integration capacitor (C INT ) is connected to the storage capacitor (C MEM ), and thus it is possible to estimate the potential at the second node (N2) generated by the reset and representing the first reset voltage (Vresetint).

8. The imaging device according to any one of claims 1 to 7, wherein The coupling transistor (Mc) and the bias stage (M DI , 120), in particular direct injection (DI) or buffered direct injection (BDI) bias stages are arranged in series.

9. The imaging device according to any one of claims 1 to 8, wherein The coupling transistor (Mc) includes one electrode of its source or drain connected to the electrode of the photodetector (102) and one electrode of its drain or source connected to the integrating capacitor (C INT ), the control circuit (199) of the reading circuit (110) being configured to apply a signal (Srap) for triggering decoupling of the photodetector (102) from the first node (N1) to the gate of the coupling transistor (Mc) during a first step of the phase of estimating the ratio R.

10. The imaging device according to claim 9, wherein The coupling transistor (Mc) is a direct injection (DI) bias transistor of the photodetector.

11. The imaging device according to any one of claims 1 to 10, wherein The read circuit (110) is further provided with a follower transistor (M) coupled to the second node. 11 ) and line selection transistor (M 21 ).

12. An imaging device according to any one of the preceding claims, wherein The first reset transistor (Mr1) includes an electrode set at a first reset voltage (Vresetint), and wherein the second reset transistor (Mr2) includes an electrode set at a second reset voltage (Vresetmem) different from the first reset voltage.

Images