Silicon wafer polishing method, device and equipment and readable storage medium
By determining the target parameters of the polishing pad and fixed ring, the problem of silicon wafer flatness being difficult to meet the requirements is solved, and an automatic polishing effect based on the target flatness requirements is achieved.
Patent Information
- Application Number
- CN202510734578.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-04
- Publication Date
- 2025-09-09
AI Technical Summary
In the prior art, it is impossible to determine the appropriate platform width and groove width of the polishing pad and the thickness of the retaining ring, resulting in difficulty in achieving the required flatness of the silicon wafer.
By obtaining the target flatness requirement of the silicon wafer to be polished, the target surface parameters of the polishing pad and the target thickness of the retaining ring are determined using the first correspondence, including the boss width, groove width and retaining ring thickness, and polishing is performed using a polishing pad and retaining ring with target parameters.
The parameters of the polishing pad and the fixed ring are automatically obtained according to the target flatness requirements, ensuring that the silicon wafer meets the flatness requirements after polishing, and solving the problem of difficulty in achieving flatness due to inappropriate parameters in the existing technology.
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Figure CN120606324A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor processing technology, and in particular to a silicon wafer polishing method, device, equipment and readable storage medium. Background Art
[0002] In the final polishing equipment of Chemical Mechanical Polishing (CMP), only the front side of the silicon wafer needs to be polished. This is the last process to control the flatness of the silicon wafer and is the final processing equipment that determines the quality of the flatness of the silicon wafer. In addition, the final polishing equipment is also a key process to control Nano (the flatness requirement after the silicon wafer is divided into areas of preset size). The Nano (2*2) requirement of high-end products even reaches below 3nm. The Nano level can be effectively improved by increasing the width of the boss of the polishing pad, but if the width of the boss is too large, the polishing liquid will not be able to enter the interior of the polishing head, reducing the polishing efficiency. The thickness of the fixing ring on the adsorption pad will cause different forces on the edge of the silicon wafer, thereby affecting the edge flatness of the silicon wafer. At present, it is impossible to determine the appropriate width of the boss of the polishing pad, the width of the groove, and the thickness of the fixing ring. Summary of the Invention
[0003] Embodiments of the present invention provide a silicon wafer polishing method, apparatus, device and readable storage medium to solve the problem in the prior art that it is impossible to determine the appropriate width of the boss and groove of the polishing pad and the thickness of the fixing ring, resulting in difficulty in achieving the required flatness of the silicon wafer.
[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions:
[0005] In a first aspect, an embodiment of the present invention provides a silicon wafer polishing method, comprising:
[0006] Obtain the target flatness requirement of the silicon wafer to be polished;
[0007] The target surface parameters of the polishing pad and the target thickness of the retaining ring are determined based on a first correspondence and a target flatness requirement; wherein the first correspondence is a correspondence between the flatness requirement of the silicon wafer, the surface parameters of the polishing pad, and the thickness of the retaining ring on the adsorption pad; the polishing pad is used to polish the silicon wafer to be polished, and the polishing pad includes a first surface having alternatingly distributed protrusions and grooves, and the surface parameters include the widths of the protrusions and the widths of the grooves; the adsorption pad includes a backing cloth and a retaining ring bonded to the backing cloth; during the polishing process, the silicon wafer to be polished is placed within the retaining ring and is fixed by adsorption to the first surface;
[0008] The silicon wafer to be polished is polished by using a polishing pad having the target surface parameters and an adsorption pad having a fixed ring with the target thickness.
[0009] Optionally, the target flatness requirement includes at least one of the following:
[0010] The minimum range of the front side reference of the edge part, the minimum range of the front side reference of the part, the ideal range of the overall back side reference, the range of the near-edge curvature height, and the flatness requirement value after dividing the silicon wafer into areas of preset sizes.
[0011] Optionally, the first corresponding relationship includes: a corresponding relationship table or a corresponding relationship curve.
[0012] Optionally, the target surface parameters include a width of a target boss and a width of a target groove.
[0013] Optionally, in the first corresponding relationship, the width of the boss is greater than or equal to 3 mm or,
[0014] In the first corresponding relationship, the width of the boss is greater than or equal to 3 mm and less than or equal to 10 mm.
[0015] Optionally, in the first corresponding relationship, the width of the groove is less than or equal to 2 mm; or,
[0016] In the first corresponding relationship, the width of the groove is in the range of less than or equal to 2 mm and greater than or equal to 1 mm.
[0017] Optionally, in the first corresponding relationship, the thickness of the fixing ring is less than or equal to 810 μm.
[0018] Optionally, in the first corresponding relationship, the thickness range of the fixing ring is less than or equal to 810 μm and greater than or equal to 770 μm.
[0019] In a second aspect, an embodiment of the present invention provides a silicon wafer polishing device, comprising:
[0020] An acquisition module is used to obtain the target flatness requirement of the silicon wafer to be polished;
[0021] a determination module, configured to determine target surface parameters of the polishing pad and a target thickness of the retaining ring based on a first correspondence and the target flatness requirement; wherein the first correspondence is a correspondence between the flatness requirement of the silicon wafer, the surface parameters of the polishing pad, and the thickness of the retaining ring on the adsorption pad; the polishing pad is configured to polish the silicon wafer to be polished, and the polishing pad includes a first surface having alternatingly distributed protrusions and grooves, and the surface parameters include widths of the protrusions and the widths of the grooves; the adsorption pad includes a backing cloth and a retaining ring bonded to the backing cloth; during the polishing process, the silicon wafer to be polished is disposed within the retaining ring and is fixed by adsorption to the first surface;
[0022] A control module is used to polish the silicon wafer to be polished by using a polishing pad having the target surface parameters and an adsorption pad having a fixed ring with the target thickness.
[0023] In a third aspect, an embodiment of the present invention provides a silicon wafer polishing device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the silicon wafer polishing method described above are implemented.
[0024] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the silicon wafer polishing method described above when executed by a processor.
[0025] The beneficial effects of the present invention are:
[0026] The silicon wafer polishing method of the embodiment of the present invention, using the first correspondence, can automatically determine the target surface parameters of the polishing pad and the target thickness of the retaining ring for polishing a silicon wafer to be polished with target flatness requirements. The method then uses a polishing pad with the target surface parameters and an adsorption pad with a retaining ring having the target thickness to polish the silicon wafer to be polished, ensuring that the polished silicon wafer meets the target flatness requirements. This solves the problem in the prior art of being unable to determine the appropriate land widths and groove widths of the polishing pad and the thickness of the retaining ring, resulting in difficulty in achieving the required flatness of the silicon wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 A schematic diagram showing the steps of a silicon wafer polishing method according to an embodiment of the present invention;
[0028] Figure 2 A schematic structural diagram of a polishing pad according to an embodiment of the present invention is shown;
[0029] Figure 3 A schematic diagram showing the structure of an adsorption pad according to an embodiment of the present invention;
[0030] Figure 4 A schematic diagram showing the flatness of the silicon wafer surface corresponding to the first embodiment and the second embodiment of the present invention;
[0031] Figure 5 A schematic diagram showing a radial removal profile of a silicon wafer according to a third embodiment of the present invention;
[0032] Figure 6 A schematic diagram showing a radial removal profile of a silicon wafer according to a fourth embodiment of the present invention;
[0033] Figure 7 A schematic diagram showing a radial removal profile of a silicon wafer according to a fifth embodiment of the present invention;
[0034] Figure 8 A schematic diagram showing a module of a silicon wafer polishing device according to an embodiment of the present invention;
[0035] Figure 9 A schematic structural diagram showing a silicon wafer polishing apparatus according to an embodiment of the present invention; DETAILED DESCRIPTION
[0036] To make the technical problems, technical solutions, and advantages to be solved by the present invention more apparent, a detailed description will be given below with reference to the accompanying drawings and specific embodiments. In the following description, specific details such as specific configurations and components are provided solely to facilitate a comprehensive understanding of the embodiments of the present invention. Therefore, it should be clear to those skilled in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present invention. In addition, for the sake of clarity and brevity, descriptions of known functions and configurations have been omitted.
[0037] It should be understood that references throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present invention. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0038] The present invention provides a silicon wafer polishing method to solve the problem in the prior art that the width of the boss and the width of the groove of the polishing pad and the thickness of the adsorption pad cannot be determined appropriately, resulting in difficulty in achieving the required flatness of the silicon wafer.
[0039] like Figure 1 As shown, an embodiment of the present invention provides a silicon wafer polishing method, comprising the following steps:
[0040] Step 101, obtaining the target flatness requirement of the silicon wafer to be polished;
[0041] Step 102: Determine target surface parameters of the polishing pad and target thickness of the retaining ring based on a first correspondence and the target flatness requirement; wherein the first correspondence is a correspondence between the flatness requirement of the silicon wafer, the surface parameters of the polishing pad, and the thickness of the retaining ring on the adsorption pad; the polishing pad is used to polish the silicon wafer to be polished, and the polishing pad includes a first surface having alternatingly distributed protrusions and grooves, and the surface parameters include the width of the protrusions and the width of the grooves; the adsorption pad includes a backing cloth and a retaining ring attached to the backing cloth; during the polishing process, the silicon wafer to be polished is placed within the retaining ring and is fixed by adsorption to the first surface;
[0042] Step 103 : polishing the silicon wafer to be polished by using a polishing pad having the target surface parameters and an adsorption pad having a fixed ring with the target thickness.
[0043] Optionally, the first corresponding relationship includes: a corresponding relationship table or a corresponding relationship curve.
[0044] It should be noted that the first corresponding relationship is determined by acquiring multiple sets of historical data, where the historical data are the corresponding relationship between the flatness requirement of the silicon wafer and the surface parameters of the polishing pad and the thickness of the retaining ring.
[0045] It should be noted that after determining the polishing pad with the target surface parameters and the fixing ring with the target thickness, the polishing pad and the adsorption pad are replaced manually or by machine on the polishing equipment, and the polishing pad and the adsorption pad on the polishing equipment are replaced with a polishing pad with the target surface parameters and an adsorption pad with the fixing ring with the target thickness.
[0046] like Figure 2 As shown, the first surface of the polishing pad is alternately provided with lands 11 and grooves 12 , the width of the lands is M, and the width of the grooves is N.
[0047] like Figure 3 As shown, the adsorption pad includes: a backing cloth 21 and a fixing ring 22;
[0048] The outer diameter of the fixing ring 22 is the same as the diameter of the back cloth 21 .
[0049] In an embodiment of the present application, during the process of polishing the silicon wafer, the silicon wafer is placed in the fixing ring, and the adsorption pad is bonded to the first surface of the polishing pad to polish the silicon wafer.
[0050] The silicon wafer polishing method of the present invention automatically determines the target surface parameters of the polishing pad and the target thickness of the retaining ring for polishing a silicon wafer with target flatness requirements. The method then uses a polishing pad with the target surface parameters and an adsorption pad with a retaining ring with the target thickness to polish the silicon wafer, ensuring that the polished silicon wafer meets the target flatness requirements. This method solves the problem in the prior art of being unable to determine the appropriate land widths and groove widths of the polishing pad and the thickness of the retaining ring, resulting in difficulty in achieving the required flatness of the silicon wafer.
[0051] Optionally, the target flatness requirement includes at least one of the following:
[0052] Edge Site Frontsurface referenced leastRange (ESFQR), Site Frontsurface referencedleastRange (SFQR), Global Backsurface-referencedIdealRange (GBIR), near-edge curvature height preset range (near-edge curvature), and flatness requirement value (Nano) after dividing the silicon wafer into regions of preset sizes.
[0053] It should be noted that different target surface parameters and target thicknesses of the fixing ring correspond to different surface flatness data of the polished silicon wafer; according to the first corresponding relationship, when the target flatness requirements are obtained, the surface parameters of the polishing pad for polishing the silicon wafer to be polished and the thickness of the fixing ring can be directly obtained.
[0054] In one embodiment of the present invention, the first correspondence is as shown in Table 1, wherein the target flatness requirement includes one or more of a minimum range of a front-side reference at an edge portion, a minimum range of a front-side reference at a portion, an ideal range of an overall back-side reference, a preset range of a near-edge curvature height, and a flatness requirement value after dividing the silicon wafer into regions of a preset size.
[0055] Table 1
[0056] Flatness requirements Width of boss Groove width Thickness of retaining ring Nano2*2 3mm 1mm 810μm ESFQR 10mm 2mm 810μm GBIR 10mm 2mm 770μm SFQR, near edge curvature height 10 mm 2mm 710μm … … … …
[0057] It should be noted that the near-edge curvature height is measured by the radial second-order derivative method (ZDD).
[0058] It should be noted that, the greater the thickness of the fixing ring, the smaller the amount of removal from the edge of the silicon wafer; and the greater the width of the boss, the better the Nano improvement effect on the silicon wafer.
[0059] Optionally, Nano represents the flatness of each small area after the silicon wafer is divided into small areas; Nano2*2 represents the flatness of each small area after the silicon wafer is divided into small areas of 2nm×2nm.
[0060] Optionally, the target surface parameters include a width of a target boss and a width of a target groove.
[0061] Optionally, in the first corresponding relationship, the width of the boss is greater than or equal to 3 mm; or,
[0062] In the first corresponding relationship, the width of the boss is greater than or equal to 3 mm and less than or equal to 10 mm.
[0063] That is, in the first corresponding relationship, the widths of all the bosses are greater than or equal to 3 mm; or, the widths of all the bosses are greater than or equal to 3 mm and less than or equal to 10 mm.
[0064] In one embodiment of the present invention, the width of the protrusion is 3nm and 10mm, which respectively correspond to the flatness requirements, for example, the value of Nano is as follows: Figure 4 As shown in FIG, when the width of the bump is 10 mm, the nano level of the silicon wafer is significantly improved compared to when the width of the bump is 3 nm.
[0065] It should be noted that, through experiments, it has been verified that when the width of the boss is less than 3 nm or greater than 10 nm, it is difficult to ensure that the surface flatness of the silicon wafer meets the requirements even if the width of the groove and the thickness of the fixing ring are adjusted.
[0066] The silicon wafer polishing method implemented in the present application can eliminate the problem that the width of the boss is too large or too small, which makes it difficult to make the surface flatness of the silicon wafer meet the requirements even by adjusting the width of the groove and the thickness of the fixing ring, by numerically limiting the width of the boss in the first corresponding relationship.
[0067] Optionally, in the first corresponding relationship, the width of the groove is less than or equal to 2 mm; or,
[0068] In the first corresponding relationship, the width of the groove is in the range of less than or equal to 2 mm and greater than or equal to 1 mm.
[0069] That is, in the first corresponding relationship, the width of all the grooves is less than or equal to 2 mm; or, the width of the grooves ranges from less than or equal to 2 mm to greater than or equal to 1 mm.
[0070] In one embodiment of the present invention, the groove width is 2 mm.
[0071] It should be noted that, through experiments, it has been verified that when the width of the groove is less than 1 mm or greater than 2 mm, even if the width of the boss and the thickness of the fixing ring are adjusted, it is difficult to ensure that the surface flatness of the silicon wafer meets the requirements.
[0072] The silicon wafer polishing method implemented in the present application can eliminate the problem that the width of the groove is too large or too small, which makes it difficult to make the surface flatness of the silicon wafer meet the requirements even by adjusting the width of the boss and the thickness of the fixing ring, by numerically limiting the width of the groove in the first corresponding relationship.
[0073] Optionally, in the first corresponding relationship, the thickness of the fixing ring is less than or equal to 810 μm.
[0074] Optionally, in the first corresponding relationship, the thickness range of the fixing ring is less than or equal to 810 μm and greater than or equal to 770 μm.
[0075] It should be noted that, through experiments and verification, when the thickness of the fixing ring is greater than 810 μm or less than 770 μm, even if the width of the boss and the width of the groove are adjusted, it is difficult to ensure that the surface flatness of the silicon wafer meets the requirements.
[0076] In the first embodiment of the present invention, the width of the boss is 3 mm, the width of the groove is 1 mm, and the thickness of the fixing ring is 810 μm;
[0077] In the second embodiment of the present invention, the width of the boss is 10 mm, the width of the groove is 1 mm, and the thickness of the fixing ring is 810 μm;
[0078] In a third embodiment of the present invention, the width of the boss is 10 mm, the width of the groove is 2 mm, and the thickness of the fixing ring is 810 μm;
[0079] In a fourth embodiment of the present invention, the width of the boss is 10 mm, the width of the groove is 2 mm, and the thickness of the fixing ring is 790 μm;
[0080] In a fifth embodiment of the present invention, the width of the boss is 3 mm, the width of the groove is 1 mm, and the thickness of the fixing ring is 770 μm.
[0081] Regarding the first to fifth embodiments above:
[0082] like Figure 4 As shown in FIG. 1 , the values of Nano2*2 of the polished silicon wafer are respectively when the width of the boss is 3 mm and 10 mm (corresponding to the first embodiment and the second embodiment, respectively).
[0083] In the case where the thickness of the fixing ring is relatively large, for example, a schematic diagram of the removal profile obtained by polishing a silicon wafer using the data of the third embodiment is shown as follows: Figure 5 As shown, the edge removal of the silicon wafer is small, which can meet the higher edge part front side benchmark minimum / range ESFQR requirements;
[0084] The thickness of the fixing ring is reduced, for example, a schematic diagram of the removal profile obtained by polishing a silicon wafer using the data of the fourth embodiment is shown as follows: Figure 6 As shown in the figure, the overall removal amount along the radial direction of the silicon wafer is relatively uniform, and the flatness of the silicon wafer changes little before and after polishing, which can meet the higher overall backside-reference ideal range GBIR requirements;
[0085] Continue to reduce the thickness of the fixing ring, for example, use the data of the fifth embodiment to polish the silicon wafer to obtain a schematic diagram of the removal profile, as shown in FIG. Figure 7 As shown in the figure, the edge removal of the silicon wafer is large, which can meet the higher silicon wafer surface flatness quality ratio SFQR requirements.
[0086] The silicon wafer polishing method implemented in this application can eliminate the problem that the thickness of the fixing ring is too large or too small, which makes it difficult to achieve the required flatness of the silicon wafer surface even by adjusting the width of the boss and the width of the groove. Figure 8 As shown, an embodiment of the present invention also provides a silicon wafer polishing device 800, comprising:
[0087] An acquisition module 801 is used to obtain a target flatness requirement of a silicon wafer to be polished;
[0088] Determination module 802 is configured to determine target surface parameters of the polishing pad and target thickness of the retaining ring based on a first correspondence and the target flatness requirement; wherein the first correspondence is a correspondence between the flatness requirement of the silicon wafer, the surface parameters of the polishing pad, and the thickness of the retaining ring on the adsorption pad; the polishing pad is configured to polish the silicon wafer to be polished, and the polishing pad includes a first surface having alternatingly distributed protrusions and grooves, and the surface parameters include widths of the protrusions and the widths of the grooves; the adsorption pad includes a backing cloth and a retaining ring attached to the backing cloth; during the polishing process, the silicon wafer to be polished is disposed within the retaining ring and is secured by adsorption to the first surface;
[0089] The control module 803 is configured to polish the silicon wafer to be polished by using a polishing pad having the target surface parameters and an adsorption pad having a fixed ring with the target thickness.
[0090] The silicon wafer polishing apparatus of the present invention, using the first correspondence, can automatically determine the target surface parameters of the polishing pad and the target thickness of the retaining ring for polishing a silicon wafer with target flatness requirements. The apparatus can then polish the silicon wafer using a polishing pad with the target surface parameters and an adsorption pad with a retaining ring with the target thickness, ensuring that the polished silicon wafer meets the target flatness requirements. This solves the problem in the prior art of being unable to determine the appropriate land widths and groove widths of the polishing pad and the thickness of the retaining ring, resulting in difficulty in achieving the required flatness of the silicon wafer.
[0091] like Figure 9 As shown, an embodiment of the present invention also provides a silicon wafer polishing device 900, including: a memory 902, a processor 901 and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the silicon wafer polishing method described above when executing the computer program.
[0092] In addition, a specific embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When executed by a processor, the program implements the steps of the aforementioned silicon wafer polishing method. The program can achieve the same technical effects and is not further described here to avoid repetition.
[0093] An embodiment of the present application also provides a computer program product, including computer instructions. When the computer instructions are executed by a processor, the various processes of the above-mentioned silicon wafer polishing method embodiment are implemented and can achieve the same technical effect. To avoid repetition, they will not be repeated here.
[0094] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary personnel in this technical field, several improvements and modifications can be made without departing from the principles described in the present invention. These improvements and modifications are also within the scope of protection of the present invention.
Claims
1. A silicon wafer polishing method, characterized in that: include: Obtain the target flatness requirement of the silicon wafer to be polished; The target surface parameters of the polishing pad and the target thickness of the retaining ring are determined based on a first correspondence and the target flatness requirement. The first correspondence is a correspondence between the flatness requirement of the silicon wafer, the surface parameters of the polishing pad, and the thickness of the retaining ring on the adsorption pad. The polishing pad is used to polish the silicon wafer to be polished, and the polishing pad includes a first surface having alternatingly distributed protrusions and grooves, and the surface parameters include the widths of the protrusions and the widths of the grooves. The adsorption pad includes a backing cloth and a retaining ring bonded to the backing cloth. During the polishing process, the silicon wafer to be polished is placed within the retaining ring and is fixed by adsorption to the first surface. The silicon wafer to be polished is polished by using a polishing pad having the target surface parameters and an adsorption pad having a fixed ring with the target thickness.
2. The silicon wafer polishing method according to claim 1, wherein The target flatness requirement includes at least one of the following: The minimum range of the front side reference of the edge part, the minimum range of the front side reference of the part, the ideal range of the overall back side reference, the preset range of the near-edge curvature height, and the flatness requirement value after dividing the silicon wafer into areas of preset sizes.
3. The silicon wafer polishing method according to claim 1, wherein The first corresponding relationship includes: a corresponding relationship table or a corresponding relationship curve.
4. The silicon wafer polishing method according to claim 3, wherein: In the first corresponding relationship, the width of the boss is greater than or equal to 3 mm; or, In the first corresponding relationship, the width of the boss is greater than or equal to 3 mm and less than or equal to 10 mm.
5. The silicon wafer polishing method according to claim 3, wherein: In the first corresponding relationship, the width of the groove is less than or equal to 2 mm; or, In the first corresponding relationship, the width of the groove is in the range of less than or equal to 2 mm and greater than or equal to 1 mm.
6. The silicon wafer polishing method according to claim 3, wherein: In the first corresponding relationship, the thickness of the fixing ring is less than or equal to 810 μm.
7. The silicon wafer polishing method according to claim 3, wherein: In the first corresponding relationship, the thickness range of the fixing ring is less than or equal to 810 μm and greater than or equal to 770 μm.
8. A silicon wafer polishing device, characterized in that: include: An acquisition module is used to obtain the target flatness requirement of the silicon wafer to be polished; a determination module, configured to determine target surface parameters of the polishing pad and a target thickness of the retaining ring based on a first correspondence and the target flatness requirement; wherein the first correspondence is a correspondence between the flatness requirement of the silicon wafer, the surface parameters of the polishing pad, and the thickness of the retaining ring on the adsorption pad; the polishing pad is configured to polish the silicon wafer to be polished, and the polishing pad includes a first surface having alternatingly distributed protrusions and grooves, and the surface parameters include widths of the protrusions and the widths of the grooves; the adsorption pad includes a backing cloth and a retaining ring bonded to the backing cloth; during the polishing process, the silicon wafer to be polished is disposed within the retaining ring and is fixed by adsorption to the first surface; A control module is used to polish the silicon wafer to be polished by using a polishing pad having the target surface parameters and an adsorption pad having a fixed ring with the target thickness.
9. A silicon wafer polishing device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the silicon wafer polishing method according to any one of claim 7 are implemented.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the silicon wafer polishing method according to any one of claims 1 to 7 are implemented.