Control system of multi-axis motion platform

Abstract

The invention provides a control system of a multi-axis motion platform, the control system comprises an upper computer and a control case, the control case at least comprises a single-board computer, a motion control card, a position resolving card, a synchronous clock card and a bus, the upper computer is connected with the single-board computer through a network cable, and the single-board computer is connected with the motion control card. The single-board computer, the motion control card, the position resolving card and the synchronous clock card are connected through a backboard VME bus, a backboard SRIO bus, a PDB bus and an SYNC synchronous bus, the upper computer is used for generating a first control instruction based on user operation obtained through a human-computer interaction interface, sending the first control instruction to the single-board computer in a network communication mode, and sending the first control instruction to the single-board computer in a network communication mode. The single-board computer is used for sending the received first control instruction to the motion control card, so that the motion control card drives the actuator to complete motion based on the first control instruction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor motion control technology, and in particular to a control system for a multi-axis motion platform. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, the performance requirements for precision motion stage control systems are becoming increasingly stringent. Precision motion stages in modern semiconductor equipment typically utilize a multi-axis linkage control architecture, with hundreds of high-precision sensors deployed in the system to monitor the stage's position, velocity, acceleration, and other state parameters in real time. The feedback data generated by these sensors needs to be transmitted in real time to the motion controller, which must complete a series of complex control operations within a strictly specified servo cycle. These operations include multi-axis position resolution, precision trajectory interpolation, position-acceleration error compensation, motor decoupling control, and other algorithmic implementations. Furthermore, the controller must handle system errors, save control process data, and other important tasks. Finally, the servo operation results must be promptly transmitted to the drivers of each motor.

[0003] Traditional solutions typically deploy the control system on a Windows PC platform, connecting to a DSP motion control card via Ethernet. In this architecture, the motion control driver's application interface runs on the host PC. The issuance of motion control instructions requires breaking the driver's application interface into multiple individual instructions, transmitted one by one. The network communication time for each application interface is equal to the sum of the times for N individual instructions, where N ranges from 1 to 10. In practical applications, the total execution time for a complete motion application instruction can reach 10 milliseconds, failing to meet high-performance requirements. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a control system for a multi-axis motion platform to solve the technical problem of slow instruction issuance speed in the existing high-speed and high-precision control architecture of multi-axis motion platforms.

[0005] In a first aspect, the present invention provides a control system for a multi-axis motion platform. The control system includes a host computer and a control chassis. The control chassis includes at least a single-board computer, a motion control card, a position solver card, a synchronous clock card, and a bus. The host computer and the single-board computer are connected via a network cable. The single-board computer, the motion control card, the position solver card, and the synchronous clock card are connected via a backplane VME bus, a backplane SRIO bus, a PDB bus, and a SYNC synchronization bus. Among them, the host computer is used to generate a first control instruction based on the user operation obtained through the human-computer interaction interface, and send it to the single-board computer through network communication. The single-board computer is used to send the received first control instruction to the motion control card, so that the motion control card drives the actuator to complete the movement based on the first control instruction.

[0006] In an optional embodiment, the motion control card includes a digital signal processor and a field programmable gate array, and the single-board computer sends the first control instruction to the digital signal processor via the VME bus, and sets the first control instruction sending identifier to a first identification value; the digital signal processor determines whether the first control instruction is received based on the first control instruction receiving identifier, and if so, drives the actuator to complete the movement based on the first control instruction; after the movement is completed, the digital signal processor generates an interrupt signal and sends it to the single-board computer via the VME bus; the single-board computer generates feedback information corresponding to the first control instruction in response to the interrupt signal, and sends it to the host computer via the network.

[0007] In an optional embodiment, the synchronous clock card generates a synchronization signal according to a preset frequency and sends it to the field programmable gate array via the SYNC synchronization bus; the field programmable gate array responds to the synchronization signal, generates a doorbell signal and sends it to the sensor acquisition board via optical fiber to obtain the acquisition parameters uploaded by the sensor and send it to the digital signal processor for storage.

[0008] In an optional embodiment, the field programmable gate array generates an interrupt signal in response to the synchronization signal and sends it to a digital signal processor. The digital signal processor calculates control parameters corresponding to the first control instruction based on pre-stored acquisition parameters in response to the interrupt signal to generate a second control instruction and sends it to the power amplifier board; the power amplifier board sends the second control instruction to the driver to drive the actuator to complete the movement indicated by the first control instruction.

[0009] In an optional implementation, the timing of the doorbell signal is earlier than that of the interrupt signal.

[0010] In an optional embodiment, the first control instruction is used to indicate the motion module identifier, and the first control instruction includes at least the motion module identifier; the single-board computer stores the first control instruction in the instruction space corresponding to the motion module identifier based on the motion module identifier in the first control instruction; the digital signal processor allocates the first control instruction to the functional core corresponding to the motion module identifier for processing based on the motion module identifier in the first control instruction.

[0011] In an optional implementation, the field programmable gate array responds by storing the acquired acquisition parameters in a memory space corresponding to the motion module identifier.

[0012] In an optional embodiment, the digital signal processor includes multiple functional cores and a management core, and the management core is used to carry the SYS / BIOS operating system and create network communication tasks.

[0013] In an optional implementation, the digital signal processor further includes a log core, which is used to initialize the log module and allocate a buffer zone for the system log.

[0014] In an optional embodiment, the digital signal processor further includes a trace diagnosis core, which is used to initialize the trace diagnosis module and allocate a buffer for trace diagnosis information.

[0015] The present application provides a control system for a multi-axis motion platform, the control system includes a host computer and a control chassis, the control chassis includes at least a single-board computer, a motion control card, a position solver card, a synchronous clock card, and a bus, the host computer and the single-board computer are connected via a network cable, and the single-board computer, the motion control card, the position solver card, and the synchronous clock card are connected via a backplane VME bus, a backplane SRIO bus, a PDB bus, and a SYNC synchronous bus, respectively. The host computer is used to generate a first control instruction based on the user operation obtained through the human-computer interaction interface, and send it to the single-board computer via a network communication method. The single-board computer is used to send the received first control instruction to the motion control card, so that the motion control card drives the actuator to complete the movement based on the first control instruction. The present application proposes a high-speed and high-precision control system for a multi-axis motion platform based on a VME control system and a DSP+FPGA heterogeneous processing platform. The driver software can be deployed to the single-board computer according to real-time requirements, the motion control real-time firmware can be deployed to the DSP, and the real-time data acquisition function can be realized through the FPGA. It meets the requirements of multi-axis high-speed and high-precision motion control and improves the response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic structural diagram of a control system for a multi-axis motion platform provided in an embodiment of the present application; Figure 2 A software architecture diagram of a control system for a multi-axis motion platform provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a motion control card provided in an embodiment of the present application; Figure 4 An address mapping diagram for communication between a PPC and a DSP provided in an embodiment of the present application; Figure 5 A communication flow chart between a PPC and a DSP provided in an embodiment of the present application; Figure 6 A structural diagram of a multi-core DSP provided in an embodiment of the present application; FIG7 (a) is a flowchart of a management core program provided by an embodiment of the present application; FIG7 (b) is a flowchart of a service function core provided by an embodiment of the present application; FIG7 (c) is a flowchart of a log core program provided by an embodiment of the present application; FIG7( d ) is a flowchart of a tracking diagnosis core program provided by an embodiment of the present application; Figure 8 A schematic diagram of memory space allocation for a core provided in an embodiment of the present application; Figure 9 A timing diagram of data collection provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0019] Example 1 Figure 1 This is a structural diagram of a control system for a multi-axis motion platform provided in an embodiment of the present application. Figure 1 As shown, an embodiment of the present application provides a control system for a multi-axis motion platform, the control system includes a host computer and a control chassis, the control chassis includes at least a single-board computer, a motion control card, a position solver card, a synchronous clock card, and a bus.

[0020] The host computer and the single-board computer are connected via a network cable. The single-board computer, motion control card, position solver card, and synchronous clock card are connected via the backplane VME bus, backplane SRIO bus, PDB bus, and SYNC synchronous bus respectively. Among them, the host computer is used to generate a first control instruction based on the user operation obtained through the human-computer interaction interface, and send it to the single-board computer through network communication. The single-board computer is used to send the received first control instruction to the motion control card, so that the motion control card drives the actuator to complete the movement based on the first control instruction.

[0021] The host computer here sends motion control instructions to the DSP through the network. The DSP receives the control commands, parses the commands, and performs further processing based on the parsing results. The task types of control instructions may include: initialization commands, downloading firmware, sending machine constants, obtaining motion controller status, tracking diagnostic commands, motion commands, and termination command-related servo calculations.

[0022] The single-board computer (SBC) processor can be a high-performance T2080 PowerPC processor equipped with the VxWorks 7 operating system. The SBC and motion control card exchange commands and data via the backplane VME bus. The SRIO bus, as a high-speed serial bus, enables higher-bandwidth data processing and is used for transmission of real-time data. The PDB is a custom data bus that enables position data acquisition and transmission. The motion control card utilizes a heterogeneous architecture comprised of a multi-core DSP and FPGA, enhancing data acquisition and processing capabilities. The synchronous clock card provides synchronization signals for timing control of data acquisition and computation. The position solver card broadcasts measured axis position data to the motion control card.

[0023] like Figure 2 As shown, Figure 2 The software architecture diagram of the control system of a multi-axis motion platform provided in the embodiment of the present application. Figure 2 As shown in the figure, the control system software is divided into three levels: control layer, sub-control layer, and real-time control layer. The control layer software is deployed on a Windows platform equipped with a host computer, the sub-control layer software (driver software) is deployed on a VxWorls system equipped with a single-board computer, and the real-time control layer is deployed on a DSP.

[0024] The host computer runs the control system's software terminal and provides control command issuance via the human-machine interface. The single-board computer receives and parses control commands, performing subsequent processing based on the results. Control commands include initialization, firmware downloads, machine constant issuance, motion controller status acquisition, diagnostic tracking, log acquisition, motion commands, and termination commands.

[0025] Specifically, such as Figure 3 As shown, the motion control card includes a digital signal processor and a field-programmable gate array. This card connects to the sensor acquisition and power amplifier boards via fiber optic interfaces. The sensor amplifier board is connected to the driver, which in turn is connected to the actuator it controls. Three data channels exist between the DSP and FPGA. GPIO is used to configure the DSP boot mode and is also multiplexed as a servo interrupt trigger signal for the DSP. EMIF serves as an intermediary for the DSP to access VME space. SRIO is the data channel between the DSP and FPGA, enabling data exchange and doorbell signal notification.

[0026] This application provides a control system for a multi-axis motion stage. Based on real-time requirements, the driver software is deployed on a single-board computer (SBC), the real-time motion control firmware is deployed on a DSP, and real-time data acquisition is implemented using an FPGA. This system meets the requirements for high-speed, high-precision multi-axis motion control. Direct data acquisition using a DSP increases system overhead, while the FPGA is used to control the timing of data acquisition, processing, and distribution, ensuring deterministic system latency.

[0027] Compared to the traditional method (driver software deployed on a Windows PC), this method significantly improves productivity. In the prior art, driver software is deployed on a PC, connected to a DSP via a network, and the driver's application interface runs on the host PC. To issue motion control instructions, the driver's application interface is split into multiple instructions and issued one by one. The network time required for one application interface is the sum of the times required for N individual instructions. The value of N ranges from 1 to 10, and the network communication time from the PC to the DSP ranges from several hundred microseconds to 1 millisecond. The total time required for a single motion application instruction is on the order of 10 milliseconds at most. Using the technical solution of this application, after deploying the driver software on a single-board computer (SBC), the driver software application interface runs on a PowerPC. Motion instructions are issued to the motion control card via the backplane VME. For the same amount of data, VME communication takes approximately 10 microseconds. However, the same application instruction can be issued within 100 microseconds. Compared to the prior art, this significantly improves the response speed of instruction issuance, thereby contributing to increased semiconductor production.

[0028] Example 2 Traditional motion controllers rely on a single processor to handle calculations for numerous axes, resulting in insufficient computing power and difficulty meeting high real-time requirements. Existing projects either run an operating system (OS) or run entirely on bare cores, making it difficult to flexibly configure both management and computing functions.

[0029] In order to further improve the data processing speed of the control system of multiple motion axes in the real-time acquisition scenario of numerous sensors, the digital signal processor includes multiple functional cores and management cores. The management core is used to carry the SYS / BIOS operating system and create network communication tasks. In one embodiment of the present application, the DSP can use an eight-core c6678, and the eight cores can process motion control related data and algorithm implementation in parallel. By adopting a combination of an operating system and a bare core, the needs of system management and real-time computing are taken into account. Among them, the core of the bare core to implement the motion function adopts the same processing framework to ensure development consistency and improve development efficiency.

[0030] Figure 4 This is the address mapping diagram for communication between PPC and DSP. Figure 4As shown, the VME communication addresses between the single-board computer (PPC) and the DSP are divided according to core functionality. The total VME space is 256KB, evenly divided among the eight cores. This space is converted to EMIF space via the FPGA's dual-port RAM. Reading and writing to the EMIF space by the DSP translates to reading and writing to the PPC VME space. A separate project file is created for each core to facilitate debugging.

[0031] The communication instruction interaction process between PPC and DSP is as follows Figure 5 , specifically including the single-board computer sending the first control instruction to the digital signal processor through the VME bus, and setting the first control instruction sending identifier to the first identifier value; the digital signal processor determines whether the first control instruction is received based on the first control instruction receiving identifier, and if so, drives the actuator to complete the movement based on the first control instruction; after the movement is completed, the digital signal processor generates an interrupt signal and sends it to the single-board computer through the VME bus; the single-board computer generates feedback information corresponding to the first control instruction in response to the interrupt signal, and sends it to the host computer through network communication.

[0032] Here, DSP responds to PPC using VME interrupt triggering, which can quickly notify PPC.

[0033] The address space mapping for Core 0 receiving commands can be performed as follows: VMECmdStruct * CORE0VmeCmd = (VMECmdStruct*) (BASE_ADDR + 0x1000). BASE_ADDR is 0x74000000. By determining the memory allocation scheme and communication logic between the PPC and DSP, a static one-to-one mapping is implemented, isolating the memory partitions and preventing crosstalk. The communication logic uses VME interrupts on the DSP to notify the PPC, which improves communication efficiency compared to writing flags.

[0034] This application proposes a multi-core hybrid task processing framework built on the DSP. By adapting corresponding peripheral resources to different cores, the main core serves as the management core and runs the SYS / BIOS operating system, while the other cores do not have an operating system and run as bare cores. This framework can simultaneously meet the needs of rapid response in complex situations involving multiple data.

[0035] In a specific embodiment, in order to achieve high-speed and high-precision motion control, multi-axis control is performed using multi-core parallel processing, such as Figure 6As shown in the figure, multi-core tasks are divided as follows: Core 0 serves as the management core, running the SYS / BIOS operating system. It primarily performs initial configuration and bootstrapping slave cores. Cores 1 through 5 are motion function cores, implementing closed-loop control of each motion module. Core 6 is the logging module. Deploying the logging module in a separate core enables real-time logging and uploading without affecting the real-time performance of motion control. Core 7 is the tracking and diagnostic module. Because tracking and diagnostic tasks involve the transmission of large amounts of data, they are also deployed in a separate core. Separating business functions from basic function cores facilitates integrated management.

[0036] After DSP core 0 is powered on, the system performs a series of initializations. First, the main function executes EMIF initialization, configuring the VME address, GPIO interrupt configuration, network NDK initialization, and SRIO initialization. Memory allocation and address remapping are also performed. Multi-core communication uses shared memory, namely the MSMC memory space within the DSP. The memory base address is 0x0c000000, and the space size is 4MB. Memory consistency must be maintained when multiple cores operate on shared memory. For ease of use, XMC is used to remap the shared memory area in core 0. The remapping interface requires that the cache of the remapped memory area be closed after remapping.

[0037] Core 0 creates a network task to transmit non-real-time diagnostic data. Core 0 retains network communication capabilities, reserving a channel for subsequent system interconnection and serving as a second diagnostic interface (non-real-time interface). This second diagnostic interface can transmit a wider range of diagnostic information than the first. Core 0 runs the NDK protocol stack and retains network communication capabilities, reserving a channel for subsequent system interconnection. As a second diagnostic interface, this second diagnostic interface can transmit a wider range of diagnostic information than the first.

[0038] As shown in Figures 7(a)-7(d), the processing flow of each core is as follows: Management core 0 is equipped with the SYS / BIOS operating system, initializes the relevant peripherals, and then creates a network communication task as the second functional interface for tracking and diagnosis. Business function cores 1-5 do not have the SYS / BIOS operating system and use the same task framework to mainly complete motion control related functions. The log core mainly allocates log read and write buffers and initializes the log module. The tracking and diagnosis core is similar to the log core. Inter-core communication uses shared memory, and the shared memory partition is as follows: Figure 8 The multi-cores communicate with each other using shared memory, and the corresponding memory area is divided according to the data size required by the kernel.

[0039] Specifically, the first control instruction may be used to indicate the motion module type and include at least a motion module identifier. Based on the motion module identifier in the first control instruction, the single-board computer stores the first control instruction in an instruction space corresponding to the motion module identifier. Based on the motion module identifier in the first control instruction, the digital signal processor assigns the first control instruction to a functional core corresponding to the motion module identifier for processing. The field programmable gate array responds by storing the acquired acquisition parameters in a memory space corresponding to the motion module identifier.

[0040] The motion module identification here may include a coarse motion module identification, a fine motion module identification, a vertical module identification, a balancing mass module identification, and a cable platform module identification.

[0041] Because the multi-core DSP parallel processing architecture involves large amounts of frequent data exchange, shared memory is used to establish global physical memory for data sharing. A unified, independently addressable data storage space is planned for each interacting data type. Distributed local memory with a transparent storage interface is also designed for each parallel core. Data in the shared memory is refreshed periodically by the system's data stream. The shared memory area is divided into three memory blocks: MSMC_REGION0, MSMC_REGION1, and MSMC_REGION2. MSMC_REGION0 is used for inter-core communication data, typically containing global variables. MSMC_REGION1 is used for communication between the DSP and FPGA, and between the DSP and PowerPC, for transferring large amounts of data. This area is further divided into fiber optic uplink data (sensor acquisition data) and fiber optic downlink data (actuator control data). Both the fiber optic uplink and downlink data areas are 2048 bytes in size. The control process data area is 0x80000 bytes. The trace diagnostic and logging modules are both 0x80000 bytes. Since logging and tracing diagnostics require long-term recording, as the program runs, infinitely expanding the buffer will result in excessive memory usage. Therefore, a ring buffer is used to store the logging and tracing diagnostics modules.

[0042] The digital signal processor further includes a log core for initializing the log module and allocating a buffer for the system log. The digital signal processor further includes a trace diagnosis core for initializing the trace diagnosis module and allocating a buffer for trace diagnosis information.

[0043] Data from the tracing and diagnostic core and the logging core can be transmitted via the backplane SRIO. The DSP SRIO communication is configured as follows: Lane A and Lane B are used for connection to the FPGA, meaning two receive channels are used. A single channel has a rate of 5 Gbps, and a dual-channel configuration achieves a communication rate of 10 Gbps. This improves the real-time performance of data acquisition. The DSP backplane SRIO communication is configured as 1x, using Lane C. SRIO communication uses Direct IO. The port number for communication with the FPGA is port 0, and the port number for communication with the backplane is port 2. The logging module core transmits log data to the Power PC via SRIO. After data transmission is complete, a doorbell notification signal is sent. The same method is used for the tracing and diagnostic module and the logging module. By using Direct IO + Doorbell for SRIO data transmission and notification, the communication advantages of SRIO are fully utilized, improving system real-time performance.

[0044] The PPC-to-DSP communication model in the entire system uses static address allocation and pre-established isolation and partitioning, resulting in cross-over and overlapping use of simulated memory. This introduces unpredictable issues. For the DSP real-time computing core, the FPGA statically allocates and optimizes performance for critical data, including sensor data collected via optical fiber and actuator force output data. This ensures deterministic latency in critical data links, manages data jitter, and ensures servo control performance.

[0045] Example 3 In a specific embodiment, a multi-core hybrid task processing framework can be built on the DSP by adapting corresponding peripheral resources to different cores. The main core serves as the management core and is equipped with the SYS / BIOS operating system, while the other cores do not have an operating system and run as bare cores.

[0046] Among them, the synchronous clock card generates a synchronous sampling signal according to the preset frequency and sends it to the field programmable gate array through the SYNC synchronization bus; the field programmable gate array responds to the synchronization signal, generates a doorbell signal and sends it to the sensor acquisition board through optical fiber to obtain the acquisition parameters uploaded by the sensor, and sends it to the digital signal processor to save it in the corresponding space.

[0047] The field programmable gate array generates an interrupt signal in response to the synchronization signal and sends it to the digital signal processor. The digital signal processor, in response to the interrupt signal, calculates control parameters corresponding to the first control instruction based on pre-stored acquisition parameters to generate a second control instruction and sends it to the power amplifier board. The power amplifier board sends the second control instruction to the driver to drive the actuator to complete the movement indicated by the first control instruction. The doorbell signal is earlier in timing than the interrupt signal.

[0048] The preset frequency here can be 200us. After receiving the 200us interrupt from the synchronization clock card, the motion control card converts the data into motion parameters through calculation, and then transmits the control register instructions to the PACB via optical fiber. The PACB interprets the control instructions of the corresponding register and controls the analog quantity through the DAC.

[0049] like Figure 9 As shown, at time t0, an interrupt signal immediately triggers the FPGA fiber controller in the fiber interface unit to send a command to read fiber data. The motion control card's FPGA sends an SRIO doorbell signal to the sensor acquisition card's FPGA data acquisition module. The data acquisition module then sends the collected data via optical fiber to the motion control card's FPGA. To ensure that all fiber data within the current sampling period can be read, the time interval Δt between t0 and t1 can be 5µs. To ensure data stability, it is usually set to 6µs in practice. The data transmitted via the optical fiber is directly filled into the DSP's SRIO data buffer.

[0050] At time t1, an interrupt signal arrives, and the sampled data begins to be processed to execute motion control. The actuator output of the calculated result is sent to the power amplifier board via the optical fiber interface, thus completing the acquisition, calculation and output process of the servo system.

[0051] The interrupt signal uses GPIO synchronous interrupt technology to enable multiple DSPs to enter the GPIO interrupt at the same time. Since DSP GPIO8-15 are visible to all cores, the system selects GPIO11 as the interrupt control signal. In this GPIO interrupt service subroutine, the sampling task is processed.

[0052] The present application provides a control system for a multi-axis motion platform, which adopts a data acquisition timing method, uses SRIO to collect and send data through optical fiber, and designs data sampling in advance of data processing, so as to prepare sensor data in advance and perform servo calculations. In response to the requirements of real-time acquisition-servo calculation-real-time output, a high-latency and low-jitter acquisition timing is designed, which can optimize the input and output servo loop delays and improve the servo control performance.

[0053] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0054] In addition, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0055] Furthermore, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0056] It should be noted that if the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the existing technology, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0057] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0058] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A control system for a multi-axis motion platform, characterized in that: The control system includes a host computer and a control chassis, the control chassis includes at least a single-board computer, a motion control card, a position resolution card, a synchronous clock card, and a bus, the host computer and the single-board computer are connected via a network cable, and the single-board computer, the motion control card, the position resolution card, and the synchronous clock card are connected via a backplane VME bus, a backplane SRIO bus, a PDB bus, and a SYNC synchronous bus, respectively. The host computer is used to generate a first control instruction based on the user operation obtained through the human-computer interaction interface and send it to the single-board computer through the network communication mode. The single-board computer is used to send the received first control instruction to the motion control card, so that the motion control card drives the actuator to complete the motion based on the first control instruction.

2. The system according to claim 1, wherein: The motion control card includes a digital signal processor and a field programmable gate array, The single board computer sends the first control instruction to the digital signal processor via the VME bus, and sets the first control instruction sending identifier to a first identifier value; The digital signal processor determines, based on the first control instruction reception identifier, whether the first control instruction is received, and if so, drives the actuator to complete the movement based on the first control instruction; After the movement is completed, the digital signal processor generates an interrupt signal and sends it to the single board computer via the VME bus; The single board computer generates feedback information corresponding to the first control instruction in response to the interrupt signal, and sends the feedback information to the host computer via a network communication method.

3. The system according to claim 2, characterized in that The synchronous clock card generates a synchronous signal according to the preset frequency and sends it to the field programmable gate array through the SYNC synchronous bus; The field programmable gate array generates a doorbell signal in response to the synchronization signal and sends the signal to the sensor acquisition board through the optical fiber to obtain the acquisition parameters uploaded by the sensor and send the acquired parameters to the digital signal processor for storage.

4. The system according to claim 3, characterized in that The field programmable gate array generates an interrupt signal in response to the synchronization signal and sends it to the digital signal processor. The digital signal processor calculates a control parameter corresponding to the first control instruction based on pre-stored acquisition parameters in response to the interrupt signal to generate a second control instruction and sends it to the power amplifier board. The power amplifier board sends the second control instruction to the driver to drive the actuator to complete the movement indicated by the first control instruction.

5. The system according to claim 4, characterized in that The timing of the doorbell signal is earlier than that of the interrupt signal.

6. The system according to claim 4, characterized in that The first control instruction is used to indicate the motion module identifier, and the first control instruction at least includes the motion module identifier; The single board computer stores the first control instruction in an instruction space corresponding to the motion module identifier based on the motion module identifier in the first control instruction; The digital signal processor allocates the first control instruction to a functional core corresponding to the motion module identifier for processing based on the motion module identifier in the first control instruction.

7. The system according to claim 6, characterized in that The field programmable gate array responds by storing the acquired acquisition parameters in a memory space corresponding to the motion module identifier.

8. The system according to claim 1, wherein: The digital signal processor includes multiple functional cores and management cores. The management core is used to carry the SYS / BIOS operating system and create network communication tasks.

9. The system according to claim 8, characterized in that The digital signal processor further includes a log core, which is used to initialize the log module and allocate a buffer zone for the system log.

10. The system according to claim 9, characterized in that The digital signal processor further includes a trace diagnosis core, which is used to initialize the trace diagnosis module and allocate a buffer for trace diagnosis information.

Images