Ion implantation compensation method

Abstract

The invention provides an ion implantation compensation method which comprises the following steps: in the processing process of a semiconductor device, measuring the actual size offset of a semiconductor intermediate device before ion implantation in a target area; on the basis of the actual size offset, a first relation and a second relation, the compensation dosage for ion implantation compensation on the target area is determined, ion implantation is carried out, the first relation is determined through simulation of the semiconductor device, and the first relation represents the relation between the size offset of the semiconductor device and the driving current variation in simulation; the second relation is determined through simulation of the semiconductor device, and the second relation represents the relation between the ion adjustment dosage and the driving current variation of the semiconductor device in simulation. In the processing process of the semiconductor device, the size deviation of the effective channel length of the device caused by the process deviation of photoetching, etching and the like is effectively corrected, the manufacturing yield of the device is improved, and the production cost of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to an ion implantation compensation method. Background Art

[0002] As semiconductor processes continue to shrink, the effective channel length of a device directly affects the drive current and overall device performance. This effective channel length can include critical sidewall dimensions and gate dimensions. Particularly in the manufacturing process of devices under 55nm, due to process variations such as photolithography and etching, the effective channel length of the device often shifts due to the size of the sidewalls or gate, affecting the device's drive current and overall performance.

[0003] To address this issue, the traditional approach is to measure the device after photoresist formation. If the sidewall or gate dimensions are found to be out of specification, the device is reworked to adjust the critical sidewall and gate dimensions to ensure that the effective channel length does not shift, thereby preventing the device's drive current and overall performance from being affected by effective channel length shift. However, this method increases device production costs and is difficult to completely avoid the problem of effective channel length shift caused by etching, resulting in a low device manufacturing yield. Therefore, how to improve device manufacturing yield while reducing device production costs is an urgent problem that needs to be solved. Summary of the Invention

[0004] The present invention provides an ion implantation compensation method, which can reduce the production cost of a device and improve the manufacturing yield of the device.

[0005] According to a first aspect of the present invention, there is provided an ion implantation compensation method, comprising: During the processing of semiconductor devices, the actual size deviation of the semiconductor intermediate device is measured before ion implantation in the target area; Based on the actual size offset, the first relationship and the second relationship, a compensation dose for ion implantation compensation of the target area is determined and ion implantation is performed, the first relationship is determined by simulating the semiconductor device, and the first relationship characterizes the relationship between the size offset of the semiconductor device and the change in driving current in the simulation, the second relationship is determined by simulating the semiconductor device, and the second relationship characterizes the relationship between the ion adjustment dose and the change in driving current of the semiconductor device in the simulation.

[0006] Optionally, the method for determining the first relationship by simulation includes: forming a simulated intermediate device corresponding to the semiconductor intermediate device in simulation software; Performing a plurality of size offset simulations on the simulated intermediate device to obtain a plurality of first simulated driving currents corresponding to the first size offsets; Based on the multiple first size offsets and the first simulated driving currents corresponding to the multiple first size offsets, a relationship between the size offsets and the driving current variation of the simulated intermediate device is determined.

[0007] Optionally, the method for performing the size offset simulation each time includes: Performing a first lateral shift on the first total lateral dimension of the simulated intermediate device in the simulation software to obtain a simulated intermediate device after the shift; In the simulation software, performing ion implantation simulation of a target region on the shifted simulated intermediate device to form a first simulated device under test; A current measurement is performed on the first simulated device under test to obtain a first simulated driving current corresponding to the first size offset.

[0008] Optionally, the method for determining the second relationship by simulation includes: forming a simulated intermediate device corresponding to the semiconductor intermediate device in simulation software; Performing a plurality of ion dose adjustment simulations on the simulated intermediate device to obtain a plurality of second simulated driving currents corresponding to the first ion adjustment doses; Based on the plurality of first ion adjustment doses and the second simulated driving currents corresponding to the plurality of first ion adjustment doses, a relationship between the ion adjustment dose and the driving current variation of the semiconductor device in the simulation is determined.

[0009] Optionally, the method of performing each ion dose adjustment simulation includes: Adjusting the ion implantation dose of the target area by a first ion adjustment dose in the simulation software to obtain a first target implantation dose; performing ion implantation simulation according to the first target implantation dose in the simulation software to obtain a second simulated device under test; Current measurement is performed on the second simulated device under test to obtain a second simulated driving current corresponding to the first ion adjustment dose.

[0010] Optionally, the simulated intermediate device includes a simulated semiconductor substrate, a simulated gate structure and a first simulated sidewall; or, the simulated intermediate device includes a simulated semiconductor substrate, a simulated gate structure, a first simulated sidewall, a simulated lightly doped region and a second simulated sidewall.

[0011] Optionally, during the processing of the semiconductor device, measuring the actual size offset of the semiconductor intermediate device before ion implantation in the target area includes: providing a semiconductor substrate; forming an actual gate structure located on the semiconductor substrate and a first actual sidewall spacer located on the semiconductor substrate and on a sidewall of the actual gate structure to obtain a semiconductor intermediate device; measuring a second total lateral dimension of the semiconductor intermediate device to obtain a measured total dimension, where the second total lateral dimension is the sum of a dimension of the actual gate structure and a dimension of the first actual spacer; Acquire a first target total size of the semiconductor intermediate device, where the first target total size is the sum of a preset size of the actual gate structure and a preset size of the first actual sidewall spacer; An actual size offset is determined based on the measured overall size and the first target overall size.

[0012] Optionally, before measuring the second total lateral dimension of the semiconductor intermediate device, measuring the actual dimension offset of the semiconductor intermediate device before ion implantation in the target region during the processing of the semiconductor device further includes: forming an actual lightly doped region located in the semiconductor substrate and a second actual sidewall spacer located on the semiconductor substrate and on the sidewalls of the first actual sidewall spacer, to obtain the semiconductor intermediate device; The second total lateral size also includes the size of the second actual sidewall, and the first target total size also includes the size of the second actual sidewall.

[0013] Optionally, determining a compensation dose for ion implantation compensation in a target area based on the actual size offset, the first relationship, and the second relationship and performing ion implantation includes: Substituting the actual size offset, the first relationship, and the second relationship into a compensation dose calculation model to obtain a compensation dose for ion implantation compensation of the target area, the compensation dose calculation model comprising: Among them, CD represents the actual size offset, Indicates the change in driving current, Indicates the size offset, Indicates ion adjustment dose, Indicates the first relationship, Represents the second relationship, Indicates the unit conversion factor; Ions are implanted into the target area according to the compensation dose.

[0014] Optionally, before determining a compensation dose for ion implantation compensation of the target area based on the actual size offset, the first relationship, and the second relationship, the ion implantation compensation method further includes: determining a target offset of the semiconductor intermediate device according to the actual size offset; The step of determining a compensation dose for ion implantation compensation in a target area based on the actual size offset, the first relationship, and the second relationship and performing ion implantation includes: Based on the target offset, the first relationship, and the second relationship, a compensation dose for ion implantation compensation in the target area is determined and ion implantation is performed.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The technical solution of the present invention provides an ion implantation compensation method. During the processing of a semiconductor device, the actual size offset of the semiconductor intermediate device before ion implantation in the target area is measured; based on the actual size offset, a first relationship, and a second relationship, a compensation dose for ion implantation compensation in the target area is determined and ion implantation is performed. The first relationship is determined by simulating the semiconductor device, and the first relationship represents the relationship between the size offset of the semiconductor device and the change in drive current in the simulation. The second relationship is determined by simulating the semiconductor device, and the second relationship represents the relationship between the ion adjustment dose and the change in drive current of the semiconductor device in the simulation. That is, the first relationship and the second relationship are determined in advance by simulation, wherein the first relationship represents the relationship between the size offset of the semiconductor device and the change in drive current in the simulation, and the second relationship represents the relationship between the ion adjustment dose and the change in drive current of the semiconductor device in the simulation. Then, during the processing of the semiconductor device, based on the actual size offset, the first relationship and the second relationship, the compensation dose for ion implantation compensation of the target area is determined and ion implantation is performed, thereby effectively correcting the size offset of the effective channel length of the device caused by process deviations such as lithography and etching, avoiding the influence of the size offset of the effective channel length on the driving current and overall performance of the device, achieving precise control of the driving current of the device, ensuring the overall performance of the device, and improving the manufacturing yield of the device.

[0016] In addition, the ion implantation compensation method provided by the technical solution of the present invention does not require rework of the device during the processing of the semiconductor device to avoid the impact of the dimensional deviation of the effective channel length on the driving current and overall performance of the device, thereby greatly reducing the production cost of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is a flow chart of the ion implantation compensation method provided by an embodiment of the present invention; Figure 2 is a structural schematic diagram of a semiconductor device provided by an embodiment of the present invention; Figure 3 1 is a schematic diagram of the size deviation of the first simulated sidewall in the ion implantation compensation method provided by an embodiment of the present invention; Figure 4 is an IV characteristic curve diagram of a simulated NMOS provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0020] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions; for example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements that are not explicitly listed or that are inherent to such processes, methods, products, or apparatuses. In addition, directional terms such as above, below, up, down, upward, downward, left, right, and the like are used relative to the exemplary embodiments as they are shown in the figures, with an upward or upper direction being toward the top of the corresponding figure and a downward or lower direction being toward the bottom of the corresponding figure.

[0021] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0022] Figure 1This is a flow chart of the ion implantation compensation method provided by an embodiment of the present invention. The method can be executed by an electronic device, such as a computer, a server, etc. The following embodiments will be described by taking the device integrated into an electronic device as an example. Figure 1 , the method may specifically include the following steps: Step 101 : During the processing of the semiconductor device, the actual size offset of the semiconductor intermediate device is measured before ion implantation in the target area.

[0023] Semiconductor devices can be understood as devices made of various materials through specific processes. A semiconductor device can be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which is a device made of three materials: metal, oxide (SiO2 or SiN), and semiconductor.

[0024] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention. Figure 2 , the semiconductor device may include a semiconductor substrate, an actual gate structure, a first actual sidewall, a second actual sidewall, an actual lightly doped region and an actual source and drain region. The actual gate structure is located on the surface of the semiconductor substrate. The first actual sidewall and the second actual sidewall are in contact with the semiconductor substrate and are both located in the semiconductor substrate. The actual lightly doped region and the actual source and drain region are located in the semiconductor substrate. The first actual sidewall is located on the sidewall of the actual gate structure, and the first actual sidewall is also located between the sidewall of the second actual sidewall and the sidewall of the actual gate structure. The actual lightly doped region is located in the semiconductor substrate below the first actual sidewall and the second actual sidewall. The second actual sidewall is located on the sidewall of the first actual sidewall, and the second actual sidewall is also located above the actual lightly doped region. The actual source and drain region is located below the actual gate structure, the first actual sidewall, and the second actual sidewall, and is located in the actual lightly doped region.

[0025] In this embodiment, the actual size offset may be understood as the offset of the device structure of the semiconductor device, specifically the offset of the device structure of the semiconductor intermediate device.

[0026] Specifically, during the processing of semiconductor devices, measuring the actual size offset of the semiconductor intermediate device before ion implantation in the target area can include: providing a semiconductor substrate; forming a device structure located on the semiconductor substrate to obtain a semiconductor intermediate device; measuring a second total lateral dimension of the device structure to obtain a measured total dimension; obtaining a preset first target total dimension of the device structure; and determining the actual size offset based on the measured total dimension and the first target total dimension.

[0027] The device structure may include an actual gate structure and a first actual spacer on the sidewall of the actual gate structure, or the device structure may include an actual gate structure, a first actual spacer on the sidewall of the actual gate structure, and a second actual spacer on the sidewall of the first actual spacer. The following describes different situations.

[0028] In one embodiment, the device structure may include an actual gate structure and a first actual spacer on a sidewall of the actual gate structure, and the actual size offset may include a size offset of the actual gate structure and the first actual spacer.

[0029] In this embodiment, during the processing of the semiconductor device, measuring the actual size offset of the semiconductor intermediate device before ion implantation in the target area can include: providing a semiconductor substrate; forming an actual gate structure located on the semiconductor substrate, and a first actual side wall located on the semiconductor substrate and located on the side wall of the actual gate structure to obtain a semiconductor intermediate device; measuring a second total lateral dimension of the semiconductor intermediate device to obtain a measured total dimension; obtaining a first target total dimension of the semiconductor intermediate device; and determining the actual size offset based on the measured total dimension and the first target total dimension.

[0030] The second total lateral dimension is the sum of the dimensions of the actual gate structure and the dimensions of the first actual spacer. The dimensions of the actual gate structure are determined based on the thickness of the actual gate structure. The dimensions of the first actual spacer are determined based on the thickness of the first actual spacer. The first target total dimension is the sum of the preset dimensions of the actual gate structure and the dimensions of the first actual spacer.

[0031] In this embodiment, determining the actual size offset according to the measured total size and the first target total size may include: subtracting the measured total size from the first target total size to obtain the actual size offset.

[0032] In the above embodiment, the semiconductor intermediate device including the semiconductor substrate, the actual gate structure and the first actual spacer can be referred to as a first semiconductor intermediate device.

[0033] In another embodiment, the device structure may include an actual gate structure, a first actual sidewall spacer of the actual gate structure, and a second actual sidewall spacer of the first actual sidewall spacer. The actual size offset may further include a size offset of the second actual sidewall spacer, and the actual size offset includes the size offset of the actual gate structure, the first actual sidewall spacer, and the second actual sidewall spacer.

[0034] In this embodiment, during the processing of the semiconductor device, measuring the actual size offset of the semiconductor intermediate device before ion implantation in the target area can include: providing a semiconductor substrate; forming an actual gate structure located on the semiconductor substrate, a first actual sidewall located on the semiconductor substrate and located on the sidewall of the actual gate structure, an actual lightly doped region located in the semiconductor substrate, and a second actual sidewall located on the semiconductor substrate and located on the sidewall of the first actual sidewall to obtain a semiconductor intermediate device; measuring a second total lateral dimension of the semiconductor intermediate device to obtain a measured total dimension; obtaining a first target total dimension of the semiconductor intermediate device; and determining the actual size offset based on the measured total dimension and the first target total dimension.

[0035] In this embodiment, the second total lateral dimension is the sum of the dimensions of the actual gate structure, the dimensions of the first actual spacer, and the dimensions of the second actual spacer. The dimensions of the actual gate structure are determined based on the thickness of the actual gate structure, the dimensions of the first actual spacer are determined based on the thickness of the first actual spacer, and the dimensions of the second actual spacer are determined based on the thickness of the second actual spacer. The first target total dimension is the sum of the preset dimensions of the actual gate structure, the dimensions of the first actual spacer, and the dimensions of the second actual spacer.

[0036] In this embodiment, the semiconductor intermediate device includes a semiconductor substrate, an actual gate structure located on the semiconductor substrate, a first actual side wall located on the semiconductor substrate and located on the side wall of the actual gate structure, an actual lightly doped region located on both sides of the actual gate structure and located within the semiconductor substrate, and a second actual side wall located on the semiconductor substrate and located on the side wall of the first actual side wall away from the actual gate structure, which can be referred to as a second semiconductor intermediate device.

[0037] Step 102 : determining a compensation dose for ion implantation compensation in the target area based on the actual size offset, the first relationship, and the second relationship, and performing ion implantation.

[0038] Among them, the first relationship is determined by simulating the semiconductor device, and the first relationship represents the relationship between the size offset of the semiconductor device and the change in driving current in the simulation; the second relationship is determined by simulating the semiconductor device, and the second relationship represents the relationship between the ion adjustment dose and the change in driving current of the semiconductor device in the simulation.

[0039] In one embodiment, determining the first relationship through simulation may include: forming a simulated intermediate device corresponding to the semiconductor intermediate device in simulation software; performing several size offset simulations on the simulated intermediate device to obtain first simulated driving currents corresponding to multiple first size offsets; and determining the relationship between the size offset of the simulated intermediate device and the driving current change based on the multiple first size offsets and the first simulated driving currents corresponding to the multiple first size offsets.

[0040] In one embodiment, each size offset simulation may include: performing a first lateral offset on a first total lateral dimension of a simulated intermediate device in the simulation software to obtain a simulated intermediate device after the offset; completing an ion implantation simulation of a target area on the simulated intermediate device after the offset in the simulation software to form a first simulated device under test; and performing current measurement on the first simulated device under test to obtain a first simulated driving current corresponding to the first size offset.

[0041] In one embodiment, determining the second relationship through simulation may include: forming a simulated intermediate device corresponding to the semiconductor intermediate device in simulation software; performing several ion dose adjustment simulations on the simulated intermediate device to obtain a second simulated driving current corresponding to multiple first ion adjustment doses; and determining the relationship between the ion adjustment dose and the driving current change of the semiconductor device in the simulation based on the multiple first ion adjustment doses and the second simulated driving current corresponding to the multiple first ion adjustment doses.

[0042] In one embodiment, each ion dose adjustment simulation may include: adjusting the ion implantation dose of the target area in the simulation software to obtain a first ion adjustment dose; performing an ion implantation simulation in the simulation software according to the first ion adjustment dose to obtain a second simulated device under test; and measuring the current of the second simulated device under test to obtain a second simulated driving current corresponding to the first ion adjustment dose.

[0043] As previously described, the semiconductor intermediate device can be either a first semiconductor intermediate device or a second semiconductor intermediate device. Depending on the semiconductor intermediate device, the simulated intermediate device, the first size shift amount for size shifting, the simulated intermediate device after shifting, the first ion adjustment dose, the first simulated drive current, the second simulated drive current, and the target area may all be different. This will be described below in different cases.

[0044] In this embodiment, the semiconductor device in the simulation corresponds to the semiconductor device and may include a simulated substrate, a simulated gate structure, a first simulated sidewall, a second simulated sidewall, a simulated lightly doped region, and a simulated source / drain region. The simulated gate structure is located on the surface of the simulated substrate. The first simulated sidewall and the second simulated sidewall are in contact with the simulated substrate. The simulated lightly doped region and the simulated source / drain region are located within the simulated substrate. The first simulated sidewall is located on the sidewall of the simulated gate structure, and the first simulated sidewall is also located between the sidewall of the second simulated sidewall and the sidewall of the simulated gate structure. The simulated lightly doped region is located below the first simulated sidewall and the second simulated sidewall. The second simulated sidewall is located on the sidewall of the first simulated sidewall, and the second simulated sidewall is also located above the simulated lightly doped region. The simulated source / drain region is located below the simulated gate structure, the first simulated sidewall, the second simulated sidewall, and the simulated lightly doped region.

[0045] In one embodiment, a method for determining a first relationship through simulation may include: forming a simulated intermediate device (specifically, a first simulated intermediate device) corresponding to the semiconductor intermediate device in simulation software, where the simulated intermediate device may include a simulated gate structure and a first simulated sidewall; performing several size offset simulations on the simulated intermediate device to obtain a first simulated driving current corresponding to multiple first size offsets; and determining the relationship between the size offset of the simulated intermediate device and the driving current change based on the multiple first size offsets and the first simulated driving current corresponding to the multiple first size offsets.

[0046] In this embodiment, the first simulation intermediate device corresponds to the first semiconductor intermediate device. The target region includes an actual lightly doped region.

[0047] In this embodiment, the first size offset is a size offset for offsetting the size of the first simulation intermediate device, and the first simulation driving current is a simulation driving current corresponding to the first simulation intermediate device.

[0048] In this embodiment, the method for performing each size offset simulation may include: performing a first lateral offset on the first total lateral dimension of the simulated intermediate device in the simulation software to obtain the simulated intermediate device after the offset (specifically, it may be a second simulated intermediate device); in the simulation software, completing an ion implantation simulation of the target area of ​​the simulated intermediate device after the offset to form a first simulated device under test; and performing current measurement on the first simulated device under test to obtain a first simulated driving current corresponding to the first size offset.

[0049] In this embodiment, ion implantation simulation of the target area is completed for the offset simulated intermediate device, which may specifically include: performing ion implantation simulation of the lightly doped area of ​​the offset simulated intermediate device (i.e., the second simulated intermediate device), and forming a second simulated side wall and a simulated source and drain area to form a first simulated device under test.

[0050] In this embodiment, the first total lateral dimension is the sum of the dimension of the simulated gate structure and the dimension of the first simulated sidewall spacer, the dimension of the simulated gate structure is determined based on the thickness of the simulated gate structure, the dimension of the first simulated sidewall spacer is determined based on the thickness of the first simulated sidewall spacer, and the offset of the first lateral offset is the first dimension offset.

[0051] In this embodiment, the first dimension offset of each dimension offset simulation may be the same or different, and the first dimension offset of each dimension offset simulation needs to be determined according to actual needs. For example, the first dimension offset may be any value such as ±1, ±2, ±3, etc. When the first dimension offset is a positive number, it can be understood that the first total lateral dimension has undergone a dimension offset in the first direction. When the first dimension offset is a negative number, it can be understood that the first total lateral dimension has undergone a dimension offset in the second direction. The first direction and the second direction are opposite. In other embodiments, when the first total lateral dimension has undergone a dimension offset in the first direction, the first dimension offset may be a negative number; when the first total lateral dimension has undergone a dimension offset in the second direction, the first dimension offset may be a positive number, and this application does not impose any restrictions on this.

[0052] In a specific embodiment, determining the relationship between the size offset and the driving current change of a semiconductor device in a simulation based on multiple first size offsets and the first simulated driving currents corresponding to the multiple first size offsets may include: determining multiple first simulated driving current changes based on the multiple first size offsets and the first simulated driving currents corresponding to the multiple first size offsets; and determining the driving current change based on the multiple first simulated driving current changes.

[0053] For example, Figure 3 This is a schematic diagram illustrating the dimensional offset of the first simulated sidewall spacer in the ion implantation compensation method provided by an embodiment of the present invention. Assume that the initial dimension of the first total lateral dimension is 3 nm. If the driving current change IDS corresponding to a dimensional offset of 1.5 is determined through simulation, the numerical change of the first dimensional offset during several dimensional offset simulations can be set to increment in sequence. The value of each increment of the first dimensional offset is 1. The multiple first dimensional offsets can include: +1.5 (nm), +2.5 (nm), and +3.5 (nm). The "+" indicates that the first total lateral dimension has shifted in the first direction. If there are three first dimensional offsets, three dimensional offset simulations are performed on the first simulated intermediate device to obtain the first simulated driving current corresponding to each first dimensional offset (the first simulated driving current corresponding to +1.5 is IDS1, the first simulated driving current corresponding to +2.5 is IDS2, and the first simulated driving current corresponding to +3.5 is IDS3). Then, IDS2 can be subtracted from IDS1 to obtain the first simulated driving current change ΔIDS1, and IDS3 can be subtracted from IDS2 to obtain the first simulated driving current change ΔIDS2. Finally, the average value IDS of △IDS1 and △IDS2 is determined, and IDS is determined as the driving current change corresponding to the size offset 1.

[0054] As another example, if the driving current change IDS corresponding to a dimension offset of 2 is determined through simulation, the numerical change of the first dimension offset during several dimension offset simulations can be set to increment in sequence. The value of each increment of the first dimension offset is 2. The multiple first dimension offsets can include: +2 (nm), +4 (nm), and +6 (nm). The "+" indicates that the first total lateral dimension has been offset in the first direction. If there are three first dimension offsets, three dimension offset simulations are performed on the simulated intermediate device (specifically, the first simulated intermediate device) to obtain the first simulated driving current corresponding to each first dimension offset (the first simulated driving current corresponding to +2 is IDS1, the first simulated driving current corresponding to +4 is IDS2, and the first simulated driving current corresponding to +6 is IDS3). Then, IDS2 can be subtracted from IDS1 to obtain the first simulated driving current change ΔIDS1, and IDS3 can be subtracted from IDS2 to obtain the first simulated driving current change ΔIDS2. Finally, the average value IDS of ΔIDS1 and ΔIDS2 is determined, and IDS is determined as the driving current change corresponding to dimension offset 2.

[0055] In this embodiment, the method for determining the second relationship through simulation may include: forming a simulated intermediate device (specifically, a third simulated intermediate device) corresponding to the semiconductor intermediate device in the simulation software, and the simulated intermediate device may include a simulated gate structure and a first simulated side wall; performing several ion dose adjustment simulations on the simulated intermediate device to obtain a second simulated driving current corresponding to multiple first ion adjustment doses; based on the multiple first ion adjustment doses and the second simulated driving current corresponding to the multiple first ion adjustment doses, determining the relationship between the ion adjustment dose and the driving current change of the semiconductor device in the simulation.

[0056] In this embodiment, the third intermediate simulation device is consistent with the first simulation intermediate device described above, that is, it includes a simulated semiconductor substrate, a simulated gate structure located on the simulated semiconductor substrate, and a first simulated sidewall located on the simulated semiconductor substrate and on the sidewall of the simulated gate structure.

[0057] In this embodiment, the method for performing each ion dose adjustment simulation may include: adjusting the ion implantation dose of the first ion in the simulated lightly doped area by a first ion adjustment dose in the simulation software to obtain a first target implantation dose; performing ion implantation simulation according to the first target implantation dose in the simulation software to form a simulated lightly doped area to obtain a simulated intermediate device after ion implantation (specifically, it may be a fourth simulated intermediate device); completing the device processing process of the second simulated side wall and the simulated source and drain region on the simulated intermediate device after ion implantation in the simulation software to obtain a second simulated device to be tested; and performing current measurement on the second simulated device to be tested to obtain a second simulated driving current corresponding to the first ion adjustment dose.

[0058] In this embodiment, the first ion can be understood as the ion implanted when forming the actual lightly doped region. The first ion adjustment dose can be any value. When the first ion adjustment dose is a positive number, it indicates an increase in the implantation dose of the first ion. When the first ion adjustment dose is a negative number, it indicates a decrease in the implantation dose of the first ion.

[0059] In a specific embodiment, determining the relationship between the ion adjustment dose and the driving current change of a semiconductor device in a simulation based on multiple first ion adjustment doses and the second simulated driving current corresponding to the multiple first ion adjustment doses may include: determining multiple third simulated driving current changes based on the multiple first ion adjustment doses and the second simulated driving current corresponding to the multiple first ion adjustment doses; and determining the driving current change based on the multiple third simulated driving current changes.

[0060] For example, if the ion adjustment dose of the first ion is determined to be 0.1e by simulation, 15 The driving current change IDS corresponding to / cm² can be set to increase the value of the first ion adjustment dose in the simulation of several ion dose adjustment. The value of each increase in the first ion adjustment dose is 0.1e 15 The plurality of first ion adjustment doses may include: -0.1e 15 / cm², 0 / cm², +0.1e 15 / cm². “-” means the first ion implantation dose per square centimeter is reduced by 0.1e 15 “+” indicates that the implantation dose of the first ion per square centimeter increases by 0.1e 15 The first ion adjustment dose includes three, and the third simulation intermediate device is simulated for three ion dose adjustment to obtain the second simulation driving current (-0.1e 15 The second simulation driving current corresponding to / cm² is IDS1, the second simulation driving current corresponding to 0 / cm² is IDS2, and +0.1e 15 / cm² corresponds to the second simulated driving current IDS3). Then, IDS2 can be subtracted from IDS1 to obtain the third simulated driving current change △IDS1, and IDS3 can be subtracted from IDS2 to obtain the third simulated driving current change △IDS2. Finally, the average value IDS of △IDS1 and △IDS2 is determined, and IDS is determined as the ion adjustment dose 0.1e 15 / cm 2 The corresponding driving current change.

[0061] In this embodiment, a simulated gate structure and a first simulated side wall of the semiconductor device in the simulation can be formed in the simulation software to obtain a first simulated intermediate device; several size offset simulations are performed on the first simulated intermediate device to obtain first simulated driving currents corresponding to multiple first size offsets, and based on the multiple first size offsets and the first simulated driving currents corresponding to the multiple first size offsets, the relationship between the size offset of the semiconductor device in the simulation and the change in driving current is determined, that is, the first relationship is obtained.

[0062] Then, a simulated gate structure and a first simulated side wall are formed in the simulation software to obtain a third simulated intermediate device; several ion dose adjustment simulations are performed on the third simulated intermediate device to obtain a second simulated driving current corresponding to multiple first ion adjustment doses, and based on the multiple first ion adjustment doses and the second simulated driving current corresponding to the multiple first ion adjustment doses, the relationship between the ion adjustment dose and the driving current change of the semiconductor device in the simulation is determined, that is, the second relationship is obtained.

[0063] Finally, during the processing of the semiconductor device, an actual gate structure and a first actual sidewall spacer are formed; a second total lateral dimension of the semiconductor intermediate device is measured to obtain a measured total dimension; a first target total dimension of the semiconductor intermediate device is obtained; and an actual dimension offset is determined based on the measured total dimension and the first target total dimension. A target offset is determined based on the actual dimension offset, and precise ion implantation compensation is performed during the actual lightly doped region formation stage based on the target offset, the first relationship, and the second relationship. This effectively corrects the dimensional offset of the device's effective channel length caused by process deviations such as photolithography and etching before the second actual sidewall spacer is formed, thereby preventing the dimensional offset of the effective channel length from affecting the device's drive current and overall performance. This allows for precise control of the device's drive current, ensures overall device performance, and improves the device's manufacturing yield.

[0064] Figure 4 This is an IV characteristic curve of the simulated NMOS provided by the embodiment of the present invention. The simulation software simulates the precise ion implantation compensation in the actual lightly doped region formation stage, and obtains Figure 4 The IV characteristic curve of the simulated NMOS is shown in FIG. Figure 4 It can be seen that by performing precise ion implantation compensation during the actual lightly doped region formation stage, as the target offset increases, the simulated NMOS drive current gradually approaches the standard drive current, verifying the effectiveness of the ion implantation compensation method provided in the embodiment of the present invention.

[0065] In another embodiment, a method for determining a first relationship by simulation may include: forming a simulated intermediate device (specifically, a fifth simulated intermediate device) corresponding to the semiconductor intermediate device in simulation software, the simulated intermediate device including a simulated gate structure, a first simulated side wall, a simulated lightly doped region, and a second simulated side wall; performing several size offset simulations on the fifth simulated intermediate device to obtain a first simulated driving current corresponding to multiple first size offsets; and determining the relationship between the size offset and the driving current change of the semiconductor device in the simulation based on the multiple first size offsets and the first simulated driving current corresponding to the multiple first size offsets.

[0066] In this embodiment, the simulated intermediate device (specifically, the fifth simulated intermediate device) corresponds to the second semiconductor intermediate device. The target region includes a source and drain region.

[0067] In this embodiment, the first size offset is a size offset for offsetting the size of the fifth simulated intermediate device, and the first simulated driving current is a simulated driving current corresponding to the fifth simulated intermediate device.

[0068] In this embodiment, the method for performing each size offset simulation may include: performing a first lateral offset on the first total lateral dimension of the simulated intermediate device (specifically, the fifth simulated intermediate device) in the simulation software to obtain the simulated intermediate device after the offset (specifically, the sixth simulated intermediate device); completing the device processing process of the simulated source and drain regions of the simulated intermediate device after the offset (specifically, the sixth simulated intermediate device) in the simulation software to form a first simulated device to be tested, and performing current measurement on the first simulated device to be tested to obtain a first simulated driving current corresponding to the first size offset.

[0069] In this embodiment, the first total lateral dimension is the sum of the dimensions of the simulated gate structure, the dimensions of the first simulated spacer, and the dimensions of the second simulated spacer. The dimensions of the simulated gate structure are determined based on the thickness of the simulated gate structure. The dimensions of the first simulated spacer are determined based on the thickness of the first simulated spacer. The dimensions of the second simulated spacer are determined based on the thickness of the second simulated spacer. The offset amount of the first lateral offset is the first dimension offset.

[0070] In this embodiment, based on multiple first size offsets and the first simulated driving currents corresponding to the multiple first size offsets, the relationship between the size offsets and the driving current changes of the semiconductor device in the simulation is determined. For details, please refer to the relevant content of the previous embodiment and will not be repeated here.

[0071] In this embodiment, the method for determining the second relationship through simulation may include: forming a simulated intermediate device corresponding to the semiconductor intermediate device in the simulation software (specifically, it may be a seventh simulated intermediate device), the simulated intermediate device including a simulated gate structure, a first simulated side wall, a simulated lightly doped area and a second simulated side wall; performing several ion dose adjustment simulations on the simulated intermediate device to obtain a second simulated driving current corresponding to multiple first ion adjustment doses; based on the multiple first ion adjustment doses and the second simulated driving current corresponding to the multiple first ion adjustment doses, determining the relationship between the ion adjustment dose and the driving current change of the semiconductor device in the simulation.

[0072] In this embodiment, the seventh intermediate simulation device is consistent with the fifth simulation intermediate device described above, that is, it includes a simulated semiconductor substrate, a simulated gate structure located on the simulated semiconductor substrate, a first simulated side wall located on the simulated semiconductor substrate and located on the side wall of the simulated gate structure, a simulated lightly doped region located in the simulated semiconductor substrate on both sides of the simulated gate structure, and a second simulated side wall located on the side wall of the first simulated side wall away from the simulated gate structure.

[0073] In this embodiment, the method for performing each ion dose adjustment simulation may include: adjusting the ion implantation dose of the first ion in the simulated source and drain region by a first ion adjustment dose in the simulation software to obtain a first target implantation dose; performing ion implantation simulation according to the first target implantation dose in the simulation software to form a simulated source and drain region to obtain a second simulated device under test; and performing current measurement on the second simulated device under test to obtain a second simulated driving current corresponding to the first ion adjustment dose.

[0074] In this embodiment, the first ions can be understood as ions implanted when forming actual source and drain regions. Regarding the first ion adjustment dose, and determining the relationship between the ion adjustment dose and the change in drive current of the semiconductor device in the simulation based on multiple first ion adjustment doses and the second simulated drive current corresponding to the multiple first ion adjustment doses, please refer to the relevant description of the previous embodiment and will not be repeated here.

[0075] In this embodiment, a simulated gate structure, a first simulated side wall, a simulated lightly doped region and a second simulated side wall of the semiconductor device in the simulation can be formed in the simulation software to obtain a fifth simulated intermediate device; several size offset simulations are performed on the fifth simulated intermediate device to obtain first simulated driving currents corresponding to multiple first size offsets, and based on the multiple first size offsets and the first simulated driving currents corresponding to the multiple first size offsets, the relationship between the size offset and the driving current change of the semiconductor device in the simulation is determined, that is, the first relationship is obtained.

[0076] Then, a simulated gate structure, a first simulated side wall, a simulated lightly doped area and a second simulated side wall are formed in the simulation software to obtain a seventh simulated intermediate device; several ion dose adjustment simulations are performed on the seventh simulated intermediate device to obtain a second simulated driving current corresponding to multiple first ion adjustment doses, and based on the multiple first ion adjustment doses and the second simulated driving current corresponding to the multiple first ion adjustment doses, the relationship between the ion adjustment dose and the driving current change of the semiconductor device in the simulation is determined, that is, the second relationship is obtained.

[0077] Finally, during the processing of the semiconductor device, an actual gate structure, a first actual sidewall, an actual lightly doped region, and a second actual sidewall can be formed; the second total lateral dimension of the semiconductor device can be measured to obtain a measured total dimension; the second target total dimension of the semiconductor device can be obtained; and the actual dimension offset can be determined based on the measured total dimension and the second target total dimension. The target offset can be determined based on the actual dimension offset. Based on the target offset, the first relationship, and the second relationship, ion implantation compensation can be performed during the actual source and drain region formation stage, thereby effectively correcting the dimensional offset of the device's effective channel length caused by process deviations such as photolithography and etching before the actual source and drain regions are formed, thereby avoiding the impact of the dimensional offset of the effective channel length on the device's drive current and overall performance, achieving precise control of the device's drive current, ensuring the overall performance of the device, and improving the device's manufacturing yield.

[0078] In other embodiments, the above-mentioned ion implantation compensation method for the actual lightly doped region formation stage and the ion implantation compensation method for the actual source and drain region formation stage can be used to perform ion implantation compensation on the semiconductor device in both the actual lightly doped region formation stage and the actual source and drain region formation stage. This can more effectively correct the dimensional deviation of the effective channel length of the device caused by process deviations such as lithography and etching, avoid the influence of the dimensional deviation of the effective channel length on the driving current and overall performance of the device, achieve precise control of the driving current of the device, ensure the overall performance of the device, and improve the manufacturing yield of the device.

[0079] In one embodiment, based on the actual size offset, the first relationship, and the second relationship, determining the compensation dose for ion injection compensation of the target area and performing ion injection can include: substituting the actual size offset, the first relationship, and the second relationship into the compensation dose calculation model to obtain the compensation dose for ion injection compensation of the target area, and performing ion injection on the target area according to the compensation dose.

[0080] As described above, the first relationship represents the relationship between the size offset of the semiconductor device and the change in the driving current in the simulation, and the second relationship represents the relationship between the ion adjustment dose and the change in the driving current of the semiconductor device in the simulation.

[0081] In this embodiment, the compensation dose calculation model may include: Among them, CD represents the actual size offset, Indicates the change in driving current, Indicates the size offset, Indicates ion adjustment dose, Indicates the first relationship, Represents the second relationship, Indicates the unit conversion factor.

[0082] In one embodiment, the actual size offset CD can be understood as the offset between the sum of the size of the actual gate structure of the semiconductor device and the size of the first actual sidewall spacer. The size offset SCD is the first size offset for the size offset of the first simulated intermediate device. The ion adjustment dose LD can be understood as the first ion adjustment dose for the first ion ion dose adjustment simulation of the third simulated intermediate device.

[0083] In this embodiment, performing ion implantation on the target region according to the compensation dose may include: performing ion implantation compensation on the first ion implantation in the target region according to the positive or negative value of the compensation dose to form an actual lightly doped region.

[0084] For example, when the compensating dose is positive, the ion implantation dose of the first ion is increased by the compensating dose to obtain a first target ion implantation dose, and ion implantation is performed at the first target ion implantation dose to form an actual lightly doped region. When the compensating dose is negative, the ion implantation dose of the first ion is reduced by the compensating dose to obtain the first target ion implantation dose, and ion implantation is performed at the first target ion implantation dose to form an actual lightly doped region.

[0085] In another embodiment, the actual size offset CD can be understood as the offset of the sum of the size of the actual gate structure of the semiconductor device, the size of the first actual sidewall spacer, and the size of the second actual sidewall spacer. The size offset SCD is the first size offset for the size offset of the fifth simulated intermediate device, and the ion adjustment dose LD can be understood as the ion adjustment dose of the first ion for the sixth simulated intermediate device.

[0086] In this embodiment, performing ion implantation on the target region according to the compensation dose may include: performing ion implantation compensation on the first ion implantation on the target region according to the positive or negative value of the compensation dose to form an actual source / drain region.

[0087] For example, when the compensating dose is positive, the ion implantation dose of the first ion is increased by the compensating dose to obtain a first target ion implantation dose, and ion implantation is performed at the first target ion implantation dose to form the actual source and drain regions. When the compensating dose is negative, the ion implantation dose of the first ion is reduced by the compensating dose to obtain the first target ion implantation dose, and ion implantation is performed at the first target ion implantation dose to form the actual source and drain regions.

[0088] In one embodiment, before determining the compensation dose for ion implantation compensation of the target area based on the actual size offset, the first relationship and the second relationship, the ion implantation compensation method may further include: determining a target offset of the semiconductor intermediate device according to the actual size offset.

[0089] In a specific embodiment, determining the target offset of the semiconductor intermediate device based on the actual size offset can include: rounding down the actual size offset to obtain the target offset of the semiconductor intermediate device, which can avoid over-compensation of ion implantation compensation, improve the accuracy of ion implantation compensation, and effectively correct the size offset of the effective channel length of the device caused by process deviations such as lithography and etching.

[0090] For example, the actual size offset is 2.5 (nm). Since 1≤2.5≤3, the actual size offset is rounded down to obtain a target offset of 2 nm for the semiconductor intermediate device. Based on the target offset, the first relationship, and the second relationship, a compensation dose for ion implantation compensation in the target area is determined and ion implantation is performed to avoid overcompensation of the ion implantation compensation.

[0091] In this embodiment, based on the actual size offset, the first relationship and the second relationship, the compensation dose for ion injection compensation of the target area is determined and ion injection is performed, which may include: based on the target offset, the first relationship and the second relationship, the compensation dose for ion injection compensation of the target area is determined and ion injection is performed, so as to avoid over-compensation of ion injection compensation.

[0092] In a specific embodiment, determining a compensation dose for ion implantation compensation in a target area based on the target offset, the first relationship, and the second relationship and performing ion implantation may include: The target offset, the first relationship, and the second relationship are substituted into a compensation dose calculation model to obtain a compensation dose for ion implantation compensation in the target area. Ions are implanted in the target area according to the compensation dose.

[0093] Among them, the compensation dose calculation model includes: Among them, CDD represents the target offset, Indicates the change in driving current, Indicates the size offset, Indicates ion adjustment dose, Indicates the first relationship, Represents the second relationship, In one embodiment, an electronic device is provided, which may be a server. Figure 5 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

[0094] Please refer to Figure 5 , provides an electronic device 50, including: processor 51; and a memory 52 for storing executable instructions of the processor; The processor 51 is configured to execute the above-mentioned method by executing the executable instructions.

[0095] The processor 51 can communicate with the memory 52 via a bus 53 .

[0096] The processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a program, and a database. The internal memory provides an environment for the operation of the operating system and program in the non-volatile storage medium. The database of the electronic device is used to store data such as the actual size offset of the semiconductor device, the first relationship, and the second relationship. When executed by the processor, the program implements the above-mentioned ion implantation compensation method.

[0097] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, which implements the above-mentioned ion implantation compensation method when executed by a processor.

[0098] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An ion implantation compensation method, characterized in that: include: During the processing of semiconductor devices, the actual dimensional offset of the semiconductor intermediate device is measured before ion implantation in the target area; Based on the actual size offset, the first relationship and the second relationship, a compensation dose for ion implantation compensation of the target area is determined and ion implantation is performed, the first relationship is determined by simulating the semiconductor device, and the first relationship characterizes the relationship between the size offset of the semiconductor device and the change in driving current in the simulation, the second relationship is determined by simulating the semiconductor device, and the second relationship characterizes the relationship between the ion adjustment dose and the change in driving current of the semiconductor device in the simulation.

2. The ion implantation compensation method according to claim 1, wherein: The method for determining the first relationship by simulation includes: forming a simulated intermediate device corresponding to the semiconductor intermediate device in simulation software; Performing a plurality of size offset simulations on the simulated intermediate device to obtain a plurality of first simulated driving currents corresponding to the first size offsets; Based on the multiple first size offsets and the first simulated driving currents corresponding to the multiple first size offsets, a relationship between the size offsets and the driving current variation of the simulated intermediate device is determined.

3. The ion implantation compensation method according to claim 2, wherein: The method for performing each dimension deviation simulation includes: Performing a first lateral shift on the first total lateral dimension of the simulated intermediate device in the simulation software to obtain a simulated intermediate device after the shift; In the simulation software, performing ion implantation simulation of a target region on the shifted simulated intermediate device to form a first simulated device under test; A current measurement is performed on the first simulated device under test to obtain a first simulated driving current corresponding to the first size offset.

4. The ion implantation compensation method according to claim 1, wherein: The method for determining the second relationship by simulation includes: forming a simulated intermediate device corresponding to the semiconductor intermediate device in simulation software; Performing a plurality of ion dose adjustment simulations on the simulated intermediate device to obtain a plurality of second simulated driving currents corresponding to the first ion adjustment doses; Based on the plurality of first ion adjustment doses and the second simulated driving currents corresponding to the plurality of first ion adjustment doses, a relationship between the ion adjustment dose and the driving current variation of the semiconductor device in the simulation is determined.

5. The ion implantation compensation method according to claim 4, characterized in that: The method of performing each ion dose adjustment simulation includes: Adjusting the ion implantation dose of the target area by a first ion adjustment dose in the simulation software to obtain a first target implantation dose; performing ion implantation simulation according to the first target implantation dose in the simulation software to obtain a second simulated device under test; Current measurement is performed on the second simulated device under test to obtain a second simulated driving current corresponding to the first ion adjustment dose.

6. The ion implantation compensation method according to any one of claims 2 to 5, characterized in that: The simulated intermediate device includes a simulated semiconductor substrate, a simulated gate structure and a first simulated sidewall; or, the simulated intermediate device includes a simulated semiconductor substrate, a simulated gate structure, a first simulated sidewall, a simulated lightly doped region and a second simulated sidewall.

7. The ion implantation compensation method according to claim 1, wherein: The method of measuring the actual size offset of the semiconductor intermediate device before ion implantation in the target area during the processing of the semiconductor device comprises: providing a semiconductor substrate; forming an actual gate structure located on the semiconductor substrate and a first actual sidewall spacer located on the semiconductor substrate and on a sidewall of the actual gate structure to obtain a semiconductor intermediate device; measuring a second total lateral dimension of the semiconductor intermediate device to obtain a measured total dimension, where the second total lateral dimension is the sum of a dimension of the actual gate structure and a dimension of the first actual spacer; Acquire a first target total size of the semiconductor intermediate device, where the first target total size is the sum of a preset size of the actual gate structure and a preset size of the first actual sidewall spacer; An actual size offset is determined based on the measured overall size and the first target overall size.

8. The ion implantation compensation method according to claim 7, wherein: Before measuring the second total lateral dimension of the semiconductor intermediate device, measuring the actual dimension offset of the semiconductor intermediate device before ion implantation in the target region during the processing of the semiconductor device further includes: forming an actual lightly doped region located in the semiconductor substrate and a second actual sidewall spacer located on the semiconductor substrate and on the sidewalls of the first actual sidewall spacer, to obtain the semiconductor intermediate device; The second total lateral size also includes the size of the second actual sidewall, and the first target total size also includes the size of the second actual sidewall.

9. The ion implantation compensation method according to claim 1, wherein: The step of determining a compensation dose for ion implantation compensation in a target area based on the actual size offset, the first relationship, and the second relationship and performing ion implantation includes: Substituting the actual size offset, the first relationship, and the second relationship into a compensation dose calculation model to obtain a compensation dose for ion implantation compensation of the target area, the compensation dose calculation model comprising: Among them, CD represents the actual size offset, Indicates the change in driving current, Indicates the size offset, Indicates ion adjustment dose, Indicates the first relationship, Represents the second relationship, Indicates the unit conversion factor; Ions are implanted into the target area according to the compensation dose.

10. The ion implantation compensation method according to claim 1, wherein: Before determining the compensation dose for ion implantation compensation of the target area based on the actual size offset, the first relationship, and the second relationship, the ion implantation compensation method further includes: determining a target offset of the semiconductor intermediate device according to the actual size offset; The step of determining a compensation dose for ion implantation compensation in a target area based on the actual size offset, the first relationship, and the second relationship and performing ion implantation includes: Based on the target offset, the first relationship, and the second relationship, a compensation dose for ion implantation compensation in the target area is determined and ion implantation is performed.

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