Testing device and testing method for memory device

Abstract

A test device and a test method for a memory device are provided. The test device for a memory device includes: a first exclusive OR (XOR) gate outputting a first operation signal by performing an XOR operation between a clock signal and an output signal output from the memory device; an oscillator configured to: output an oscillation signal; and an output circuit configured to determine a period of the oscillating signal. The output circuit may be configured to count a number of rising edges of the oscillation signal while the first operation signal remains at a high level, and determine an access time of the memory device based on the counted number of rising edges and a period of the oscillation signal.

Description

[0001] This application is based on and claims the benefit of Korean Patent Application No. 10-2024-0033402 filed on March 8, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Example embodiments relate to a testing device and a testing method for a memory device. Background Art

[0003] Semiconductor memory devices are classified into volatile memory devices (such as static random access memory (SRAM) devices or dynamic random access memory (DRAM) devices) and non-volatile memory devices (such as flash memory devices, phase change random access memory (PRAM) devices, magnetic random access memory (MRAM) devices, resistive random access memory (RRAM) devices, or ferroelectric random access memory (FRAM) devices). Volatile memory devices lose their stored data when their power supply is cut off, while non-volatile memory devices retain their stored data even when their power supply is cut off.

[0004] In a memory device, defects may occur due to various factors. Various defects in a memory device, such as write defects in a memory cell, may occur probabilistically, and therefore, the memory device needs to be tested.

[0005] For example, there is an increasing demand for test devices and test methods for accurately measuring timing specifications including a read speed, access time, setup time, or hold time of a memory device to ensure normal operation of the memory device. Summary of the Invention

[0006] Example embodiments provide a test device for accurately measuring timing specifications of a memory device.

[0007] According to one or more example embodiments, a test device for a memory device includes: a first exclusive-OR (XOR) gate configured to output a first operation signal by performing an XOR operation between a clock signal and an output signal output from the memory device; an oscillator configured to output an oscillation signal; and an output circuit configured to determine a period of the oscillation signal. The output circuit may be configured to count the number of rising edges of the oscillation signal while the first operation signal remains at a high level, and to determine an access time of the memory device based on the counted number of rising edges and the period of the oscillation signal.

[0008] According to one or more example embodiments, a test method for a memory device includes: determining a period of an oscillation signal output from an oscillator; counting a number of rising edges of the oscillation signal that occur while a first operating signal is maintained at a high level, the first operating signal being a result of an exclusive OR (XOR) operation between a clock signal and an output signal output from the memory device; and determining an access time of the memory device based on the number of counted rising edges and the period of the oscillation signal.

[0009] According to one or more example embodiments, a test device for a memory device includes: an oscillator configured to output an oscillation signal; a first exclusive-OR (XOR) gate configured to perform an XOR operation between a clock signal and an output signal output from the memory device; a first chain circuit and a second chain circuit configured to output delayed clocks in which different delay times are applied to the clock signal; a second XOR gate configured to perform an XOR operation between the signal output from the first chain circuit and the signal output from the second chain circuit; and an output circuit configured to determine a period of the oscillation signal. The output circuit may be configured to determine an access time of the memory device based on the number of rising edges of the oscillation signal that occur when a first operation signal output from the first XOR gate remains at a high level and the period of the oscillation signal; and to determine a unit delay time based on the number of rising edges of the oscillation signal that occur when a second operation signal output from the second XOR gate remains at a high level. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0011] Figure 1 is a block diagram of a memory system according to one or more example embodiments.

[0012] Figure 2A is a circuit diagram of a memory system including a test device for measuring an access time of a memory device according to one or more example embodiments.

[0013] Figure 2B It shows Figure 2A 1 is a diagram of a configuration of a test device for determining an access time of a memory device.

[0014] Figure 3A is a circuit diagram of a memory system including a test apparatus according to one or more example embodiments, the test apparatus including a first chain circuit and a second chain circuit.

[0015] Figure 3Bis a diagram illustrating a configuration in which a control logic circuit controls a first chain circuit and a second circuit to output delayed clocks to which different delay times are applied, according to one or more example embodiments.

[0016] Figure 3C It shows Figure 3A A diagram of a configuration of a test apparatus for determining a unit delay time of a first chain circuit and a second chain circuit.

[0017] Figure 4A : is a circuit diagram showing a configuration in which a test apparatus outputs a third delayed clock and a fourth delayed clock to which different delay times are applied through a first chain circuit.

[0018] Figure 4B It shows that Figure 4A A diagram of a configuration of a test apparatus for determining a first threshold setup time through an output circuit when a third delayed clock is output through a first chain circuit.

[0019] Figure 4C It shows that Figure 4A A diagram of a configuration of a test apparatus for determining a second threshold setup time through an output circuit when a fourth delayed clock is output through a first chain circuit.

[0020] Figure 5A is a circuit diagram illustrating a configuration in which a test apparatus outputs a fifth delayed clock and a sixth delayed clock to which different delay times are applied through a first chain circuit according to one or more example embodiments.

[0021] Figure 5B It shows that Figure 5A A diagram of a configuration of a test apparatus for determining a first threshold hold time through an output circuit when a third delayed clock is output through a first chain circuit.

[0022] Figure 5C It shows that Figure 5A A diagram of a configuration of a test apparatus for determining a second threshold hold time through an output circuit when a fourth delayed clock is output through a first chain circuit.

[0023] Figure 6A is a circuit diagram illustrating a configuration of a first chain circuit according to one or more example embodiments.

[0024] Figure 6B It shows Figure 6A A circuit diagram of a configuration of a first chain circuit with a first internal multiplexer and a second internal multiplexer.

[0025] Figure 7 is a circuit diagram illustrating a memory system including a test apparatus further including a second multiplexer according to one or more example embodiments.

[0026] Figure 8 is a circuit diagram illustrating a memory system including a test apparatus further including a third multiplexer according to one or more example embodiments.

[0027] Figure 9 is a flowchart illustrating a test method for determining an access time of a memory device according to one or more example embodiments.

[0028] Figure 10 is a flowchart illustrating a method for determining unit delay times of a first chain circuit and a second chain circuit included in a test apparatus according to one or more example embodiments.

[0029] Figure 11 is a flowchart illustrating a testing method for determining a setup time of a memory device based on a unit delay time according to one or more example embodiments.

[0030] Figure 12 is a flowchart illustrating a testing method for determining a retention time of a memory device based on a unit delay time according to one or more example embodiments. DETAILED DESCRIPTION

[0031] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0032] Figure 1 is a block diagram illustrating a memory system according to one or more example embodiments.

[0033] Reference Figure 1 , a memory system 100 according to one or more example embodiments may include a test device 110 and a memory device 120 .

[0034] The memory system 100 may include a memory device 120 configured to store input data.

[0035] For example, the memory device 120 may store data input from the outside. In addition, the memory device 120 may output the stored data in response to a write request input from the outside.

[0036] The memory device 120 may include a non-volatile memory (such as, for example, but not limited to, flash memory, magnetic random access memory (RAM) (MRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), or resistive RAM (ReRAM), but example embodiments are not limited thereto). Examples of the memory device 120 may include, for example, but not limited to, dynamic random access memory (DRAM) (such as, for example, double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, or Rambus dynamic random access memory (RDRAM)).

[0037] Furthermore, the memory system 100 may include a test device 110 electrically connected to the memory device 120 .

[0038] For example, the test device 110 may transmit the clock signal CK and the input signal Din to the memory device 120. In addition, the test device 110 may obtain the output signal Dout output from the memory device 120.

[0039] The test device 110 may perform a test operation on the memory device 120 .

[0040] For example, the test device 110 may determine (or measure) a timing specification of the memory device 120 using at least a portion of the clock signal CK, the input signal Din, and the output signal Dout.

[0041] According to one or more example embodiments, the test device 110 may determine the access time of the memory device 120 based on a result of an exclusive OR (XOR) operation between the clock signal CK and the output signal Dout.

[0042] For example, the test device 110 may determine the access time of the memory device 120 by performing a logic AND operation on a result of an XOR operation between the clock signal CK and the output signal Dout, and an oscillation signal output from the oscillator.

[0043] For example, the access time may be understood as corresponding to the time taken for the memory device 120 to output the output signal Dout in response to the clock signal CK from the test device 110 in a state where the input signal Din is input to the memory device 120 .

[0044] For example, the access time may be understood as corresponding to the time from when the clock signal CK is input to the memory device 120 to when the output signal Dout is output from the memory device 120 in a state where the input signal Din is input to the memory device 120 .

[0045] For example, access time may be understood to correspond to the time it takes the memory device 120 to output data in response to an input command or to store data in response to a write command.

[0046] According to one or more example embodiments, the test device 110 may determine (or measure) at least a portion of a setup time and a hold time of the memory device 120 using the clock signal CK and the input signal Din.

[0047] For example, the test apparatus 110 may determine the unit delay time based on a result of an exclusive OR operation between delayed clocks generated by applying different delay times to the clock signal CK.

[0048] For example, the test apparatus 110 may determine the unit delay time by performing a logic AND operation on a result of an exclusive OR operation between delayed clocks generated by applying different delay times to the clock signal CK and an oscillation signal output from the oscillator.

[0049] Furthermore, the test device 110 may determine at least a portion of the setup time and the hold time of the memory device 120 based on the clock signal CK, the input signal Din, and the unit delay time.

[0050] For example, the test device 110 may determine the setup time and / or retention time of the memory device 120 based on an XOR operation result between the clock signal CK having a fixed delay time and the input signal Din and the unit delay time.

[0051] For example, the setup time of the memory device 120 may represent a minimum time during which the logic level of the input signal Din should be maintained before a rising edge or a falling edge of the clock signal CK applied to the memory device 120 .

[0052] For example, the setup time of the memory device 120 may represent a minimum amount of time required for the input signal Din to be determined to have a logic low level or a logic high level.

[0053] The retention time of the memory device 120 may represent a minimum amount of time during which the logic level of the input signal Din should be maintained after a rising edge or a falling edge of the clock signal CK applied to the memory device 120 .

[0054] For example, the retention time of the memory device 120 may represent a minimum time required to output the input signal Din.

[0055] Based on the above configuration, the test device 110 can measure the timing specification of the memory device 120 based on at least a portion of the input signal Din and the clock signal CK input to the memory device 120 and the output signal Dout output from the memory device 120 .

[0056] Therefore, the test device 110 may also be referred to as, for example, a built-in self-test (BIST) device, a design-for-test (DFT) device, etc.

[0057] Furthermore, referring to the above configuration, the test device 110 can measure the timing specification of the memory device 120 based on the oscillation signal output from the oscillator.

[0058] As a result, the memory system 100 (or the test apparatus 110 ) according to one or more example embodiments may accurately measure the timing specification of the memory device 120 .

[0059] Figure 2A is a circuit diagram of a memory system including a test device for measuring access time of a memory device according to one or more example embodiments, and Figure 2B It shows Figure 2A 1 is a diagram of a configuration of a test device for determining an access time of a memory device.

[0060] Reference Figure 2A and Figure 2B , a memory system 100A according to one or more example embodiments may include a test device 110A and a memory device 120 .

[0061] Figure 2A The memory system 100A shown in FIG. 1 can be understood as Figure 1 An example of a memory system 100 is shown in FIG.

[0062] Therefore, the same or substantially the same components may be denoted by the same reference numerals, and redundant descriptions are omitted to avoid repetition.

[0063] Reference Figure 2A The test device 110A according to one or more example embodiments may include an oscillator 220, a first XOR gate XOR1, and an output circuit 230. In addition, the test device 110A may further include an AND gate A electrically connected between the first XOR gate XOR1 and the oscillator 220 and the output circuit 230.

[0064] The test device 110A may include a first XOR gate XOR1 configured to perform an exclusive OR (XOR) operation between the clock signal CK and the output signal Dout output from the memory device 120 .

[0065] The output signal Dout may be understood as a data signal output by the memory device 120 in response to the input signal Din and the clock signal CK.

[0066] For example, the first XOR gate XOR1 may perform an XOR operation between the clock signal CK and the output signal Dout to output the first operation signal CS1 .

[0067] Reference Figure 2B For example, the first operating signal CS1 may have a waveform maintained at a high level (eg, “1”) during a period AT, which is from the time when a rising edge of the clock signal CK occurs to the time when a rising edge of the output signal Dout occurs.

[0068] Furthermore, the testing device 110A may include an oscillator 220 configured to output an oscillation signal OCS.

[0069] The oscillator 220 according to one or more example embodiments may output an oscillation signal OCS having a specified period. For example, the oscillator 220 may output an oscillation signal OCS having a rising edge occurring according to a specified period.

[0070] For example, the oscillator 220 may include a plurality of inverters connected in series. The oscillator 220 may be referred to as a ring oscillator. However, the type and configuration of the oscillator 220 are not limited to the above examples, and the oscillator 220 may be understood to have various types and configurations that can generate an oscillation signal OCS having a specific period.

[0071] Furthermore, the testing device 110A may include an output circuit 230 configured to determine a period of the oscillation signal OCS.

[0072] For example, the output circuit 230 may divide the oscillation signal OCS to determine the period of the oscillation signal OCS.

[0073] For example, the output circuit 230 may divide the frequency of the oscillation signal OCS to determine that the period of the oscillation signal OCS is 100 picoseconds (ps). For example, the output circuit 230 may be referred to as a frequency divider.

[0074] Furthermore, the output circuit 230 may count the number of rising edges of the first output signal OS1 during the period AT.

[0075] For example, the test device 110A may include an AND gate A configured to perform a logic AND operation between the first operating signal CS1 and the oscillation signal OCS.

[0076] For example, the AND gate A may output a first output signal OS1 , which is a result of an AND operation between the first operating signal CS1 and the oscillation signal OCS.

[0077] Reference Figure 2B When the first operating signal CS1 is maintained at a high level, the first output signal OS1 may have the same waveform as the waveform of the oscillation signal OCS. Although the output circuit 230 may divide the frequency of the oscillation signal OCS to determine the period of the oscillation signal OCS (e.g., 100 ps), for the sake of brevity, the frequency division of the oscillation signal OCS is omitted.

[0078] For example, the output circuit 230 may count the number of rising edges of the oscillation signal OCS (or the first output signal OS1 ) that occur while the first operating signal CS1 is maintained at a high level.

[0079] For example, output circuit 230 may be referred to as a counter configured to count the number of rising edges of its input signal.

[0080] Furthermore, the output circuit 230 may determine the access time of the memory device 120 based on the number of rising edges of the oscillation signal OCS counted while the first operating signal CS1 is maintained at a high level.

[0081] For example, the output circuit 230 may determine the access time of the memory device 120 based on the number of rising edges of the oscillation signal OCS counted while the first operating signal CS1 remains at a high level and the period of the oscillation signal OCS.

[0082] For example, refer to Figure 2B , the output circuit 230 may determine that five rising edges of the oscillation signal OCS occur when the first operating signal CS1 is maintained at a high level.

[0083] Furthermore, the output circuit 230 may determine the access time of the memory device 120 to be 500 ps based on five rising edges of the oscillation signal OCS occurring while the first operating signal CS1 remains at a high level and a period of the oscillation signal OCS being 100 ps.

[0084] For example, the output circuit 230 may determine that the time taken for the memory device 120 to output the output signal Dout in response to the rising edge of the clock signal CK in a state in which the input signal Din is input to the memory device 120 is 500 ps.

[0085] With reference to the above configuration, the test apparatus 110A according to one or more example embodiments may divide the frequency of the oscillation signal OCS to determine a period of the oscillation signal OCS.

[0086] Furthermore, the test device 110A may measure the access time of the memory device 120 using the determined period and the result of the exclusive OR operation between the clock signal CK and the output signal Dout.

[0087] As a result, the memory system 100A according to one or more example embodiments may improve the accuracy of an operation or process of measuring an access time of the memory device 120 .

[0088] Figure 3A is a circuit diagram of a memory system 100B including a test apparatus including a first chain circuit and a second chain circuit according to one or more example embodiments. Figure 3B is a diagram illustrating a configuration in which a control logic circuit controls a first chain circuit and a second circuit to output delayed clocks to which different delay times are applied, according to one or more example embodiments. Figure 3C It shows Figure 3A A diagram of a configuration of a test apparatus for determining a unit delay time of a first chain circuit and a second chain circuit. Figure 4A : is a circuit diagram showing a configuration in which a test apparatus outputs a third delayed clock and a fourth delayed clock to which different delay times are applied through a first chain circuit. Figure 4B It shows that Figure 4A A diagram of a configuration of a test apparatus for determining a first threshold setup time through an output circuit when a third delayed clock is output through a first chain circuit. Figure 4C It shows that Figure 4A A diagram of a configuration of a test apparatus for determining a second threshold setup time through an output circuit when a fourth delayed clock is output through a first chain circuit.

[0089] Reference Figures 3A to 3C as well as Figures 4A to 4C , a memory system 100B according to one or more example embodiments may include a test device 110B and a memory device 120 .

[0090] The test device 110B may include a first chain circuit 211 , a second chain circuit 212 , a control logic circuit 210 , a first multiplexer MUX1 , a second XOR gate XOR2 , an oscillator 220 , an AND gate A, and an output circuit 230 .

[0091] The test apparatus 110B according to one or more example embodiments may further include a clock generator 240 configured to generate a clock signal CK. The clock generator 240 may generate the clock signal CK having a specified frequency using a phase-locked loop (PLL) circuit and / or an oscillator circuit.

[0092] Figure 3A and Figure 4A The memory system 100B shown in FIG. 1 can be understood as Figure 1 An example of a memory system 100 is shown in FIG.

[0093] Therefore, the same or substantially the same components may be denoted by the same reference numerals, and redundant descriptions are omitted to avoid repetition.

[0094] According to one or more example embodiments, the test device 110B may include a first chain circuit 211 and a second chain circuit 212 each configured to receive a clock signal CK.

[0095] For example, the test device 110B may include a first chain circuit 211 configured to receive the clock signal CK and including a plurality of inverters. In addition, the test device 110B may include a second chain circuit 212 configured to receive the clock signal CK and including a plurality of inverters.

[0096] For example, the first chain circuit 211 and the second chain circuit 212 may be implemented with substantially the same configuration. For example, at least a portion of the plurality of inverters included in each of the first chain circuit 211 and the second chain circuit 212 may be connected in series.

[0097] Furthermore, the test device 110B may include a control logic circuit 210 electrically connected to the first chain circuit 211 and the second chain circuit 212 .

[0098] For example, the control logic circuit 210 may control at least a portion of the first chain circuit 211 and the second chain circuit 212 to output delayed clocks DS1 and DS2 obtained by applying different delay times to the clock signal CK.

[0099] According to one or more example embodiments, the control logic circuit 210 may control the first chain circuit 211 to output the first delayed clock DS1 to which a first delay time equal to a first integer multiple of the unit delay time is applied.

[0100] For example, the control logic circuit 210 may control the first chain circuit 211 to output the clock signal CK input to the first chain circuit 211 through an electrical path including at least a portion of a plurality of inverters included in the first chain circuit 211 .

[0101] The unit delay time may be understood to correspond to a delay time caused by one of a plurality of inverters.

[0102] Reference Figure 3B , the control logic circuit 210 may control the first chain multiplexer CM1 to output the clock signal CK input to the first chain circuit 211A as the first delayed clock DS1 through the 1st-4th path P14 including eight inverters connected in series.

[0103] For example, the control logic circuit 210 may control the first chain circuit 211A to output the first delayed clock DS1 obtained by applying a first delay time equal to 8 times the unit delay time to the clock signal CK through the first chain multiplexer CM1 .

[0104] Furthermore, the control logic circuit 210 may control the second chain circuit 212 to output the second delayed clock DS2 to which a second delay time equal to a second integer multiple of the unit delay time is applied.

[0105] For example, the control logic circuit 210 may control the second chain circuit 212 to output the clock signal CK input to the second chain circuit 212 through an electrical path including at least a portion of a plurality of inverters included in the second chain circuit 212 .

[0106] Reference Figure 3B , the control logic circuit 210 may control the second chain multiplexer CM2 to output the clock signal CK input to the second chain circuit 212A as the second delayed clock DS2 through the 2-1 path P21 including two inverters connected in series.

[0107] For example, the control logic circuit 210 may control the second chain circuit 212A to output the second delayed clock DS2 through the second chain multiplexer CM2 , where the second delayed clock DS2 is obtained by adding a delay time equal to twice the unit delay time to the clock signal CK.

[0108] Furthermore, the test device 110B may include a first multiplexer MUX1 electrically connected between the second chain circuit 212 and the memory device 120 .

[0109] For example, the first multiplexer MUX1 may selectively output one of the input signal Din and the second delayed clock DS2.

[0110] For example, the first multiplexer MUX1 may output the second delayed clock DS2 to the memory device 120 in response to the first selection signal SEL1 .

[0111] Furthermore, the test device 110B may include a second XOR gate XOR2 configured to perform an XOR operation between a signal output from the first chain circuit 211 and a signal output from the second chain circuit 212 .

[0112] For example, the test device 110B may include a second XOR gate XOR2 configured to perform an XOR operation between the signal output from the first chain circuit 211 and the signal output from the first multiplexer MUX1 .

[0113] According to one or more example embodiments, the second XOR gate XOR2 may perform an XOR operation between the first delayed clock DS1 and the second delayed clock DS2 .

[0114] For example, the second XOR gate XOR2 may output the second operation signal CS2 as a result of XORing the first delayed clock DS1 and the second delayed clock DS2.

[0115] For example, refer to Figure 3C The second XOR gate XOR2 can output the second operating signal CS2 having a waveform maintained at a high level (e.g., “1”) in a period TD, which is from the time when the rising edge of the second delayed clock DS2 occurs to the time when the rising edge of the first delayed clock DS1 occurs.

[0116] In addition, the output circuit 230 may count the number of rising edges of the second output signal OS2 during the period TD.

[0117] For example, the test device 110B may include an AND gate A configured to perform an AND operation between the second operating signal CS2 and the oscillation signal OCS. For example, the AND gate A may output the second output signal OS2 based on the result of the AND operation between the second operating signal CS2 and the oscillation signal OCS.

[0118] Reference Figure 3C , when the second operating signal CS2 is maintained at a high level, the second output signal OS2 may have the same waveform as that of the oscillation signal OCS.

[0119] The output circuit 230 may count the number of rising edges of the oscillation signal OCS that occur while the second operating signal CS2 is maintained at a high level.

[0120] In addition, the output circuit 230 may determine the unit delay time based on the number of rising edges of the oscillation signal OCS counted while the second operating signal CS2 is maintained at a high level.

[0121] For example, the output circuit 230 may determine a unit delay time corresponding to a delay time caused by a single inverter based on the number of rising edges of the oscillation signal OCS counted while the second operating signal CS2 remains at a high level and the period of the oscillation signal OCS.

[0122] For example, refer to Figure 3C , the output circuit 230 may determine that 12 rising edges of the oscillation signal OCS occur when the second operating signal CS2 is maintained at a high level.

[0123] Furthermore, the output circuit 230 may determine that the time difference TD between the first delayed clock DS1 and the second delayed clock DS2 is 1200 ps based on 12 rising edges of the oscillation signal OCS occurring when the second operating signal CS2 remains at a high level and a period of the oscillation signal OCS being 100 ps.

[0124] In addition, the output circuit 230 may determine the unit delay time based on a difference between the number of inverters included in an electrical path through which the first delayed clock DS1 is output and the number of inverters included in an electrical path through which the second delayed clock DS2 is output.

[0125] For example, the first delayed clock DS1 may be output via a 1-4 path P14 including eight inverters connected in series, and the second delayed clock DS2 may be output via a 2-1 path P21 including two inverters connected in series. When the first delayed clock DS1 and the second delayed clock DS2 have a delay time difference corresponding to six inverters therebetween, the output circuit 230 may determine that the unit delay time is 200 ps by dividing the time difference TD 1200 ps between the two delayed clocks DS1 and DS2 by 6.

[0126] For example, the output circuit 230 may determine that the unit delay time caused by a single inverter among the plurality of inverters included in each of the first chain circuit 211 and the second chain circuit 212 is 200 ps.

[0127] Referring to the above configuration, the test apparatus 110B according to one or more example embodiments may determine a unit delay time using a period of the oscillation signal OCS and a result of an exclusive OR operation between delayed clocks DS1 and DS2 generated by applying different delay times to the clock signal CK.

[0128] The unit delay time may be understood as a time corresponding to a delay time caused by a single inverter included in each of the first chain circuit 211 and the second chain circuit 212 .

[0129] Reference Figure 4A , the control logic circuit 210 can control the first multiplexer MUX1 to output the input signal Din to the memory device 120 .

[0130] Furthermore, the control logic circuit 210 according to one or more example embodiments may control the first chain circuit 211 to output the third delayed clock DS3 to which a third delay time equal to a third integer multiple of the unit delay time is applied.

[0131] For example, refer to Figure 4B , the control logic circuit 210 may control the first chain circuit 211 to output the third delayed clock DS3 generated by advancing the clock signal CK by a first time T1 equal to twice the unit delay time.

[0132] According to one or more example embodiments, the second XOR gate XOR2 may perform an XOR operation between the third delayed clock DS3 and the input signal Din. For example, the second XOR gate XOR2 may output a third operation signal CS3 as a result of XORing the third delayed clock DS3 and the input signal Din.

[0133] For example, the second XOR gate XOR2 may perform an XOR operation between the third delayed clock DS3 and the input signal Din based on the memory device 120 outputting the output signal Dout having a high level in response to the third delayed clock DS3.

[0134] Reference Figure 4B The second XOR gate XOR2 can output a third operation signal CS3, which has a waveform that remains at a high level (e.g., “1”) from the time when the rising edge of the input signal Din occurs to the time when the rising edge of the third delayed clock DS3 occurs.

[0135] In addition, the output circuit 230 may count the number of rising edges of the third output signal OS3 .

[0136] The AND gate A may output a third output signal OS3 based on a result of an AND operation between the third operating signal CS3 and the oscillation signal OCS.

[0137] Reference Figure 4B , when the third operating signal CS3 is maintained at a high level, the third output signal OS3 may have the same waveform as that of the oscillation signal OCS.

[0138] For example, the output circuit 230 may count the number of rising edges of the oscillation signal OCS (or the third output signal OS3 ) that occur while the third operating signal CS3 is maintained at a high level.

[0139] Furthermore, the output circuit 230 may determine the first threshold establishment time ST1 based on the number of rising edges of the oscillation signal OCS counted while the third operating signal CS3 maintains a high level and the period of the oscillation signal OCS.

[0140] For example, refer to Figure 4B , the output circuit 230 may determine that four rising edges of the oscillation signal OCS occur when the third operating signal CS3 is maintained at a high level.

[0141] Furthermore, the output circuit 230 may determine that the first threshold setup time ST1 is 400 ps based on four rising edges of the oscillation signal OCS occurring while the third operating signal CS3 is maintained at a high level and a period of the oscillation signal OCS being 100 ps.

[0142] In addition, the control logic circuit 210 can control the first chain circuit 211 to output the fourth delayed clock DS4 to which the fourth delay time equal to the fourth integer multiple of the unit delay time is applied based on the memory device 120 outputting the output signal Dout having a high level in response to the third delayed clock DS3.

[0143] For example, refer to Figure 4C, the control logic circuit 210 may control the first chain circuit 211 to output the fourth delayed clock DS4 generated by advancing the clock signal CK by a second time T2 equal to four times the unit delay time.

[0144] In addition, the second XOR gate XOR2 may perform an XOR operation between the fourth delayed clock DS4 and the input signal Din.

[0145] For example, the second XOR gate XOR2 may output the fourth operation signal CS4 as a result of XORing the fourth delayed clock DS4 and the input signal Din.

[0146] For example, refer to Figure 4C The second XOR gate XOR2 can output a fourth operation signal CS4, which has a waveform that remains at a high level (e.g., “1”) from the time when the rising edge of the input signal Din occurs to the time when the rising edge of the fourth delayed clock DS4 occurs.

[0147] In addition, the output circuit 230 may count the number of rising edges of the fourth output signal OS4 .

[0148] The AND gate A may output a fourth output signal OS4 based on a result of an AND operation between the fourth operating signal CS4 and the oscillation signal OCS.

[0149] Reference Figure 4C , when the fourth operating signal CS4 is maintained at a high level, the fourth output signal OS4 may have the same waveform as that of the oscillation signal OCS.

[0150] For example, the output circuit 230 may count the number of rising edges of the oscillation signal OCS (or the fourth output signal OS4 ) that occur while the fourth operating signal CS4 is maintained at a high level.

[0151] Furthermore, the output circuit 230 may determine the second threshold establishment time ST2 based on the number of rising edges of the oscillation signal OCS counted while the fourth operating signal CS4 is maintained at a high level and the period of the oscillation signal OCS.

[0152] For example, refer to Figure 4C , the output circuit 230 may determine that three rising edges of the oscillation signal OCS occur when the fourth operating signal CS4 is maintained at a high level.

[0153] Furthermore, the output circuit 230 may determine that the second threshold setup time ST2 is 300 ps based on three rising edges of the oscillation signal OCS occurring while the fourth operating signal CS4 remains at a high level and a period of the oscillation signal OCS being 100 ps.

[0154] Reference Figure 4B, the memory device 120 may output an output signal Dout having a high level (eg, “1”) in response to the input signal Din and the third delayed clock DS3. The input signal Din and the third delayed clock DS3 may be understood as being in a state that satisfies the setup time of the memory device 120.

[0155] Reference Figure 4C , the memory device 120 may output an output signal Dout having a low level (e.g., “0”) in response to the input signal Din and the fourth delayed clock DS4. The input signal Din and the fourth delayed clock DS4 may be understood as being in a setup time violation state that does not satisfy the setup time of the memory device 120.

[0156] Therefore, the test device 110B may determine that the setup time of the memory device 120 has a value between the first threshold setup time ST1 and the second threshold setup time ST2.

[0157] For example, the test device 110B (or the control logic circuit 210) may determine that the setup time of the memory device 120 has a value between the time difference between the rising edge of the third delayed clock DS3 and the rising edge of the input signal Din (corresponding to the first threshold setup time ST1) and the time difference between the rising edge of the fourth delayed clock DS4 and the rising edge of the input signal Din (corresponding to the second threshold setup time ST2).

[0158] Referring to the above configuration, the test device 110B may determine a unit delay time caused by the inverter included in each of the chain circuits 211 and 212 using a result of an exclusive OR operation between the delay clocks DS1 and DS2 to which different delay times are applied.

[0159] Furthermore, the test device 110B may determine the setup time of the memory device 120 based on the result of the exclusive OR operation between the input signal Din and the delayed clocks DS3 and DS4.

[0160] In an example embodiment, the test device 110B (or the control logic circuit 210 ) may apply different delay times to the input signal Din to generate a plurality of delayed input signals.

[0161] For example, the test device 110B may apply different delay times to the input signal Din, so that the rising edge of the input signal Din is delayed by different delay times.

[0162] Furthermore, the test device 110B may determine the setup time of the memory device 120 based on the result of the exclusive OR operation between each of the plurality of delayed input signals and the clock signal CK.

[0163] Therefore, the memory system 100B according to one or more example embodiments may improve the accuracy of an operation (or process) of measuring a setup time of the memory device 120 .

[0164] Figure 5A is a circuit diagram illustrating a configuration in which a test apparatus outputs a fifth delayed clock and a sixth delayed clock to which different delay times are applied through a first chain circuit according to one or more example embodiments. Figure 5B It shows that Figure 5A A diagram of a configuration of a test apparatus for determining a first threshold hold time through an output circuit when a third delayed clock is output through a first chain circuit. Figure 5C It shows that Figure 5A A diagram of a configuration of a test apparatus for determining a second threshold hold time through an output circuit when a fourth delayed clock is output through a first chain circuit.

[0165] Reference Figures 5A to 5C , a memory system 100B according to one or more example embodiments may include a test device 110B and a memory device 120 .

[0166] Will understand, Figure 5A The memory system 100B shown in FIG. Figure 3A and Figure 4A The memory system 100B shown in FIG. 1 has substantially the same configuration.

[0167] Therefore, the same or substantially the same components may be denoted by the same reference numerals, and redundant descriptions are omitted to avoid repetition.

[0168] Reference Figure 5A , the control logic circuit 210 can control the first multiplexer MUX1 to output the input signal Din to the memory device 120 .

[0169] Furthermore, the control logic circuit 210 according to one or more example embodiments may control the first chain circuit 211 to output the fifth delayed clock DS5 to which a fifth delay time equal to a fifth integer multiple of the unit delay time is applied.

[0170] For example, refer to Figure 5B , the control logic circuit 210 may control the first chain circuit 211 to output the fifth delayed clock DS5 obtained by delaying the clock signal CK by a first time T1 equal to twice the unit delay time.

[0171] According to one or more example embodiments, the second XOR gate XOR2 may perform an XOR operation between the fifth delayed clock DS5 and the input signal Din. For example, the second XOR gate XOR2 may output a fifth operation signal CS5 as a result of XORing the fifth delayed clock DS5 and the input signal Din.

[0172] For example, the second XOR gate XOR2 may perform an XOR operation between the fifth delayed clock DS5 and the input signal Din based on the memory device 120 outputting the output signal Dout having a high level in response to the fifth delayed clock DS5.

[0173] Reference Figure 5B The second XOR gate XOR2 can output a fifth operation signal CS5 having a waveform maintained at a high level (eg, “1”) from the time when the rising edge of the fifth delayed clock DS5 occurs to the time when the falling edge of the input signal Din occurs.

[0174] In addition, the output circuit 230 may count the number of rising edges of the fifth output signal OS5 .

[0175] The AND gate A may output a fifth output signal OS5 based on a result of an AND operation between the fifth operating signal CS5 and the oscillation signal OCS.

[0176] Reference Figure 5B , when the fifth operating signal CS5 is maintained at a high level, the fifth output signal OS5 may have the same waveform as that of the oscillation signal OCS.

[0177] For example, the output circuit 230 may count the number of rising edges of the oscillation signal OCS (or the fifth output signal OS5 ) that occur while the fifth operating signal CS5 is maintained at a high level.

[0178] In addition, the output circuit 230 may determine the first threshold maintaining time HT1 based on the number of rising edges of the oscillation signal OCS counted while the fifth operating signal CS5 is maintained at a high level and the period of the oscillation signal OCS.

[0179] For example, refer to Figure 5B , the output circuit 230 may determine that three rising edges of the oscillation signal OCS occur when the fifth operating signal CS5 is maintained at a high level.

[0180] Furthermore, the output circuit 230 may determine that the first threshold holding time HT1 is 300 ps based on three rising edges of the oscillation signal OCS occurring when the fifth operating signal CS5 is maintained at a high level and a period of the oscillation signal OCS being 100 ps.

[0181] In addition, the control logic circuit 210 can control the first chain circuit 211 to output the sixth delayed clock DS6 to which the sixth delay time equal to the sixth integer multiple of the unit delay time is applied based on the memory device 120 outputting the output signal Dout having a high level in response to the fifth delayed clock DS5.

[0182] For example, refer to Figure 5C, the control logic circuit 210 can control the first chain circuit 211 to output the sixth delayed clock DS6, which is obtained by delaying the clock signal CK by a second time T2 equal to four times the unit delay time.

[0183] In addition, the second XOR gate XOR2 may perform an XOR operation between the sixth delayed clock DS6 and the input signal Din.

[0184] For example, the second XOR gate XOR2 may output the sixth operation signal CS6 as a result of XORing the sixth delayed clock DS6 and the input signal Din.

[0185] For example, refer to Figure 5C The second XOR gate XOR2 can output a sixth operation signal CS6, which has a waveform that remains at a high level (e.g., “1”) from the time when the rising edge of the sixth delayed clock DS6 occurs to the time when the falling edge of the input signal Din occurs.

[0186] In addition, the output circuit 230 may count the number of rising edges of the sixth output signal OS6 .

[0187] The AND gate A may output a sixth output signal OS6 as a result of an AND operation between the sixth operation signal CS6 and the oscillation signal OCS.

[0188] Reference Figure 5C , when the sixth operating signal CS6 is maintained at a high level, the sixth output signal OS6 may have the same waveform as that of the oscillation signal OCS.

[0189] For example, the output circuit 230 may count the number of rising edges of the oscillation signal OCS (or the sixth output signal OS6 ) that occur while the sixth operating signal CS6 is maintained at a high level.

[0190] In addition, the output circuit 230 may determine the second threshold holding time HT2 based on the number of rising edges of the oscillation signal OCS counted while the sixth operating signal CS6 is maintained at a high level and the period of the oscillation signal OCS.

[0191] For example, refer to Figure 5C , the output circuit 230 may determine that two rising edges of the oscillation signal OCS occur when the sixth operating signal CS6 is maintained at a high level.

[0192] Furthermore, the output circuit 230 may determine that the second threshold holding time HT2 is 200 ps based on two rising edges of the oscillation signal OCS occurring when the sixth operating signal CS6 is maintained at a high level and a period of the oscillation signal OCS being 100 ps.

[0193] Reference Figure 5B, the memory device 120 may output an output signal Dout having a high level (eg, “1”) in response to the input signal Din and the fifth delayed clock DS5. It will be understood that the input signal Din and the fifth delayed clock DS5 are in a state that satisfies the retention time of the memory device 120.

[0194] Reference Figure 5C , the memory device 120 may output an output signal Dout having a low level (e.g., “0”) in response to the input signal Din and the sixth delayed clock DS6. It will be understood that the input signal Din and the sixth delayed clock DS6 are in a retention time violation state that does not satisfy the retention time of the memory device 120.

[0195] Therefore, the test device 110B may determine that the retention time of the memory device 120 has a value between the first threshold retention time HT1 and the second threshold retention time HT2.

[0196] For example, the test device 110B (or the control logic circuit 210) may determine that the retention time of the memory device 120 has a value between the time difference between the rising edge of the fifth delayed clock DS5 and the falling edge of the input signal Din (corresponding to the first threshold retention time HT1) and the time difference between the rising edge of the sixth delayed clock DS6 and the falling edge of the input signal Din (corresponding to the second threshold retention time HT2).

[0197] Referring to the above configuration, the test device 110B according to one or more example embodiments may determine the retention time of the memory device 120 based on a result of an exclusive OR operation between the input signal Din and the delayed clocks DS5 and DS6 .

[0198] According to one or more example embodiments, the test device 110B (or the control logic circuit 210 ) may apply different delay times to the input signal Din to generate a plurality of delayed input signals.

[0199] Furthermore, the test device 110B may determine the retention time of the memory device 120 based on a result of an exclusive OR operation between each of the plurality of delayed input signals and the clock signal CK.

[0200] As a result, the memory system 100B according to one or more example embodiments may improve the accuracy of an operation (or process) of measuring the retention time of the memory device 120 .

[0201] Figure 6A is a circuit diagram illustrating a configuration of a first chain circuit according to one or more example embodiments. Figure 6B It shows Figure 6A A circuit diagram of a configuration of a first chain circuit with a first internal multiplexer and a second internal multiplexer.

[0202] Reference Figure 6A , the first chain circuit 211B according to one or more example embodiments may include delay elements C1 to C14 each including at least one inverter.

[0203] According to one or more example embodiments, each of the delay elements C1 to C14 may include at least two inverters connected in series. For example, the first delay element C1 may include two inverters connected in series. For example, the fourth delay element C4 may include eight inverters connected in series.

[0204] Furthermore, the first chain circuit 211B may include a plurality of internal multiplexers IM1 to IM20 electrically connected to the delay elements C1 to C14 .

[0205] For example, the first chain circuit 211B may include a first internal multiplexer IM1 electrically connected to the first delay element C1 and the second delay element C2. In addition, the first chain circuit 211B may include a second internal multiplexer IM2 electrically connected to the first internal multiplexer IM1.

[0206] According to one or more example embodiments, the control logic circuit 210 may control the plurality of internal multiplexers IM1 to IM20 included in the first chain circuit 211B to control a delay time applied to the clock signal CK.

[0207] For example, the control logic circuit 210 may control the plurality of internal multiplexers IM1 to IM20 so that the clock signal CK is delayed and output by at least a portion of the plurality of delay elements C1 to C14 included in the first chain circuit 211B.

[0208] Reference Figure 6B , the first internal multiplexer IM1 may include a first input port IP1 , a second input port IP2 and a first output port OP1 .

[0209] The second internal multiplexer IM2 may include a third input port IP3, a fourth input port IP4, and a second output port OP2. The second internal multiplexer IM2 may receive a signal output from the first output port OP1 through the third input port IP3 and the fourth input port IP4.

[0210] According to one or more example embodiments, the first internal multiplexer IM1 and the second internal multiplexer IM2 may be implemented with substantially the same structure. In addition, the plurality of internal multiplexers IM1 to IM20 may be implemented with substantially the same structure.

[0211] For example, the electrical distance between the third input port IP3 and the second output port OP2 may be the same as or similar to the electrical distance between the first input port IP1 and the first output port OP1 .

[0212] Furthermore, the electrical distance between the fourth input port IP4 and the second output port OP2 may be the same as or similar to the electrical distance between the second input port IP2 and the first output port OP1 .

[0213] Furthermore, the control logic circuit 210 according to one or more example embodiments may control the first and second internal multiplexers IM1 and IM2 so that a signal input to the first internal multiplexer IM1 is output through paths having different electrical distances within the first and second internal multiplexers IM1 and IM2.

[0214] For example, the control logic circuit 210 may control the first internal multiplexer IM1 to output the signal input to the first input port IP1 through the first signal S1 while controlling the second internal multiplexer IM2 to output the signal input to the fourth input port IP4 through the second signal S2 .

[0215] For example, the control logic circuit 210 may control the second internal multiplexer IM2 to output the signal input to the third input port IP3 while controlling the first internal multiplexer IM1 to output the signal input to the second input port IP2 .

[0216] For example, the control logic circuit 210 may control electrically connected internal multiplexers (eg, IM1 and IM2 ) to output signals input to input ports that do not correspond to each other at the internal multiplexers (eg, IM1 and IM2 ).

[0217] Furthermore, the second chain circuit (eg, Figure 3A The second chain circuit 212 may have substantially the same structure as the first chain circuit 211B.

[0218] Referring to the above configuration, the control logic circuit 210 (or the memory system 100 ) according to one or more example embodiments may control electrically connected internal multiplexers so that a signal output from each of the delay elements C1 to C14 is output through a path having a different electrical distance.

[0219] Therefore, the memory system 100 according to one or more example embodiments may significantly reduce errors caused by mismatches between internal paths of each of the internal multiplexers IM1 to IM20 when controlling the delay of the clock signal CK through the chain circuits 211B and 212 .

[0220] For example, the memory system 100 according to one or more example embodiments may control the delay of the clock signal CK through the above configuration to improve the accuracy of an operation (or process) of measuring a timing specification of the memory device 120 .

[0221] Figure 7is a circuit diagram illustrating a memory system including a test apparatus further including a second multiplexer according to one or more example embodiments.

[0222] Reference Figure 7 A memory system 100C according to one or more example embodiments may include a test device 110C and a memory device 120. The test device 110C may include a first chain circuit 211, a second chain circuit 212, a control logic circuit 210, a first multiplexer MUX1, a second multiplexer MUX2, a first XOR gate XOR1, a second XOR gate XOR2, an oscillator 220, an AND gate A, and an output circuit 230.

[0223] Figure 7 The memory system 100C shown in FIG. 1 can be understood as Figure 1 Therefore, the same or substantially the same components may be denoted by the same reference numerals, and redundant descriptions are omitted to avoid repetition.

[0224] Reference Figure 7 , the test device 110C according to one or more example embodiments may include a second multiplexer MUX2 electrically connected to the first XOR gate XOR1 and the second XOR gate XOR2 .

[0225] For example, the test device 110C may include a second multiplexer MUX2 electrically connected between the first and second XOR gates XOR1 and XOR2 and the AND gate A.

[0226] The second multiplexer MUX2 according to one or more example embodiments may selectively output a signal output from the first XOR gate XOR1 and a signal output from the second XOR gate XOR2 in response to a second selection signal SEL2 .

[0227] According to one or more example embodiments, the control logic circuit 210 may control the second multiplexer MUX2 to selectively output the signal output from the first XOR gate XOR1 and the signal output from the second XOR gate XOR2 to the AND gate A through the second selection signal SEL2 .

[0228] For example, the control logic circuit 210 may transmit the signal output from the first XOR gate XOR1 to the AND gate A through the second multiplexer MUX2, so that the output circuit 230 determines the access time of the memory device 120 based on the signal output from the first XOR gate XOR1. For example, the output circuit 230 may count the number of rising edges of the signal output through the AND gate A while the signal output from the second multiplexer MUX2 remains at a high level.

[0229] For example, the control logic circuit 210 may send the signal output from the second XOR gate XOR2 to the AND gate A through the second multiplexer MUX2 so that the output circuit 230 determines the setup time and / or hold time of the memory device 120 based on the signal output from the second XOR gate XOR2.

[0230] With reference to the above configuration, the test device 110C according to one or more example embodiments may measure an access time of the memory device 120 , a setup time, and / or a retention time of the memory device 120 based on the second selection signal SEL2 .

[0231] For example, the test device 110C according to one or more example embodiments may determine the timing specifications (access time, setup time, and / or hold time) of the memory device 120 using a minimum circuit configuration.

[0232] Therefore, the memory system 100C can significantly reduce the configuration and / or area of ​​a circuit for measuring the timing specification of the memory device 120 .

[0233] Figure 8 is a circuit diagram illustrating a memory system including a test apparatus further including a third multiplexer according to one or more example embodiments.

[0234] Reference Figure 8 A memory system 100D according to one or more example embodiments may include a test device 110D and a memory device 120. Furthermore, the test device 110D may include a first chain circuit 211, a second chain circuit 212, a control logic circuit 210, a first multiplexer MUX1, a second multiplexer MUX2, a third multiplexer MUX3, a first XOR gate XOR1, a second XOR gate XOR2, an oscillator 220, an AND gate A, and an output circuit 230.

[0235] Figure 8 The memory system 100D shown in FIG. 1 can be understood as Figure 1 Therefore, the same or substantially the same components may be denoted by the same reference numerals, and redundant descriptions are omitted to avoid repetition.

[0236] Reference Figure 8 , the test device 110D according to one or more example embodiments may include a third multiplexer MUX3 electrically connected between the AND gate A and the output circuit 230 .

[0237] For example, the third multiplexer MUX3 may selectively output the first output signal OS1 and the first inversion signal IOS1 output from the AND gate A in response to the third selection signal SEL3.

[0238] The first inverted signal IOS1 may be understood as a signal obtained by inverting the first output signal OS1 through an inverter.

[0239] The control logic circuit 210 according to one or more example embodiments may control the third multiplexer MUX3 to selectively output the first output signal OS1 and the first inverted signal IOS1 to the output circuit 230 through the third selection signal SEL3 .

[0240] For example, the control logic circuit 210 may control the third multiplexer MUX3 to alternately output the first output signal OS1 and the first inverted signal IOS1 to the output circuit 230 through the third selection signal SEL3 .

[0241] In addition, the output circuit 230 may count the number of rising edges of the first average signal corresponding to the average value of the first output signal OS1 and the first inversion signal IOS1 output through the third multiplexer MUX3 .

[0242] With reference to the above configuration, the test device 110D (or the output circuit 230 ) according to one or more example embodiments may count the number of rising edges based on a signal corresponding to an average value of a signal output from the AND gate A and a signal obtained by inverting the output signal.

[0243] Furthermore, output circuit 230 may determine the timing specification of memory device 120 based on the number of counted rising edges.

[0244] Therefore, the memory system 100D according to one or more example embodiments may significantly reduce the influence of errors occurring in a time domain adjacent to an edge of the first output signal OS1 due to internal components of the test device 110D.

[0245] Figure 9 is a flowchart illustrating a test method for determining an access time of a memory device according to one or more example embodiments.

[0246] Reference Figure 9 , the test device 110 (or the memory system 100 ) according to one or more example embodiments may determine the access time of the memory device 120 based on a result of an exclusive OR operation between the clock signal CK and the output signal Dout.

[0247] The output signal Dout may be referred to as a data signal output from the memory device 120 in response to the input signal Din and the clock signal CK input to the memory device 120 .

[0248] In operation S10 , the test apparatus 110 according to one or more example embodiments may determine a period of the oscillation signal OCS.

[0249] For example, the test device 110 (or the output circuit 230 ) may determine the period of the oscillation signal OCS by dividing the frequency of the oscillation signal OCS output from the oscillator 220 .

[0250] In operation S20 , the test apparatus 110 according to one or more example embodiments may count the number of rising edges of the oscillation signal OCS that occur while the first operating signal CS1 is maintained at a high level.

[0251] The test device 110 may output a first operation signal CS1 as a result of an exclusive OR operation of the clock signal CK and the output signal Dout.

[0252] In addition, the testing device 110 may perform an AND operation on the first operating signal CS1 and the oscillation signal OCS.

[0253] Furthermore, the test device 110 (or the output circuit 230 ) may count the number of rising edges of the first output signal OS1 output as a result of the AND operation of the first operating signal CS1 and the oscillation signal OCS.

[0254] In operation S30 , the test device 110 according to one or more example embodiments may determine an access time of the memory device 120 .

[0255] For example, the test device 110 may determine the access time of the memory device 120 based on the number of rising edges of the oscillation signal OCS counted while the first operating signal CS1 remains at a high level and the period of the oscillation signal OCS.

[0256] For example, the test device 110 may determine that the access time of the memory device 120 is 500 ps based on five rising edges of the oscillation signal OCS occurring while the first operating signal CS1 remains at a high level and a period of the oscillation signal OCS being 100 ps.

[0257] The access time may be understood as corresponding to the time taken for the memory device 120 to output the output signal Dout in response to the clock signal CK in a state where the input signal Din is input to the memory device 120 .

[0258] For example, in a state where the input signal Din is input to the memory device 120 , the output circuit 230 may determine that the time taken for the memory device 120 to output the rising edge of the output signal Dout in response to the rising edge of the clock signal is 500 ps.

[0259] Referring to the above configuration, the test apparatus 110 according to one or more example embodiments may determine the period of the oscillation signal OCS by dividing the frequency of the oscillation signal OCS.

[0260] Furthermore, the test device 110 may determine the access time of the memory device 120 using the determined period and the result of the exclusive OR operation between the clock signal CK and the output signal Dout.

[0261] As a result, the memory system 100 according to one or more example embodiments may improve the accuracy of an operation (or process) of measuring an access time of the memory device 120 .

[0262] Figure 10 is a flowchart illustrating a method for determining unit delay times of a first chain circuit and a second chain circuit included in a test apparatus according to one or more example embodiments.

[0263] Reference Figure 10 , the test apparatus 110 according to one or more example embodiments may determine a unit delay time caused by one of a plurality of inverters included in each of the first chain circuit 211 and the second chain circuit 212 .

[0264] In operation S10 , the test apparatus 110 according to one or more example embodiments may determine a period of the oscillation signal OCS.

[0265] For example, the test device 110 (or the output circuit 230 ) may determine the period of the oscillation signal OCS by dividing the frequency of the oscillation signal OCS output from the oscillator 220 .

[0266] In operation S21 , the test apparatus 110 according to one or more example embodiments may generate a first delayed clock DS1 and a second delayed clock DS2 .

[0267] For example, the test apparatus 110 may generate the first delayed clock DS1 and the second delayed clock DS2 obtained by applying different delay times to the clock signal CK by controlling the first chain circuit 211 and the second chain circuit 212 .

[0268] For example, the test device 110 may generate a first delayed clock DS1 to which a first delay time equal to a first integer multiple of the unit delay time is applied by controlling the first chain circuit 211. In addition, the test device 110 may generate a second delayed clock DS2 to which a second delay time equal to a second integer multiple of the unit delay time is applied by controlling the second chain circuit 212. The second integer may be smaller than the first integer, but example embodiments are not limited thereto.

[0269] In operation S31 , the test apparatus 110 according to one or more example embodiments may count the number of rising edges of the oscillation signal OCS that occur while the second operating signal CS2 is maintained at a high level.

[0270] The test apparatus 110 according to one or more example embodiments may output the second operation signal CS2 as a result of an exclusive OR operation on the first delayed clock DS1 and the second delayed clock DS2 .

[0271] In addition, the testing device 110 may perform an AND operation on the second operating signal CS2 and the oscillation signal OCS.

[0272] Furthermore, the test device 110 (or the output circuit 230 ) may count the number of rising edges of the second output signal OS2 output as a result of an AND operation of the second operating signal CS2 and the oscillation signal OCS.

[0273] Furthermore, in operation S41, the test device 110 may determine the unit delay time of the first chain circuit 211 and the second chain circuit 212. The test device 110 may determine that the time difference TD between the first delayed clock DS1 and the second delayed clock DS2 is 1200 ps based on 12 rising edges of the oscillation signal OCS occurring when the second operating signal CS2 is maintained at a high level and a period of the oscillation signal OCS of 100 ps.

[0274] In addition, the test device 110 may determine the unit delay time based on a difference between the number of inverters included in an electrical path through which the first delayed clock DS1 is output and the number of inverters included in an electrical path through which the second delayed clock DS2 is output.

[0275] For example, when two delayed clocks DS1 and DS2 have a delay time difference corresponding to six inverters therebetween, the test apparatus 110 may determine the unit delay time as 200 ps by dividing the time difference TD 1200 ps between the first delayed clock DS1 and the second delayed clock DS2 by 6.

[0276] For example, the test apparatus 110 may determine that a unit delay time caused by one of the plurality of inverters included in each of the first chain circuit 211 and the second chain circuit 212 is 200 ps.

[0277] Referring to the above configuration, the test apparatus 110 according to one or more example embodiments may determine a unit delay time using a result of an exclusive OR operation between delayed clocks DS1 and DS2 obtained by applying different delay times to the clock signal CK and a period of the oscillation signal OCS.

[0278] As a result, the memory system 100 according to one or more example embodiments may accurately determine a unit delay time of a circuit that applies a delay to the clock signal CK to determine a timing specification of the memory device 120 .

[0279] Figure 11is a flowchart illustrating a testing method for determining a setup time of a memory device based on a unit delay time according to one or more example embodiments.

[0280] Reference Figure 10 and Figure 11 , the test device 110 according to one or more example embodiments may determine the setup time of the memory device 120 based on a result of an exclusive OR operation between the delayed clock and the input signal.

[0281] In operation S51 , the test device 110 according to one or more example embodiments may input an input signal Din having a waveform transitioning from a low level to a high level to the memory device 120 .

[0282] For example, the test device 110 may set the value of the output signal Dout output from the memory device 120 to “0” and then input the input signal Din having a waveform transitioning from a low level to a high level to the memory device 120 .

[0283] In operation S61 , the test apparatus 110 according to one or more example embodiments may reduce the delay time of the clock signal CK by an integer multiple of the unit delay time.

[0284] For example, the test apparatus 110 may control the first chain circuit 211 to output a delayed clock to which a delay time equal to an integral multiple of the unit delay time is applied, to the clock signal CK.

[0285] For example, the test device 110 may control the first chain circuit 211 to output the third delayed clock DS3 having a third delay time equal to a third integer multiple of the unit delay time to the clock signal CK. For example, the third integer may be "2", but example embodiments are not limited thereto.

[0286] In operation S71 , the test apparatus 110 according to one or more example embodiments may determine whether the output signal Dout is output at a high level.

[0287] For example, the test device 110 may determine whether the memory device 120 outputs the output signal Dout having a high level in response to the input signal Din and the rising edge of the third delayed clock DS3 .

[0288] For example, when the memory device 120 outputs an output signal Dout having a high level (e.g., “1”) in response to the input signal Din and the third delayed clock DS3, the input signal Din and the third delayed clock DS3 may be understood as being in a state satisfying a setup time of the memory device 120.

[0289] In addition, the test device 110 may output a fourth delayed clock DS4 to which a fourth delay time equal to a fourth integer multiple of the unit delay time is applied, to the clock signal CK, based on the memory device 120 outputting the output signal Dout having a high level in response to the rising edge of the third delayed clock DS3. For example, the fourth integer may be "4", but example embodiments are not limited thereto.

[0290] In addition, for example, when the memory device 120 outputs an output signal Dout having a low level (e.g., “0”) in response to the input signal Din and the fourth delayed clock DS4, the input signal Din and the fourth delayed clock DS4 can be understood as being in a setup time violation state that does not satisfy the setup time of the memory device 120.

[0291] In operation S81, the test device 110 may determine the first threshold establishment time ST1 by counting the number of rising edges of the oscillation signal OCS that occur when the third operating signal CS3 is maintained at a high level. The third operating signal CS3 may be referred to as a result of an exclusive OR operation between the third delayed clock DS3 and the input signal Din.

[0292] In operation S91, the test device 110 can determine the second threshold establishment time ST2 by counting the number of rising edges of the oscillation signal OCS that occur when the fourth operating signal CS4 is maintained at a high level. The fourth operating signal CS4 can be referred to as the result of an exclusive OR operation between the fourth delayed clock DS4 and the input signal Din.

[0293] According to one or more example embodiments, the setup time of the memory device 120 may have a value between the first threshold setup time ST1 and the second threshold setup time ST2. For example, the test device 110 may determine that the setup time of the memory device 120 has a value between the first threshold setup time ST1 and the second threshold setup time ST2.

[0294] Referring to the above configuration, the test device 110 may determine the setup time of the memory device 120 based on the result of the exclusive OR operation between the input signal Din and the delayed clocks DS3 and DS4.

[0295] As a result, the memory system 100 according to one or more example embodiments may improve the accuracy of an operation (or process) of measuring a setup time of the memory device 120 .

[0296] Figure 12 is a flowchart illustrating a testing method for determining a retention time of a memory device based on a unit delay time according to one or more example embodiments.

[0297] Reference Figure 10 and Figure 12, the test device 110 according to one or more example embodiments may determine the retention time of the memory device 120 based on a result of an exclusive OR operation between the delayed clock and the input signal.

[0298] In operation S52 , the test device 110 according to one or more example embodiments may input an input signal Din having a waveform transitioning from a high level to a low level to the memory device 120 .

[0299] For example, the test device 110 may set the value of the output signal Dout output from the memory device 120 to “0” and then input the input signal Din having a waveform transitioning from a high level to a low level to the memory device 120 .

[0300] In operation S62 , the test apparatus 110 according to one or more example embodiments may increase the delay time of the clock signal CK by an integer multiple of the unit delay time.

[0301] For example, the test apparatus 110 may control the first chain circuit 211 to output a delayed clock to which a delay time equal to an integral multiple of the unit delay time is applied, to the clock signal CK.

[0302] For example, the test device 110 may control the first chain circuit 211 to output the fifth delayed clock DS5 to which a fifth delay time equal to a fifth integer multiple of the unit delay time is applied, to the clock signal CK.

[0303] In operation S72 , the test apparatus 110 according to one or more example embodiments may determine whether the output signal Dout is output at a high level.

[0304] For example, the test device 110 may determine whether the memory device 120 outputs the output signal Dout having a high level in response to the input signal Din and the rising edge of the fifth delayed clock DS5 .

[0305] For example, when the memory device 120 outputs an output signal Dout having a high level (e.g., “1”) in response to the input signal Din and the fifth delayed clock DS5, the input signal Din and the fifth delayed clock DS5 may be understood as being in a state satisfying the retention time of the memory device 120.

[0306] In addition, the test device 110 can output the sixth delayed clock DS6 to which the sixth delay time equal to the sixth integer multiple of the unit delay time is applied to the clock signal CK based on the memory device 120 outputting the output signal Dout having a high level in response to the rising edge of the fifth delayed clock DS5.

[0307] In addition, for example, when the memory device 120 outputs an output signal Dout having a low level (e.g., “0”) in response to the input signal Din and the sixth delayed clock DS6, the input signal Din and the sixth delayed clock DS6 can be understood as being in a retention time violation state that does not satisfy the retention time of the memory device 120.

[0308] In operation S82, the test device 110 may determine the first threshold holding time HT1 by counting the number of rising edges of the oscillation signal OCS that occur when the fifth operating signal CS5 is maintained at a high level. The fifth operating signal CS5 may be referred to as a result of an exclusive OR operation between the fifth delayed clock DS5 and the input signal Din.

[0309] In operation S92, the test device 110 may determine the second threshold holding time HT2 by counting the number of rising edges of the oscillation signal OCS that occur when the sixth operating signal CS6 is maintained at a high level. The sixth operating signal CS6 may be referred to as a result of an exclusive OR operation between the sixth delayed clock DS6 and the input signal Din.

[0310] According to one or more example embodiments, the retention time of the memory device 120 may have a value between the first retention time threshold HT1 and the second retention time threshold HT2. For example, the test device 110 may determine that the retention time of the memory device 120 has a value between the first retention time threshold HT1 and the second retention time threshold HT2.

[0311] Referring to the above configuration, the test device 110 may determine the retention time of the memory device 120 based on the result of the exclusive OR operation between the input signal Din and the delayed clocks DS5 and DS6.

[0312] As a result, the memory system 100 according to one or more example embodiments may improve the accuracy of an operation (or process) of measuring the retention time of the memory device 120 .

[0313] As described above, the test device 110 according to one or more example embodiments may measure the access time of the memory device 120 using the period of the oscillation signal OCS and a result of an exclusive OR operation between the clock signal CK and the output signal Dout.

[0314] As a result, the memory system 100 according to one or more example embodiments may improve the accuracy of an operation (or process) of measuring an access time of the memory device 120 .

[0315] Furthermore, the test apparatus 110 according to one or more example embodiments may determine a unit delay time caused by each inverter included in each of the chain circuits 211 and 212 using a result of an exclusive OR operation between the delay clocks DS1 and DS2 to which different delay times are applied.

[0316] Furthermore, the test device 110 may determine the setup time of the memory device 120 based on a result of an exclusive OR operation between the input signal Din and the delayed clocks DS3 and DS4.

[0317] As a result, the memory system 100 according to one or more example embodiments may improve the accuracy of an operation (or process) of measuring a setup time of the memory device 120 .

[0318] Furthermore, the test device 110 according to one or more example embodiments may determine the retention time of the memory device 120 based on a result of an exclusive OR operation between the input signal Din and the delayed clocks DS5 and DS6 .

[0319] As a result, the memory system 100 according to one or more example embodiments may improve the accuracy of an operation (or process) of measuring the retention time of the memory device 120 .

[0320] As described above, a test apparatus according to example embodiments may improve the accuracy of an operation of measuring a timing specification of a memory device.

[0321] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A test device for a memory device, the test device comprising: a first XOR gate configured to output a first operation signal by performing an XOR operation between the clock signal and an output signal output from the memory device; The oscillator is configured to: output an oscillation signal; as well as The output circuit is configured to: determine the period of the oscillation signal, The output circuit is configured as follows: When the first operation signal is maintained at a high level, counting the number of rising edges of the oscillation signal; and An access time of the memory device is determined based on the number of counted rising edges and the period of the oscillation signal.

2. The testing device according to claim 1, further comprising: a first chain circuit and a second chain circuit, each configured to receive a clock signal and each including a plurality of inverters; as well as A control logic circuit is connected to the first chain circuit and the second chain circuit, The control logic circuit is configured to control the first chain circuit and the second chain circuit so that the first chain circuit and the second chain circuit output delayed clocks to which delay times equal to different integer multiples of the unit delay time are applied respectively, and The unit delay time corresponds to the time delayed by one of the plurality of inverters.

3. The testing device according to claim 2, further comprising: a first multiplexer configured to output any one of a signal output from the second chain circuit and an input signal input to the memory device based on a first selection signal; as well as a second XOR gate configured to output a second operation signal by performing an XOR operation between the signal output from the first multiplexer and the signal output from the first chain circuit; The control logic circuit is further configured as follows: controlling the first chain circuit to output a first delayed clock to which a first delay time equal to a first integer multiple of the unit delay time is applied; and controlling the second chain circuit and the first multiplexer to output a second delayed clock to which a second delay time equal to a second integer multiple of the unit delay time is applied, and The output circuit is further configured to determine the unit delay time by counting the number of rising edges of the oscillation signal that occur when the second operation signal remains at a high level.

4. The testing device according to claim 3, wherein: When the input signal changes from a low level to a high level, the control logic circuit is further configured to: controlling the first chain circuit to output a third delayed clock to which a third delay time equal to a third integer multiple of the unit delay time is applied; and controlling the first chain circuit to output a fourth delayed clock to which a fourth delay time equal to a fourth integer multiple of the unit delay time is applied based on the output signal having a high level being output from the memory device in response to a rising edge of the third delayed clock, wherein the output signal having a low level is output in response to the fourth delay time; and The output circuit is further configured to determine a setup time of the memory device based on the third delayed clock and the fourth delayed clock.

5. The testing device according to claim 4, wherein: The output circuit is configured to determine the settling time: determining a first threshold establishment time by counting the number of rising edges of the oscillation signal occurring while a third operating signal is maintained at a high level, the third operating signal being a result of an exclusive OR operation between a third delayed clock and the input signal; determining the second threshold setup time by counting the number of rising edges of the oscillation signal occurring while a fourth operating signal is maintained at a high level, the fourth operating signal being a result of an exclusive OR operation between a fourth delayed clock and the input signal; and The settling time is determined to have a value between a first threshold settling time and a second threshold settling time.

6. The testing device according to claim 3, wherein: When the input signal changes from high level to low level, the control logic circuit is configured as follows: controlling the first chain circuit to output a fifth delayed clock to which a fifth delay time equal to a fifth integral multiple of the unit delay time is applied; and controlling the first chain circuit to output a sixth delayed clock to which a sixth delay time equal to a sixth integer multiple of the unit delay time is applied based on the output signal having a high level being output from the memory device in response to the fifth delayed clock, wherein the output signal having a low level is output in response to the sixth delayed clock; and The output circuit is further configured to determine a retention time of the memory device based on the fifth delayed clock and the sixth delayed clock.

7. The testing device according to claim 6, wherein: The output circuit is configured to: determining a first threshold holding time by counting the number of rising edges of the oscillation signal occurring while a fifth operating signal is maintained at a high level, the fifth operating signal being a result of an exclusive OR operation between a fifth delayed clock and the input signal; determining the second threshold holding time by counting the number of rising edges of the oscillation signal occurring while a sixth operation signal is maintained at a high level, the sixth operation signal being a result of an exclusive OR operation between a sixth delayed clock and the input signal, and The hold time is determined to have a value between a first threshold hold time and a second threshold hold time.

8. The testing device according to claim 3, further comprising: a second multiplexer electrically connected to the first XOR gate and the second XOR gate; as well as an AND gate electrically connected between the second multiplexer and the oscillator and output circuit, and configured to receive the signal output from the second multiplexer and the oscillation signal, The output circuit is further configured to count the number of rising edges of the signal output through the AND gate when the signal output from the second multiplexer remains at a high level.

9. The testing device according to claim 8, further comprising: a third multiplexer configured to receive the first output signal output from the AND gate and a first inverted version of the first output signal; The output circuit is configured to count the number of rising edges of a first average signal corresponding to an average of the first output signal output from the third multiplexer and the first inverted version.

10. The testing device according to any one of claims 2 to 9, wherein: The first chain circuit includes: a first internal multiplexer electrically connected to at least a portion of the plurality of inverters and comprising a first input port, a second input port, and a first output port; and The second internal multiplexer includes a third input port, a fourth input port, and a second output port, wherein the signal output from the first output port is received through the third input port and the fourth input port. The electrical distance between the third input port and the second output port is the same as the electrical distance between the first input port and the first output port. wherein the electrical distance between the fourth input port and the second output port is the same as the electrical distance between the second input port and the first output port, and The control logic circuit is configured to control the first internal multiplexer and the second internal multiplexer to output a signal input to the first internal multiplexer to the second output port through paths having different electrical distances in the first internal multiplexer and the second internal multiplexer.

11. A testing method for a memory device, the testing method comprising: determining a period of an oscillation signal output from the oscillator; counting the number of rising edges of the oscillation signal that occur while a first operating signal is maintained at a high level, the first operating signal being a result of an exclusive OR operation between the clock signal and an output signal output from the memory device; and An access time of the memory device is determined based on the number of counted rising edges and the period of the oscillation signal.

12. The testing method according to claim 11, further comprising: generating a first delayed clock and a second delayed clock, the first delayed clock being obtained by applying a first delay time equal to a first integer multiple of the unit delay time to the clock signal, and the second delayed clock being obtained by applying a second delay time equal to a second integer multiple of the unit delay time to the clock signal; counting the number of rising edges of the oscillation signal that occur while a second operation signal is maintained at a high level, the second operation signal being a result of an exclusive OR operation between the first delayed clock and the second delayed clock; and The unit delay time is determined based on the number of rising edges of the oscillation signal counted while the second operation signal is maintained at a high level and the period of the oscillation signal.

13. The testing method according to claim 12, further comprising: inputting an input signal transitioning from a low level to a high level into the memory device; inputting a third delayed clock to which a third delay time equal to a third integral multiple of the unit delay time is applied to the memory device; based on the output signal having a high level being output from the memory device in response to a rising edge of the third delayed clock, inputting a fourth delayed clock to which a fourth delay time equal to a fourth integer multiple of the unit delay time is applied to the memory device, wherein the output signal having a low level is output in response to the fourth delayed clock; as well as A setup time of the memory device is determined based on the third delayed clock and the fourth delayed clock.

14. The testing method according to claim 13, wherein: The steps to determine the build time include: determining a first threshold establishment time by counting the number of rising edges of the oscillation signal occurring while a third operating signal is maintained at a high level, the third operating signal being a result of an exclusive OR operation between a third delayed clock and the input signal; determining a second threshold setup time by counting the number of rising edges of the oscillation signal occurring while a fourth operating signal is maintained at a high level, the fourth operating signal being a result of an exclusive OR operation between a fourth delayed clock and the input signal; and The settling time is determined to have a value between a first threshold settling time and a second threshold settling time.

15. The testing method according to claim 13, further comprising: inputting an input signal transitioning from a high level to a low level into the memory device; inputting a fifth delayed clock to which a fifth delay time equal to a fifth integral multiple of the unit delay time is applied to the memory device; based on the output signal having a high level being output from the memory device in response to the fifth delayed clock, inputting a sixth delayed clock to which a sixth delay time equal to a sixth integral multiple of the unit delay time is applied to the memory device, wherein the output signal having a low level is output in response to the sixth delayed clock; and A retention time of the memory device is determined based on the fifth delayed clock and the sixth delayed clock.

16. A testing device for a memory device, the testing device comprising: The oscillator is configured to: output an oscillation signal; a first XOR gate configured to: perform an XOR operation between the clock signal and an output signal output from the memory device; The first chain circuit and the second chain circuit are configured to: output a delayed clock, where the delayed clock is obtained by respectively applying different delay times to the clock signal; a second XOR gate configured to: perform an XOR operation between a signal output from the first chain circuit and a signal output from the second chain circuit; and The output circuit is configured to: determine the period of the oscillation signal, The output circuit is configured as follows: determining an access time of the memory device based on the number of rising edges of the oscillation signal and the period of the oscillation signal that occur while the first operation signal output from the first XOR gate remains at a high level; and The unit delay time is determined based on the number of rising edges of the oscillation signal that occurs while the second operation signal output from the second XOR gate is maintained at a high level.

17. The testing device of claim 16, further comprising: A control logic circuit is connected to the first chain circuit and the second chain circuit, The control logic circuit is configured as follows: controlling the first chain circuit to output a first delayed clock to which a first delay time equal to a first integer multiple of the unit delay time is applied; and controlling the second chain circuit to output a second delayed clock to which a second delay time equal to a second integer multiple of the unit delay time is applied, and The second XOR gate is configured to output a second operation signal as a result of an XOR operation between the first delayed clock and the second delayed clock.

18. The testing device according to claim 17, wherein: When the input signal changes from low level to high level, the control logic circuit is configured as follows: controlling the first chain circuit to output a third delayed clock to which a third delay time equal to a third integer multiple of the unit delay time is applied; and controlling the first chain circuit to output a fourth delayed clock to which a fourth delay time equal to a fourth integer multiple of the unit delay time is applied, based on the output signal having a high level being output in response to the third delayed clock, wherein the output signal having a low level is output in response to the fourth delayed clock; and The output circuit is further configured to determine a setup time of the memory device based on the third delayed clock and the fourth delayed clock.

19. The testing device according to claim 18, wherein: When the input signal changes from high level to low level, the control logic circuit is configured as follows: controlling the first chain circuit to output a fifth delayed clock to which a fifth delay time equal to a fifth integral multiple of the unit delay time is applied; and controlling the first chain circuit to output a sixth delayed clock to which a sixth delay time equal to a sixth integer multiple of the unit delay time is applied based on the output signal having a high level being output in response to the fifth delayed clock, wherein the output signal having a low level is output in response to the sixth delayed clock; and The output circuit is further configured to determine a retention time of the memory device based on the fifth delayed clock and the sixth delayed clock.

20. The testing device of claim 16, further comprising: a second multiplexer electrically connected to the first XOR gate and the second XOR gate; and an AND gate electrically connected between the second multiplexer and the output circuit and configured to receive the signal output from the second multiplexer and the oscillation signal, The output circuit is further configured to count the number of rising edges of the signal output through the AND gate when the signal output from the second multiplexer remains at a high level.

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