Memory element including recessed gate structure with high k gate dielectric layer and method

Abstract

The present disclosure provides a memory device including a first high-k gate dielectric layer disposed in a semiconductor substrate. An upper surface of the first high-k gate dielectric layer is higher than an upper surface of the semiconductor substrate. The memory element also includes a first metal gate electrode layer disposed over the first high-k gate dielectric layer. A lower portion of the first metal gate electrode layer is surrounded by the first high-k gate dielectric layer, and a width of an upper portion of the first metal gate electrode layer is greater than a width of the lower portion of the first metal gate electrode layer. The memory element also includes a first dielectric portion disposed over the first metal gate electrode layer.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 596,957 (i.e., the priority date is "March 6, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a memory device and a method for manufacturing the same, and more particularly to a memory device including a recessed gate structure with a high-K gate dielectric layer and a method for manufacturing the same. Background Art

[0003] Due to its simple structure, dynamic random access memory (DRAM) can provide more memory cells per unit chip area than other types of memory, such as static random access memory (SRAM). DRAM is composed of multiple DRAM cells, each of which includes a capacitor for storing information and a transistor coupled to the capacitor to regulate when the capacitor is charged or discharged. During a read operation, a word line (WL) is asserted, turning on the transistor. The enabled transistor allows a sense amplifier to read the voltage across the capacitor via a bit line (BL). During a write operation, the data to be written is provided on the BL while the WL is asserted.

[0004] To meet the demand for greater memory capacity, the size of DRAM memory cells continues to shrink, significantly increasing the packing density of these DRAMs. However, the manufacturing and integration of memory cells involves many complex steps and operations. The integration of memory cells is becoming increasingly complex. The increasing complexity of memory cell manufacturing and integration can lead to defects. Therefore, there is a need to continuously improve the structure and manufacturing process of memory cells to address their defects and improve performance.

[0005] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0006] One embodiment of the present disclosure provides a memory element. The memory element includes a first high-k gate dielectric layer disposed in a semiconductor substrate. An upper surface of the first high-k gate dielectric layer is higher than an upper surface of the semiconductor substrate. The memory element also includes a first metal gate electrode layer disposed above the first high-k gate dielectric layer. A lower portion of the first metal gate electrode layer is surrounded by the first high-k gate dielectric layer, and a width of an upper portion of the first metal gate electrode layer is greater than a width of a lower portion of the first metal gate electrode layer. The memory element also includes a first dielectric portion disposed above the first metal gate electrode layer.

[0007] In one embodiment, the first metal gate electrode layer is in direct contact with the upper surface of the first high-k gate dielectric layer. In one embodiment, the first metal gate electrode layer is separated from the semiconductor substrate by the first high-k gate dielectric layer. In one embodiment, the first high-k gate dielectric layer is separated from the first dielectric portion by the first metal gate electrode layer. In one embodiment, the upper surface of the semiconductor substrate is higher than a lower surface of the lower portion of the first metal gate electrode layer. In one embodiment, an upper surface of an upper portion of the first metal gate electrode layer is higher than the upper surface of the first high-k gate dielectric layer.

[0008] In one embodiment, the width of the upper portion of the first metal gate electrode layer is substantially the same as a width of the first high-k gate dielectric layer. In one embodiment, the width of the upper portion of the first metal gate electrode layer is substantially the same as a width of the first dielectric portion. In one embodiment, in a cross-sectional view of the memory device, a sidewall of the first high-k gate dielectric layer is vertically aligned with a sidewall of the upper portion of the first metal gate electrode layer. In one embodiment, in a cross-sectional view of the memory device, the sidewall of the upper portion of the first metal gate electrode layer is vertically aligned with a sidewall of the first dielectric portion. In one embodiment, the first high-k gate dielectric layer and the first metal gate electrode layer form a recessed gate structure in the peripheral circuit region of the memory device.

[0009] In one embodiment, the memory device further comprises a second high-k gate dielectric layer disposed above the semiconductor substrate; a second metal gate electrode layer disposed above the second high-k gate dielectric layer; and a second dielectric portion disposed above the second metal gate electrode layer. In one embodiment, the second high-k gate dielectric layer and the second metal gate electrode layer form a planar gate structure in the peripheral circuit region of the memory device. In one embodiment, in a cross-sectional view of the memory device, a sidewall of the second high-k gate dielectric layer is vertically aligned with a sidewall of the second metal gate electrode layer. In one embodiment, in a cross-sectional view of the memory device, a sidewall of the second metal gate electrode layer is vertically aligned with a sidewall of the second dielectric portion.

[0010] Another embodiment of the present disclosure provides a memory element. The memory element includes a recessed gate structure disposed in the semiconductor substrate. The recessed gate structure includes a first high-k gate dielectric layer and a first metal gate electrode layer. An upper surface of the first high-k gate dielectric layer is higher than an upper surface of the semiconductor substrate, and the first metal gate electrode layer extends above the upper surface of the first high-k gate dielectric layer. The memory element also includes a planar gate structure disposed above the semiconductor substrate and spaced apart from the recessed gate structure. The planar gate structure includes a second high-k gate dielectric layer and a second metal gate electrode layer disposed above the second high-k gate dielectric layer.

[0011] In one embodiment, the recessed gate structure and the planar gate structure are disposed in the peripheral circuit region of the memory device. In one embodiment, the first metal gate electrode layer is in direct contact with the upper surface of the first high-k gate dielectric layer. In one embodiment, a material of the first high-k gate dielectric layer is the same as a material of the second high-k gate dielectric layer. In one embodiment, a material of the first metal gate electrode layer is the same as a material of the second metal gate electrode layer. In one embodiment, the first metal gate electrode layer has a lower portion and an upper portion, the lower portion being surrounded by the first high-k gate dielectric layer, the upper portion being located above the upper surface of the first high-k gate dielectric layer, wherein a width of the upper portion of the first metal gate electrode layer is greater than a width of the lower portion of the first metal gate electrode layer.

[0012] In one embodiment, the width of the upper portion of the first metal gate electrode layer is substantially the same as a width of the first high-k gate dielectric layer. In one embodiment, a sidewall of the first high-k gate dielectric layer is exposed through the semiconductor substrate, and in a cross-sectional view of the memory device, the sidewall of the first high-k gate dielectric layer is vertically aligned with a sidewall of the upper portion of the first metal gate electrode layer. In one embodiment, the memory device further includes a first dielectric portion disposed above the recessed gate structure and a second dielectric portion disposed above the planar gate structure, wherein a material of the first dielectric portion is the same as a material of the second dielectric portion.

[0013] In one embodiment, the first dielectric portion is separated from the first high-k gate dielectric layer by the first metal gate electrode layer. In one embodiment, a width of the first dielectric portion is substantially the same as a width of the first metal gate electrode layer above the upper surface of the first high-k gate dielectric layer. In one embodiment, in a cross-sectional view of the memory device, a sidewall of the first dielectric portion is vertically aligned with a sidewall of the first metal gate electrode layer. In one embodiment, in a cross-sectional view of the memory device, a sidewall of the second high-k gate dielectric layer, a sidewall of the second metal gate electrode layer, and a sidewall of the second dielectric portion are vertically aligned.

[0014] Another embodiment of the present disclosure provides a method for fabricating a memory element. The fabrication method includes forming a recess in a semiconductor substrate, and forming a high-k gate dielectric material to cover an upper surface of the semiconductor substrate and line the recess. The fabrication method also includes forming a metal gate electrode material to cover the high-k gate dielectric material, and forming a first dielectric layer to cover the metal gate electrode material. The fabrication method also includes forming a first patterned photoresist above the first dielectric layer, and using the first patterned photoresist as a mask to etch the high-k gate dielectric material, the metal gate electrode material, and the first dielectric layer to form a recessed gate structure and a first dielectric portion above the recessed gate structure. The recessed gate structure includes a first high-k gate dielectric layer and a first metal gate electrode layer located above the first high-k gate dielectric layer, and an upper surface of the first high-k gate dielectric layer is higher than the upper surface of the semiconductor substrate.

[0015] In one embodiment, an upper surface of the first metal gate electrode layer is higher than the upper surface of the first high-k gate dielectric layer. In one embodiment, the first metal gate electrode layer has a lower portion surrounded by the first high-k gate dielectric layer and an upper portion located above the upper surface of the first high-k gate dielectric layer, wherein a width of the upper portion of the first metal gate electrode layer is greater than a width of the lower portion of the first metal gate electrode layer. In one embodiment, in a cross-sectional view of the memory device, a sidewall of the first dielectric portion is vertically aligned with a sidewall of the upper portion of the first metal gate electrode layer. In one embodiment, in a cross-sectional view of the memory device, the sidewall of the upper portion of the first metal gate electrode layer is vertically aligned with a sidewall of the first high-k gate dielectric layer.

[0016] In one embodiment, a fabrication technique for a planar gate structure and a second dielectric portion above the planar gate structure includes etching. In one embodiment, after etching, the first dielectric portion is covered by a first portion of the first patterned photoresist, and the second dielectric portion is covered by a second portion of the first patterned photoresist. In one embodiment, before forming the recess, the fabrication method further includes forming a trench in the semiconductor substrate and forming a gate dielectric layer to cover the upper surface of the semiconductor substrate and line the trench. In addition, before forming the recess, the fabrication method includes forming a gate electrode layer in the trench and above the gate dielectric layer, and forming a dielectric cap layer above the gate electrode layer, wherein a remaining portion of the trench above the gate electrode layer is filled with the dielectric cap layer. In one embodiment, the recess is formed in a peripheral circuit region of the memory device, and the trench is formed in an array region of the memory device.

[0017] In one embodiment, before forming the recess, the preparation method further includes forming a second patterned photoresist over the dielectric cap layer, and forming a second dielectric layer over the dielectric cap layer and covering the second patterned photoresist. In one embodiment, before forming the recess, the preparation method further includes forming a lower layer to cover the second dielectric layer, and etching the lower layer to expose the second dielectric layer. In one embodiment, before forming the lower layer, the preparation method further includes partially removing the second dielectric layer to expose the dielectric cap layer and the second patterned photoresist. In one embodiment, after etching the lower layer, the preparation method further includes etching the second dielectric layer, the dielectric cap layer, and the gate dielectric layer to form an opening exposing the upper surface of the semiconductor substrate, and etching the semiconductor substrate through the opening to form the recess.

[0018] The present disclosure provides an embodiment of a memory element and a method for preparing the same. In some embodiments, the memory element includes a high-k gate dielectric layer disposed in a semiconductor substrate and a metal gate electrode layer disposed above the high-k gate dielectric layer. In some embodiments, an upper surface of the high-k gate dielectric layer is higher than an upper surface of the semiconductor substrate. In addition, a lower portion of the metal gate electrode layer is surrounded by the high-k gate dielectric layer, and a width of an upper portion of the metal gate electrode layer is greater than a width of the lower portion of the metal gate electrode layer. Therefore, the gate-to-substrate leakage current can be reduced. In addition, since the high-k gate dielectric layer and the metal gate electrode layer form a recessed gate structure in a peripheral circuit region, and a planar gate structure is simultaneously formed in the peripheral circuit region, the drive current of the memory element can be increased. As a result, the performance of the memory element can be improved.

[0019] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] When with Figure 1 Various aspects of the present disclosure will be best understood from the following detailed description when read together. It should be understood that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0021] Figure 1 is a schematic cross-sectional view illustrating a memory element according to some embodiments of the present disclosure.

[0022] Figure 2 It is an enlarged schematic diagram illustrating some embodiments of the present disclosure. Figure 1 A portion of the memory element in the.

[0023] Figure 3 is a flow chart illustrating a method for preparing a memory element according to some embodiments of the present disclosure.

[0024] Figure 4 is a schematic cross-sectional view illustrating an intermediate stage of forming a patterned mask over an upper surface of a semiconductor substrate during formation of a memory device according to some embodiments of the present disclosure.

[0025] Figure 5is a schematic cross-sectional view illustrating an intermediate stage of etching a semiconductor substrate to form a trench in an array region during formation of a memory device according to some embodiments of the present disclosure.

[0026] Figure 6 is a schematic cross-sectional view illustrating an intermediate stage of sequentially forming a gate dielectric layer and a gate electrode layer in a trench and above an upper surface of a semiconductor substrate during formation of a memory device according to some embodiments of the present disclosure.

[0027] Figure 7 is a cross-sectional schematic diagram illustrating an intermediate stage of recessing a gate electrode layer and forming a dielectric cap layer in a trench and above an upper surface of a semiconductor substrate during formation of a memory device according to some embodiments of the present disclosure.

[0028] Figure 8 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a patterned photoresist over a dielectric cap layer in a peripheral circuit region during formation of a memory element according to some embodiments of the present disclosure.

[0029] Figure 9 is a schematic cross-sectional view illustrating an intermediate stage of forming a dielectric layer to cover a patterned photoresist and a dielectric cap layer during formation of a memory device according to some embodiments of the present disclosure.

[0030] Figure 10 is a schematic cross-sectional view illustrating an intermediate stage of etching a dielectric layer to form dielectric spacers on sidewalls of a patterned photoresist during formation of a memory device according to some embodiments of the present disclosure.

[0031] Figure 11 is a schematic cross-sectional view illustrating an intermediate stage of forming an underlayer to cover patterned photoresist and dielectric spacers during formation of a memory device according to some embodiments of the present disclosure.

[0032] Figure 12 is a schematic cross-sectional view illustrating an intermediate stage of etching an underlying layer to expose patterned photoresist and dielectric spacers during formation of a memory element according to some embodiments of the present disclosure.

[0033] Figure 13 is a schematic cross-sectional view illustrating an intermediate stage of etching dielectric spacers and underlying layers to expose a semiconductor substrate during formation of a memory device according to some embodiments of the present disclosure.

[0034] Figure 14 is a schematic cross-sectional view illustrating an intermediate stage of removing an underlying layer and patterning photoresist during formation of a memory device according to some embodiments of the present disclosure.

[0035] Figure 15 is a schematic cross-sectional view illustrating an intermediate stage of etching a semiconductor substrate to form a recess in a peripheral circuit region during formation of a memory element according to some embodiments of the present disclosure.

[0036] Figure 16 is a schematic cross-sectional view illustrating an intermediate stage of removing various layers above the semiconductor substrate in the peripheral circuit region during formation of a memory device according to some embodiments of the present disclosure.

[0037] Figure 17 is a schematic cross-sectional view illustrating an intermediate stage of forming a high-k gate dielectric material to line a recess and cover an upper surface of a semiconductor substrate during formation of a memory device according to some embodiments of the present disclosure.

[0038] Figure 18 is a schematic cross-sectional view illustrating an intermediate stage of forming a metal gate electrode material in a recess and above an upper surface of a semiconductor substrate during formation of a memory element according to some embodiments of the present disclosure.

[0039] Figure 19 is a schematic cross-sectional view illustrating an intermediate stage of forming a dielectric layer over a metal gate electrode material during formation of a memory element according to some embodiments of the present disclosure.

[0040] Figure 20 is a schematic cross-sectional view illustrating an intermediate stage of forming a patterned photoresist over a dielectric layer in a peripheral circuit region during formation of a memory element according to some embodiments of the present disclosure.

[0041] Figure 21 is a cross-sectional schematic diagram illustrating an intermediate stage of using a patterned photoresist as a mask to etch underlying materials during formation of a memory element to form a recessed gate structure and a planar gate structure in a peripheral circuit region according to some embodiments of the present disclosure.

[0042] Figure 22 is a schematic cross-sectional view illustrating an intermediate stage of forming an underlying layer to cover a dielectric layer above a patterned photoresist during formation of a memory element according to some embodiments of the present disclosure.

[0043] Figure 23 is a schematic cross-sectional view illustrating an intermediate stage of etching an underlying layer to expose a dielectric layer above a patterned photoresist during formation of a memory element according to some embodiments of the present disclosure.

[0044] Figure 24 is a schematic cross-sectional view illustrating an intermediate stage of etching a dielectric layer and an underlying layer to expose a semiconductor substrate during formation of a memory device according to some embodiments of the present disclosure.

[0045] Figure 25 is a schematic cross-sectional view illustrating an intermediate stage of removing an underlying layer and patterning photoresist during formation of a memory device according to some embodiments of the present disclosure.

[0046] Figure 26is a schematic cross-sectional view illustrating an intermediate stage of etching a semiconductor substrate to form a recess in a peripheral circuit region during formation of a memory element according to some embodiments of the present disclosure.

[0047] Figure 27 FIG. 1 is a partial schematic diagram illustrating an integrated circuit including a memory cell array according to some embodiments of the present disclosure.

[0048] The description of the accompanying drawings is as follows:

[0049] 10: Preparation method

[0050] 50: Memory unit

[0051] 51: Field-effect transistor

[0052] 53: Capacitor

[0053] 55: Drain

[0054] 57: Source

[0055] 59: Gate

[0056] 100: Memory element

[0057] 101: Semiconductor substrate

[0058] 103a: Isolation Structure

[0059] 103b: Isolation Structure

[0060] 105: Mask layer

[0061] 107: Patterned Mask

[0062] 110: Opening

[0063] 112: Groove

[0064] 115: Gate dielectric layer

[0065] 117: Gate electrode layer

[0066] 117a: Gate electrode

[0067] 117b: Gate electrode

[0068] 117c: Gate electrode

[0069] 117d: Gate electrode

[0070] 119: Dielectric cover layer

[0071] 121: Patterned photoresist

[0072] 121a: Part

[0073] 121b: Part

[0074] 123: Dielectric layer

[0075] 123a: Dielectric interstitial

[0076] 123b: Dielectric interstitial

[0077] 123c: Dielectric interstitial

[0078] 123d: Dielectric interstitial

[0079] 125: Lower level

[0080] 128a: Opening

[0081] 128b: Opening

[0082] 128c: Opening

[0083] 128d: Opening

[0084] 133: Patterned photoresist

[0085] 136a: Depression

[0086] 136b: Depression

[0087] 136c: Concave

[0088] 136d: Depression

[0089] 141: High-k gate dielectric material

[0090] 141a: High-k gate dielectric layer

[0091] 141b: High-k gate dielectric layer

[0092] 141c: High-k gate dielectric layer

[0093] 141d: High-k gate dielectric layer

[0094] 141e: High-k gate dielectric layer

[0095] 141f: High-k gate dielectric layer

[0096] 143: Metal gate electrode materials

[0097] 143a: Metal gate electrode layer

[0098] 143b: Metal gate electrode layer

[0099] 143c: Metal gate electrode layer

[0100] 143d: Metal gate electrode layer

[0101] 143e: Metal gate electrode layer

[0102] 143f: Metal gate electrode layer

[0103] 145a: Recessed gate structure

[0104] 145b: Recessed gate structure

[0105] 145c: Recessed gate structure

[0106] 145d: Recessed gate structure

[0107] 145e: Planar gate structure

[0108] 145f: Planar gate structure

[0109] 147: Dielectric layer

[0110] 147a: Dielectric part

[0111] 147b: Dielectric part

[0112] 147c: Dielectric part

[0113] 147d: Dielectric part

[0114] 147e: Dielectric part

[0115] 147f: Dielectric part

[0116] 151: Patterned photoresist

[0117] 151a: Part

[0118] 151b: Part

[0119] 151c: Part

[0120] 151d: Partial

[0121] 151e: Part

[0122] 151f: Part

[0123] 225: Lower level

[0124] 228a: Opening

[0125] 228b: Opening

[0126] 228c: Opening

[0127] 228d: Opening

[0128] 336a: Depression

[0129] 336b: Depression

[0130] 336c: Concave

[0131] 336d: Depression

[0132] 1000: Memory element

[0133] A: Peripheral circuit area

[0134] B: Array area

[0135] B1: lower surface

[0136] BL: Bit Line

[0137] C: Part

[0138] L: lower part

[0139] S11: Steps

[0140] S13: Steps

[0141] S15: Steps

[0142] S17: Steps

[0143] S19: Steps

[0144] S21: Steps

[0145] SW1: Sidewall

[0146] SW2: Sidewall

[0147] SW3: Sidewall

[0148] SW4: Sidewall

[0149] SW5: Sidewall

[0150] SW6: Sidewall

[0151] SW7: Sidewall

[0152] SW8: Sidewall

[0153] SW9: Sidewall

[0154] SW10: Sidewall

[0155] T1: upper surface

[0156] T2: upper surface

[0157] T3: Upper surface

[0158] T4: upper surface

[0159] T5: Upper surface

[0160] U: upper part

[0161] W1: width

[0162] W2: width

[0163] WL: character line DETAILED DESCRIPTION

[0164] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0165] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0166] Figure 1 is a schematic cross-sectional view illustrating a memory element 100 according to some embodiments of the present disclosure. Figure 2 It is an enlarged schematic diagram illustrating some embodiments of the present disclosure. Figure 1 A portion C of the memory element 100 in FIG.

[0167] like Figure 1 As shown, according to some embodiments, the memory device 100 includes a peripheral circuit region A and an array region B. In some embodiments, the memory device 100 includes a semiconductor substrate 101, a plurality of recessed gate structures 145a, 145b, 145c, and 145d disposed in the semiconductor substrate 101, and a plurality of planar gate structures 145e and 145f disposed above the semiconductor substrate 101. The recessed gate structures 145a, 145b, 145c, and 145d and the planar gate structures 145e and 145f are disposed in the peripheral circuit region A.

[0168] In some embodiments, the recessed gate structures 145a, 145b, 145c, and 145d and the planar gate structures 145e and 145f are spaced apart from one another. In some embodiments, the recessed gate structure 145a includes a high-k gate dielectric layer 141a and a metal gate electrode layer 143a disposed over the high-k gate dielectric layer 141a. In some embodiments, the memory device 100 includes a dielectric portion 147a disposed over the metal gate electrode layer 143a of the recessed gate structure 145a.

[0169] Similarly, in some embodiments, recessed gate structure 145b includes a high-k gate dielectric layer 141b and a metal gate electrode layer 143b disposed over high-k gate dielectric layer 141b, recessed gate structure 145c includes a high-k gate dielectric layer 141c and a metal gate electrode layer 143c disposed over high-k gate dielectric layer 141c, and recessed gate structure 145d includes a high-k gate dielectric layer 141d and a metal gate electrode layer 143d disposed over high-k gate dielectric layer 141d. In some embodiments, memory device 100 includes dielectric portions 147b, 147c, and 147d disposed over the metal gate electrode layers 143b, 143c, and 143d of recessed gate structures 145b, 145c, and 145d, respectively.

[0170] like Figure 2 As shown, according to some embodiments, the high-k gate dielectric layer 141a of the recessed gate structure 145a has an upper surface T2 that is higher than the upper surface T1 of the semiconductor substrate. Furthermore, the metal gate electrode layer 143a includes a lower portion L surrounded by the high-k gate dielectric layer 141a and an upper portion U located above the upper surface T2 of the high-k gate dielectric layer 141a. In some embodiments, the upper surface T1 of the semiconductor substrate 101 is higher than a lower surface B1 of the lower portion L of the first metal gate electrode layer 143a.

[0171] In some embodiments, an upper portion U of the metal gate electrode layer 143a is in direct contact with an upper surface T2 of the high-k gate dielectric layer 141a, and an upper surface T3 of the upper portion U of the metal gate electrode layer 143a is higher than the upper surface T2 of the high-k gate dielectric layer 141a and the upper surface T1 of the semiconductor substrate 101. In some embodiments, a width W2 of the upper portion U of the metal gate electrode layer 143a is greater than a width W1 of the lower portion L of the metal gate electrode layer 143a.

[0172] In addition, if Figure 1 and Figure 2As shown, according to some embodiments, a sidewall SW1 of high-k gate dielectric layer 141a, a sidewall SW2 of upper portion U of metal gate electrode layer 143a, and a sidewall SW3 of dielectric portion 147a are vertically aligned in the cross-sectional view of memory device 100. Similar features also exist in recessed gate structures 145b, 145c, and 145d and are not repeated here.

[0173] In some embodiments, planar gate structure 145e includes a high-k gate dielectric layer 141e disposed above semiconductor substrate 101 and a metal gate electrode layer 143e disposed above high-k gate dielectric layer 141e. Planar gate structure 145f includes a high-k gate dielectric layer 141f disposed above semiconductor substrate 101 and a metal gate electrode layer 143f disposed above high-k gate dielectric layer 141f. In some embodiments, memory device 100 includes dielectric portions 147e and 147f disposed above metal gate electrode layers 143e and 143f of planar gate structures 145e and 145f, respectively. In some embodiments, sidewall SW4 of high-k gate dielectric layer 141e, sidewall SW5 of metal gate electrode layer 143e, and sidewall SW6 of dielectric portion 147e are vertically aligned in a cross-sectional view of memory device 100. Similar features also exist in planar gate structure 145f and are not repeated here.

[0174] In array region B, memory device 100 includes isolation structures 103 a and 103 b disposed in semiconductor substrate 101, defining an active region therebetween; a mask layer 105 disposed above semiconductor substrate 101; and a plurality of gate electrodes 117 a, 117 b, 117 c, and 117 d disposed in semiconductor substrate 101. In some embodiments, gate electrode 117 a is disposed in isolation structure 103 a, gate electrodes 117 b and 117 c are disposed in the active region between isolation structures 103 a and 103 b, and gate electrode 117 d is disposed in isolation structure 103 b.

[0175] Furthermore, according to some embodiments, in array region B, memory device 100 includes a gate dielectric layer 115 covering mask layer 105 and extending into semiconductor substrate 101 to surround gate electrodes 117 a, 117 b, 117 c, and 117 d; and a dielectric cap layer 119 disposed over gate dielectric layer 115 and extending into semiconductor substrate 101 to cover gate electrodes 117 a, 117 b, 117 c, and 117 d. In some embodiments, memory device 100 is part of a DRAM.

[0176] The present disclosure provides embodiments of a memory device 100 and a method for fabricating the same. In some embodiments, the memory device 100 includes recessed gate structures 145a, 145b, 145c, and 145d and planar gate structures 145e and 145f in a peripheral circuit region A. In some embodiments, the recessed gate structures 145a, 145b, 145c, and 145d include high-k gate dielectric layers 141a, 141b, 141c, and 141d disposed in a semiconductor substrate 101; and metal gate electrode layers 143a, 143b, 143c, and 143d disposed above the high-k gate dielectric layers 141a, 141b, 141c, and 141d.

[0177] In addition, the planar gate structures 145e, 145f and the recessed gate structures 145a, 145b, 145c, 145d are simultaneously formed in the peripheral circuit region A, which can increase the driving current of the memory device 100. As a result, the performance of the memory device can be improved.

[0178] Figure 3 1 is a flow chart illustrating a method 10 for manufacturing a memory element 100 according to an embodiment of the present disclosure. The method 10 includes steps S11, S13, S15, S17, S19 and S21. Figure 3 Steps S11 to S21 are described in detail.

[0179] Figure 4 is a cross-sectional schematic diagram illustrating an intermediate stage during the formation of the memory element 100 according to some embodiments of the present disclosure. Figure 4 As shown, a semiconductor substrate 101 is provided.

[0180] The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0181] In some embodiments, semiconductor substrate 101 includes an epitaxial layer. For example, semiconductor substrate 101 includes an epitaxial layer covering a bulk semiconductor. In some embodiments, semiconductor substrate 101 is a semiconductor-on-insulator (SOS) substrate, which may include a substrate, a buried oxide layer overlying the substrate, and a semiconductor layer overlying the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOS substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0182] Please still refer to Figure 4 According to some embodiments, isolation structures 103 a and 103 b are formed in the semiconductor substrate 101 to define an active region in the array region B. The isolation structures 103 a and 103 b are shallow trench isolation (STI) structures. Furthermore, the isolation structures 103 a and 103 b may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0183] The formation of the isolation structures 103a and 103b may include forming a patterned mask (not shown) above the upper surface T1 of the semiconductor substrate 101; etching the semiconductor substrate 101 to form a plurality of openings (not shown) using the patterned mask as a mask; depositing a dielectric material in the openings of the semiconductor substrate 101 and above the upper surface T1; and planarizing the dielectric material until the upper surface T1 of the semiconductor substrate 101 is exposed.

[0184] In addition, a plurality of doped regions (not shown) may be formed in the active region defined by the isolation structures 103a and 103b. These doped regions will become source / drain regions in the array region B of the memory device 100. Then, according to some embodiments, as Figure 4 As shown, a mask layer 105 is formed above the upper surface T1 of the semiconductor substrate 101 .

[0185] In some embodiments, a mask layer 105 is formed in the peripheral circuit region A and the array region B. In some embodiments, the isolation structures 103a and 103b and the active region in the array region B are covered by the mask layer 105. Next, according to some embodiments, a patterned mask 107 having a plurality of openings 110 is formed over the mask layer 105. In some embodiments, the openings 110 are located in the array region B, and portions of the mask layer 105 in the array region B are partially exposed through the openings 110 of the patterned mask 107.

[0186] In some embodiments, the mask layer 105 comprises silicon nitride, silicon oxide, silicon oxynitride, other suitable materials, or combinations thereof. In some embodiments, the mask layer 105 and the patterned mask 107 comprise different materials, so that different etching selectivities can be achieved in a subsequent etching process. In some embodiments, the mask layer 105 is formed using a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other suitable deposition processes.

[0187] Subsequently, the patterned mask 107 is used as an etching mask to etch the mask layer 105 and the semiconductor substrate 101 to form a plurality of trenches 112. Figure 5 As shown. The trench 112 may extend through the doped regions in the active region to form source / drain regions (not shown). In some embodiments, the trench 112 may be formed using a wet etching process, a dry etching process, or a combination thereof. After forming the trench 112, the patterned mask 107 may be removed. In some embodiments, the patterned mask 107 is removed by a stripping process, an ashing process, an etching process, or other suitable process.

[0188] Next, according to some embodiments, Figure 6 As shown, a gate dielectric layer 115 is formed to line the trench 112 and is located above the mask layer 105 (i.e., above the upper surface T1 of the semiconductor substrate 101), and a gate electrode layer 117 is formed above the gate dielectric layer 115. In some embodiments, after the gate dielectric layer 115 is formed, the remaining portion of the trench 112 is filled with the gate electrode layer 117 in subsequent processes. In some embodiments, the gate dielectric layer 115 and the gate electrode layer 117 are extended to cover the mask layer 105 in the peripheral circuit area A.

[0189] In some embodiments, the gate dielectric layer 115 includes silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant (high-k), or a combination thereof. In some embodiments, the gate electrode layer 117 includes a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or can be a multilayer structure including any combination of the above materials. In some embodiments, the manufacturing technology of the gate dielectric layer 115 includes a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process, or other suitable deposition processes. In addition, according to some embodiments, the manufacturing technology of the gate electrode layer 117 includes a deposition process, such as a CVD process, a PVD process, a sputtering process, an electroplating process, or other suitable deposition processes.

[0190] Then, according to some embodiments, Figure 7As shown, the gate electrode layer 117 is recessed to form a plurality of gate electrodes 117a, 117b, 117c and 117d in the trench 112 (refer to FIG. Figure 5 ), and a dielectric cap layer 119 is formed over the gate dielectric layer 115 and the gate electrodes 117a, 117b, 117c, and 117d. In some embodiments, the gate electrode layer 117 is partially removed by performing an etching process. The etching process can be a wet etching process, a dry etching process, or a combination thereof.

[0191] According to some embodiments, after partially removing gate electrode layer 117, the remaining portions of trench 112 above gate electrodes 117a, 117b, 117c, and 117d are filled with a dielectric capping layer 119. In some embodiments, dielectric capping layer 119 extends to cover gate dielectric layer 115 in peripheral circuit region A. In some embodiments, dielectric capping layer 119 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. In some embodiments, dielectric capping layer 119 is formed using a deposition process, such as a CVD process, a PVD process, an ALD process, a spin-on process, or other suitable deposition process.

[0192] Then, according to some embodiments, as Figure 8 As shown, a patterned photoresist 121 is formed over the dielectric capping layer 119 in the peripheral circuit region A. In some embodiments, the patterned photoresist 121 includes portions 121a and 121b, and the portions 121a and 121b are spaced apart from each other.

[0193] Next, according to some embodiments, Figure 9 As shown, a dielectric layer 123 is formed over the dielectric cap layer 119 and covers the patterned photoresist 121. In some embodiments, the upper surface T4 and opposite sidewalls SW7 and SW8 of a portion 121a of the patterned photoresist 121 are covered by the dielectric layer 123. In some embodiments, the upper surface T5 and opposite sidewalls SW9 and SW10 of a portion 121b of the patterned photoresist 121 are covered by the dielectric layer 123. In some embodiments, the dielectric layer 123 is extended to cover the dielectric cap layer 119 in the array region B.

[0194] In some embodiments, dielectric layer 123 comprises silicon oxide. However, any other suitable dielectric material may be used, such as silicon nitride, silicon oxynitride, or other suitable dielectric materials. In some embodiments, dielectric layer 123 is fabricated using a CVD process, a PVD process, a spin-on process, other suitable processes, or a combination thereof.

[0195] Then, according to some embodiments, Figure 10As shown, dielectric layer 123 is partially removed by an etching process to form dielectric spacers 123a, 123b, 123c, and 123d. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof. According to some embodiments, after performing the etching process, upper surfaces T4 and T5 of patterned photoresist 121 are exposed, and the remaining portion of dielectric layer 123 forms dielectric spacers 123a, 123b, 123c, and 123d on sidewalls SW7, SW8, SW9, and SW10 of portions 121a and 121b of patterned photoresist 121. In some embodiments, after the etching process, the upper surface of dielectric cap layer 119 is partially exposed.

[0196] Then, according to some embodiments, as Figure 11 As shown, a lower layer 125 is formed over dielectric cap layer 119 and covers portions 121a and 121b of patterned photoresist 121 and dielectric spacers 123a, 123b, 123c, and 123d. In some embodiments, lower layer 125 extends to cover dielectric cap layer 119 in array region B. In some embodiments, lower layer 125 comprises an organic material for gap filling and uniformity. In some embodiments, lower layer 125 comprises a photoresist material. In some embodiments, lower layer 125 is formed using a deposition process, such as a CVD process, a PVD process, an ALD process, a spin-on process, or other suitable deposition process.

[0197] Next, according to some embodiments, Figure 12 As shown, lower layer 125 is partially removed by an etch-back process to expose dielectric spacers 123a, 123b, 123c, and 123d. In some embodiments, the etch-back process includes a wet etch process, a dry etch process, or a combination thereof. In some embodiments, lower layer 125 is etched until dielectric spacers 123a, 123b, 123c, and 123d and portions 121a and 121b of patterned photoresist 121 are exposed. In some embodiments, after lower layer 125 is partially removed, upper surfaces T4 and T5 of portions 121a and 121b of patterned photoresist 121 are exposed.

[0198] Then, according to some embodiments, Figure 13As shown, an etching process is performed to form openings 128a, 128b, 128c, and 128d in the peripheral circuit region A. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the dielectric spacers 123a, 123b, 123c, and 123d are removed during the etching process, and the dielectric cap layer 119, the gate dielectric layer 115, and the mask layer 105 are partially removed by the etching process. In some embodiments, the upper surface T1 of the semiconductor substrate 101 is partially exposed through the openings 128a, 128b, 128c, and 128d in the peripheral circuit region A.

[0199] Then, according to some embodiments, as Figure 14 As shown, portions 121a, 121b of the patterned photoresist 121 and the lower layer 125 (see FIG. Figure 13 ), and form a patterned photoresist 133 to cover the array region B. In some embodiments, the patterned photoresist 121 and the underlying layer 125 are removed by a stripping process, an ashing process, an etching process, or other suitable processes. In some embodiments, the patterned photoresist 133 formed in the array region B is used to protect the underlying structure during subsequent processing steps.

[0200] Next, according to some embodiments, Figure 15 As shown, the semiconductor substrate 101 is etched to form recesses 136a, 136b, 136c and 136d in the peripheral circuit region A. The various steps are shown as follows: Figure 3 Step S11 of the manufacturing method 10 is shown. In some embodiments, the semiconductor substrate 101 is etched through the openings 128a, 128b, 128c, and 128d. In some embodiments, the recesses 136a, 136b, 136c, and 136d in the peripheral circuit region A are formed by a wet etching process, a dry etching process, or a combination thereof.

[0201] Then, according to some embodiments, Figure 16 As shown, the dielectric cap layer 119, the gate dielectric layer 115, and the mask layer 105 in the peripheral circuit region A are removed. In some embodiments, the dielectric cap layer 119, the gate dielectric layer 115, and the mask layer 105 in the peripheral circuit region A are removed by a stripping process, an ashing process, an etching process, or other suitable processes. In some embodiments, during the process of removing the dielectric cap layer 119, the gate dielectric layer 115, and the mask layer 105 in the peripheral circuit region A, the structure in the array region B is exposed to the patterned photoresist 133 (refer to FIG. 1 ). Figure 15 According to some embodiments, after the upper surface T1 of the semiconductor substrate 101 is exposed in the peripheral circuit region A, the patterned photoresist 133 in the array region B is removed.

[0202] Then, according to some embodiments, as Figure 17 As shown, a high-k gate dielectric material 141 is formed to line the recesses 136a, 136b, 136c, 136d and cover the upper surface T1 of the semiconductor substrate 101. The various steps are shown as follows: Figure 3 This is step S13 of the manufacturing method 10. In some embodiments, the high-k gate dielectric material 141 is extended to cover the dielectric cap layer 119 in the array region B.

[0203] In some embodiments, the high-k gate dielectric material 141 includes HfSiON, HfON, another suitable dielectric material having a higher dielectric constant (k) than silicon dioxide, or a combination thereof. In some embodiments, the high-k gate dielectric material 141 is formed using a deposition process such as a CVD process, a PVD process, an ALD process, a spin-on process, or other suitable deposition process.

[0204] Next, according to some embodiments, Figure 18 As shown, a metal gate electrode material 143 is formed to cover the high-k gate dielectric material 141. The various steps are shown as follows: Figure 3 In some embodiments, the recesses 136a, 136b, 136c, and 136d are formed in the high-k gate dielectric material 141 ( Figure 17 ) is filled with a metal gate electrode material 143. In some embodiments, the metal gate electrode material 143 extends above the upper surface T1 of the semiconductor substrate. In some embodiments, the metal gate electrode material 143 extends to cover the high-k gate dielectric material 141 in the array region B.

[0205] In some embodiments, the metal gate electrode material 143 includes TiN, W, Ru, Al, RuAl alloy, other suitable metals, or combinations thereof. In some embodiments, the metal gate electrode material 143 is formed using a deposition process such as a CVD process, a PVD process, a sputtering process, an electroplating process, or other suitable deposition processes.

[0206] Then, according to some embodiments, Figure 19 As shown, a dielectric layer 147 is formed to cover the metal gate electrode material 143. The various steps are shown as follows Figure 3 10 . In some embodiments, dielectric layer 147 is extended to cover metal gate electrode material 143 in array region B. In some embodiments, dielectric layer 147 comprises silicon nitride. However, any other suitable dielectric material may be used, such as silicon oxide, silicon oxynitride, or other suitable dielectric materials. In some embodiments, dielectric layer 147 is formed using a CVD process, a PVD process, a spin-on process, other suitable processes, or a combination thereof.

[0207] Then, according to some embodiments, as Figure 20 As shown, a patterned photoresist 151 is formed on the dielectric layer 147 in the peripheral circuit region A. The various steps are shown as follows Figure 3 Step S19 of the manufacturing method 10 is shown. In some embodiments, the patterned photoresist 151 includes portions 151a, 151b, 151c, 151d, 151e, and 151f, and the portions 151a to 151f are spaced apart from each other.

[0208] Next, according to some embodiments, Figure 21 As shown, an etching process is performed using the patterned photoresist 151 as a mask to form recessed gate structures 145a, 145b, 145c, 145d and planar gate structures 145e, 145f in the peripheral circuit region A. In some embodiments, the dielectric layer 147, the metal gate electrode material 143, and the high-k gate dielectric material 141 are etched to expose the upper surface T1 of the semiconductor substrate 101 in the peripheral circuit region A. The various steps are shown as follows: Figure 3 Step S21 in the preparation method 10 shown.

[0209] In some embodiments, the remaining portions of the high-k gate dielectric material 141 and the remaining portions of the metal gate electrode material 143 form recessed gate structures 145a, 145b, 145c, 145d, and planar gate structures 145e and 145f. In some embodiments, the recessed gate structure 145a includes a high-k gate dielectric layer 141a and a metal gate layer 143a, the recessed gate structure 145b includes a high-k gate dielectric layer 141b and a metal gate electrode layer 143b, the recessed gate structure 145c includes a high-k gate dielectric layer 141c and a metal gate electrode layer 143c, and the recessed gate structure 145d includes a high-k gate dielectric layer 141d and a metal gate electrode layer 143d. Furthermore, in some embodiments, the planar gate structure 145e includes a high-k gate dielectric layer 141e and a metal gate electrode layer 143e, and the planar gate structure 145f includes a high-k gate dielectric layer 141f and a metal gate electrode layer 143f.

[0210] Additionally, according to some embodiments, the remaining portion of dielectric layer 147 forms dielectric portions 147a, 147b, 147c, 147d, 147e, and 147f. In some embodiments, dielectric portions 147a, 147b, 147c, and 147d are disposed over recessed gate structures 145a, 145b, 145c, and 145d, respectively. In some embodiments, dielectric portions 147e and 147f are disposed over planar gate structures 145e and 145f, respectively.

[0211] Then, refer back to Figure 1 According to some embodiments, the patterned photoresist 151 in the peripheral circuit region A is removed (refer to Figure 21 ) portions 151a, 151b, 151c, 151d, 151e, and 151f of the array region B are removed, and the high-k gate dielectric material 141, the metal gate electrode material 143, and the dielectric layer 147 in the array region B are removed. In some embodiments, the patterned photoresist 151 in the peripheral circuit region A is removed by a stripping process, an ashing process, an etching process, or other suitable process. Some of the processes for removing the high-k gate dielectric material 141, the metal gate electrode material 143, and the dielectric layer 147 in the array region B are similar or identical to the processes for removing the patterned photoresist 151, and the details are not repeated here.

[0212] Figures 22 to 25 is a cross-sectional schematic diagram illustrating an intermediate stage during the formation of the memory element 100 in some embodiments of the present disclosure. It should be understood that Figure 22 The structure shown in the previous steps is the same as Figures 4 to 9 The steps shown are basically the same, and for the relevant detailed description, please refer to the previous paragraphs and will not be repeated here.

[0213] According to some embodiments, Figure 22 As shown, after the dielectric layer 123 is formed, a lower layer 225 is formed over the dielectric layer 123. In some embodiments, the lower layer 225 is formed to cover the structures in the peripheral circuit region A and the array region B. Some of the materials and processes used to form the lower layer 225 are similar to those used to form the lower layer 125 (see Figure 11 ) are similar or identical in material and process, and the details are not repeated here.

[0214] Next, according to some embodiments, Figure 23 As shown, the lower layer 225 is partially removed by an etch-back process to expose the dielectric layer 123. In some embodiments, the etch-back process includes a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the lower layer 225 is etched until the dielectric layer 123 is exposed.

[0215] Then, according to some embodiments, Figure 24 As shown, an etching process is performed to form openings 228a, 228b, 228c, and 228d in the peripheral circuit region A. In some embodiments, the etching process includes an ion bombardment process. In some embodiments, the etching process partially removes the dielectric layer 123, the dielectric cap layer 119, the gate dielectric layer 115, and the mask layer 105. In some embodiments, the upper surface T1 of the semiconductor substrate 101 is partially exposed through the openings 228a, 228b, 228c, and 228d in the peripheral circuit region A.

[0216] Then, according to some embodiments, as Figure 25 As shown, the portions 121a, 121b of the patterned photoresist 121 and the lower layer 225 (see FIG. Figure 24 In some embodiments, the patterned photoresist 121 and the lower layer 225 are removed by a stripping process, an ashing process, an etching process, or other suitable processes.

[0217] like Figure 14 As shown, after removing the patterned photoresist 121 and the lower layer 225, the remaining portion of the dielectric layer 123 is removed by a stripping process, an ashing process, an etching process, or other suitable processes, and then a patterned photoresist 133 is formed to cover the array region B. In some embodiments, the patterned photoresist 133 formed in the array region B is used to protect the underlying structure during subsequent processing steps. After forming the patterned photoresist 133, the process steps are similar to those of Figures 15 to 21 The steps shown are similar or identical to Figure 1 The memory element 100 is shown and will not be described in detail here.

[0218] Please refer back Figure 25 , after removing the patterned photoresist 121 and the lower layer 225, a patterned photoresist 133 is formed to cover the array region B. According to some other embodiments, such as Figure 26 As shown, the semiconductor substrate 101 is then etched to form recesses 336a, 336b, 336c, and 336d in the peripheral circuit region A. In some embodiments, the semiconductor substrate 101 is etched through the openings 228a, 228b, 228c, and 228d. Some of the processes for forming the recesses 336a, 336b, 336c, and 336d are similar to those for forming the recesses 136a, 136b, 136c, and 136d (see FIG. Figure 15 ) and the details thereof will not be repeated here.

[0219] After the recesses 336a, 336b, 336c, and 336d are formed in the peripheral circuit region A, the remaining portions of the dielectric layer 123, the dielectric cap layer 119, the gate dielectric layer 115, and the mask layer 105 in the peripheral circuit region A are removed by a stripping process, an ashing process, an etching process, or other suitable processes. In some embodiments, during the process of removing these layers above the semiconductor substrate 101 in the peripheral circuit region A, the structures in the array region B are protected by the patterned photoresist 133. Then, the patterned photoresist 133 in the array region B is removed, and the subsequent process steps are similar to those in the embodiment of the present invention. Figures 16 to 21 The steps shown are similar or identical to those shown in FIG. Figure 1 The detailed information of the memory device 100 is not repeated here.

[0220] Figure 27FIG1 is a partial schematic diagram of an exemplary integrated circuit (e.g., memory element 1000) including an array of memory cells 50 according to some embodiments. In some embodiments, memory element 1000 comprises a DRAM. In some embodiments, memory element 1000 comprises a plurality of memory cells 50 arranged in a grid pattern and comprising a plurality of columns and rows. The number of memory cells 50 can vary depending on system requirements and manufacturing technology.

[0221] In some embodiments, each memory cell 50 includes an access element and a storage element. The access element is configured to provide controlled access to the storage element. Specifically, according to some embodiments, the access element is a field-effect transistor (FET) 51 and the storage element is a capacitor 53. In each memory cell 50, the FET 51 includes a drain 55, a source 57, and a gate 59. One terminal of the capacitor 53 is electrically connected to the source 57 of the FET 51, and the other terminal of the capacitor 53 can be electrically connected to ground. In addition, in each memory cell 50, the gate 59 of the FET 51 is electrically connected to a word line WL, and the drain 55 of the FET 51 is electrically connected to the bit line BL.

[0222] The above description refers to the terminal of the FET 51 electrically connected to the capacitor 53 as the source 57, and the terminal of the FET 51 electrically connected to the bit line BL as the drain 55. However, during read and write operations, the terminal of the FET 51 electrically connected to the capacitor 53 may be the drain, and the terminal of the FET 51 electrically connected to the bit line BL may be the source. That is, depending on how the voltages applied to the source, drain, and gate control the FET 51, either terminal of the FET 51 may be the source or the drain.

[0223] By controlling the voltage at gate 59 via word line WL, a potential is generated across FET 51, allowing charge to flow from drain 55 to capacitor 53. Thus, the charge stored in capacitor 53 can be interpreted as a binary data value in memory cell 50. For example, a positive charge stored in capacitor 53 above a threshold voltage can be interpreted as a binary "1." If the charge in capacitor 53 is below the threshold value, a binary value "0" is said to be stored in memory cell 50.

[0224] The bit line BL is configured to read data from and write data to the memory cell 50. The word line WL is configured to activate the FET 51 to access a specific column of the memory cell 50. Therefore, the memory device 1000 also includes a peripheral circuit area, which may include an address buffer, a column decoder, and a row decoder. The column decoder and the row decoder selectively access the memory cell 50 in response to address signals provided to the address buffer during read, write, and update operations. The address signals are typically provided by an external controller such as a microprocessor or other type of memory controller.

[0225] Please refer back Figure 1 and Figure 2 , the peripheral circuit region A may be any region in the address buffer, the column decoder, or the row decoder, and the array region B may be any region of the memory cell 50 in the memory element 1000 .

[0226] The present disclosure provides embodiments of a memory device 100 and a method for manufacturing the same. In some embodiments, the memory device 100 includes recessed gate structures 145a, 145b, 145c, and 145d and planar gate structures 145e and 145f in a peripheral circuit region A. In some embodiments, the recessed gate structures 145a, 145b, 145c, and 145d include high-k gate dielectric layers 141a, 141b, 141c, and 141d disposed in a semiconductor substrate 101 and metal gate electrode layers 143a, 143b, 143c, and 143d disposed above the high-k gate dielectric layers 141a, 141b, 141c, and 141d, respectively. Thus, gate-to-substrate leakage current can be reduced. In addition, the planar gate structures 145e, 145f and the recessed gate structures 145a, 145b, 145c, 145d are simultaneously formed in the peripheral circuit region A, which can increase the driving current of the memory device 100. As a result, the performance of the memory device can be improved.

[0227] One embodiment of the present disclosure provides a memory element. The memory element includes a first high-k gate dielectric layer disposed in a semiconductor substrate. An upper surface of the first high-k gate dielectric layer is higher than an upper surface of the semiconductor substrate. The memory element also includes a first metal gate electrode layer disposed above the first high-k gate dielectric layer. A lower portion of the first metal gate electrode layer is surrounded by the first high-k gate dielectric layer, and a width of an upper portion of the first metal gate electrode layer is greater than a width of a lower portion of the first metal gate electrode layer. The memory element also includes a first dielectric portion disposed above the first metal gate electrode layer.

[0228] Another embodiment of the present disclosure provides a memory element. The memory element includes a recessed gate structure disposed in the semiconductor substrate. The recessed gate structure includes a first high-k gate dielectric layer and a first metal gate electrode layer. An upper surface of the first high-k gate dielectric layer is higher than an upper surface of the semiconductor substrate, and the first metal gate electrode layer extends above the upper surface of the first high-k gate dielectric layer. The memory element also includes a planar gate structure disposed above the semiconductor substrate and spaced apart from the recessed gate structure. The planar gate structure includes a second high-k gate dielectric layer and a second metal gate electrode layer disposed above the second high-k gate dielectric layer.

[0229] Another embodiment of the present disclosure provides a method for fabricating a memory element. The fabrication method includes forming a recess in a semiconductor substrate, and forming a high-k gate dielectric material to cover an upper surface of the semiconductor substrate and line the recess. The fabrication method also includes forming a metal gate electrode material to cover the high-k gate dielectric material, and forming a first dielectric layer to cover the metal gate electrode material. The fabrication method also includes forming a first patterned photoresist above the first dielectric layer, and using the first patterned photoresist as a mask to etch the high-k gate dielectric material, the metal gate electrode material, and the first dielectric layer to form a recessed gate structure and a first dielectric portion above the recessed gate structure. The recessed gate structure includes a first high-k gate dielectric layer and a first metal gate electrode layer located above the first high-k gate dielectric layer, and an upper surface of the first high-k gate dielectric layer is higher than the upper surface of the semiconductor substrate.

[0230] Embodiments of the present disclosure have several advantageous features. By forming a recessed gate structure having a high-k gate dielectric layer and a metal gate electrode layer in the peripheral circuit region, gate-to-substrate leakage current can be reduced. Furthermore, since both a planar gate structure and a recessed gate structure are formed in the peripheral circuit region, the drive current of the memory element 100 can be increased. Consequently, the performance of the memory element can be improved.

[0231] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0232] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A memory element comprising: a first high-k gate dielectric layer disposed in a semiconductor substrate, wherein an upper surface of the first high-k gate dielectric layer is higher than an upper surface of the semiconductor substrate; a first metal gate electrode layer disposed above the first high-k gate dielectric layer, wherein a lower portion of the first metal gate electrode layer is surrounded by the first high-k gate dielectric layer, and wherein a width of an upper portion of the first metal gate electrode layer is greater than a width of the lower portion of the first metal gate electrode layer; and A first dielectric portion is disposed above the first metal gate electrode layer. 2 . The memory device of claim 1 , wherein the first metal gate electrode layer is in direct contact with the upper surface of the first high-k gate dielectric layer. 3 . The memory device as claimed in claim 1 , wherein the first metal gate electrode layer is separated from the semiconductor substrate by the first high-k gate dielectric layer. 4 . The memory device of claim 1 , wherein the first high-k gate dielectric layer is separated from the first dielectric portion by the first metal gate electrode layer. 5 . The memory device as claimed in claim 1 , wherein the upper surface of the semiconductor substrate is higher than a lower surface of the lower portion of the first metal gate electrode layer. 6 . The memory device of claim 1 , wherein a top surface of the upper portion of the first metal gate electrode layer is higher than the top surface of the first high-k gate dielectric layer. 7 . The memory device of claim 1 , wherein the width of the upper portion of the first metal gate electrode layer is substantially the same as a width of the first high-k gate dielectric layer. 8 . The memory device of claim 1 , wherein the width of the upper portion of the first metal gate electrode layer is substantially the same as a width of the first dielectric portion. 9 . The memory device of claim 1 , wherein in a cross-sectional view of the memory device, a sidewall of the first high-k gate dielectric layer is vertically aligned with a sidewall of the upper portion of the first metal gate electrode layer. 10 . The memory device of claim 9 , wherein in a cross-sectional view of the memory device, the sidewall of the upper portion of the first metal gate electrode layer is vertically aligned with a sidewall of the first dielectric portion. 11 . The memory device of claim 1 , wherein the first high-k gate dielectric layer and the first metal gate electrode layer form a recessed gate structure in a peripheral circuit region of the memory device.

12. The memory element of claim 11 , further comprising: a second high-k gate dielectric layer disposed above the semiconductor substrate; a second metal gate electrode layer disposed above the second high-k gate dielectric layer; as well as A second dielectric portion is disposed above the second metal gate electrode layer. 13 . The memory device of claim 12 , wherein the second high-k gate dielectric layer and the second metal gate electrode layer form a planar gate structure in the peripheral circuit region of the memory device. 14 . The memory device of claim 12 , wherein in a cross-sectional view of the memory device, a sidewall of the second high-k gate dielectric layer is vertically aligned with a sidewall of the second metal gate electrode layer. 15 . The memory device of claim 14 , wherein in a cross-sectional view of the memory device, the sidewall of the second metal gate electrode layer is vertically aligned with a sidewall of the second dielectric portion.

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