Semiconductor device, preparation method thereof and storage system

Abstract

The invention provides a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises a first semiconductor structure, a second semiconductor structure, a first signal transmission structure and a bonding pad. The first semiconductor structure comprises a transistor, the transistor comprises a source / drain doped region and a grid electrode, the second semiconductor structure is connected to the side, close to the grid electrode, of the first semiconductor structure, and the first signal transmission structure is connected to the side, away from the grid electrode, of the source / drain doped region. The bonding pad is located on the side, away from the second semiconductor structure, of the first semiconductor structure and comprises a first bonding pad connected with the first signal transmission structure. The first bonding pad is arranged on the side, close to the source / drain doped region, of the first semiconductor structure, so that power can be directly supplied to the source / drain doped region through the first signal transmission structure, and the voltage drop of the first signal transmission structure is reduced.

Description

Technical Field

[0001] The present application generally relates to the field of electronic devices, and more particularly, to a semiconductor device, a method for manufacturing the same, and a storage system. Background Art

[0002] Traditional power supply networks need to pass through the entire memory structure to power the control circuits that control the memory array for read and write operations. However, this power supply network structure design has always suffered from the problem of large voltage drop. Summary of the Invention

[0003] The purpose of this application is to provide a semiconductor device, a manufacturing method thereof, and a storage system, aiming to reduce the voltage drop of a first signal transmission structure.

[0004] In a first aspect, the present application provides a semiconductor device, comprising:

[0005] A first semiconductor structure includes a transistor, wherein the transistor includes source / drain doped regions and a gate;

[0006] a second semiconductor structure connected to a side of the first semiconductor structure close to the gate;

[0007] a first signal transmission structure connected to a side of the source / drain doping region away from the gate;

[0008] The pad is located on a side of the first semiconductor structure away from the second semiconductor structure and includes a first pad connected to the first signal transmission structure.

[0009] In some embodiments, the first semiconductor structure further comprises:

[0010] The first metal interconnection layer is located on a side of the gate away from the source / drain doping region.

[0011] In some embodiments, the pad further includes a second pad, the second pad is located on a side of the first semiconductor structure away from the second semiconductor structure, and the semiconductor device further includes:

[0012] The second signal transmission structure extends along a first direction in the first semiconductor structure and connects the first metal interconnection layer and the second pad.

[0013] In some embodiments, the second semiconductor structure includes:

[0014] A first memory array includes a first stacked structure and a first channel structure extending along the first direction through the first stacked structure, wherein the first stacked structure includes alternately stacked gate layers and interlayer insulating layers, and the first channel structure includes a first channel layer extending along the first direction;

[0015] a second metal interconnection layer, located on one side of the first memory array along the first direction;

[0016] The first source layer is located on a side of the first memory array away from the second metal interconnection layer, and the first source layer is connected to the first channel layer.

[0017] In some embodiments, the second metal interconnection layer is located between the first memory array and the first metal interconnection layer, and the first metal interconnection layer is connected to the second metal interconnection layer through a bonding layer.

[0018] In some embodiments, the second metal interconnect layer is located on a side of the first memory array away from the first semiconductor structure, and the first source layer is connected to a sidewall of the first channel structure.

[0019] In some embodiments, the second semiconductor structure further comprises:

[0020] A first array of through contacts and a second array of through contacts are both arranged parallel to the first storage array in the first direction;

[0021] The first array of through contacts connects the second metal interconnection layer and the first source layer, and the second array of through contacts connects the first metal interconnection layer and the second metal interconnection layer.

[0022] In some embodiments, the second semiconductor structure further comprises:

[0023] a gate connection structure, extending along the first direction in the first stacked structure and connected to the gate layer;

[0024] a bit line contact connected to one end of the first channel structure close to the second metal interconnection layer;

[0025] The gate connection structure and the bit line contact are respectively connected to the second metal interconnection layer.

[0026] In some embodiments, the semiconductor device further includes a third semiconductor structure, wherein the third semiconductor structure is bonded to a side of the second semiconductor structure away from the first semiconductor structure; the third semiconductor structure includes:

[0027] a second memory array comprising a second stacked structure and a second channel structure penetrating the second stacked structure along the first direction, wherein the second channel structure comprises a second channel layer extending along the first direction;

[0028] a third metal interconnection layer, located on a side of the second memory array away from the second semiconductor structure;

[0029] The second source layer is connected to an end portion of the second channel layer and is bonded to the first source layer.

[0030] In some embodiments, the second semiconductor structure further includes a third array of through contacts parallel to the first memory array in the first direction, the third array of through contacts being connected to the second metal interconnect layer;

[0031] The third semiconductor structure further includes a fourth array of through contacts parallel to the second memory array in the first direction, the fourth array of through contacts being connected to the third metal interconnect layer;

[0032] The third array of through contacts and the fourth array of through contacts are bonded together.

[0033] In some embodiments, the third semiconductor structure further includes a fifth array of through contacts parallel to the second memory array in the first direction, and the second source layer is connected to the third metal interconnection layer through the fifth array of through contacts.

[0034] In some embodiments, the first semiconductor structure further comprises:

[0035] A connection contact is located on a side of the source / drain doped region away from the first signal transmission structure, the connection contact connects the gate and the first metal interconnection layer, and connects the second signal transmission structure and the first metal interconnection layer.

[0036] In a second aspect, the present application provides a method for preparing a semiconductor device, the method comprising:

[0037] forming a first semiconductor structure, the first semiconductor structure including a transistor, the transistor including source / drain doped regions and a gate;

[0038] forming a second semiconductor structure;

[0039] connecting the second semiconductor structure to a side of the first semiconductor structure close to the gate;

[0040] forming a first signal transmission structure connected to a side of the source / drain doped region away from the gate;

[0041] A pad is formed on a side of the first semiconductor structure away from the second semiconductor structure, and the pad includes a first pad connected to the first signal transmission structure.

[0042] In some embodiments, the step of forming the first semiconductor structure includes:

[0043] providing a semiconductor layer;

[0044] forming source / drain doped regions in the semiconductor layer;

[0045] forming a gate on the source / drain doped region;

[0046] A first metal interconnection layer is formed on a side of the gate away from the source / drain doping region.

[0047] In some embodiments, the step of forming the second semiconductor structure includes:

[0048] forming a first memory array, the first memory array comprising a first stacked structure and a first channel structure penetrating the first stacked structure along a first direction, the first stacked structure comprising alternately stacked gate layers and interlayer insulating layers, and the first channel structure comprising a first channel layer extending along the first direction;

[0049] forming a second metal interconnection layer on one side of the first memory array along the first direction;

[0050] A first source layer is formed on a side of the first memory array away from the second metal interconnection layer, and the first source layer is connected to the first channel layer.

[0051] In some embodiments, the step of connecting the second semiconductor structure to a side of the first semiconductor structure close to the gate includes:

[0052] The first metal interconnection layer and the second metal interconnection layer are connected through a bonding metal layer.

[0053] In some embodiments, the step of connecting the second semiconductor structure to a side of the first semiconductor structure close to the gate includes:

[0054] Connecting a side of the second semiconductor structure close to the first source layer to the first metal interconnection layer.

[0055] In some embodiments, the pad further includes a second pad, and the method for preparing the semiconductor device further includes:

[0056] A second signal transmission structure extending along a first direction is formed in the first semiconductor structure, wherein the second signal transmission structure connects the first metal interconnection layer and the second pad.

[0057] In some embodiments, the step of forming the first semiconductor structure further includes:

[0058] Before forming the first metal interconnection layer, a connection contact is formed on a side of the source / drain doped region away from the first signal transmission structure, wherein the connection contact connects the gate and the first metal interconnection layer, and connects the second signal transmission structure and the first metal interconnection layer.

[0059] In some embodiments, the method for preparing the semiconductor device further includes:

[0060] forming a third semiconductor structure, the third semiconductor structure comprising a second memory array, a third metal interconnect layer, and a second source layer, the second memory array comprising a second stacked structure and a second channel structure penetrating the second stacked structure along the first direction, the second channel structure comprising a second channel layer extending along the first direction, and the second source layer being connected to an end of the second channel layer;

[0061] The second source layer is bonded to the first source layer.

[0062] In a third aspect, the present application provides a storage system, comprising:

[0063] The semiconductor device according to any of the above embodiments;

[0064] A controller is connected to the semiconductor device and is used to control the semiconductor device to store data.

[0065] The present application provides a semiconductor device, a preparation method thereof, and a storage system, wherein the semiconductor device includes a first semiconductor structure, a second semiconductor structure, a first signal transmission structure, and a pad. The first semiconductor structure includes a transistor, the transistor includes a source / drain doped region and a gate, the second semiconductor structure is connected to the side of the first semiconductor structure close to the gate, the first signal transmission structure is connected to the side of the source / drain doped region away from the gate, the pad is located on the side of the first semiconductor structure away from the second semiconductor structure, and includes a first pad connected to the first signal transmission structure. The present application sets the first pad on the side of the first semiconductor structure close to the source / drain doped region, so that the source / drain doped region can be powered directly through the first signal transmission structure, thereby reducing the voltage drop of the first signal transmission structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0067] Figure 1ais a schematic structural diagram of a semiconductor device provided by some embodiments of the present application;

[0068] Figure 1b Some embodiments of this application provide Figure 1a Schematic diagram of the enlarged structure of the semiconductor device at point A;

[0069] Figure 2 is a schematic structural diagram of a semiconductor device provided by some embodiments of the present application;

[0070] Figure 3a is a schematic structural diagram of a semiconductor device provided by some embodiments of the present application;

[0071] Figure 3b Some embodiments of this application provide Figure 3a Schematic diagram of the enlarged structure of the semiconductor device at B;

[0072] Figure 4 is a schematic flow chart of a method for manufacturing a semiconductor device provided in some embodiments of the present application;

[0073] Figures 5a-5c is a schematic structural diagram of a semiconductor device during the manufacturing process provided by some embodiments of the present application;

[0074] Figure 6a-6b is a schematic structural diagram of a semiconductor device during the manufacturing process provided by some embodiments of the present application;

[0075] Figure 7 This is a structural diagram of the storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0076] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0077] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of this application.

[0078] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0079] As used herein, the term "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer that may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers and one or more dielectric layers.

[0080] It should be noted that the illustrations provided in the embodiments of the present application are only schematic illustrations of the basic concept of the present application. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed at will, and the component layout may also be more complicated.

[0081] See also Figure 1a , Figure 1a The following is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present application. The semiconductor device can be a wafer or a three-dimensional memory, or a portion of a three-dimensional memory. The three-dimensional memory can be applied to communications products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data. Consumer electronics products include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, and gaming products.

[0082] The semiconductor device 100 includes a first semiconductor structure 10, a second semiconductor structure 20, a first signal transmission structure 31, and a pad 40. The first semiconductor structure 10 includes a transistor T, which includes a source / drain doped region 11 and a gate 12. The second semiconductor structure 20 is connected to a side of the first semiconductor structure 10 close to the gate 12. The first signal transmission structure 31 is connected to a side of the source / drain doped region 11 away from the gate 12. The pad 40 is located on a side of the first semiconductor structure 10 away from the second semiconductor structure 20 and includes a first pad 41 connected to the first signal transmission structure 31.

[0083] The first semiconductor structure 10 may be a control circuit, which may include a complementary metal oxide semiconductor (CMOS) and a plurality of transistors T, such as a P-type field effect transistor T and an N-type field effect transistor T.

[0084] Specifically, the first semiconductor structure 10 includes a semiconductor layer 101 (including a first surface and a second surface disposed opposite each other), source / drain doped regions 11 spaced apart on one surface (e.g., the first surface) of the semiconductor layer 101, and a gate 12 located outside the first surface of the semiconductor layer 101. The two source / drain doped regions 11, the semiconductor layer 101 therebetween, and the gate 12 form a transistor T. The first semiconductor structure 10 may further include a gate insulating layer located between the gate 12 and the semiconductor layer 101.

[0085] In some embodiments, the semiconductor layer 101 may include a P-type semiconductor layer, wherein the source / drain doping regions 11 may include N-type semiconductor ions. The semiconductor layer 101 may also include an N-type semiconductor layer, wherein the source / drain doping regions 11 may include P-type semiconductor ions.

[0086] The first pad 41 can be arranged outside the second surface of the semiconductor layer 101. The first pad 41 can be connected to the first signal transmission structure 31 through the lead-out structure 102 to directly transmit the first signal (such as a power signal) to the source / drain doped region 11. Not only is the wire wider and the resistance lower, but the voltage drop problem can also be alleviated, thereby improving the performance of the first signal transmission structure 31.

[0087] In some embodiments, the first semiconductor structure 10 may further include a first metal interconnection layer 13 , which is located on a side of the gate 12 away from the source / drain doped regions 11 . The gate 12 is connected to the first metal interconnection layer 13 .

[0088] In some embodiments, the pad 40 may further include a second pad 42, which is separated from the first pad 41. The semiconductor device 100 may further include a second signal transmission structure 32, which extends along the first direction (Z) within the first semiconductor structure 10 and connects the first metal interconnect layer 13 and the second pad 42. Specifically, the second signal transmission structure 32 may be located between two adjacent transistors T and extend through the semiconductor layer 101 along the first direction (Z). One end of the second signal transmission structure 32 is connected to the second pad 42, and the other end is connected to the first metal interconnect layer 13.

[0089] In some embodiments, the first semiconductor structure 10 may further include a connection contact 14, which is located on a side of the source / drain doped region 11 (or semiconductor layer 101) away from the first signal transmission structure 31. The connection contact 14 connects the gate 12 and the first metal interconnection layer 13, and connects the second signal transmission structure 32 and the first metal interconnection layer 13.

[0090] The second semiconductor structure 20 may be a memory structure, which may include a first memory array 21, a second metal interconnect layer 22, and a first source layer 23. The second metal interconnect layer 22 is located on one side of the first memory array 21 along the first direction (Z), and the first source layer 23 is located on a side of the first memory array 21 away from the second metal interconnect layer 22.

[0091] like Figure 1a As shown, the second metal interconnection layer 22 is located between the first memory array 21 and the first metal interconnection layer 13, and the first metal interconnection layer 13 and the second metal interconnection layer 22 are connected via a bonding layer (not shown).

[0092] In some embodiments, the first source layer 23 may be a semiconductor substrate, such as silicon (Si), germanium (Ge), a SiGe substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. In other embodiments, the semiconductor substrate may be a substrate comprising other elemental semiconductors or compound semiconductors, or may be a stacked structure, such as Si / SiGe.

[0093] In some embodiments, the semiconductor device 100 includes not only the first source layer 23 , but also a substrate (not shown) located on a side of the first source layer 23 away from the first memory array 21 .

[0094] Please combine Figure 1b , Figure 1b Some embodiments of this application provide Figure 1a Schematic diagram of the enlarged structure of the semiconductor device at point A.

[0095] The first memory array 21 includes a first stacked structure 211 and a first channel structure 212 extending through the first stacked structure 211 along the first direction (Z). The first stacked structure 211 includes alternating gate layers 211a (first gate layers 211a) and interlayer insulating layers 211b. The first channel structure 212 includes a first channel layer 2121 extending along the first direction (Z). The first source layer 23 is connected to the first channel layer 2121.

[0096] In some embodiments, the first channel structure 212 may further include a first storage layer 2122 surrounding the first channel layer 2121, and a filling layer 2123 surrounded by the first channel layer. The bottom of the first channel layer 2121 extends beyond the first storage layer 2122 and connects to the first source layer 23. The first storage layer 2122 includes a tunneling insulating layer 2122a surrounding the first channel layer 2121, a charge trapping layer 2122b surrounding the tunneling insulating layer 2122a, and a blocking insulating layer 2122c surrounding the charge trapping layer 2122b. Exemplary materials for the blocking insulating layer 2122c and the tunneling insulating layer 2122a are silicon oxide, and for the charge trapping layer 2122b are silicon nitride, forming a silicon oxide-silicon nitride-silicon oxide (ONO) structure. The first channel layer 2121 may be polysilicon, but it will be appreciated that other materials may be selected for these layers.

[0097] Continue reading Figure 1a The second semiconductor structure 20 may further include a gate connection structure 24 (a first gate connection structure 24). The gate connection structure 24 extends along the first direction (Z) in the first stacked structure 211 and is connected to the gate layer 211a. Specifically, one end of the gate connection structure 24 is connected to the gate layer 211a, and the other end is connected to the second metal interconnect layer 22 via a contact structure. The first semiconductor structure 10 can transmit word line signals to the gate connection structure 24 through the first metal interconnect layer 13 and the second metal interconnect layer 22, thereby achieving control of the gate layer 211a.

[0098] The second semiconductor structure 20 may further include a bitline contact 25, which is connected to an end of the first channel structure 212 near the second metal interconnect layer 22. Specifically, the bitline contact 25 is connected between the second metal interconnect layer 22 and the first channel structure 212. The first semiconductor structure 10 can transmit a bitline signal to the first channel structure 212 through the first metal interconnect layer 13 and the second metal interconnect layer 22, thereby controlling the first channel structure 212.

[0099] In some embodiments, the second semiconductor structure 20 may further include a first array of through contacts 26. The first array of through contacts 26 is arranged parallel to the first memory array 21 in the first direction (Z). Specifically, the first array of through contacts 26 is arranged parallel to the first channel structure 212 in the first direction (Z). The first array of through contacts 26 connects the second metal interconnect layer 22 and the first source layer 23. Therefore, the first semiconductor structure 10 can apply a source signal to the first source layer 23 through the second metal interconnect layer 22 and the first array of through contacts 26.

[0100] The inventors have discovered that if the pad 40 is set on the side of the first semiconductor structure 10 close to the second semiconductor structure 20, or on the side of the second semiconductor structure 20 away from the first semiconductor structure 10, the first signal transmission structure 31 needs to pass through the stack of other components layer by layer to supply power to the source / drain / electrode doping areas, which not only occupies the space of the signal network composed of each metal interconnection layer, making it difficult to further shrink the size of the first semiconductor structure 10, but also the power density and voltage drop increase sharply, and the power loss is difficult to control below 10%.

[0101] In the semiconductor device 100 in the embodiment of the present application, the pad 40 is arranged on the surface of the first semiconductor structure 10 near the source / drain doped region 11, so that the first semiconductor structure 10 can be directly powered. This not only solves the winding pressure of each metal interconnect layer and avoids the wiring congestion problem of the back-end process, but also separates the power supply network and the signal network of the metal interconnect layer, alleviates the voltage drop problem, and improves performance.

[0102] See also Figure 2 , Figure 2 Schematic diagram of the structure of the semiconductor device provided by some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures in this embodiment as in the above embodiment, and the same structures are not described in detail. Only the different structures are described in detail in this embodiment.

[0103] The semiconductor device 200 is different from the semiconductor device 100 in FIG. 1 in that the semiconductor device 200 further includes a third semiconductor structure 50 , which is bonded to a side of the second semiconductor structure 20 away from the first semiconductor structure 10 .

[0104] The third semiconductor structure 50 includes a second memory array 51, a third metal interconnection layer 52 and a second source layer 53. The third metal interconnection layer 52 is located on a side of the second memory array 51 away from the second semiconductor structure 20. The second source layer 53 is located on a side of the second memory array 51 close to the first source layer 23 and is bonded to the first source layer 23.

[0105] The second storage array 51 may also include a second stacking structure 511 and a second channel structure 512 running through the second stacking structure 511 along the first direction (Z). The second stacking structure 511 may include gate layers (second gate layers) and interlayer insulating layers alternately stacked along the first direction (Z). The second channel structure 512 includes a second channel layer extending along the first direction (Z).

[0106] You can refer to Figure 1bThe first source layer 23 is connected to the end of the first channel layer 2121, and the second source layer 53 is connected to the end of the second channel layer. That is, the connection method between the second source layer 53 and the second channel layer is the same as the connection method between the first source layer 23 and the first channel layer 2121. Because the first source layer 23 and the second source layer 53 are bonded together, and the first source layer 23 is connected to the first semiconductor structure 10 via the first array of through contacts 26, the second source layer 53 can be connected to the first semiconductor structure 10 via the first source layer 23 and the first array of through contacts 26, so that the first semiconductor structure 10 can transmit a source signal to the second channel structure 512. Therefore, the same source signal is applied to the first source layer 23 and the second source layer 53. By connecting the second semiconductor structure 20 and the third semiconductor structure 50 to a common source, the storage capacity per unit area can be increased, and the two semiconductor structures can share a control circuit.

[0107] In some embodiments, the third semiconductor structure 50 may further include a fifth array through contact 54, wherein the fifth array through contact 54 is parallel to the second storage array 51 in the first direction (Z), and the second source layer 53 is connected to the third metal interconnection layer 52 through the fifth array through contact 54. In this way, the first array through contact 26 and the fifth array through contact 54 can jointly apply source signals to the first source layer 23 and the second source layer 53, which is conducive to improving driving efficiency.

[0108] In some embodiments, the third semiconductor structure 50 may further include a second gate connection structure 55, which extends along the first direction (Z) in the second stacked structure 511 and is connected to the second gate layer. One end of the second gate connection structure 55 is connected to the second gate 12, and the other end is connected to the third metal interconnect layer 52.

[0109] In some embodiments, the second semiconductor structure 20 may further include a third array through-contact 27, which is parallel to the first memory array 21 in the first direction (Z) and connected to the second metal interconnect layer 22. The third semiconductor structure 50 may further include a fourth array through-contact 56, which is parallel to the second memory array 51 in the first direction (Z) and connected to the third metal interconnect layer 52. The third array through-contact 27 and the fourth array through-contact 56 are bonded to each other. Therefore, the third metal interconnect layer 52 can be connected to the second metal interconnect layer 22 via the third array through-contact 27 and the fourth array through-contact 56, and further connected to the first metal interconnect layer 13 and the first semiconductor structure 10, thereby enabling the first semiconductor structure 10 to control the second memory array 51 (including the second channel structure 512 and the second gate layer).

[0110] In some embodiments, the third semiconductor structure 50 may further include a substrate 57 . The substrate 57 is located on a side of the second memory array 51 close to the third metal interconnection layer 52 .

[0111] See also Figure 3a-3b , Figure 3a is a schematic structural diagram of a semiconductor device provided by some embodiments of the present application, Figure 3b Some embodiments of this application provide Figure 3a Schematic diagram of the enlarged structure of the semiconductor device at B. For ease of understanding and brief description, the same reference numerals are used for the same structures in this embodiment as in the above embodiment, and the same structures are not described in detail again. Only the different structures are described in detail in this embodiment.

[0112] The difference between the semiconductor device 300 and the semiconductor device 100 in FIG. 1 is that the second metal interconnection layer 22 is located on a side of the first memory array 21 away from the first semiconductor structure 10 , and the first source layer 23 is located on a side of the first memory array 21 close to the first semiconductor structure 10 .

[0113] In some embodiments, the first channel structure 212 includes a first channel layer 2121 and a first storage layer 2122' surrounding the sidewalls and bottom of the first channel layer 2121, the sidewalls of the first storage layer 2122' having openings to expose the sidewalls of the first channel layer 2121, and the first source layer 23 is connected to the sidewalls of the first channel layer 2121.

[0114] In some embodiments, the second semiconductor structure 20 includes not only the first source layer 23 but also a substrate 28 located on a side of the first source layer 23 away from the first memory array 21. The bottom of the first channel structure 212 is located in the substrate 28. The first semiconductor structure 10 may be connected to the substrate 28.

[0115] In some embodiments, the semiconductor device 300 further includes a substrate 60 located in the second metal interconnection layer 22 away from the first semiconductor structure 10 .

[0116] Because the second metal interconnect layer 22 and the first metal interconnect layer 13 are located on both sides of the first memory array 21, in order to enable the first semiconductor structure 10 to control the second semiconductor structure 20, the second semiconductor structure 20 further includes a second array through-contact (not shown). The second array through-contact is arranged parallel to the first memory array 21 in the first direction (Z). The second array through-contact is located at the periphery of the first memory array 21 and connects the first metal interconnect layer 13 and the second metal interconnect layer 22.

[0117] The semiconductor device provided in the embodiment of the present application includes a first semiconductor structure 10, a second semiconductor structure 20, a first signal transmission structure 31 and a pad 40. The first semiconductor structure 10 includes a transistor T, which includes a source / drain doped region 11 and a gate 12. The second semiconductor structure 20 is connected to a side of the first semiconductor structure 10 close to the gate 12. The first signal transmission structure 31 is connected to a side of the source / drain doped region 11 away from the gate 12. The pad 40 is located on a side of the first semiconductor structure 10 away from the second semiconductor structure 20 and includes a first pad 41 connected to the first signal transmission structure 31. The present application sets the first pad 41 on a side of the first semiconductor structure 10 close to the source / drain doped region 11, so that the source / drain doped region 11 can be powered directly through the first signal transmission structure 31, thereby reducing the voltage drop of the first signal transmission structure 31.

[0118] See also Figure 4 , Figure 4 This is a flow chart of a method for preparing a semiconductor device according to some embodiments of the present application. Figures 5a-5c , Figures 5a-5c This is a schematic diagram of the structure of the semiconductor device provided in some embodiments of the present application during the preparation process. This embodiment takes the preparation of the above-mentioned semiconductor device as an example to illustrate the preparation method of the semiconductor device, so please refer to the following examples: Figure 1a-1b 、 Figure 2 and Figure 3a-3b The method for preparing the semiconductor device includes the following steps S1-S5.

[0119] Step S1 : forming a first semiconductor structure 10 , wherein the first semiconductor structure 10 includes a transistor T, and the transistor T includes a source / drain doped region 11 and a gate 12 .

[0120] like Figure 5a As shown, a semiconductor layer 101 is first provided, and then source / drain doped regions 11 are formed in the semiconductor layer 101. Subsequently, a gate insulating layer (not shown) and a gate electrode 12 are formed on the surface of the semiconductor layer 101 (on the source / drain doped regions 11). A first metal interconnection layer 13 is then formed on a side of the gate electrode 12 away from the source / drain doped regions 11, wherein the first metal interconnection layer 13 is connected to the gate electrode 12 and the semiconductor layer 101.

[0121] In some embodiments, before forming the first metal interconnection layer 13, a connection contact 14 can also be formed on the side of the source / drain doping region 11 away from the first signal transmission structure 31, and the connection contact 14 connects the gate 12 and the first metal interconnection layer 13, and connects the semiconductor layer 101 and the first metal interconnection layer 13.

[0122] Step S2: forming a second semiconductor structure 20 .

[0123] like Figure 5b As shown, step S2 may include the following steps.

[0124] 1) forming a first memory array 21, wherein the first memory array 21 includes a first stacked structure 211 and a first channel structure 212 extending through the first stacked structure 211 along a first direction (Z), wherein the first stacked structure 211 includes alternately stacked gate layers (first gate layers) and interlayer insulating layers, and the first channel structure 212 includes a first channel layer extending along the first direction (Z) (refer to Figure 1b ).

[0125] Specifically, a substrate is first provided, and then a first stacking structure 211, a first channel structure 212 penetrating the first stacking structure 211, a first gate connection structure 24 connected to the first gate layer, a bit line contact 25 located on the top of the first channel structure 212, and a first array penetrating contact 26 parallel to the first channel structure 212 are formed on the substrate.

[0126] 2) Forming a second metal interconnection layer 22 on one side of the first memory array 21 along the first direction (Z).

[0127] Specifically, a second metal interconnection layer 22 may be formed on a side of the first memory array 21 away from the first source layer 23 , and the second metal interconnection layer 22 is connected to the first channel structure 212 , the first gate connection structure 24 and the first array through-contact 26 .

[0128] 3) A first source layer 23 is formed on a side of the first memory array 21 away from the second metal interconnection layer 22 , wherein the first source layer 23 is connected to the first channel layer 2121 , and the first source layer 23 is connected to the second metal interconnection layer 22 via a first array through contact 26 .

[0129] In some embodiments, reference may be made to Figure 1b , the substrate is removed to form a first source layer 23 connected to the end of the first channel layer 2121 , and the first source layer 23 is also connected to the first array through contact 26 .

[0130] In some embodiments, reference may be made to Figure 3b , a first source layer 23 connected to the sidewall of the first channel layer 2121 may be formed.

[0131] Step S3 : connecting the second semiconductor structure 20 to a side of the first semiconductor structure 10 close to the gate 12 .

[0132] In some embodiments, as Figure 5c As shown, the first metal interconnection layer 13 and the second metal interconnection layer 22 may be bonded to bond the first semiconductor structure 10 and the second semiconductor structure 20 .

[0133] In some embodiments, as Figure 3a As shown, the first metal interconnection layer 13 may be connected to a side of the second semiconductor structure 20 close to the first source layer 23 to connect the first semiconductor structure 10 and the second semiconductor structure 20 .

[0134] Step S4 : forming a first signal transmission structure 31 connected to a side of the source / drain doping region 11 away from the gate 12 .

[0135] Reference Figure 1a and Figure 3a An etching process can be performed on the surface of the semiconductor layer 101 away from the gate 12 to form a first signal transmission structure 31 connected to the source and drain doped regions. The first signal transmission structure 31 may include a conductive layer and a dielectric layer surrounding the sidewalls of the conductive layer.

[0136] The preparation of the semiconductor device may further include forming a second signal transmission structure 32 extending along the first direction (Z) within the first semiconductor structure 10. Specifically, the second signal transmission structure 32 penetrating the semiconductor layer 101 may be formed during the process of forming the first signal transmission structure 31. The second signal transmission structure 32 may be made of the same material as the first signal transmission structure 31.

[0137] Step S5 : forming a pad 40 on a side of the first semiconductor structure 10 away from the second semiconductor structure 20 , wherein the pad 40 includes a first pad 41 connected to the first signal transmission structure 31 .

[0138] like Figure 1a and Figure 3a As shown, specifically, before forming the first pad 41, a lead-out structure 102 is first formed on a side of the semiconductor layer 101 away from the gate 12, and then the first pad 41 and the second pad 42 are formed on a side of the lead-out structure 102 away from the semiconductor layer 101. The first signal transmission structure 31 connects the first metal interconnect layer 13 and the first pad 41, and the second signal transmission structure 32 connects the first metal interconnect layer 13 and the second pad 42.

[0139] See also Figure 6a-6b , Figure 6a-6b This is a schematic diagram of the structure of the semiconductor device provided in some embodiments of the present application during the preparation process. Based on step S3 ( Figure 5c ), the method for preparing the semiconductor device further includes the following steps.

[0140] 1) If Figure 6a As shown, a third semiconductor structure 50 is formed, and the third semiconductor structure 50 includes a second memory array 51, a third metal interconnection layer 52 and a second source layer 53. The second memory array 51 includes a second stacked structure 511 and a second channel structure 512 that penetrates the second stacked structure 511 along the first direction (Z). The second channel structure 512 includes a second channel layer extending along the first direction (Z), and the second source layer 53 is connected to the end of the second channel layer.

[0141] In some embodiments, the method of forming the third semiconductor structure 50 may be the same as the method of forming the second semiconductor structure 20 described above.

[0142] 2) If Figure 6b As shown, the second source layer 53 is bonded to the first source layer 23 .

[0143] exist Figure 6b Based on the bonding, step S4 and step S5 are performed to obtain Figure 2 A semiconductor structure 200 is shown.

[0144] In the method for preparing a semiconductor device provided in an embodiment of the present application, when the first semiconductor structure 10 and the second semiconductor structure 20 (and the third semiconductor structure 50) are connected, a pad 40 is formed on a side of the first semiconductor structure 10 close to the first source / drain doping region 11, so that power can be directly supplied to the source / drain doping region 11 through the first signal transmission structure 31, thereby reducing the voltage drop of the first signal transmission structure 31.

[0145] See also Figure 7 , Figure 7 4 is a schematic diagram of the structure of a storage system provided in some embodiments of the present application. The storage system 400 includes a semiconductor device 401 and a controller 402. The semiconductor device 401 may include any of the semiconductor devices in the above embodiments. The controller 402 is connected to the semiconductor device 401 and is used to control the semiconductor device 401 to store data. The semiconductor device 401 can perform data storage operations based on the control of the controller 402.

[0146] In some embodiments, the storage system may be implemented as a storage device such as a Universal Flash Storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a PCI-Express (PCI-E) type storage device, a Compact Flash (CF) card, a smart media card or a memory stick, etc.

[0147] The semiconductor device 401 includes: the first semiconductor structure as described above, including a transistor, the transistor including a source / drain doped region and a gate; a second semiconductor structure, connected to a side of the first semiconductor structure close to the gate; a first signal transmission structure, connected to a side of the source / drain doped region away from the gate; a pad, located on a side of the first semiconductor structure away from the second semiconductor structure, and including a first pad connected to the first signal transmission structure.

[0148] The description of the above embodiments is only used to help understand the technical solutions and core ideas of this application; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A first semiconductor structure includes a transistor, wherein the transistor includes source / drain doped regions and a gate; a second semiconductor structure connected to a side of the first semiconductor structure close to the gate; a first signal transmission structure connected to a side of the source / drain doping region away from the gate; The pad is located on a side of the first semiconductor structure away from the second semiconductor structure and includes a first pad connected to the first signal transmission structure.

2. The semiconductor device according to claim 1, wherein The first semiconductor structure further includes: The first metal interconnection layer is located on a side of the gate away from the source / drain doping region.

3. The semiconductor device according to claim 2, wherein The pad further includes a second pad, and the second pad is located on a side of the first semiconductor structure away from the second semiconductor structure, and the semiconductor device further includes: The second signal transmission structure extends along a first direction in the first semiconductor structure and connects the first metal interconnection layer and the second pad.

4. The semiconductor device according to claim 3, wherein The second semiconductor structure includes: A first memory array includes a first stacked structure and a first channel structure extending along the first direction through the first stacked structure, wherein the first stacked structure includes alternately stacked gate layers and interlayer insulating layers, and the first channel structure includes a first channel layer extending along the first direction; a second metal interconnection layer, located on one side of the first memory array along the first direction; The first source layer is located on a side of the first memory array away from the second metal interconnection layer, and the first source layer is connected to the first channel layer.

5. The semiconductor device according to claim 4, wherein The second metal interconnection layer is located between the first memory array and the first metal interconnection layer, and the first metal interconnection layer is connected to the second metal interconnection layer through a bonding layer.

6. The semiconductor device according to claim 4, wherein The second metal interconnection layer is located on a side of the first memory array away from the first semiconductor structure, and the first source layer is connected to a sidewall of the first channel structure.

7. The semiconductor device according to claim 6, wherein: The second semiconductor structure further includes: A first array of through contacts and a second array of through contacts are both arranged parallel to the first storage array in the first direction; The first array of through contacts connects the second metal interconnection layer and the first source layer, and the second array of through contacts connects the first metal interconnection layer and the second metal interconnection layer.

8. The semiconductor device according to claim 4, wherein The second semiconductor structure further includes: a gate connection structure, extending along the first direction in the first stacked structure and connected to the gate layer; a bit line contact connected to one end of the first channel structure close to the second metal interconnection layer; The gate connection structure and the bit line contact are respectively connected to the second metal interconnection layer.

9. The semiconductor device according to claim 4, wherein: The semiconductor device further includes a third semiconductor structure, wherein the third semiconductor structure is bonded to a side of the second semiconductor structure away from the first semiconductor structure; The third semiconductor structure includes: a second memory array comprising a second stacked structure and a second channel structure penetrating the second stacked structure along the first direction, wherein the second channel structure comprises a second channel layer extending along the first direction; a third metal interconnection layer, located on a side of the second memory array away from the second semiconductor structure; The second source layer is connected to an end portion of the second channel layer and is bonded to the first source layer.

10. The semiconductor device according to claim 9, wherein The second semiconductor structure further includes a third array of through contacts parallel to the first memory array in the first direction, the third array of through contacts being connected to the second metal interconnect layer; The third semiconductor structure further includes a fourth array of through contacts parallel to the second memory array in the first direction, the fourth array of through contacts being connected to the third metal interconnect layer; The third array of through contacts and the fourth array of through contacts are bonded together.

11. The semiconductor device according to claim 9, wherein The third semiconductor structure further includes a fifth array of through contacts parallel to the second memory array in the first direction, and the second source layer is connected to the third metal interconnection layer through the fifth array of through contacts.

12. The semiconductor device according to claim 3, wherein The first semiconductor structure further includes: A connection contact is located on a side of the source / drain doped region away from the first signal transmission structure, the connection contact connects the gate and the first metal interconnection layer, and connects the second signal transmission structure and the first metal interconnection layer.

13. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises: forming a first semiconductor structure, the first semiconductor structure including a transistor, the transistor including source / drain doped regions and a gate; forming a second semiconductor structure; connecting the second semiconductor structure to a side of the first semiconductor structure close to the gate; forming a first signal transmission structure connected to a side of the source / drain doped region away from the gate; A pad is formed on a side of the first semiconductor structure away from the second semiconductor structure, and the pad includes a first pad connected to the first signal transmission structure.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The step of forming the first semiconductor structure includes: providing a semiconductor layer; forming source / drain doped regions in the semiconductor layer; forming a gate on the source / drain doped region; A first metal interconnection layer is formed on a side of the gate away from the source / drain doping region.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The step of forming the second semiconductor structure includes: forming a first memory array, the first memory array comprising a first stacked structure and a first channel structure penetrating the first stacked structure along a first direction, the first stacked structure comprising alternately stacked gate layers and interlayer insulating layers, and the first channel structure comprising a first channel layer extending along the first direction; forming a second metal interconnection layer on one side of the first memory array along the first direction; A first source layer is formed on a side of the first memory array away from the second metal interconnection layer, and the first source layer is connected to the first channel layer.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The step of connecting the second semiconductor structure to a side of the first semiconductor structure close to the gate comprises: The first metal interconnection layer and the second metal interconnection layer are connected through a bonding metal layer.

17. The method for manufacturing a semiconductor device according to claim 15, wherein: The step of connecting the second semiconductor structure to a side of the first semiconductor structure close to the gate comprises: Connecting a side of the second semiconductor structure close to the first source layer to the first metal interconnection layer.

18. The method for manufacturing a semiconductor device according to claim 14, wherein: The pad further includes a second pad, and the method for preparing the semiconductor device further includes: A second signal transmission structure extending along a first direction is formed in the first semiconductor structure, wherein the second signal transmission structure connects the first metal interconnection layer and the second pad.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The step of forming the first semiconductor structure further includes: Before forming the first metal interconnection layer, a connection contact is formed on a side of the source / drain doped region away from the first signal transmission structure, wherein the connection contact connects the gate and the first metal interconnection layer, and connects the second signal transmission structure and the first metal interconnection layer.

20. The method for manufacturing a semiconductor device according to claim 15, wherein: The method for preparing the semiconductor device further includes: forming a third semiconductor structure, the third semiconductor structure comprising a second memory array, a third metal interconnect layer, and a second source layer, the second memory array comprising a second stacked structure and a second channel structure penetrating the second stacked structure along the first direction, the second channel structure comprising a second channel layer extending along the first direction, and the second source layer being connected to an end of the second channel layer; The second source layer is bonded to the first source layer.

21. A storage system, characterized in that: include: The semiconductor device according to any one of claims 1 to 12; A controller is connected to the semiconductor device and is used to control the semiconductor device to store data.

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