Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, a well region, a gate structure, a first insulating pillar, a pair of first dielectric spacers, and a contact member. The silicon carbide substrate has a first region and a second region, and has a first conductivity type. The epitaxial layer is disposed on the silicon carbide substrate and has a first conductivity type. The well region is located in the epitaxial layer and has a second conductive type. The gate structure is disposed in the epitaxial layer of the first region. The first insulating column is arranged right above the gate structure and protrudes out of the top surface of the epitaxial layer. The first dielectric spacer is disposed on opposite sidewalls of the first insulating post. A contact feature extends from above the epitaxial layer into the well region. A first sidewall of the contact feature in the epitaxial layer is aligned with a first outer sidewall of one of the pair of first dielectric spacers.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a power transistor device with a self-aligned contact feature and a method for forming the same. Background Art

[0002] The semiconductor industry continues to improve the integration density of various electronic components by continuously reducing the minimum component size, allowing more components to be integrated into a given area. For example, the trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET), widely used in power switch devices, utilizes a vertical structure design to reduce the cell pitch to increase functional density. It uses the back of the chip as the drain, while the source and gate of multiple transistors are fabricated on the front of the chip. As a result, the driving current flows in a vertical direction instead of in-plane, which enables the semiconductor device to achieve high reverse voltage resistance and low on-resistance.

[0003] However, as the functional density requirements for semiconductor devices continue to increase, the complexity of the components integrated into semiconductor devices and their formation methods has also increased, and there are certain electronic characteristics that require trade-offs in performance that need to be considered. Therefore, although existing semiconductor devices are generally suitable and sufficient for their intended purposes, they are not completely satisfactory in all aspects. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, a well region, a gate structure, a first insulating pillar, a pair of first dielectric spacers, and a contact component. The silicon carbide substrate has a first region and a second region and has a first conductivity type. The epitaxial layer is disposed on the top surface of the silicon carbide substrate. The epitaxial layer has a first conductivity type. The well region is located in the epitaxial layer. The well region has a second conductivity type. The gate structure is disposed in the epitaxial layer of the first region. The gate structure extends along a first direction. The first insulating pillar is disposed directly above the gate structure and protrudes from the top surface of the epitaxial layer along the first direction. The pair of first dielectric spacers are disposed on opposite sidewalls of the first insulating pillar. The contact component extends from above the epitaxial layer into the well region. The first sidewall of the contact component in the epitaxial layer is aligned with the first outer sidewall of one of the pair of first dielectric spacers.

[0005] Some embodiments of the present invention provide a method for forming a semiconductor device. The method includes providing a silicon carbide substrate having a first region and a second region and having a first conductivity type; growing an epitaxial layer on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; forming a first trench in the epitaxial layer in the first region along a first direction; forming an electrode material column in the first trench; oxidizing the top of the electrode material column to form a first insulating column, and forming an unoxidized electrode material column in the first trench to form a gate electrode, wherein the first insulating column protrudes from the top surface of the epitaxial layer along the first direction; forming a pair of first dielectric spacers on opposite sidewalls of the first insulating column; performing an etching process using an etching mask on the first dielectric spacer to form a contact hole in the epitaxial layer; and forming a contact component in the contact hole.

[0006] Some embodiments of the present invention provide semiconductor devices and methods for forming the same, which can avoid contact-trench overlay errors and subsequent photoresist rework problems caused by conventional photolithography processes, improve the electrical uniformity and reliability of semiconductor devices, and save high-resolution mask and photolithography process costs when device density is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description will provide a better understanding of the present invention when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are provided for illustrative purposes only. Indeed, the dimensions of the elements may be arbitrarily increased or decreased to clearly illustrate the features of the present invention.

[0008] Figure 1 Schematic cross-sectional views of semiconductor devices according to some embodiments of the present invention.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 To form Figure 1 FIG2 is a schematic cross-sectional view of a semiconductor device at an intermediate stage according to some embodiments of the present invention.

[0010] Reference numerals:

[0011] 100:Silicon carbide substrate

[0012] 100T,200T,210T,216ART,220F2-T,220AT,220BT,224BT,230GT,230T,OP1T,OP1T',OP2T: Top

[0013] 100B, 212AB, 212A-B, 212B-B, 234B, 244B: bottom

[0014] 200: epitaxial layer

[0015] 202,202P: Pad oxide layer

[0016] 204: first mask layer

[0017] 204P: First mask pattern

[0018] 206: second mask layer

[0019] 206P: Second mask pattern

[0020] 208,208P: Anti-reflection layer

[0021] 210: mask layer

[0022] 210P: Mask pattern

[0023] 212A, 212B: Grooves

[0024] 212A-S, 212B-S, 244S: Sidewall

[0025] 216, 216AR, 216B, 216BR: shielding dielectric layer

[0026] 220A, 220B, 220AR, 220BR: Conductive materials

[0027] 220F1: First electrode

[0028] 220F2: Second electrode

[0029] 220ART:Top

[0030] 224A, 224A-1, 224A-2: Gate dielectric layer

[0031] 224B: Oxide layer

[0032] 230:Electrode material column

[0033] 230G: Gate electrode

[0034] 236: Source region

[0035] 232: Gate structure

[0036] 234: Well region

[0037] 240,240R: Interlayer dielectric layer

[0038] 240T1, 240T2: Upper surface

[0039] 240S: Dielectric spacer

[0040] 240SE: Outer wall

[0041] 244: Contact hole

[0042] 246: contact doping region

[0043] 250: Contact parts

[0044] 212A-S,250S1,250S2,OP1S:Sidewall

[0045] 254:Metal layer

[0046] 300,310: Direction

[0047] 400: District 1

[0048] 400M: table area

[0049] 410: District 2

[0050] 500:Semiconductor devices

[0051] D1, D2, S1: distance

[0052] H1,H2,H3,T1:Thickness

[0053] OP1, OP2: Insulation column

[0054] PR1, PR2: Photoresist pattern

[0055] WM: Countertop width

[0056] W1, W2, W3, W4: width DETAILED DESCRIPTION

[0057] The present invention is more fully described below with reference to the accompanying drawings illustrating embodiments of the present invention. However, the present invention may be implemented in a variety of different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers in the various drawings represent the same or similar elements. It will be understood that additional steps may be provided before, during, or after the method, and that some described steps may be replaced or deleted for other embodiments of the method.

[0058] Various embodiments or examples are provided below for implementing various components of the provided semiconductor structure. Reference to a first component being formed above a second component may include embodiments in which the first and second components are in direct contact, as well as embodiments in which an additional component is formed between the first and second components, preventing direct contact. Furthermore, embodiments of the present invention may use repeated reference numerals across multiple examples. This repetition is for simplicity and clarity purposes only and does not represent a specific relationship between the various embodiments and / or configurations discussed.

[0059] Furthermore, spatially relative terms such as "below," "beneath," "below," "above," "upper," and similar terms may be used in the following description to simplify the description of the relationship of one element or component to other elements or components as shown in the figures. Such spatially relative terms encompass not only the orientation depicted in the figures, but also different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0060] In a high-density shielded gate trench MOSFET (SGT MOSFET) cell array, expensive high-resolution masks (such as deep ultraviolet (DUV) masks) and photolithography processes are required to form source contacts between adjacent transistor cells. However, during the known source contact process, photoresist rework problems often occur due to errors in contact-to-trench overlay, which increases process costs and production cycles. In addition, the above-mentioned contact-to-trench overlay errors will cause uneven electrical parameters of adjacent transistor cells, thereby failing to pass device reliability tests (such as UIS (Unclamped Inductive Switching) electrical tests) and may even cause device burnout. Therefore, it is necessary to seek a semiconductor device of an isolated gate trench MOSFET and a method for forming the same that can solve or improve the above-mentioned problems.

[0061] Figure 1 Schematic cross-sectional view of a semiconductor device 500 according to some embodiments of the present invention. In some embodiments, the semiconductor device 500 includes a power metal oxide semiconductor field effect transistor (power MOSFET), such as an isolated gate trench metal oxide semiconductor field effect transistor (SGT MOSFET). Figure 1As shown, the semiconductor device 500 includes a silicon carbide (SiC) substrate 100 , an epitaxial layer 200 , a well region 234 , a gate structure 232 , an insulating pillar OP1 , a dielectric spacer 240S, and a contact feature 250 .

[0062] like Figure 1 As shown, the silicon carbide substrate 100 has a top surface 100T and a bottom surface 100B. In addition, the silicon carbide substrate 200 has a first region 400 and a second region 410. In some embodiments, the first region 400 may be a cell region in which a power metal oxide semiconductor field effect transistor array is formed. In addition, the second region 410 may be a termination region, which is used to surround the cell region to serve as a buffer zone for the doped region in the cell region to prevent the breakdown voltage of the device at the boundary of the cell region from dropping sharply. In the embodiments below, in the cell region, the structure of two isolation gate trench metal oxide semiconductor field effect transistor units is described. In addition, in the termination region, the structure of one trench electrode (e.g., source electrode) is described. However, any number of isolation gate trench metal oxide semiconductor field effect transistor units and trench electrodes may be provided in the cell region and the termination region, and are not limited to the embodiments described herein.

[0063] In some embodiments, the conductivity type of the silicon carbide substrate 100 can be P-type or N-type depending on design requirements. In this embodiment, the silicon carbide substrate 100 can be doped with dopants to have a first conductivity type, such as N-type. In applications involving vertical trench-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), the silicon carbide substrate 200 having the first conductivity type can serve as the drain region of the final semiconductor device 500.

[0064] The epitaxial layer 200 is disposed on the top surface 100T of the silicon carbide substrate 100. In some embodiments, the epitaxial layer 200 may be doped with dopants to have a first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the epitaxial layer 200 is an N-type epitaxial layer 200. Furthermore, the doping concentration of the epitaxial layer 200 (e.g., about 10 15 -10 16 atoms / cm 3 ) is less than the doping concentration of the silicon carbide substrate 100 (10 19 -10 21 atoms / cm 3For example, when the silicon carbide substrate 100 is an N-type heavily doped (N+) silicon carbide substrate 100, the epitaxial layer 200 is an N-type lightly doped (N-) epitaxial layer 200. In applications of vertical trench-gate metal oxide semiconductor field effect transistors (vertical trench-gate MOSFETs), the epitaxial layer 200 having the first conductivity type can serve as a drift region of the final semiconductor device 500. In some embodiments, the epitaxial layer 200 comprises silicon carbide.

[0065] The well region 234 of the semiconductor device 500 is located in the epitaxial layer 200 in the first region 400 and the second region 410 and is close to the top surface 200T of the epitaxial layer 200. In some embodiments, the well region 234 may be doped with dopants to have a second conductivity type opposite to the first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the well region 234 is a P-type well region 234. In addition, the above-mentioned dopant with the second conductivity type may include aluminum (Al), boron (B) or other suitable dopants. In some embodiments, the doping concentration of the well region 234 (e.g., about 10 17 -10 18 atoms / cm 3 ) is greater than the doping concentration of the epitaxial layer 200. In some embodiments, the well region 234 may be formed using an ion implantation process. In applications of vertical trench-gate metal-oxide-semiconductor field-effect transistors, the well region 234 having the second conductivity type may serve as the channel region of the final semiconductor device 500.

[0066] The source region 236 of the semiconductor device 500 is located on the well region 234 in the first region 400 and is close to the top surface 200T of the epitaxial layer 200. In addition, the second region 410 may not have the source region 236. Figure 1 As shown, the source region 236 is surrounded by the well region 234. In some embodiments, the source region 236 may be doped with a dopant to have a first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the source region 236 is an N-type source region 236. Furthermore, the doping concentration of the source region 236 is greater than the doping concentration of the epitaxial layer 200. For example, when the epitaxial layer 200 is an N-type lightly doped (N-) epitaxial layer 200, the source region 236 is an N-type heavily doped (N+) source region 236.

[0067] exist Figure 1In the embodiment shown, two gate structures 232 are disposed in the epitaxial layer 200 of the first region 400. The two gate structures 232 are separated from each other by the epitaxial layer 200 along a direction 300 (substantially parallel to the top surface 100T of the silicon carbide substrate 100, which can also be considered a lateral direction). Furthermore, the region of the epitaxial layer 200 located between the two gate structures 232 can be considered as a mesa region 400M of the semiconductor device 500. Figure 1 As shown, the gate structure 232 extends along a direction 310 (substantially perpendicular to the top surface 100T of the silicon carbide substrate 100 and substantially perpendicular to the direction 300, which may also be considered a longitudinal direction). In some embodiments, the gate structure 232 includes a gate dielectric layer 224A and a gate electrode 230G.

[0068] The gate dielectric layer 224A extends from the top surface 200T of the epitaxial layer 200 in the first region 400 along a direction 310 into the epitaxial layer 200. In some embodiments, the gate dielectric layer 224A may be silicon oxide, other suitable dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 224A may be formed using an oxidation process. In some embodiments, the oxidation process may include thermal oxidation or other suitable processes.

[0069] The gate electrode 230G is located on the gate dielectric layer 224A. Figure 1 As shown, the top surface 230GT of the gate electrode 230G may be lower than the top surface 200T of the epitaxial layer 200. In addition, the gate dielectric layer 224A covers the bottom surface and the opposite sidewalls of the gate electrode 230G. In some embodiments, the gate electrode 230G may be a single-layer or multi-layer structure, which is formed by amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. In some embodiments, the metal may include but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt). In some embodiments, the metal nitride may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include but is not limited to tungsten silicide (WSi). x In some embodiments, the gate electrode 230G may optionally include a dopant of the second conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the gate electrode 230G is a P-type gate electrode 230G. Furthermore, the dopant of the second conductivity type may include aluminum (Al), boron (B), boron difluoride (BF2), or other suitable dopants.

[0070] The semiconductor device 500 further includes a shielding dielectric layer 216AR and a first electrode 220F1. Figure 1As shown, a shielding dielectric layer 216AR and a first electrode 220F1 are disposed in the epitaxial layer 200 in the first region 400. The first electrode 220F1 is located directly below the gate structure 232 and extends toward the silicon carbide substrate 100 along a direction 310. The first electrode 220F1 is located on the shielding dielectric layer 216AR, and the shielding dielectric layer 216AR covers the bottom surface and opposite sidewalls of the first electrode 220F1. Furthermore, the first electrode 220F1 is separated from the gate electrode 230G by a gate dielectric layer 224A near the top surface of the gate electrode 230G.

[0071] In some embodiments, the first electrode 220F1 not only reduces the gate-to-drain capacitance (Cgd) to improve the switching characteristics of the semiconductor device 500, but also has a field plate function, making the electric field distribution of the gate dielectric layer 224A near the bottom of the gate electrode 230G more uniform and increasing the breakdown voltage, thereby improving the reliability of the gate dielectric layer 224A.

[0072] The semiconductor device 500 further includes a shielding dielectric layer 216BR and a second electrode 220F2. Figure 1 As shown, a shielding dielectric layer 216BR and a second electrode 220F2 are disposed in the epitaxial layer 200 in the second region 410. The second electrode 220F2 extends from a position close to the top surface 200T of the epitaxial layer 200 toward the silicon carbide substrate 100 along a direction 310. The second electrode 220F2 is located on the shielding dielectric layer 216BR, and the shielding dielectric layer 216BR covers the bottom surface and opposite sidewalls of the second electrode 220F2.

[0073] In some embodiments, the shielding dielectric layers 216AR and 216BR may include the same material. For example, the shielding dielectric layers 216AR and 216BR may include silicon oxide, other suitable semiconductor oxide materials, or a combination thereof. In some embodiments, the shielding dielectric layers 216AR and 216BR and the gate dielectric layer 224A may be made of the same or different materials depending on actual needs. In some embodiments, the shielding dielectric layers 216AR and 216BR may be formed using a conformable deposition process, an oxidation process, or other suitable formation process. In some embodiments, the oxidation process may be thermal oxidation or other suitable process. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, other suitable processes, or a combination thereof.

[0074] In some embodiments, the first electrode 220F1 and the second electrode 220F2 may comprise the same or different material as the gate electrode 230G. In some embodiments, the first electrode 220F1 and the second electrode 220F2 may optionally include a dopant of the second conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the first electrode 220F1 and the second electrode 220F2 are a P-type first electrode 220F1 and a P-type second electrode 220F2, respectively. Furthermore, the dopant of the second conductivity type may include aluminum (Al), boron (B), boron difluoride (BF2), or other suitable dopants.

[0075] The insulating column OP1 is located in the first region 400. The insulating column OP1 is disposed directly above the gate structure 232 and protrudes from the top surface 200T of the epitaxial layer 200 along the direction 310. Figure 1 As shown, the insulating pillar OP1 completely covers and contacts the top surface 230GT of the gate electrode 230G. In the direction 300, the width W1 of the gate electrode 230G may be the same as the width W2 of the insulating pillar OP1. In some embodiments, the insulating pillar OP1 may include silicon oxide, other suitable semiconductor oxide materials, or a combination thereof. In some embodiments, the insulating pillar OP1 may be formed using an oxidation process or other suitable formation process. In some embodiments, the oxidation process may be thermal oxidation or other suitable process.

[0076] The semiconductor device 500 further includes an insulating column OP2. The insulating column OP2 is located in the second region 410 and is disposed directly above the second electrode 220F2 and protrudes from the top surface 200T of the epitaxial layer 200 along the direction 310. Figure 1 As shown, insulating pillar OP2 completely covers and contacts the top surface 220F2-T of second electrode 220F2. In direction 300, width W3 of second electrode 220F2 is the same as width W4 of insulating pillar OP2. In some embodiments, width W4 is less than width W2. In direction 310, distance D1 between top surface OP1T' of insulating pillar OP1 and top surface 200T of epitaxial layer 200 is greater than distance D2 between top surface OP2T of insulating pillar OP2 and top surface 200T of epitaxial layer 200. In some embodiments, insulating pillars OP1 and OP2 may comprise the same or similar materials or processes.

[0077] The semiconductor device 500 includes one or more pairs of dielectric spacers 240S, which are respectively disposed on opposite sidewalls of the insulating pillar OP1. Figure 1In one embodiment, the semiconductor device 500 includes two pairs of dielectric spacers 240S. In some embodiments, the dielectric spacers 240S may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glass (OSG), a low-k dielectric material, and / or other suitable dielectric materials, or combinations thereof. In some embodiments, the dielectric spacers 240S may be formed using a conformable deposition process, other suitable formation processes, and a subsequent etch-back process. In some embodiments, the deposition process may include spin-on coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), other suitable processes, or combinations thereof.

[0078] like Figure 1 As shown, the contact member 250 is disposed between two adjacent gate structures 232 along the direction 300. Furthermore, the contact member 250 is disposed between two adjacent pairs of dielectric spacers 240S along the direction 300. Figure 1 As shown in FIG. 1 , the contact members 250 are respectively adjacent to the two dielectric spacers 240S in the two pairs of dielectric spacers 240S that are close to each other. Figure 1As shown, the contact feature 250 is adjacent to one of the left pair of dielectric spacers 240S and one of the right pair of dielectric spacers 240S. The contact feature 250 extends along direction 310 into a portion of the epitaxial layer 200. Furthermore, the contact feature 250 extends along direction 310 from above the epitaxial layer 200 into the well region 234 of the first region 400 and is located above the bottom surface 234B of the well region 234. In some embodiments, the sidewalls 250S1 and 250S2 of the contact feature 250 on the top surface 200T of the epitaxial layer 200 respectively contact the outer sidewalls 240SE of the two adjacent dielectric spacers 240S in the two pairs of dielectric spacers 240S. In other words, there are no other features between the sidewalls 250S1 and 250S2 of the contact feature 250 and the two adjacent dielectric spacers 240S. Furthermore, the sidewalls 250S1 and 250S2 of the contact member 250 in the epitaxial layer 200 are respectively aligned with the outer sidewalls 240SE of the two adjacent dielectric spacers 240S in the two pairs of dielectric spacers 240S. The outer sidewalls 240SE of the dielectric spacers 240S are away from the corresponding insulating pillars OP1.

[0079] In some embodiments, the contact member 250 may include a contact barrier layer (not shown) and a contact conductive layer (not shown). In some embodiments, the contact barrier layer may be used to prevent the subsequently formed contact conductive layer from diffusing into the dielectric spacer 240S (interlayer dielectric layer). The material of the contact barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), other suitable barrier materials, or combinations thereof. In some embodiments, the contact barrier layer may be formed using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or combinations thereof.

[0080] In some embodiments, the contact conductive layer of the contact member 250 may be a single layer or a multilayer structure. The contact conductive layer may be made of tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), other suitable metals, or combinations thereof. In some embodiments, the contact conductive layer may be formed using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, other suitable processes, or combinations thereof.

[0081] like Figure 1As shown, semiconductor device 500 further includes a metal layer 254. Metal layer 254 covers contact feature 250 and is in physical and electrical contact with contact feature 250. Metal layer 254 may serve as the top metal layer of the final semiconductor device 500 and may be electrically connected to source region 236 and well region 234 via contact feature 250. Therefore, it may also be referred to as a source metal layer 254. Furthermore, metal layer 254 may also be electrically connected to first electrode 220F1 and first electrode 220F1 via other interconnects (not shown).

[0082] In some embodiments, the metal layer 254 may include copper, silver, gold, aluminum, tungsten, other suitable metal materials, or combinations thereof. In some embodiments, the metal layer 254 and the contact member 250 may include the same material or different materials.

[0083] Next, Figures 2 to 20 Methods for forming a semiconductor device 500 according to some embodiments of the present invention are described. Figures 2 to 20 To form Figure 1 FIG. 5 is a cross-sectional view of a semiconductor device 500 at an intermediate stage according to some embodiments of the present invention. Figures 2 to 20 Zhongyu Figure 1 The same or similar reference numerals represent the same or similar elements.

[0084] like Figure 2 As shown, a silicon carbide substrate 100 having a first conductivity type is provided, for example, an N-type heavily doped (N+) silicon carbide substrate 100 .

[0085] Next, an epitaxial growth process is performed to grow an epitaxial layer 200 having a first conductivity type, such as an N-type lightly doped (N-) silicon carbide epitaxial layer 200, on the top surface 100T of the silicon carbide substrate 100. In some embodiments, the epitaxial growth process includes metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable epitaxial growth processes, or combinations thereof.

[0086] Next, a pad oxide layer 202 is formed on the top surface 200T of the epitaxial layer 200 by oxidizing the surface of the epitaxial layer 200. Several deposition processes are then performed to form a mask layer 210 on the pad oxide layer 202. In some embodiments, the mask layer 210 is a multi-layer structure. For example, the mask layer 210 includes a first mask layer 204 and a second mask layer 206 located on the first mask layer 204. In some embodiments, the second mask layer 206 on the first mask layer 204 includes different insulating materials. For example, the first mask layer 204 may include silicon nitride. The second mask layer 206 may include silicon oxide. The provision of the pad oxide layer 202 can avoid excessive stress caused by direct contact between the first mask layer 204, such as silicon nitride, and the epitaxial layer 200 (e.g., including silicon carbide). Subsequently, a deposition process is performed to form an anti-reflective layer 208 on the mask layer 210.

[0087] Then, if Figure 3 As shown, a photolithography process and a subsequent patterning process are performed. Portions of the anti-reflective layer 208, the mask layer 210, and the pad oxide layer 202 thereunder are removed to form a patterned anti-reflective layer 208P, a mask pattern 210P, and the pad oxide layer 202P thereunder on the top surface 200T of the epitaxial layer 200, respectively. This exposes portions of the top surface 200T of the epitaxial layer 200 to define trench formation locations. The mask pattern 210P may include a first mask pattern 204P and a second mask pattern 206P located on the first mask pattern 204P.

[0088] Then, if Figure 4 As shown, the mask pattern 210P is used as an etching mask to perform an etching process on the epitaxial layer 200. The etching process removes the epitaxial layer 200 not covered by the mask pattern 210P to form trenches 212A and 212B in the epitaxial layer 200 in the first area 400 and the second area 410 along the direction 310. Figure 4In the illustrated embodiment, the etching process forms two trenches 212A in the epitaxial layer 200 in the first region 400 and one trench 212B in the epitaxial layer 200 in the second region 410. Two adjacent trenches 212A are spaced apart from each other along a direction 300 and define a mesa region 400M of the epitaxial layer 200. In some embodiments, the mesa region 400M has a mesa width WM along the direction 300. In some embodiments, the etching process includes dry etching. The dry etching may include plasma etching, plasma-free gas etching, sputtering, ion milling, reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma etching, or other suitable processes. Furthermore, the anti-reflective layer 208 may be removed during the etching process.

[0089] Then, if Figure 5 As shown, an oxidation process and a subsequent etching process may be performed to form a sacrificial oxide layer (SAC oxide layer) (not shown) on the sidewalls 212A-S, 212B-S and bottom surfaces 212A-B, 212B-B of the trenches 212A, 212B. An etching process is then performed to remove the sacrificial oxide layer, exposing the sidewalls 212A-S, 212B-S and bottom surfaces 212A-B, 212B-B of the trenches 212A, 212B. Figure 5 The oxidation process and etching process shown can remove the etching process ( Figure 4 ) and may remove a portion of the pad oxide layer 202P from the sidewalls 212A-S, 212B-S of the trenches 212A, 212B.

[0090] Then, if Figure 6 As shown, an oxidation process and subsequent deposition processes may be performed to fully form a shielding dielectric layer 216. The shielding dielectric layer 216 covers the top surface 210T of the mask pattern 210P and extends into the trenches 212A and 212B, conformally covering the sidewalls 212A-S and 212B-S and bottom surfaces 212A-B and 212B-B of the trenches 212A and 212B.

[0091] In some embodiments, a thermal process may be optionally performed on the shielding dielectric layer 216 to increase the density of the shielding dielectric layer 216 and improve the interface properties between the shielding dielectric layer 216 and the epitaxial layer 200. In some embodiments, the thermal process may be a rapid thermal annealing (RTA) process.

[0092] Then, if Figure 7 As shown, a deposition process and a subsequent planarization process may be performed to form conductive materials 220A and 220B in the trenches 212A and 212B, respectively. In some embodiments, the conductive materials 220A and 220B are formed simultaneously. The top surface 220AT of the conductive material 220A and the top surface 220BT of the conductive material 220B are both higher than the top surface 200T of the epitaxial layer 200 and aligned with each other. Furthermore, the conductive materials 220A and 220B comprise the same material. In some embodiments, the conductive materials 220A and 220B may be formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. In some embodiments, the metal may include but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt). In some embodiments, the metal nitride may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include but is not limited to tungsten silicide (WSi). x In some embodiments, the deposition process may include metal organic chemical vapor deposition (MOCVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition processes. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

[0093] Then, if Figure 8 As shown, a photolithography process can be performed to form a photoresist pattern PR1 above the epitaxial layer 200 in the second region 410. The photoresist pattern PR1 covers the conductive material 220B and a portion of the shielding dielectric layer 216 in the second region 410, and makes the top surface 220AT ( Figure 7 ) is exposed from the photoresist pattern PR1. Then, a selective etching process may be performed to remove a portion of the conductive material 220A from the upper portion of the trench 212A close to the top surface 200T of the epitaxial layer 200 ( Figure 7 After the selective etching process, the remaining conductive material 220A is labeled as conductive material 220AR. Conductive material 220AR fills the lower portion of trench 212A away from the top surface 200T of epitaxial layer 200 and exposes the shielding dielectric layer 216 in the upper portion of trench 212A. In some embodiments, the selective etching process includes dry etching.

[0094] Then, if Figure 9 As shown, another etching process may be performed to remove the portion of the shielding dielectric layer 216 (not covered by the residual conductive material 220AR) Figure 8). After the etching process, the shielding dielectric layer 216 remaining in the trench 212A of the first region 400 is labeled as a shielding dielectric layer 216AR, and the dielectric layer 216 covered by the photoresist pattern PR1 of the second region 410 is labeled as a shielding dielectric layer 216B. The shielding dielectric layer 216AR is located on the sidewalls 212A-S and the bottom surface 212A-B of the lower portion of the trench 212A. In some embodiments, the top surface of the shielding dielectric layer AR can be higher (not shown), lower than, or substantially coplanar with the top surface of the conductive material 220AR. Figure 9 In some embodiments, the top surface 216ART of the shielding dielectric layer 216AR may be lower than the top 220ART of the conductive material 220AR and may be slightly dished. In some embodiments, the etching process includes wet etching. After forming the shielding dielectric layers 216AR and 216B, the photoresist pattern PR1 is removed.

[0095] Then, if Figure 10 As shown, an oxidation process may be performed to form a gate dielectric layer 224A in the trench 212A and an oxide layer 224B in the trench 212B. The oxidation process includes oxidizing the sidewalls 212A-S of the upper portion of the trench 212A and the top portion 220ART of the conductive material 220AR. Figure 9 ) to form a gate dielectric layer 224A and a first electrode 220F1 in the trench 212A. The above-mentioned oxidation process also includes oxidizing the top of the conductive material 220B in the second region 410 to form an oxide layer 224B and a conductive material 220BR in the trench 212B. In an embodiment of the present invention, the gate dielectric layer 224A does not fill the trench 212A. In addition, the gate dielectric layer 224A includes a gate dielectric layer 224A-1 conformally formed on the sidewall 212A-S of the upper portion of the trench 212A, and a gate dielectric layer 224A-2 formed on the first electrode 220F1. In some embodiments, the thickness of the gate dielectric layer 224A-1 is less than the thickness of the shielding dielectric layer 216AR. Compared to the gate dielectric layer 224A-1 formed by oxidation of the epitaxial layer 200 of silicon carbide, for example, the gate dielectric layer 224A-2 is made of a conductive material 220AR (such as polysilicon) Figure 9 ) is oxidized, thus having a relatively thick thickness. Furthermore, a top surface 224BT of the oxide layer 224B may be higher than a top surface 210T of the mask pattern 210P along a direction 310. After the oxidation process, the unoxidized conductive material 220AR in the trench 212A forms a first electrode 220F1, while the unoxidized conductive material 220B in the trench 212B is labeled as conductive material 220BR.

[0096] Then, if Figure 11As shown, a deposition process and subsequent planarization and etching processes may be performed to form electrode material pillars 230 in trenches 212A. A top surface 230T of the electrode material pillars 230 may be lower than a top surface 210T of the mask pattern 210P. In some embodiments, the electrode material pillars 230 and the conductive materials 220AR and 220BR may comprise the same material, such as polysilicon. In some embodiments, the deposition process may include metal organic chemical vapor deposition (MOCVD), sputtering, resistive heating evaporation, electron beam evaporation, or other suitable deposition processes. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. In some embodiments, the etching process may include a blanket etch process.

[0097] Then, if Figure 12 As shown, another etching process may be performed to remove the second mask pattern 206P of the mask pattern 210P, exposing the first mask pattern 204P. In some embodiments, the first mask pattern 204P, the oxide layer 224B, and the shielding dielectric layer 216B comprise the same insulating material, such as silicon oxide. Therefore, the etching process also removes the oxide layer 224B and a portion of the shielding dielectric layer 216B. The remaining shielding dielectric layer 216B is designated as shielding dielectric layer 216BR. After the etching process, the electrode material pillars 230 may protrude beyond the first mask pattern 204P in direction 310. Furthermore, the conductive material 220BR may protrude beyond the shielding dielectric layer 216BR in direction 310. In some embodiments, the etching process comprises wet etching.

[0098] Then, if Figure 13 As shown, another oxidation process can be performed to oxidize the top of the electrode material column 230 (the portion close to the top surface 230T) to form the insulating column OP1, and oxidize the top of the conductive material 220BR to form the insulating column OP2. After the above oxidation process, the unoxidized electrode material column 230 forms the gate electrode 230G in the trench 212A, and the unoxidized conductive material 220BR forms the second electrode 220F2 in the trench 212B. Figure 13As shown, insulating pillars OP1 and OP2 protrude beyond the top surface 200T of epitaxial layer 200 and first mask pattern 204P along direction 310. In direction 310, insulating pillar OP1 has a thickness H1, and first mask pattern 204P has a thickness H2. In some embodiments, the ratio of thickness H1 to thickness H2 is between 3 and 5. If the ratio of thickness H1 to thickness H2 is less than 3, the thickness of insulating pillar OP1 protruding beyond second mask pattern 206P is too small, and subsequent processes may not allow for the formation of dielectric spacers on opposing sidewalls of insulating pillar OP1. If the ratio of thickness H1 to thickness H2 is greater than 5, dielectric spacers having sufficient lateral width (along direction 300) may not be formed on opposing sidewalls of insulating pillar OP1. Furthermore, insulating pillar OP2 may have a thickness H3 along direction 310. In some embodiments, because the width of electrode material pillar 230 along direction 300 is greater than the width of second electrode 220F2, thickness H3 may be less than thickness H1.

[0099] Then, if Figure 14 As shown, another selective etching process can be performed to remove the first mask pattern 204P, exposing the pad oxide layer 202P. In some embodiments, the insulating pillars OP1 and OP2 and the second mask pattern 206P comprise different insulating materials. For example, the insulating pillar OP1 is formed of silicon oxide, and the first mask pattern 204P is formed of silicon nitride. Therefore, the selective etching process does not remove the insulating pillars OP1 and OP2 and the pad oxide layer 202P. In some embodiments, the selective etching process comprises wet etching.

[0100] Then, if Figure 15 As shown, an ion implantation process may be performed to fully form a well region 234 of the second conductivity type, such as a P-type well region 234, in the epitaxial layer 200. In some embodiments, a bottom surface 234B of the well region 234 is above the first electrode 220F1 along direction 310.

[0101] Then, if Figure 16 As shown, a photolithography process can be performed to form a photoresist pattern (not shown) above the epitaxial layer 200 in the second region 410, thereby exposing the epitaxial layer 200 in the first region 400. Thereafter, another ion implantation process is performed to form a source region 236 having a first conductivity type, such as an N-type source region 236, on the well region 234 in the first region 400. After forming the source region 236, the photoresist pattern is removed.

[0102] Then, if Figure 17As shown, a deposition process can be performed to form an interlayer dielectric layer 240 on the epitaxial layer 200. The interlayer dielectric layer 240 has a thickness T1 along the direction 310. In some embodiments, the ratio of the mesa width WM to the thickness T1 can be controlled to be between 2 and 3, so that the interlayer dielectric layer 240 is conformally formed on the insulating pillars OP1, OP2 and the mesa region 400M. If the ratio of the mesa width WM to the thickness T1 is less than 2, it may not be possible to form a dielectric spacer with a sufficient lateral width (along the direction 300) on the opposite sidewalls of the insulating pillar OP1. If the ratio of the mesa width WM to the thickness T1 is greater than 3, the interlayer dielectric layer 240 may fill the space between adjacent insulating pillars OP1, and it may not be possible to form a dielectric spacer on the opposite sidewalls of the insulating pillar OP1 in subsequent processes. Figure 17 As shown, an upper surface 240T1 of the interlayer dielectric layer 240 above the top surface OP1T of the insulating pillar OP1 is higher than an upper surface 240T2 of the epitaxial layer 200 above the mesa region 400M.

[0103] Then, if Figure 18 As shown, a photolithography process may be performed to form a photoresist pattern PR2 on the epitaxial layer 200 in the second region 410. The photoresist pattern PR2 covers the interlayer dielectric layer 240 in the second region 410, so that the interlayer dielectric layer 240 ( Figure 17 ) is exposed from the photoresist pattern PR2. An etching process is then performed to remove a portion of the interlayer dielectric layer 240 from the epitaxial layer 200 in the mesa region 400M and the top surface OP1T of the insulating pillar OP1 until the top surface 200T of the epitaxial layer 200 in the mesa region 400M is exposed, thereby forming a pair of dielectric spacers 240S on the opposite sidewalls OP1S of each insulating pillar OP1. After the etching process, the remaining interlayer dielectric layer 240 covered by the photoresist pattern PR2 is labeled as interlayer dielectric layer 240R. Of the two pairs of dielectric spacers 240S formed on the opposite sidewalls OP1S of two adjacent insulating pillars OP1, the two adjacent dielectric spacers 240S are located within the mesa region 400M. Furthermore, the distance S1 between the outer sidewalls 240SE of the two adjacent dielectric spacers 240S (along direction 310) can define the lateral dimensions of the contact hole to be formed subsequently. After forming the dielectric spacers 240S, the photoresist pattern PR2 is removed.

[0104] Then, if Figure 19As shown, an etching process can be performed using the insulating pillar OP1, the dielectric spacers 240S, and the interlayer dielectric layer 240R as an etching mask to form a contact hole 244 in the epitaxial layer 200 of the first region 400. The etching process removes portions of the epitaxial layer 200 exposed from two adjacent pairs of dielectric spacers 240S adjacent to each other to form the contact hole 244. The bottom surface 244B of the contact hole 244 can be located above the bottom surface 234B of the well region 234. During the formation of the contact hole 244, the remaining interlayer dielectric layer 240R covers the top surface OP2T and opposite sidewalls of the insulating pillar OP2. In some embodiments, the etching process includes a blanket etching process, which performs anisotropic etching on a portion of the epitaxial layer 200 in the first region 400 along the outer sidewalls 240SE of the adjacent dielectric spacers 240S without using any photoresist pattern. As a result, the sidewalls 244S of the contact hole 244 are self-aligned with the outer sidewalls 240SE of the two adjacent dielectric spacers 240S.

[0105] Then, if Figure 20 As shown, an ion implantation process can be performed using the insulating pillar OP1, dielectric spacers 240S, and interlayer dielectric layer 240R as a mask to form a contact doped region 246 in the epitaxial layer 200 below the bottom surface 244B of the contact hole 244. The contact doped region 246 has the same conductivity type as the well region 234, for example, a P-type contact doped region 246. Furthermore, the doping concentration of the contact doped region 246 is greater than the doping concentration of the well region 234. For example, when the well region 234 is a P-type well region 234, the contact doped region 246 is a heavily P-type (P+) doped contact doped region 246 to serve as a wiring doping region for the well region 234. After the aforementioned ion implantation process, an annealing process can be performed to activate dopants in the well region 234, the source region 236, and the contact doped region 246. In some embodiments, the annealing process includes laser annealing, rapid thermal annealing (RTA), other suitable annealing processes, or a combination thereof.

[0106] Then, if Figure 1 As shown, a deposition process may be performed to form a contact barrier layer (not shown) on the dielectric spacer 240S and the interlayer dielectric layer 240R, and the contact barrier layer is conformably deposited in the contact hole 244 ( Figure 19); and then a contact conductive layer (not shown) is deposited on the barrier material layer. The contact conductive layer fills the remaining space in the contact hole 244. Next, a removal process (such as an etching process or a planarization process) is performed to remove the excess portions of the contact barrier layer and the contact conductive layer above the dielectric spacer 240S and the interlayer dielectric layer 240R to form a contact component 250 in the contact hole 244. The above removal process may also remove part of the insulating column OP1, the dielectric spacer 240S, and the interlayer dielectric layer 240R, so that the contact component 250, the insulating column OP1, the dielectric spacer 240S in the first region 400, and the interlayer dielectric layer 240R in the second region 410 are coplanar. The contact component 250 fills the contact hole 244 and is electrically connected to the source region 236 and the well region 234. After the above removal process, the top surface of the remaining insulating column OP1 is marked as OP1T'.

[0107] Then, if Figure 1 As shown, after forming the contact features 250, a deposition process may be performed to form a metal layer 254 entirely on the contact features 250, the insulating pillars OP1, the dielectric spacers 240S in the first region 400, and the interlayer dielectric layer 240R in the second region 410. In some embodiments, the deposition process may include a physical vapor deposition process, a chemical vapor deposition process, other suitable processes, or a combination thereof.

[0108] Subsequent processes may be further performed to form a drain contact (not shown) on the bottom surface 100B of the silicon carbide substrate 100. The drain contact may be electrically connected to the silicon carbide substrate 100. After the above processes, the semiconductor device 500 is formed.

[0109] Some embodiments of the present invention provide semiconductor devices and methods for forming the same. The method for forming the semiconductor device includes utilizing an oxidation process to oxidize the top surface of an electrode material column used to form a gate electrode to form an insulating column protruding from the top surface of the epitaxial layer, and then forming a pair of dielectric spacers on opposite side walls of the insulating column. Without using any photoresist pattern, the dielectric spacers are used as etching masks to form contact holes in the epitaxial layer. Since the position of the contact hole is defined by the dielectric spacers that are close to each other in two adjacent pairs of dielectric spacers, a contact component can be accurately formed in the middle of two adjacent grooves without the need for a photolithography process. This can avoid the contact-trench overlay error and subsequent photoresist rework problems caused by known photolithography processes, improve the electrical uniformity and reliability of the semiconductor device, and save the cost of high-resolution masks and photolithography processes when the component density is increased.

[0110] In a direction substantially perpendicular to the top surface of the silicon carbide substrate (e.g., direction 310), the silicon oxide insulating pillar protrudes from the silicon nitride mask pattern on the epitaxial layer. In some embodiments, the ratio of the thickness of the silicon oxide insulating pillar (e.g., thickness H1) to the thickness of the silicon nitride mask pattern (e.g., thickness H2) can be between 3 and 5, facilitating the subsequent formation of dielectric spacers on opposite sidewalls of the insulating pillar. The dielectric spacers can be formed by patterning an interlayer dielectric layer located on the insulating pillar. In some embodiments, the ratio of the mesa width (e.g., mesa width WM) to the thickness of the interlayer dielectric layer (thickness T1) can be controlled to be between 2 and 3, allowing the interlayer dielectric layer to be conformally formed on the insulating pillar and the mesa region, and forming dielectric spacers with appropriate lateral dimensions through subsequent etching processes to form contact features with appropriate lateral dimensions.

[0111] While the present invention has been described above with reference to the aforementioned embodiments, these are not intended to limit the present invention. Persons skilled in the art will readily appreciate that modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A silicon carbide substrate having a first region and a second region and having a first conductivity type; an epitaxial layer disposed on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; a well region located in the epitaxial layer, and the well region has a second conductivity type; a gate structure disposed in the epitaxial layer of the first region, wherein the gate structure extends along a first direction; a first insulating column, disposed directly above the gate structure and protruding from a top surface of the epitaxial layer along the first direction; a pair of first dielectric spacers disposed on opposite sidewalls of the first insulating column; and A contact member extends from above the epitaxial layer into the well region, wherein a first sidewall of the contact member in the epitaxial layer is aligned with a first outer sidewall of the one of the pair of first dielectric spacers.

2. The semiconductor device according to claim 1, wherein Also includes: a first electrode disposed in the epitaxial layer in the first region, the first electrode being located directly below the gate structure and extending along the first direction, wherein the gate structure includes a gate electrode and a gate dielectric layer, and the gate electrode is separated from the first electrode by the gate dielectric layer; a second electrode disposed in the epitaxial layer of the second region and extending along the first direction; a second insulating column, disposed directly above the second electrode and protruding from the top surface of the epitaxial layer along the first direction; and A source region is located on the well region in the first region and close to the top surface of the epitaxial layer, wherein the source region has the first conductivity type.

3. The semiconductor device according to claim 2, wherein The first insulating column completely covers and contacts a top surface of the gate electrode.

4. The semiconductor device according to claim 2, wherein A top surface of the gate electrode is lower than the top surface of the epitaxial layer.

5. The semiconductor device according to claim 2, wherein In a second direction, a first width of the gate electrode is the same as a second width of the first insulating pillar.

6. The semiconductor device according to claim 5, wherein In a second direction, a third width of the second electrode is the same as a fourth width of the second insulating pillar.

7. The semiconductor device according to claim 6, wherein The fourth width is smaller than the second width.

8. The semiconductor device according to claim 7, wherein In the first direction, a first distance between the first insulating pillar and the top surface of the epitaxial layer is greater than a second distance between the second insulating pillar and the top surface of the epitaxial layer.

9. The semiconductor device according to claim 1, wherein Also includes: another gate structure disposed in the epitaxial layer of the first region, wherein the another gate structure is separated from the gate structure by the epitaxial layer along a second direction, wherein the first direction is perpendicular to the second direction, The contact component is located between the gate structure and the other gate structure along the second direction.

10. The semiconductor device according to claim 9, wherein Also includes: another first insulating pillar, disposed directly above the another gate structure and protruding from the top surface of the epitaxial layer along the first direction; Another pair of first dielectric spacers is disposed on opposite sidewalls of the other first insulating column, The contact member is adjacent to one of the other pair of first dielectric spacers and extends into the well region of the first region, wherein a second sidewall of the contact member in the epitaxial layer is aligned with a second outer sidewall of the one of the other pair of first dielectric spacers.

11. A method for forming a semiconductor device, characterized in that: include: Providing a silicon carbide substrate having a first region and a second region and having a first conductivity type; growing an epitaxial layer on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; forming a first trench in the epitaxial layer of the first region along a first direction; forming an electrode material column in the first trench; Oxidizing a top portion of the electrode material column to form a first insulating column, wherein the unoxidized portion of the electrode material column forms a gate electrode in the first trench, wherein the first insulating column protrudes from a top surface of the epitaxial layer along the first direction; forming a pair of first dielectric spacers on opposite sidewalls of the first insulating pillar; performing an etching process using the pair of first dielectric spacers as an etching mask to form a contact hole in the epitaxial layer; as well as A contact component is formed in the contact hole.

12. The method for forming a semiconductor device according to claim 11, wherein: Also includes: forming a mask pattern on a top surface of the epitaxial layer, wherein the first insulating pillar is formed of a first insulating material, and the mask pattern is formed of a second insulating material, the first insulating material being different from the second insulating material; removing the epitaxial layer not covered by the mask pattern to form the first trench; After forming the first insulating pillar, removing the mask pattern; After removing the mask pattern, a well region is formed in the epitaxial layer, and the well region has a second conductivity type; and A source region is formed on the well region of the first region, wherein the source region has the first conductivity type.

13. The method for forming a semiconductor device according to claim 12, wherein: Before removing the mask pattern, in the first direction, the first insulating pillar has a first thickness, the mask pattern has a second thickness, and the ratio of the first thickness to the second thickness is between 3 and 5.

14. The method for forming a semiconductor device according to claim 12, wherein: Before forming the electrode material column, a first electrode is formed in a lower portion of the first trench.

15. The method for forming a semiconductor device according to claim 14, wherein: Also includes: forming a second trench in the epitaxial layer in the second region along the first direction; forming a second conductive material in the second trench; and A top portion of the second conductive material is oxidized to form a second insulating column. The unoxidized second conductive material forms a second electrode in the second trench. The second insulating column protrudes from the top surface of the epitaxial layer along the first direction.

16. The method for forming a semiconductor device according to claim 15, wherein: Also includes: During the formation of the second conductive material, a first conductive material is formed in the first trench, wherein the first conductive material and the second conductive material comprise the same material; forming a first photoresist pattern above the epitaxial layer in the second region; removing a portion of the first conductive material from an upper portion of the first trench; removing the first photoresist pattern; as well as performing an oxidation process to form a first gate dielectric layer in the first trench, wherein forming the first gate dielectric layer includes oxidizing a top portion of the first conductive material, and the unoxidized first conductive material forms the first electrode, During the oxidation process, a top portion of the second conductive material is oxidized to form a second oxide layer.

17. The method for forming a semiconductor device according to claim 15, wherein: Also includes: forming another first trench in the epitaxial layer of the first region, wherein the another first trench is spaced apart from the first trench along a second direction and defines a mesa region of the epitaxial layer, wherein the mesa region has a mesa width along the second direction; forming another gate structure in the another first trench and another first insulating pillar directly above the another gate structure; and forming another pair of first dielectric spacers on opposite sidewalls of the other first insulating pillar, wherein one of the pair of first dielectric spacers and one of the other pair of first dielectric spacers are located in the mesa region, The etching process removes the portion of the epitaxial layer exposed from the one of the pair of first dielectric spacers and the one of the other pair of first dielectric spacers to form the contact hole.

18. The method for forming a semiconductor device according to claim 17, wherein: include: After forming the first insulating column and the second insulating column, forming an interlayer dielectric layer on the epitaxial layer; forming a second photoresist pattern on the epitaxial layer in the second region; removing a portion of the interlayer dielectric layer from the epitaxial layer in the mesa region and the top surfaces of the first insulating pillar and the further first insulating pillar to form the pair of first dielectric spacers and the further pair of first dielectric spacers; and The second photoresist pattern is removed.

19. The method for forming a semiconductor device according to claim 18, wherein: The dielectric layer has a first thickness along the first direction, and a ratio of the mesa width to the first thickness is between 2 and 3.

20. The method for forming a semiconductor device according to claim 18, wherein: A first upper surface of the interlayer dielectric layer above the first insulating pillar is higher than a second upper surface above the mesa region.

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