Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and is applied to the technical field of semiconductors. In the application, the semiconductor device comprises a substrate, an active region and a shallow trench isolation region, and the substrate comprises a unit region and a peripheral region adjacent to the unit region; the shallow trench isolation region is disposed adjacent to the active region, and the shallow trench isolation region includes a first insulating film and a second insulating film.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The explosive growth of emerging technologies like artificial intelligence and 5G communications is placing ever-more stringent demands on the performance of semiconductor devices. To meet these challenges, advanced semiconductor processes are continuously moving toward smaller feature sizes. Smaller feature sizes allow for more transistors to be integrated onto a chip of the same area. Maintaining device performance while shrinking feature sizes is a critical issue that needs to be addressed. Summary of the Invention

[0003] The purpose of this application is to provide a semiconductor device, comprising:

[0004] a substrate comprising a cell region and a peripheral region adjacent to the cell region;

[0005] Active regions are located on the substrate, the active regions are spaced apart along a first direction and alternately arranged along a second direction, and the active regions include a first active region and a second active region located on one side of the first active region;

[0006] A shallow trench isolation region is located on the substrate, the shallow trench isolation region is adjacent to the active area, and the shallow trench isolation region includes

[0007] a first insulating film extending from the cell region to the peripheral region and directly contacting the active region;

[0008] The second insulating film is located in the peripheral region, directly contacts the first insulating film and is separated from the active region, wherein at least one second insulating film is located between the most adjacent second active regions along the second direction.

[0009] Furthermore, the shallow trench isolation region further includes a third insulating film, the third insulating film is located in the cell region, and the third insulating film is arranged between an end portion of the first active region and an end portion of the second active region along the first direction.

[0010] Furthermore, a length S1 of the second insulating film along the first direction is greater than a length S3 of the third insulating film along the first direction.

[0011] Furthermore, the at least one second insulating film has at least a length S1 and a width S2, and 2 times the width S2 is smaller than the length S1.

[0012] Furthermore, it also includes a peripheral isolation region, which is located outside the first insulating film.

[0013] Furthermore, the shallow trench isolation region further includes a fourth insulating film, and the fourth insulating film is located between the peripheral isolation region and the first active region.

[0014] Furthermore, a profile of the second active region is different from a profile of the first active region.

[0015] Furthermore, adjacent second active regions have different lengths in the first direction.

[0016] Furthermore, the first insulating film and the second insulating film are made of different materials.

[0017] Furthermore, it also includes word line structures, which extend along the second direction in a separated manner and intersect with the active area and the shallow trench isolation area. At least one word line structure passes through the first active area and exposes at least part of the second insulating film.

[0018] Furthermore, at least one of the second insulating films does not overlap with the word line structure.

[0019] Furthermore, it also includes word line structures, which extend along the second direction in a separated manner and are interlaced with the active area and the shallow trench isolation area. At least one word line structure passes through the second active area and exposes a portion of the second insulating film, and the second insulating film partially overlaps with the word line structure.

[0020] The present application also discloses another semiconductor device, comprising:

[0021] substrate;

[0022] Active regions are located on the substrate, wherein the active regions are spaced apart along a first direction and alternately arranged along a second direction;

[0023] A shallow trench isolation region is located on the substrate, the shallow trench isolation region is adjacent to the active area, and the shallow trench isolation region includes

[0024] a first insulating film directly contacting the active region;

[0025] The second insulating film is in direct contact with the first insulating film and separated from the active region; wherein at least one second insulating film is located between the active regions with the most adjacent edges along the second direction.

[0026] Furthermore, at least one of the second insulating films has at least a length S1 and a width S2, and twice the width S2 is smaller than the length S1.

[0027] The present application also discloses another semiconductor device, comprising:

[0028] substrate;

[0029] Active regions are located on the substrate, wherein the active regions are spaced apart along a first direction and alternately arranged along a second direction;

[0030] A shallow trench isolation region is located on the substrate, the shallow trench isolation region is adjacent to the active area, and the shallow trench isolation region includes

[0031] a first insulating film directly contacting the active region;

[0032] a second insulating film, directly contacting the first insulating film and separated from the active region;

[0033] a peripheral isolation region, located outside the first insulating film and in direct contact with the first insulating film;

[0034] Wherein, at least one second insulating film is located between the active region and the peripheral isolation region along the first direction.

[0035] Furthermore, at least one of the second insulating films has at least a length S1 and a width S2, and twice the width S2 is smaller than the length S1.

[0036] Furthermore, the second insulating film and the peripheral isolation region are separated by the first insulating film.

[0037] Furthermore, the active region includes a first active region and a second active region located on one side of the first active region, and the second insulating film is located between the peripheral isolation region and the first active region located at the outermost edge in the first direction.

[0038] The present application provides a method for manufacturing a semiconductor device, which may at least include:

[0039] Providing a substrate, the substrate comprising a cell region and a peripheral region adjacent to the cell region;

[0040] forming active regions on the substrate, wherein the active regions are spaced apart along a first direction and alternately arranged along a second direction, and the active regions include a first active region and a second active region located on one side of the first active region;

[0041] A shallow trench isolation region is formed on the substrate, wherein the shallow trench isolation region is adjacent to the active region, and the shallow trench isolation region includes

[0042] a first insulating film extending from the cell region to the peripheral region and directly contacting the active region;

[0043] The second insulating film is located in the peripheral region, directly contacts the first insulating film and is separated from the active region, wherein at least one second insulating film is located between the most adjacent second active regions along the second direction.

[0044] Compared with the prior art, the technical solution provided by the present application can improve the stability of the active area structure by adding a second insulating film between the active areas most adjacent to the edge. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following detailed description, they are used to explain the present application but do not constitute a limitation of the present application. In the accompanying drawings:

[0046] Figure 1a A top view of a semiconductor device provided in one embodiment of the present application;

[0047] Figure 1b for Figure 1a A magnified view of the middle;

[0048] Figure 2a A top view of a semiconductor device provided in another embodiment of the present application;

[0049] Figure 2b for Figure 2a Enlarged view of middle B;

[0050] Figure 3a A top view of a semiconductor device provided in another embodiment of the present application;

[0051] Figure 3b for Figure 3a Enlarged view of middle C;

[0052] Figure 4a A top view of a semiconductor device provided in yet another embodiment of the present application;

[0053] Figure 4b for Figure 4a Enlarged view of middle D;

[0054] Figures 5 to 11 A schematic diagram of a method for manufacturing a semiconductor device provided in one embodiment of the present application;

[0055] Figure 12 This is a schematic diagram of a method for manufacturing a semiconductor device provided in another embodiment of the present application.

[0056] Wherein, description of the accompanying drawings:

[0057] 20-first active region, 30-second active region, 301-protrusion, 31-first sub-active region, 32-second sub-active region, 33-third sub-active region, 34-fourth sub-active region, 41-first insulating film, 42-second insulating film, 421-recess, 43-third insulating film, 44-fourth insulating film, 45-peripheral isolation region, 451-recess, 452-protrusion, ss1-sidewall, ss2-sidewall, t s1-end, ts2-end, 60-word line structure, 61-first word line, 62-second word line, PR-peripheral region, CR-cell region, T1-second cell trench, T2-second cell trench, T3-third cell trench, T4-fourth cell trench, 110-peripheral mask pattern, 120-sidewall, 130-peripheral component, 131-logic active structure, M1-first mask layer, M2-second mask layer. DETAILED DESCRIPTION

[0058] In order to make the technical solutions and advantages of the embodiments of the present application clearer, a variety of different implementation methods or embodiments are disclosed below. To simplify the disclosure, specific examples of each element and arrangement are described below. Of course, these are merely examples and are not intended to limit the scope of protection of the present application. For example, a first feature described later in the specification is formed above or on a second feature, and may include an implementation method in which the first and second features are formed in a directly connected manner, or an implementation method in which an additional feature is formed between the first and second features, so that the first and second features may not be directly connected. In addition, the figures and / or letters may be repeated in different examples in these disclosures. This repetition is for brevity and clarity and does not itself represent the relationship between the various implementation methods and / or structures to be discussed. Furthermore, when a first element is described in a manner connected or combined with a second element, the description includes an implementation method in which the first and second elements are directly connected or combined with each other, and also includes an implementation method in which one or more other intervening elements are added to indirectly connect or combine the first and second elements.

[0059] Please refer to Figure 1aIn some embodiments, a semiconductor device includes a substrate, an active region, and a shallow trench isolation region; the substrate includes a cell region CR and a peripheral region PR adjacent to the cell region CR; the active region is located on the substrate, the active regions are spaced apart along a first direction D1 and alternately arranged along a second direction D2, and the active region includes a first active region 20 and a second active region 30 located on one side of the first active region 20; the shallow trench isolation region is located on the substrate, the shallow trench isolation region is adjacent to the active region, and the shallow trench isolation region includes a first insulating film 41 and a second insulating film 42, wherein the first insulating film 41 extends from the cell region CR to the peripheral region PR and is in direct contact with the active region; the second insulating film 42 is located in the peripheral region PR, is in direct contact with the first insulating film 41, and is separated from the active region; wherein at least one second insulating film 42 is located between the most adjacent second active regions 30 along the second direction D2. The first direction is the extension direction of the active region, and the second direction intersects the first direction. In some embodiments, at least one of the second insulating film 42 , the third insulating film 43 , and the fourth insulating film 44 includes a gap.

[0060] Please continue to refer to Figure 1a In some embodiments, a semiconductor device includes a substrate, an active area, and a shallow trench isolation area; the active area is located on the substrate, the active areas are spaced apart along a first direction D1, and alternately arranged along a second direction D2; the shallow trench isolation area is located on the substrate, the shallow trench isolation area is adjacent to the active area, and the shallow trench isolation area includes a first insulating film 41 and a second insulating film 42, wherein the first insulating film 41 is in direct contact with the active area; the second insulating film 42 is in direct contact with the first insulating film 41 and is separated from the active area, and the second insulating film 42 can be separated from the active area by the first insulating film 41; at least one second insulating film 42 is located between the second active areas 30 with the most adjacent edges along the second direction D2.

[0061] Please continue to refer to Figure 3a 、 Figure 3b 、 Figure 4a 、 Figure 4bIn some embodiments, a semiconductor device includes a substrate, an active region, a shallow trench isolation region, and a peripheral isolation region 45. The active region is located on the substrate, spaced apart along a first direction D1 and alternately arranged along a second direction D2. The shallow trench isolation region is located on the substrate, adjacent to the active region, and includes a first insulating film 41 and a second insulating film 42. The first insulating film 41 is in direct contact with the active region, and the second insulating film 42 is in direct contact with the first insulating film 41 and separated from the active region. The peripheral isolation region 45 is located outside the first insulating film 41 and in direct contact with the first insulating film 41. At least one second insulating film 42 is located between the active region and the peripheral isolation region 45 along the first direction D1. In some embodiments, the active region includes a first active region 20 and a second active region 30 located to one side of the first active region 20. The second insulating film 42 is located in the first direction between the peripheral isolation region 45 and the second active region 30 located at the outermost edge.

[0062] Please continue to refer to Figure 3a 、 Figure 3b 、 Figure 4a 、 Figure 4b The side of the peripheral isolation region 45 facing the second active region has a continuous uneven surface or a continuous rough surface, which includes a plurality of interconnected protrusions 452 and a plurality of recesses 451, wherein the second insulating film 42 is located between the protrusions 452 and the first active region 20 along the first direction. The second active region 30 has a protrusion 301, which corresponds to the recess 451 of the peripheral isolation region 45 along the first direction. The second insulating film 42 has a groove 421, which corresponds to the protrusion 452 of the peripheral isolation region 45 along the first direction. In this way, the peripheral isolation region 45 can better cooperate with the active region and the second insulating film 42, thereby enhancing the stability of the active region.

[0063] In some embodiments, the substrate may be a semiconductor substrate 10 that may include a silicon substrate, a silicon-germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable materials. The substrate and the active area may be of the same material, or the substrate may be regarded as part of the active area, and the shallow trench isolation region may be regarded as a structure provided in the substrate for defining the active area. The active area may be obtained by patterning the substrate, so the active structure may include semiconductor materials (such as silicon) in the substrate, and the shallow trench isolation region may include a single layer or multiple layers of insulating materials, such as oxide insulating materials, nitride insulating materials, or other suitable insulating materials. The first direction D1 and the second direction D2 are both directions parallel to the substrate, wherein in Figure 1a The first direction is D1, the second direction is D2, and the first direction D1 intersects with the second direction D2.

[0064] In some embodiments, the active regions include first active regions 20 and second active regions 30, wherein all first active regions 20 have substantially the same profile and extend along a first direction D1. Specifically, the first active regions 20 have a larger dimension in the first direction D1, while the second active regions 30 have a different profile than the first active regions 20. Adjacent second active regions 30 have different dimensions in the first direction D1. Furthermore, the second active regions 30 may be located on one side of all first active regions 20 or on opposite sides of all first active regions 20. A first insulating film 41 directly contacts and surrounds the first active regions 20 and the second active regions 30. A second insulating film 42 is located within the first insulating film 41 and is separated from the first active regions 20 and the second active regions 30 by the first insulating film 41.

[0065] Please refer to Figure 1a 、 Figure 1b In some embodiments, the second active region 30 includes at least a first sub-active region 31, a second sub-active region 32, a third sub-active region 33, and a fourth sub-active region 34, which are arranged adjacent to each other. In the second direction D2, the first sub-active region 31 and the third sub-active region 33 are the most adjacent to the second sub-active region 32. At least one second insulating film 42 is located between the second sub-active region 32 and the third sub-active region 33. In this embodiment, the first insulating film 41 is filled between the first sub-active region 31 and the second sub-active region 32, and the first insulating film 41 and the second insulating film 42 are filled between the second sub-active region 32 and the third sub-active region 33. In other embodiments, the second insulating film 42 may also be filled between the first sub-active region 31 and the second sub-active region 32, that is, the second insulating film 42 is provided on both sides of the second sub-active region 32 in the second direction D2.

[0066] In some embodiments, the first insulating film 41 and the second insulating film 42 are made of different materials. For example, the first insulating film 41 is made of silicon oxide, and the second insulating film 42 is made of silicon nitride. Under the same etching conditions, the etching rate of the second insulating film 42 will be slower than the etching rate of the first insulating film 41, that is, the second insulating film 42 will be more difficult to remove. By adding a second insulating film 42 made of a different material from the first insulating film 41 in the adjacent second active region 30, the stability of the active region can be improved and better support can be formed. That is, adding a second insulating film 42 between the sidewalls of the outermost active region can improve the stability of the active region. Please continue to refer to Figure 1b In some embodiments, the second insulating film 42 has a length S1 and a width S2, and the width S2 is twice smaller than the length S1. The second insulating film 42 is in the shape of a long strip, that is, the second insulating film 42 has a large overlapping area with the projection of the second active region in the second direction, which can improve the stability of the second active region.

[0067] Please refer to Figure 2aIn some embodiments, the shallow trench isolation region in the semiconductor device further includes a third insulating film 43, the third insulating film 43 extending from the cell region CR to the peripheral region PR, and the third insulating film 43 is disposed between the end ts2 of the first active region 20 and the end ts1 of the second active region 30 along the first direction D1. For details, please refer to Figure 2b Along the first direction D1, the first active region 20 has an end ts2 facing the third insulating film 43, and the second active region 30 has an end ts1 facing the third insulating film 43. The third insulating film 43 is located between the end ts2 of the first active region 20 and the end ts1 of the second active region 30. The second insulating film 42 is located between the sidewall ss1 of the second active region 30 and the sidewall ss1 of another second active region 30 along the second direction D2. The material of the third insulating film 43 can be the same as or different from that of the first insulating film 41 and the second insulating film 42. In one embodiment, the material of the third insulating film 43 is the same as that of the second insulating film 42, and the material of the third insulating film 43 is different from that of the first insulating film 41.

[0068] In some embodiments, the shallow trench isolation region in the semiconductor device further includes a fifth insulating film (not shown). The fifth insulating film is located in the cell region CR and is positioned between the ends of adjacent first active regions 20 along the first direction D1. Due to the different profiles of the first active region 20 and the second active region 30, the different insulating films are exposed to different environments. Consequently, the fifth insulating film, the third insulating film 43, and the second insulating film 42 have different dimensions. The third insulating film 43 has an irregular shape with four inwardly concave edges, while the second insulating film 42 has a long, concave strip shape. Since the dimensions of the first active regions 20 are generally the same, the structure of the fifth insulating film between the ends of the first active regions 20 is also generally the same. Similarly, since the dimensions of adjacent second active regions 30 are different, for example, the lengths of adjacent second active regions 30 in the first direction D1 are different, the dimensions of the third insulating film 43 between the first active region 20 and the second active region 30 may be different and / or the same, while the dimensions of the second insulating film 42 between the second active regions 30 may be different and / or the same. In one embodiment, a length s1 of the second insulating film 42 along the first direction D1 is greater than a length s3 of the third insulating film 43 along the first direction D1 .

[0069] Please refer to Figure 3a 、 Figure 3bIn some embodiments, the semiconductor device further includes a peripheral isolation region 45, which is located outside the first insulating film 41. The second insulating film 42 is separated from the peripheral isolation region 45 by the first insulating film 41. In the second direction D2, one end of the second insulating film 42 faces the end of the first active region 20, and the other end faces the peripheral isolation region 45. Since the second insulating film 42 has different surrounding environments at both ends of the second direction D2, that is, it is located between the peripheral isolation region 45 and the first active region 20 in the first direction D1, and between two adjacent second active regions 30 in the second direction D2, the second insulating film 42 has a length S1 in the first direction D1 and a width S2 in the second direction D2. The length S1 is much greater than the width S2, that is, the second insulating film 42 is in the shape of an elongated strip. The distance between the first active region 20 and the peripheral isolation region 45 in the first direction D1 is greater than the distance between the most adjacent second active region 30 in the second direction D2. The second insulating film 42 is arranged in the area formed by the two most adjacent second active regions 30, the first active region 20, and the peripheral isolation region 45. In this way, the second insulating film 42 can improve the stability of the edge active region.

[0070] In some embodiments, the shallow trench isolation region in the semiconductor device further includes a fourth insulating film 44, which is located along the second direction D2 between the peripheral isolation region 45 and the edge of the first active region 20. The material of the fourth insulating film 44 can be the same as or different from the material of the second insulating film 42, and the material of the fourth insulating film 44 can be selected from at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

[0071] Please refer to Figure 1a In some embodiments, the semiconductor device further includes wordline structures 60. The wordline structures 60 extend in a spaced-apart manner along the second direction D2 and intersect with the active areas and shallow trench isolation regions. At least one wordline structure 60 passes through the first active area 20, exposing at least a portion of the second insulating film 42 or the entire second insulating film 42. In some embodiments, a fifth insulating film (not shown) is positioned between the ends of adjacent first active areas 20 along the first direction D1. At least one wordline structure 60 passes through the fifth insulating film between the ends of adjacent first active areas 20 and is positioned on the fifth insulating film. The width of the wordline structure 60 is greater than the width of the fifth insulating film, meaning that the fifth insulating film is completely covered by the wordline structure 60.

[0072] In some embodiments, at least one second insulating film 42 does not overlap with the word line. The word line structure 60 is located in the cell region CR, while the second insulating film 42 is located in the peripheral region PR. This means that the second insulating film 42 does not contact the word line structure 60, and the word line structure 60 does not damage the original structure of the second insulating film 42. The word line structure 60 crosses the first active region 20, and at least one word line structure 60 contacts the end of the second active region 30.

[0073] Please refer to Figure 3a 、 Figure 3b In some embodiments, the word line structures 60 extend along the second direction D2, with at least one word line structure 60 passing through both the fourth insulating film 44 and the peripheral isolation region 45. The word line structure 60 at the outermost edge passes through the first active region 20 and the third insulating film 43, exposing a portion of the third insulating film 43. In some embodiments, at least one third insulating film 43 is completely located between the first active region 20 and the second active region 30, i.e., at least one third insulating film 43 does not contact the word line structure 60.

[0074] Please refer to Figure 4a In some embodiments, the present invention further includes word line structures 60. The word line structures 60 extend in a spaced-apart manner along the second direction D2 and intersect with the active areas and shallow trench isolation areas. At least one word line structure 60 passes through the second active area 30 and exposes the second insulating film 42. The second insulating film 42 partially overlaps with the word line structure 60. The word line structure 60 includes a first word line 61 and a second word line 62. The first word line 61 is located on at least one side of all the second word lines 62. The first word line 62 passes through the second active area 30 and exposes the second insulating film 42. The second insulating film 42 partially overlaps with the first word line 61.

[0075] In some embodiments, at least one second word line 62 passes through the first active region 20, the third insulating film 43, the fourth insulating film 44, and the peripheral isolation region 45, exposing portions of the third insulating film 43, the fourth insulating film 44, and the peripheral isolation region 45. A first word line 61 crosses at least the second active region 30 and a portion of the second insulating film 42 along the second direction D2. The first word line 61 also extends beyond the peripheral isolation region 45, which has a bumpy ring-shaped structure. The width of the first word line 61 can be the same as or different from the width of the second word line 62.

[0076] Please refer to Figure 4a 、 Figure 4b In some embodiments, at least two adjacent second active regions 30 have a first width W1 between them in the second direction D2, and the adjacent first active regions 20 have a third width W3 between them in the second direction D2. Adjacent first and second active regions 20 and 30 have a second width W2 in the second direction D2, where the second width W2 is greater than the first width W1, and the first width W1 is greater than the third width W3. This means that sufficient width is left between the adjacent second active regions 30 to accommodate the second insulating film 42, while the adjacent first active regions 20 are only provided with the first insulating film 41 in the second direction. In other embodiments, a fourth width W4 is further provided between the adjacent second active regions 30, where the fourth width W4 is less than the third width W3. The width can be an average width or a maximum width.

[0077] Please refer to Figure 1a In some embodiments, a method for preparing a semiconductor device includes providing a substrate, the substrate including a cell region CR and a peripheral region PR adjacent to the cell region CR; forming active regions on the substrate, the active regions being spaced apart along a first direction D1 and alternately arranged along a second direction D2, the active regions including a first active region 20 and a second active region 30 located on one side of the first active region 20; forming shallow trench isolation regions on the substrate, the shallow trench isolation regions being adjacent to the active regions, the shallow trench isolation regions including a first insulating film 41 and a second insulating film 42; the first insulating film 41 extending from the cell region CR to the peripheral region PR and directly contacting the active region; the second insulating film 42 being located in the peripheral region PR, the second insulating film 42 being directly contacting the first insulating film 41 and spaced apart from the active region, wherein at least one second insulating film 42 is located between the most adjacent second active regions 30 along the second direction D2.

[0078] Please refer to Figure 5 In some embodiments, a mask structure is formed on a substrate, which is a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. The mask structure includes a buffer layer and a mask layer sequentially stacked on the substrate. The mask layer can be a single layer or a multilayer structure, for example, it can be at least one of silicon oxide, silicon nitride, polysilicon, and amorphous carbon. The buffer layer can be silicon oxide. The mask layer is patterned to form a unit mask pattern 100 and a peripheral mask pattern 110 surrounding the unit mask pattern 100. The unit mask pattern 100 includes a plurality of strip-shaped separation patterns 100 extending along the first direction D1 and arranged at intervals. The peripheral mask pattern has a rectangular shape in a plane, but is not limited thereto and can also be other planar shapes.

[0079] Please refer to Figure 6 In some embodiments, a spacer 120 may be formed covering the plurality of strip-shaped separation patterns 100. For example, this may be formed using an atomic layer deposition (ALD) process to form a first mask layer M1 covering the peripheral mask pattern 110. The spacer 120 may comprise, for example, silicon oxide. The plurality of spacers 120 may be formed by forming a spacer material layer covering the plurality of strip-shaped separation patterns 100 and the substrate surface, and then removing (e.g., etching) the spacer material layer covering the upper surfaces of the strip-shaped separation patterns 100 and the spacer material layer covering the upper surface of the substrate to obtain the spacer 120. The first mask layer M1 may comprise photoresist and / or other materials (such as an anti-reflective coating (ARC) material).

[0080] Please refer to Figure 7 In some embodiments, an etching process is used to remove a plurality of strip-shaped separation patterns 100 , leaving the ring-shaped sidewall spacer 120 , and then the first mask layer M1 is removed.

[0081] Please refer to Figure 8 、 Figure 9 , forming a second mask layer M2 that partially covers the peripheral mask pattern 110 and partially covers the multiple sidewalls 120, and then removing the portion of the sidewalls 120 not covered by the second mask layer M2, to obtain strip sidewalls 120 arranged at intervals along the first direction D1 and rectangular peripheral parts 130 arranged at intervals, and then removing the second mask layer M2.

[0082] Please refer to Figure 10 A trimming process may be performed to remove portions of the strip-shaped sidewalls 120 to form a plurality of trimmed spaces 121. The plurality of trimmed spaces 121 may be arranged in a honeycomb shape, or in a hexagonal, triangular, or circular shape. For example, the plurality of trimmed spaces 121 may be arranged in a row along the first direction D1 and in a zigzag or other shape along the second direction D2. The strip-shaped sidewalls 120 may be separated by the trimmed spaces 121 to form a strip extending along the first direction D1.

[0083] Please refer to Figure 11 After performing the trimming process, the buffer layer (not shown) and the substrate are patterned using the strip spacers 120 and the peripheral member 130 as etching masks to form a plurality of active regions 10 and at least one logic active structure 131 .

[0084] Please refer to Figure 12 In some embodiments, the shape and position of the trimming space 121 can be adjusted to obtain active areas with other profiles. The multiple active areas are spaced apart along the first direction D1 and alternately arranged along the second direction D2. The active areas include a first active area 20 and a second active area 30 located on one side of the first active area 20. Cell trenches are formed between the multiple active areas. The cell trenches include a first cell trench T1, a second cell trench T2, a third cell trench T3, and a fourth cell trench T4. The first cell trench T1 is located between the sidewalls of two adjacent first active areas 20 along the first direction D1. The second cell trench T2 is located between the most adjacent second active areas 30 along the second direction D2. The third cell trench T3 is located between the ends of the adjacent first active areas 20 and the ends of the second active areas 30 along the first direction D1. The fourth cell trench T4 is located between the ends ts of the two most adjacent first active areas 20 along the second direction D2.

[0085] Please refer to Figure 1aThe first insulating film 41 conformally covers each inner surface of the first, second, third, and fourth cell trenches T1, T2, T3, and T4. The first insulating film 41 can be formed by first forming a semiconductor layer on each inner surface of the first, second, third, and fourth cell trenches T1, T2, T3, and T4, and then oxidizing the semiconductor layer to form the first insulating film 41. The first insulating film 41 can be silicon oxide. The first insulating film 41 can be a single layer or a multilayer material. The first insulating film 41 at least fills the fourth cell trench T4 and partially fills the second, third, and fourth cell trenches T2, T3, and T4. A second insulating film 42 is formed on the first insulating film 41 and directly contacts the first insulating film 41, separated from the active region. At least one second insulating film 42 is located between the most adjacent second active regions 30 along the second direction D2. The material of the second insulating film 42 is different from that of the first insulating film 41. For example, the material of the first insulating film 41 is silicon oxide, and the material of the second insulating film 42 is silicon nitride.

[0086] In some embodiments, the second insulating film 42, the third insulating film 43, and the fourth insulating film 44 can be made of the same material, such as silicon nitride. The second insulating film 42, the third insulating film 43, and the fourth insulating film 44 can be formed simultaneously on the first insulating film 41, wherein the second insulating film 42 is located in the second cell trench T2, the third insulating film 43 is located in the third cell trench T3, and the fifth insulating film is located in the fourth cell trench T4. The second cell trench T2, the third cell trench T3, and the fourth cell trench T4 are respectively filled with the second insulating film 42, the third insulating film 43, and the fifth insulating film.

[0087] In some embodiments, because the second insulating film 42, the third insulating film 43, and the fifth insulating film do not completely fill the second cell trench T2, the third cell trench T3, and the fourth cell trench T4, an insulating material layer is formed on the second insulating film 42, the third insulating film 43, and the fourth insulating film 44. The insulating material layer can be made of the same material as the second insulating film 42, such as silicon nitride or silicon oxide. In some embodiments, the peripheral isolation region 45 conformally covers the outside of all first insulating films 41 and all active areas.

[0088] In summary, the technical solution provided by the present application can improve the stability of the active area structure by adding a second insulating film between the active areas most adjacent to the edges.

[0089] The above are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. A semiconductor device, characterized in that: include: a substrate comprising a cell region and a peripheral region adjacent to the cell region; Active regions are located on the substrate, the active regions are spaced apart along a first direction and alternately arranged along a second direction, and the active regions include a first active region and a second active region located on one side of the first active region; A shallow trench isolation region is located on the substrate, the shallow trench isolation region is adjacent to the active area, and the shallow trench isolation region includes a first insulating film extending from the cell region to the peripheral region and directly contacting the active region; The second insulating film is located in the peripheral region, directly contacts the first insulating film and is separated from the active region, wherein at least one second insulating film is located between the most adjacent second active regions along the second direction.

2. The semiconductor device according to claim 1, wherein The shallow trench isolation region further includes a third insulating film. The third insulating film is located in the cell region and is disposed between an end portion of the first active region and an end portion of the second active region along the first direction.

3. The semiconductor device according to claim 2, wherein A length S1 of the second insulating film along the first direction is greater than a length S3 of the third insulating film along the first direction.

4. The semiconductor device according to claim 1, wherein The at least one second insulating film has at least a length S1 and a width S2, and 2 times the width S2 is smaller than the length S1.

5. The semiconductor device according to claim 1, wherein The invention also includes a peripheral isolation region, wherein the peripheral isolation region is located outside the first insulating film.

6. The semiconductor device according to claim 5, wherein The shallow trench isolation region further includes a fourth insulating film, and the fourth insulating film is located between the peripheral isolation region and the first active region.

7. The semiconductor device according to claim 5, wherein The profile of the second active region is different from the profile of the first active region.

8. The semiconductor device according to claim 1, wherein Adjacent second active regions have different lengths in the first direction.

9. The semiconductor device according to claim 1, wherein The first insulating film and the second insulating film are made of different materials.

10. The semiconductor device according to claim 1, wherein It also includes word line structures, which extend along the second direction in a spaced-apart manner and intersect with the active area and the shallow trench isolation area. At least one word line structure passes through the first active area and exposes at least a portion of the second insulating film.

11. The semiconductor device according to claim 10, wherein: At least one second insulating film does not overlap with the word line structure.

12. The semiconductor device according to claim 2, wherein It also includes word line structures, which extend along the second direction in a separated manner and are interlaced with the active area and the shallow trench isolation area. At least one word line structure passes through the second active area and exposes a portion of the second insulating film, and the second insulating film partially overlaps with the word line structure.

13. A semiconductor device, characterized in that: include: substrate; Active regions are located on the substrate, wherein the active regions are spaced apart along a first direction and alternately arranged along a second direction; A shallow trench isolation region is located on the substrate, the shallow trench isolation region is adjacent to the active area, and the shallow trench isolation region includes a first insulating film directly contacting the active region; The second insulating film is in direct contact with the first insulating film and separated from the active region; wherein at least one second insulating film is located between the active regions with the most adjacent edges along the second direction.

14. A semiconductor device, characterized in that: include: substrate; Active regions are located on the substrate, wherein the active regions are spaced apart along a first direction and alternately arranged along a second direction; A shallow trench isolation region is located on the substrate, the shallow trench isolation region is adjacent to the active area, and the shallow trench isolation region includes a first insulating film directly contacting the active region; a second insulating film, directly contacting the first insulating film and separated from the active region; a peripheral isolation region, located outside the first insulating film and in direct contact with the first insulating film; Wherein, at least one second insulating film is located between the active region and the peripheral isolation region along the first direction.

15. The semiconductor device according to claim 14, wherein: The second insulating film is separated from the peripheral isolation region by the first insulating film.

16. The semiconductor device according to claim 14, wherein: The active region includes a first active region and a second active region located on one side of the first active region. The second insulating film is located between the peripheral isolation region and the first active region located at the outermost edge in a first direction.

17. The semiconductor device according to claim 16, wherein: The side of the peripheral isolation region close to the second active region includes a continuous rough surface, the surface including protrusions and recesses, the protrusions corresponding to the second insulating film along the first direction, and the recesses corresponding to the second active region along the first direction.

18. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a cell region and a peripheral region adjacent to the cell region; forming active regions on the substrate, wherein the active regions are spaced apart along a first direction and alternately arranged along a second direction, and the active regions include a first active region and a second active region located on one side of the first active region; A shallow trench isolation region is formed on the substrate, wherein the shallow trench isolation region is adjacent to the active region, and the shallow trench isolation region includes a first insulating film extending from the cell region to the peripheral region and directly contacting the active region; The second insulating film is located in the peripheral region, directly contacts the first insulating film and is separated from the active region, wherein at least one second insulating film is located between the most adjacent second active regions along the second direction.

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