Integrated circuit and operating method thereof

Abstract

An integrated circuit is provided that includes a first temperature sensitive device and a second temperature sensitive device. The first temperature sensitive device is configured to generate a reference voltage at an output terminal of the integrated circuit. The second temperature-sensitive device is coupled to the output terminal of the integrated circuit through the resistor and configured to work in cooperation with the first temperature-sensitive device to generate a first bias current flowing from the output terminal of the integrated circuit to a ground node through the resistor and the first temperature-sensitive device. The first bias current monotonically increases as the absolute temperature of the integrated circuit increases. The embodiment of the invention also provides a method for operating the integrated circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuits and methods of operating the same. Background Art

[0002] The current trend toward integrated circuit (IC) miniaturization has led to the development of smaller, more efficient, more powerful, and faster devices. This miniaturization process also creates more stringent design and manufacturing requirements, as well as reliability challenges. Electronic design automation (EDA) tools are used to create, optimize, and verify standard cell layout designs for integrated circuits, ensuring they meet both design and manufacturing specifications. Summary of the Invention

[0003] According to one aspect of an embodiment of the present application, an integrated circuit is provided, comprising: a first temperature-sensitive device configured to generate a reference voltage at an output terminal of the integrated circuit; and a second temperature-sensitive device coupled to the output terminal of the integrated circuit via a resistor, and configured to cooperate with the first temperature-sensitive device to generate a first bias current, the first bias current flowing from the output terminal of the integrated circuit through the resistor and the first temperature-sensitive device to a ground node, wherein the first bias current increases monotonically with an increase in the absolute temperature of the integrated circuit.

[0004] According to another aspect of an embodiment of the present application, an integrated circuit is provided, comprising: a first temperature-sensitive device; and a second temperature-sensitive device, coupled to the first temperature-sensitive device via a resistor, and configured to function as a first voltage source that varies with the absolute temperature of the integrated circuit, and to cooperate with the first temperature-sensitive device to function as a second voltage source that varies with the absolute temperature of the integrated circuit, wherein the second temperature-sensitive device is further configured to compensate the first voltage source with the second voltage source to generate a reference voltage at an output terminal of the integrated circuit.

[0005] According to another aspect of an embodiment of the present application, a method for operating an integrated circuit is provided, comprising: providing an integrated circuit comprising a first temperature-sensitive device and a second temperature-sensitive device; generating a bias current using a first voltage on the first temperature-sensitive device and a second voltage on the second temperature-sensitive device, wherein the bias current flows from an output terminal of the integrated circuit through a resistor and the first temperature-sensitive device; and generating a reference voltage at the output terminal of the integrated circuit based on the second voltage and the bias current, wherein the first voltage and the second voltage monotonically decrease with an increase in the absolute temperature of the integrated circuit, and the bias current monotonically increases with an increase in the absolute temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a schematic diagram of a voltage reference circuit according to some embodiments of the present disclosure.

[0008] Figure 1B is a diagram of a stacked gate device according to some embodiments of the present disclosure.

[0009] Figure 1C yes Figure 1B Equivalent circuit diagram of the stacked-gate device in Figure 1.

[0010] Figure 1D is a diagram of a stacked gate device having multiple finger structures according to some embodiments of the present disclosure.

[0011] Figure 1E yes Figure 1D Equivalent circuit diagram of the stacked-gate device in .

[0012] Figure 2A is a schematic diagram of a stacked gate device in a diode-connected configuration according to some embodiments of the present disclosure.

[0013] Figure 2B It shows Figure 2A FIG. 5 is a diagram showing the change in the voltage-temperature curve of the stacked gate device in FIG.

[0014] Figure 3 is a schematic diagram of a voltage reference circuit according to some embodiments of the present disclosure.

[0015] Figures 4A-4D According to some embodiments of the present disclosure,

[0016] Schematic diagram of fine-tuning the number of finger-like stacked gate devices.

[0017] Figures 5A-5D Schematic diagram of a buffer circuit in different implementations according to some embodiments of the present disclosure.

[0018] Figure 6 is a schematic diagram of a voltage reference circuit according to some embodiments of the present disclosure.

[0019] Figure 7 is a flow chart of a method of operating a voltage reference circuit according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are formed to be in direct contact, and may also include embodiments in which an accessory component may be formed between the first component and the second component such that the first component and the second component are not in direct contact. Furthermore, the present invention may refer to repeated numbers and / or letters in various examples. This repetition is for simplicity and clarity, but does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "over," "upper," and the like, may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0022] Further, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it can be directly connected or coupled to the other element or intervening elements may be present.

[0023] Specific language is used below to disclose the embodiments or examples shown in the accompanying drawings. However, it should be understood that these embodiments and examples are not intended to be limiting. Any changes or modifications in the disclosed embodiments, as well as any further applications of the principles disclosed herein, are contemplated as would normally occur to one of ordinary skill in the art.

[0024] Furthermore, it is understood that various processing steps and / or components of a device may be described only briefly. Furthermore, additional processing steps or components may be added, and certain of the following processing steps or components may be removed and / or modified while still practicing the present claims. Therefore, it should be understood that the following descriptions represent examples only and are not intended to indicate that one or more steps or components are required.

[0025] In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity, but it does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0026] In some embodiments, a voltage reference circuit is implemented to generate a reference voltage using a stacked gate device. The stacked gate device includes a plurality of field effect transistors having a common gate terminal and having channels connected in series. A first temperature-sensitive device is implemented based on the first stacked gate device to generate a first gate-source voltage that decreases monotonically with the absolute temperature of the voltage reference circuit. A second temperature-sensitive device is implemented based on the second stacked gate device to generate a second gate-source voltage that decreases monotonically with the absolute temperature of the voltage reference circuit. A bias current that increases monotonically with absolute temperature is generated based on the first gate-source voltage and the second gate-source voltage. The temperature dependence of the reference voltage generated by the voltage reference circuit can be compensated using the first voltage and the bias current.

[0027] Figure 1A is a schematic diagram of a voltage reference circuit according to some embodiments of the present disclosure. Figure 1B is a diagram of a stacked gate device according to some embodiments of the present disclosure. Figure 1C yes Figure 1B Equivalent circuit diagram of the stacked-gate device in Figure 1.

[0028] In some embodiments, the voltage reference circuit 100A is a bandgap voltage reference circuit that provides a reference voltage VREF. The voltage reference circuit 100A may include transistors M1 to M2, temperature sensitive devices 110 and 120, and a trimming circuit 130, such as Figure 1A As shown. Transistors M1 to M2 may be field effect transistors (FETs, hereinafter referred to as "transistors"). Each of transistors M1 to M2 has a gate terminal and a channel between a source terminal and a drain terminal. The current passing through the channel depends on the voltage difference applied to the gate terminal of each transistor M1 to M2.

[0029] Voltage reference circuit 100A includes stacked-gate devices X1, X2, and X2_trim0 through X2_trimx. Each of stacked-gate devices X1 and X2 includes a plurality of field-effect transistors stacked together. Reference numerals X1 and X2 are also used to denote the number of FETs connected in series within each stacked-gate device X1 and X2. Furthermore, each stacked-gate device X2_trim0 through X2_trimx has the same number of stacked transistors as stacked-gate device X2 within temperature-sensitive device 120. However, the number of finger structures within stacked-gate devices X2_trim0 through X2_trimx may differ from that within stacked-gate device X2. Details of the stacked-gate devices are described below.

[0030] In some embodiments, the stacked gate device 150, Figure 1BAlso referred to as "stack X" in the figure, it can be regarded as a three-terminal transistor device having a gate terminal 151, a source / drain (S / D) terminal 152, and a (S / D) terminal 153. The equivalent circuit diagram of the stacked gate device 150 includes a plurality of transistors 1501 arranged in a cascode structure or a stack structure, as shown in FIG. Figure 1C As shown. The total number of stacked transistors 1501 is represented by an integer X. For example, the gate terminals of the transistors 1501 are connected together to form the gate terminal 151 of the stacked gate device 150. In addition, the transistors 1501 can be N-type FETs, and the N-type channels of the transistors 1501 (e.g., X transistors 1501) are connected in series between the (S / D) terminal 152 and the (S / D) terminal 153 of the stacked gate device 150. For example, the (S / D) terminal of the first transistor 1501 serves as the (S / D) terminal 152 of the stacked gate device 150, and the (S / D) terminal of the first transistor 1501 is connected to the (S / D) terminal of the second transistor 1501, the (S / D) terminal of the second transistor 1501 is connected to the (S / D) terminal 1501 of the third transistor, and so on. In other words, for each integer n between 1 and X-1, the (S / D) terminal of the nth transistor 1501 is connected to the (S / D) terminal of the (n+1)th transistor 1501. Therefore, the (S / D) terminal of the last transistor 1501 (i.e., the Xth transistor 1501) serves as the (S / D) terminal 153 of the stacked gate device 150.

[0031] Figure 1D is a diagram of a stacked gate device having multiple finger structures according to some embodiments of the present disclosure. Figure 1E yes Figure 1D Equivalent circuit diagram of the stacked-gate device in .

[0032] In some embodiments, Figure 1B The stacked gate device 150 shown in FIG. 1 includes one or more stacked gate devices TX1 to TXN arranged in parallel, such as Figure 1D As shown, where N is a positive integer. Each stacked gate device TX1 to TXN can be regarded as a finger structure or "finger", which includes X transistors 1501 arranged in a cascode structure or a stacked structure, as shown in FIG. Figure 1EAs shown. For example, the channels of transistors 1501 within each stacked gate device TX1 to TXN are connected in series to form the corresponding channels of each stacked gate device TX to TXN. In addition, the channels of each stacked gate device TX1 to TXN are coupled between (S / D) terminals 152 and (S / D) terminals 153 of the stacked gate device 150, and the gate terminals of the stacked gate devices TX1 to TXN are connected to the gate terminal 151 of the stacked gate device 150. When the stacked gate device 150 includes a finger structure, the equivalent circuit diagram of the stacked gate device 150 can be referred to. Figure 1C .

[0033] It should be noted that the transistors 1501 within the stacked gate devices TX1 to TXN can be manufactured within the same process and therefore have substantially the same electrical characteristics, such as channel width, channel length, threshold voltage, and transconductance. Figure 1D and Figure 1E The design of the stacked gate device X with one or more finger structures shown in FIG can be applied to Figure 1A The stacked gate devices X1, X2 and X2_trim0 to X2_trimx in FIG. 1 have substantially the same electrical characteristics.

[0034] In some embodiments, Figure 1B The gate-source voltage Vgs of the stacked gate device 150 shown in can be expressed by equation (1) as follows.

[0035]

[0036] Wherein Vth represents the threshold voltage of the stacked gate device 150; I represents the bias current flowing through the stacked gate device 150; L1 and W1 represent the channel length and channel width of the stacked gate device 150, respectively; Cox represents the gate oxide capacitance per unit area of ​​the stacked gate device 150; and μ represents the electron mobility. It should be noted that as the temperature increases, the energy of the electrons increases, and the energy barrier between the (S / D) terminal 153 of the stacked gate device 150 and the channel becomes lower, allowing more carriers to exist in the channel, thereby reducing the threshold voltage. In other words, when the bias current I is fixed, the threshold voltage Vth decreases with increasing temperature, resulting in the gate-source voltage Vgs of the stacked gate device 150 decreasing monotonically with absolute temperature (e.g., complementary to absolute temperature, CTAT).

[0037] Figure 2A is a schematic diagram of a stacked gate device in a diode-connected configuration according to some embodiments of the present disclosure. Figure 2B It shows Figure 2A FIG. 5 is a diagram showing the change in the voltage-temperature curve of the stacked gate device in FIG.

[0038] In some embodiments, the stacked gate device 150 is in a diode-connected configuration, meaning that the gate terminal 151 of the stacked gate device 150 is connected to the (S / D) terminal 152 of the stacked gate device 150 and a bias current Ib is provided to the stacked gate device 150, as shown in FIG. Figure 2A In this case, the voltage difference (eg, gate-source voltage) Vgs between the gate terminal 151 and the (S / D) terminal 153 of the stacked gate device 150 decreases as the absolute temperature of the stacked gate device X increases, as shown in FIG. Figure 2B , as shown by curve 202 in FIG. 1 . In addition, the downward slope of the voltage-temperature curve depends on the number of stacked transistors in the stacked gate device X. For example, as the number of stacked transistors increases (e.g., a larger stack X), the slope of the VT curve decreases, as shown in FIG. Figure 2B As shown by curve 204 in FIG, this indicates that the voltage difference Vgs between the gate terminal 151 and the (S / D) terminal 153 of the stacked gate device X becomes less sensitive to changes in absolute temperature. As a result, the output voltage VO1 generated by the stacked gate device 150 decreases monotonically with absolute temperature (e.g., complementary to absolute temperature, CTAT). Therefore, Figure 2A The stacked gate device 150 in the configuration shown may be considered a CTAT device.

[0039] In some embodiments, Figure 1B The stacked gate device 150 in the configuration shown has Figure 2B As the number of stacked transistors increases (e.g., a larger stack X), the downward slope of the VT curve decreases, as shown in FIG. Figure 2B As shown by curve 204 in FIG, this indicates that the voltage difference Vgs between the gate terminal 151 and the (S / D) terminal 153 of the stacked gate device X becomes less sensitive to changes in absolute temperature. That is, as the number of stacked transistors in the stacked gate device 150 increases, the downward slope of the VT (Vgs vs. absolute temperature) curve of the stacked gate device 150 can become less steep. This mechanism of the VT curve can be applied to Figure 1A Stacked gate devices X1 and X2 are shown.

[0040] Now turn your attention back to Figure 1A In some embodiments, the temperature sensitive devices 110 and 120 include stacked gate devices X1 and X2, respectively. The number X1 of stacked transistors in the stacked gate device X1 is greater than the number X2 of stacked transistors in the stacked gate device X2. Figure 2A-2BIn the embodiment, it can be seen that both stacked-gate devices X1 and X2 are CTAT devices, and that the gate-source voltages Vgs1 of stacked-gate device X1 and Vgs2 of stacked-gate device X2 decrease as the absolute temperature of voltage reference circuit 100A increases. Note that because the number X1 is greater than the number X2, stacked-gate device X1 is less sensitive to changes in absolute temperature than stacked-gate device X2. Therefore, the decrease in gate-source voltage Vgs1 of stacked-gate device X1 is less than the decrease in gate-source voltage Vgs2 of stacked-gate device X2, indicating that the voltage difference Vgs1-Vgs2 increases with increasing absolute temperature. Furthermore, while bias current Ib2 can be calculated as (Vgs1-Vgs2) / R, this means that bias current Ib2 flowing through stacked-gate device X1 increases with increasing absolute temperature. Therefore, bias current Ib2 is a PTAT current that increases monotonically with the absolute temperature of voltage reference circuit 100A.

[0041] In some embodiments, the reference voltage VREF is the same as the gate-source voltage Vgs1 of the stacked gate device X1. Figure 1A As shown. According to equation (1), the threshold voltage Vth of the stacked gate device X1 decreases with increasing absolute temperature, while the bias current Ib2 increases with increasing absolute temperature, indicating that the temperature-sensitive device 110 acts as both a PTAT voltage source and a CTAT voltage source. This means that the CTAT behavior of the threshold voltage Vth of the stacked gate device X1 can be compensated by the PTAT behavior of the bias current Ib2 flowing through the stacked gate device X1, thereby obtaining a self-compensated temperature coefficient of the reference voltage VREF. In addition, by appropriately designing the number of stacked transistors in the stacked gate devices X1 and X2 and the number of finger structures in the stacked gate device X2, the reference voltage VREF generated by the voltage reference circuit 100A can achieve a temperature coefficient substantially equal to zero. The following describes a specific method for adjusting the number of finger structures in the stacked gate device X2 using the fine-tuning circuit 130.

[0042] In some embodiments, the reference voltage VREF generated at the node N2 can be expressed in another manner, for example, VREF=Vgs2+Ib2*R, where Vgs2 represents the gate-source voltage Vgs2 of the stacked-gate device X2, and Ib2*R represents the voltage drop across the resistor R. The gate-source voltage Vgs2 is CTAT, and the bias current Ib2 is PTAT. However, the CTAT scheme can also be compensated with the PTAT scheme in another manner to generate the reference voltage VREF, thereby obtaining a self-compensated temperature coefficient of the reference voltage VREF.

[0043] In some embodiments, the gate terminals of transistors M1 and M2 are electrically connected to node N1, and the source terminals of transistors M1 and M2 are electrically connected to a power supply voltage VDD. Because transistors M1 and M2 have the same gate-source voltage Vgs, transistors M1 and M2 can be configured as a first current mirror, with the bias current Ib2 flowing through the channel of transistor M2 being proportional to the bias current Ib1 flowing through the channel of transistor M1. When transistors M1 and M2 are designed to have substantially the same electrical characteristics (e.g., channel width, channel length, threshold voltage, and transconductance), the bias current Ib2 flowing through transistor M2 is substantially equal to the bias current Ib1 flowing through transistor M1. Therefore, transistor M1 can function as a current source, as can transistor M2. As described above, bias current Ib2 is a PTAT current, indicating that bias current Ib1 is also a PTAT current.

[0044] In some embodiments, the trimming circuit 130 can be configured to adjust (e.g., trim) the voltage-temperature droop rate of the temperature sensitive device 120 using a dynamic element matching ("DEM") technique. The trimming circuit 130 may include a plurality of trimming stacked gate devices X2_trim0 to X2_trimx. A gate terminal of each trimming stacked gate device X2_trim0 to X2_trimx is coupled to a corresponding bit of the trimming code signal TC[0:x] through a corresponding buffer circuit FB0 to FBx. A drain terminal and a source terminal of each trimming stacked gate device X2_trim0 to X2_trimx are coupled between a voltage VBP, a voltage at a node N1, and a ground node. In addition, each buffer circuit FB0 to FBx may be supplied with a voltage VG, a voltage at a node N3, and a ground voltage VSS, as shown in FIG. Figure 1A shown.

[0045] It should be noted that each trim stacked gate device X2_trim0 to X2_trimx may include one or more finger structures arranged in parallel, wherein each finger structure has the same number of stacked transistors as the stacked gate device X2. In addition, the trim stacked gate devices X2_trim0 to X2_trimx may have the same number of finger structures or a different number of finger structures, depending on the type of trim code signal TC[0:x] used. Figures 4A to 4D Describe its details.

[0046] Figure 3 is a schematic diagram of a voltage reference circuit according to some embodiments of the present disclosure.

[0047] In some embodiments, a fine-tuning circuit 130 may be used to adjust the number of finger structures coupled in parallel to the stacked gate device X2. Figure 3The trimming circuit 130 in the voltage reference circuit 100B shown in FIG. 1 includes four trimming stacked-gate devices X2_trim0 through X2_trim3, which are controlled by corresponding bits of the trimming code signal TC[0:3] via corresponding buffer circuits FB0 through FB3. For example, the buffer circuits FB0 through FB3 are supplied with voltage VG (e.g., the gate voltage of the stacked-gate device X2) and ground voltage VSS. Furthermore, each bit of the trimming code signal TC[0:3] can be transferred to the gate terminals B0 through B3 of the trimming stacked-gate devices X2_trim0 through X2_trim3 via corresponding buffer circuits FB0 through FB3. Furthermore, the voltage range of each bit of the trimming code signal TC[0:3] is between voltage VG and ground voltage VSS.

[0048] In some embodiments, each trim stacked gate device X2_trim0 through X2_trim3 has the same number of fingers, e.g., 1 to N, where N is a positive integer. When trim circuit 130 employs heat table encoding, each bit of trim code signal TC[0:3] can control the same number of fingers coupled in parallel to stacked gate device X2. For simplicity, assume that stacked gate device X2 has four stacked transistors and includes one finger. Furthermore, each trim stacked gate device X2_trim0 through X2_trim3 includes one finger. When trim code signal TC[3:0] = 4'b1101, voltage VG is transmitted to gate terminals B0, B2, and B3 of trim stacked gate devices X2_trim0, X2_trim2, and X2_trim3, activating trim stacked gate devices X2_trim0, X2_trim2, and X2_trim3. At the same time, ground voltage VSS is transferred to gate terminal B1, thereby deactivating trim stacked gate device X2_trim1. Consequently, three fingers are activated and coupled in parallel with the fingers of stacked gate device X2, representing a total of four fingers for adjusting the downward slope of the VT (e.g., Vgs2 vs. absolute temperature) curve of stacked gate device X2, thereby fine-tuning the temperature coefficient of the PTAT current (e.g., Ib2 = (Vgs1 - Vgs2) / R) generated by voltage reference circuit 100B.

[0049] In some embodiments, each trim stacked gate device X2_trim0 to X2_trim3 may have a different number of finger structures, such as a power of 2. For simplicity, assume that there are 4 stacked transistors in the stacked gate device X2, and the stacked gate device X2 includes one finger structure. In addition, the trim stacked gate devices X2_trim0 to X2_trim3 include 1, 2, 4, and 8 finger structures, respectively, and each finger structure includes 4 stacked transistors, such as Figures 4A-4DWhen trim circuit 130 employs binary encoding, each bit of trim code signal TC[0:3] can control a different number of finger structures coupled in parallel with stacked gate device X2. When trim code signal TC[3:0] = 4'b1101, voltage VG is transmitted to gate terminals B0, B2, and B3 of trim stacked gate devices X2_trim0, X2_trim2, and X2_trim3, activating trim stacked gate devices X2_trim0, X2_trim2, and X2_trim3. Simultaneously, ground voltage VSS is transmitted to gate terminal B1, deactivating trim stacked gate device X2_trim1. Thus, 13 (e.g., 1+4+8) finger structures are activated to be coupled in parallel to the finger structures of the stacked gate device X2, indicating that a total of 14 finger structures are used to adjust the downward slope of the VT (e.g., Vgs2 vs. absolute temperature) curve of the stacked gate device X2, thereby fine-tuning the temperature coefficient of the PTAT current (e.g., Ib2 = (Vgs1-Vgs2) / R) generated by the voltage reference circuit 100B.

[0050] Figures 5A-5D Schematic diagram of a buffer circuit in different implementations according to some embodiments of the present disclosure.

[0051] In some embodiments, Figure 1A Each of the buffer circuits FB0 to FBx in the Figure 5A The buffer circuit 500A shown in FIG. Buffer circuit 500A includes two inverters connected in series (e.g., transistors Q1+Q2 and Q3+Q4), which are supplied with voltage VG and ground voltage VSS, respectively. An input signal TC[x] to buffer circuit 500A can be transmitted through buffer circuit 500A to gate terminal Bx of trim stacked gate device X2_trimx. Furthermore, when input signal TC[x] is in a high logic state (e.g., "1") and a low logic state (e.g., "0"), input signal TC[x] can be at voltage VG and ground voltage VSS, respectively. For example, when input signal TC[x] is in a high logic state (e.g., "1"), transistor Q2 is turned on and transistor Q1 is turned off, causing the voltage at node N7 to be pulled down to ground voltage VSS. At this time, transistor Q3 is turned on and transistor Q4 is turned off, causing the voltage at gate terminal Bx to be pulled up to voltage VG. As a result, trim stacked gate device X2_trimx is turned on (eg, selected), and one or more finger structures within trim stacked gate device X2_trimx are coupled in parallel with stacked gate device X2, indicating that the selected trim stacked gate device X2_trimx can contribute to the VT curve of temperature sensitive device 120.

[0052] On the other hand, in response to the input signal TC[x] being in a low logic state (e.g., "0"), transistor Q1 is turned on and transistor Q2 is turned off, causing the voltage at node N7 to be pulled up to voltage VG. At this time, transistor Q4 is turned on and transistor Q3 is turned off, causing the voltage at gate terminal Bx to be pulled down to ground voltage VSS. As a result, trim stacked gate device X2_trimx is turned off (e.g., unselected), and one or more finger structures within trim stacked gate device X2_trimx are not coupled in parallel with stacked gate device X2, indicating that the unselected trim stacked gate device X2_trimx has no effect on the VT curve of temperature sensitive device 120.

[0053] In some embodiments, Figure 1A Each of the buffer circuits FB0 to FBx in the Figure 5B The buffer circuit 500B shown in FIG. The input signal to the buffer circuit 500B may be TC[x]', which is complementary to the corresponding bit TC[x] of the trim signal TC. For example, in response to the input signal TC[x]' being in a high logic state (e.g., "1"), transistor Q2 is turned on and transistor Q1 is turned off, causing the voltage at the gate terminal Bx to be pulled down to the ground voltage VSS. As a result, the trim stacked gate device X2_trimx is turned off (e.g., unselected), and one or more finger structures within the trim stacked gate device X2_trimx are not coupled to the stacked gate device X2, indicating that the unselected trim stacked gate device X2_trimx has no effect on the VT curve of the temperature sensitive device 120. On the other hand, in response to the input signal TC[x]' being in a low logic state (e.g., "0"), transistor Q1 is turned on and transistor Q2 is turned off, causing the voltage at the gate terminal Bx to be pulled up to the voltage VG. As a result, trim stacked gate device X2_trimx is turned on (eg, selected), and one or more finger structures within trim stacked gate device X2_trimx are coupled in parallel with stacked gate device X2, indicating that the selected trim stacked gate device X2_trimx can contribute to the VT curve of temperature sensitive device 120.

[0054] In some embodiments, Figure 1A Each of the buffer circuits FB0 to FBx in the Figure 5CBuffer circuit 500C is implemented as shown. Buffer circuit 500C can be implemented using a CMOS transmission gate including transistors Q5 and Q6. When input signals TC[x] and TC[x]' are in a high logic state (e.g., "1") and a low logic state (e.g., "0"), respectively, transistors Q5 and Q6 are turned on, causing voltage VG to pass through buffer circuit 500C to gate terminal Bx. As a result, trim stacked gate device X2_trimx is turned on (e.g., selected), and one or more finger structures within trim stacked gate device X2_trimx are coupled in parallel with stacked gate device X2, indicating that the selected trim stacked gate device X2_trimx can contribute to the VT curve of temperature sensitive device 120. On the other hand, in response to input signals TC[x] and TC[x]' being in a low logic state (e.g., "0") and a high logic state (e.g., "1"), respectively, transistors Q5 and Q6 are turned off, causing gate terminal Bx to be in a floating state. When the gate terminal Bx of the fine-tuning stacked gate device X2_trimx is floating, the fine-tuning stacked gate device X2_trimx is cut off (i.e., not selected), and one or more finger structures within the fine-tuning stacked gate device X2_trimx are not coupled with the stacked gate device X2, indicating that the unselected fine-tuning stacked gate device X2_trimx has no effect on the VT curve of the temperature-sensitive device 120.

[0055] In some embodiments, Figure 1A Each of the buffer circuits FB0 to FBx in the Figure 5DThe buffer circuit 500D shown in FIG. Buffer circuit 500D includes switches S1 and S2, which are controlled by input signals TC[x] and TC[x]', respectively. In response to input signals TC[x] and TC[x]' being in a high logic state (e.g., "1") and a low logic state (e.g., "0"), respectively, switch S1 is activated and switch S2 is deactivated, such that voltage VG is passed to gate terminal Bx through switch S1. As a result, trim stacked gate device X2_trimx is turned on (e.g., selected), and one or more finger structures within trim stacked gate device X2_trimx are coupled in parallel with stacked gate device X2, indicating that the selected trim stacked gate device X2_trimx can contribute to the VT curve of temperature sensitive device 120. On the other hand, in response to the input signals TC[x] and TC[x]′ being in a low logic state (e.g., “0”) and a high logic state (e.g., “1”), respectively, switch S1 is deactivated and switch S2 is activated, causing the voltage at gate terminal Bx to be pulled down to ground voltage VSS. As a result, trim stacked gate device X2_trimx is turned off (e.g., unselected), and one or more finger structures within trim stacked gate device X2_trimx are not coupled to stacked gate device X2, indicating that the unselected trim stacked gate device X2_trimx has no effect on the VT curve of temperature sensitive device 120.

[0056] Figure 6 is a schematic diagram of a voltage reference circuit according to some embodiments of the present disclosure.

[0057] Figure 6 The voltage reference circuit 100C shown is Figure 1A The voltage reference circuit 100A is similar to the one shown, except that the temperature sensitive device 140 is coupled between the power supply voltage VDD and the node N3. In some embodiments, the temperature sensitive device 140 includes a stacked gate device X3 that is "scaled" to the stacked gate device X1, indicating that the stacked gate device X3 is substantially the same as the stacked gate device X1. Figure 6As shown, stacked-gate device X3 is diode-connected, with its gate terminal and (S / D) terminal electrically connected to power supply voltage VDD, and its (S / D) terminal electrically connected to node N3. Consequently, bias current Ib3 flows through the channels of stacked-gate device X3 and stacked-gate device X1, with the total current flowing through stacked-gate device X1 being Ib2 + Ib3. Note that bias current Ib2 flowing through resistor R and stacked-gate device X2 is a PTAT current, while bias current Ib3 flowing through stacked-gate device X3 is a CTAT current. Thus, bias current Ib3 can help reduce bias currents Ib1 and Ib2 while simultaneously compensating for the temperature coefficient of reference voltage VREF, thereby allowing bias current Ib2 to be fine-tuned using fine-tuning circuit 130 (e.g., each step in adjusting bias currents Ib1 and Ib2 can be reduced with each bit of fine-tuning code signal TC). Figure 6 The details of the fine-tuning circuit 130 shown in FIG. Figure 3 、 Figures 4A-4D 、 Figures 5A-5D The embodiments of the present invention will not be described in detail here.

[0058] In some embodiments, the accuracy of the reference voltage VREF generated by the voltage reference circuit 100C can be improved by reducing the ratio between the bias current Ib2 (e.g., the PTAT current) and the bias current Ib3 (e.g., the CTAT current). In some embodiments, the average value AVG and standard deviation σ of the reference voltage VREF generated by the voltage reference circuit 100C were calculated using 300 Monte Carlo simulations, with the reference voltage VREF at approximately 25°C. The error of the reference voltage VREF generated by the voltage reference circuit 100C, calculated as 3σ / AVG, was within 1.5%.

[0059] Figure 7 is a flow chart of a method of operating a voltage reference circuit according to some embodiments of the present disclosure. Figure 7 The order in which the operations of method 700 are described is for illustration only; the operations of method 700 can be performed in the same order as Figure 7 It should be understood that the order in which Figure 7 Additional operations may be performed before, during, and / or after the method 700 shown in FIG. 7 , so some of the other processes are only briefly described herein.

[0060] In operation 710, an integrated circuit including a first temperature sensitive device and a second temperature sensitive device is provided. Figure 1A In an embodiment, a voltage reference circuit 100A (eg, an integrated circuit) includes temperature sensitive devices 110 and 120 (eg, first and second temperature sensitive devices, respectively).

[0061] In operation 720, a bias current is generated using a first voltage on the first temperature sensitive device and a second voltage on the second temperature sensitive device, wherein the bias current flows from an output terminal of the integrated circuit through a resistor and the first temperature sensitive device. Figure 2A In the embodiment, because the number of X1 is greater than the number of X2, as the temperature increases, the gate-source voltage Vgs1 of stacked-gate device X1 decreases less than the gate-source voltage Vgs2 of stacked-gate device X2, resulting in the difference between Vgs1 and Vgs2 being proportional to the absolute temperature. Consequently, a bias current Ib2 is generated, which flows through the resistor and stacked-gate device X1.

[0062] In operation 730, a reference voltage is generated at an output terminal of the integrated circuit based on the second voltage and the bias current. Figure 1A In an embodiment, a CTAT scheme for the threshold voltage Vth of the stacked gate device X1 is compensated by a PTAT scheme for the bias current Ib2 flowing through the stacked gate device X1 to generate a reference voltage VREF. Alternatively, when the gate-source voltage Vgs2 (e.g., the second voltage) is CTAT and the bias current Ib2 (e.g., the bias current) is PTAT, the CTAT scheme can also be compensated by the PTAT scheme in another manner to generate the reference voltage VREF.

[0063] One aspect of the present disclosure provides an integrated circuit comprising a first temperature-sensitive device and a second temperature-sensitive device. The first temperature-sensitive device is configured to generate a reference voltage at an output terminal of the integrated circuit. The second temperature-sensitive device is coupled to the output terminal of the integrated circuit via a resistor and is configured to cooperate with the first temperature-sensitive device to generate a first bias current that flows from the output terminal of the integrated circuit through the resistor and the first temperature-sensitive device to a ground node. The first bias current increases monotonically with an increase in the absolute temperature of the integrated circuit.

[0064] In some embodiments, the resistor is coupled between an output terminal of the integrated circuit and a first node, and the integrated circuit further comprises a current source coupled to the second temperature-sensitive device and configured to generate a second bias current flowing through the second temperature-sensitive device, the second bias current being substantially equal to the first bias current.

[0065] In some embodiments, the first temperature-sensitive device includes a first stacked gate device having a gate terminal connected to an output terminal of the integrated circuit, a first terminal connected to the first node, and a second terminal connected to the ground node; and the first stacked gate device includes one or more first finger structures arranged in parallel, each first finger structure including a first number of field effect transistors connected in series.

[0066] In some embodiments, the second temperature-sensitive device includes a second stacked gate device having a gate terminal connected to the first node of the integrated circuit, a first terminal connected to the second node, and a second terminal connected to the ground node; and the second stacked gate device includes one or more second finger structures arranged in parallel, each second finger structure including a second number of field effect transistors connected in series.

[0067] In some embodiments, the first amount is greater than the second amount.

[0068] In some embodiments, field effect transistors within the first stacked gate device and the second stacked gate device have substantially equal threshold voltages.

[0069] In some embodiments, the integrated circuit further includes: a fine-tuning circuit comprising: a plurality of fine-tuning stacked gate devices arranged in parallel with the second stacked gate device; and a plurality of buffer circuits, each buffer circuit being configured to be powered by the voltage at the first node and the ground voltage, wherein each fine-tuning stacked gate device is controlled by a corresponding bit of the fine-tuning code signal through a corresponding buffer circuit.

[0070] In some embodiments, each of the fine-tuned stacked gate devices includes a different number of power-of-two finger structures, and each finger structure within the fine-tuned stacked gate device includes a second number of field effect transistors connected in series.

[0071] In some embodiments, each of the trim stacked gate devices includes an equal number of finger structures, and each finger structure within the trim stacked gate device includes a second number of field effect transistors connected in series.

[0072] In some embodiments, in response to a corresponding bit of a particular fine-tuned stacked gate device being in a first logic state, the reference voltage is provided to a gate terminal of the particular fine-tuned stacked gate device through a corresponding buffer circuit, such that the particular fine-tuned stacked gate device can be coupled in parallel to the second stacked gate device.

[0073] In some embodiments, in response to a corresponding bit of the particular fine-tuned stacked gate device being in a second logic state complementary to the first logic state, the ground voltage is provided to the gate terminal of the particular fine-tuned stacked gate device through the corresponding buffer circuit such that the particular fine-tuned stacked gate device cannot be coupled in parallel to the second stacked gate device.

[0074] In some embodiments, the integrated circuit further includes: a third temperature-sensitive device coupled between a power supply voltage and the first node and configured to generate a third bias current flowing through the third temperature-sensitive device and the first temperature-sensitive device, wherein the third bias current decreases monotonically with the absolute temperature.

[0075] In some embodiments, the third temperature-sensitive device includes a third stacked gate device having a first terminal and a gate terminal connected to the power supply voltage, and a second terminal connected to the first node, and the third stacked gate device includes one or more third finger structures arranged in parallel, each third finger structure including a first number of field effect transistors connected in series.

[0076] Another aspect of the present disclosure provides an integrated circuit comprising a first temperature-sensitive device and a second temperature-sensitive device. The second temperature-sensitive device is coupled to the first temperature-sensitive device via a resistor and configured to function as a first voltage source that varies with the absolute temperature of the integrated circuit. The second temperature-sensitive device operates in conjunction with the first temperature-sensitive device to function as a second voltage source that varies with the absolute temperature of the integrated circuit. The second temperature-sensitive device is further configured to compensate the first voltage source with the second voltage source to generate a reference voltage at an output terminal of the integrated circuit.

[0077] In some embodiments, the first voltage source provides a first voltage that is complementary to an absolute temperature of the integrated circuit, and the second voltage source provides a second voltage that is proportional to the absolute temperature.

[0078] In some embodiments, the first temperature sensitive device is configured to generate a third voltage between a first node and a ground node, and to allow a bias current to flow from an output terminal of the integrated circuit to the ground node through the resistor and the second temperature sensitive device.

[0079] In some embodiments, the bias current is equal to a voltage difference between the reference voltage and the third voltage divided by a resistance of the resistor.

[0080] In some embodiments, the first temperature sensitive device includes a first stacked gate device having a first number of first field effect transistors connected in series, and the second temperature sensitive device includes a second stacked gate device having a second number of second field effect transistors connected in series, and the second number is greater than the first number.

[0081] Another aspect of the present disclosure provides a method for operating an integrated circuit. The method includes the following steps: providing an integrated circuit including a first temperature-sensitive device and a second temperature-sensitive device; generating a bias current using a first voltage across the first temperature-sensitive device and a second voltage across the second temperature-sensitive device, wherein the bias current flows from an output terminal of the integrated circuit through a resistor and the first temperature-sensitive device; and generating a reference voltage at the output terminal of the integrated circuit based on the second voltage and the bias current. The first voltage and the second voltage decrease monotonically with increasing absolute temperature of the integrated circuit, and the bias current increases monotonically with increasing absolute temperature.

[0082] In some embodiments, an amount by which the first voltage decreases with increasing absolute temperature is less than an amount by which the second voltage decreases with increasing absolute temperature.

[0083] The methods and features of the present disclosure have been fully described in the examples and descriptions provided. It should be understood that any modifications or changes that do not depart from the spirit of the present disclosure are intended to be included within the scope of protection of the present disclosure.

[0084] In addition, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, devices, methods and steps described in this specification. As one of ordinary skill in the art will understand, existing or later developed processes, machines, manufactures, material compositions, devices, methods or steps that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described in accordance with the present invention may be used in accordance with the present invention.

[0085] Therefore, the appended claims are intended to include within their scope processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.

Claims

1. An integrated circuit comprising: a first temperature-sensitive device configured to generate a reference voltage at an output terminal of the integrated circuit; as well as a second temperature-sensitive device coupled to an output terminal of the integrated circuit through a resistor and configured to cooperate with the first temperature-sensitive device to generate a first bias current, the first bias current flowing from the output terminal of the integrated circuit through the resistor and the first temperature-sensitive device to a ground node; The first bias current increases monotonically with the increase of the absolute temperature of the integrated circuit.

2. The integrated circuit according to claim 1, wherein: The resistor is coupled between an output terminal of the integrated circuit and a first node, and the integrated circuit further includes a current source coupled to the second temperature-sensitive device and configured to generate a second bias current flowing through the second temperature-sensitive device, the second bias current being substantially equal to the first bias current.

3. The integrated circuit according to claim 2, wherein: the first temperature sensitive device comprising a first stacked gate device having a gate terminal connected to an output terminal of the integrated circuit, a first terminal connected to the first node, and a second terminal connected to the ground node; and The first stacked gate device includes one or more first finger structures arranged in parallel, each first finger structure including a first number of field effect transistors connected in series.

4. The integrated circuit according to claim 3, wherein: the second temperature sensitive device comprises a second stacked gate device having a gate terminal connected to the first node of the integrated circuit, a first terminal connected to a second node, and a second terminal connected to the ground node; and The second stacked gate device includes one or more second finger structures arranged in parallel, each second finger structure including a second number of field effect transistors connected in series.

5. The integrated circuit according to claim 4, wherein: The first number is greater than the second number.

6. The integrated circuit according to claim 5, wherein: Field effect transistors within the first stacked gate device and the second stacked gate device have substantially equal threshold voltages.

7. The integrated circuit of claim 6, further comprising: Fine-tuning circuit, including: a plurality of trim stacked gate devices arranged in parallel with the second stacked gate device; and a plurality of buffer circuits, each buffer circuit configured to be powered by the voltage at the first node and the ground voltage, Each trim stack gate device is controlled by a corresponding bit of the trim code signal through a corresponding buffer circuit.

8. The integrated circuit according to claim 7, wherein: Each of the trim stacked gate devices includes a different number of power-of-two finger structures, and each finger structure within the trim stacked gate device includes a second number of field effect transistors connected in series.

9. An integrated circuit comprising: a first temperature sensitive device; as well as a second temperature-sensitive device coupled to the first temperature-sensitive device through a resistor and configured to function as a first voltage source that varies with the absolute temperature of the integrated circuit, and to cooperate with the first temperature-sensitive device to function as a second voltage source that varies with the absolute temperature of the integrated circuit, The second temperature sensitive device is further configured to compensate the first voltage source with the second voltage source to generate a reference voltage at the output terminal of the integrated circuit.

10. A method of operating an integrated circuit, comprising: providing an integrated circuit including a first temperature sensitive device and a second temperature sensitive device; generating a bias current using a first voltage across the first temperature-sensitive device and a second voltage across the second temperature-sensitive device, wherein the bias current flows from an output terminal of the integrated circuit through a resistor and the first temperature-sensitive device; and generating a reference voltage at an output terminal of the integrated circuit according to the second voltage and the bias current, The first voltage and the second voltage decrease monotonically as the absolute temperature of the integrated circuit increases, and the bias current increases monotonically as the absolute temperature increases.

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