Heterojunction battery and preparation method thereof
The heterojunction battery preparation method using gradient design and hydrogen plasma treatment solves the problems of passivation effect and thin film stability, improves battery efficiency and reduces power attenuation.
Patent Information
- Application Number
- CN202410236473.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-01
- Publication Date
- 2025-09-09
AI Technical Summary
Existing heterojunction cells have deficiencies in passivation effect and film stability, especially the problems of amorphous silicon epitaxial crystallization and photodegradation caused by excessively high hydrogen dilution ratios, and poor film thickness uniformity caused by excessively high deposition rates.
A gradient-designed intrinsic amorphous silicon layer deposition method is adopted. By depositing multiple layers of intrinsic amorphous silicon films on the surface of a silicon wafer from the inside to the outside, and combining it with hydrogen plasma treatment, the porosity and density of the films are regulated to prepare a gradient low-density structured intrinsic amorphous silicon layer and a high-density intrinsic hydrogenated amorphous silicon layer.
It achieves excellent passivation effect, significantly improves battery efficiency, stabilizes performance, and reduces power attenuation.
Smart Images
Figure CN120614902A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a heterojunction cell and a preparation method thereof. Background Art
[0002] Heterojunction cell (HJT) is a hybrid solar cell made of crystalline silicon wafers and amorphous silicon thin films. It has many advantages such as simple preparation process, low process temperature, high open circuit voltage, high photoelectric conversion efficiency, and low temperature coefficient. It is one of the most widely used high-efficiency crystalline silicon solar technologies.
[0003] Heterojunction cells have high conversion efficiency due to their excellent surface passivation. The intrinsic amorphous silicon layer serves as a passivation layer, and the quality of its passivation directly affects the efficiency of the cell. As the hydrogen dilution ratio increases, the defect state density of the ia-Si:H (intrinsic hydrogenated amorphous silicon) film decreases, and the film becomes denser, effectively improving the passivation effect on the crystalline silicon surface. However, excessive hydrogen dilution can cause epitaxial growth of the amorphous silicon, reducing the passivation effect. Furthermore, hydrogenated amorphous silicon films have a fatal drawback: they are susceptible to photodegradation, where light exposure causes the formation of new dangling bond defect states in the amorphous silicon film.
[0004] To address these issues, existing technologies often employ high deposition rates on both the front and back sides to prevent epitaxial growth, or employ multiple layers of intrinsic amorphous silicon with a gradient of increasing hydrogen dilution ratios to achieve efficient passivation and stable films. However, these methods still fail to achieve excellent interfacial passivation performance, and excessively high deposition rates can also lead to significant variations in film thickness uniformity at different locations.
[0005] Therefore, in order to solve the above technical problems, it is necessary to provide a heterojunction battery and a preparation method thereof. Summary of the Invention
[0006] The object of the present invention is to provide a heterojunction battery and a preparation method thereof, so as to achieve excellent passivation effect and stable performance.
[0007] In order to achieve the above-mentioned purpose, the technical solution provided by one embodiment of the present invention is as follows:
[0008] A method for preparing a heterojunction battery, comprising the following steps:
[0009] providing a silicon wafer;
[0010] Depositing a first intrinsic amorphous silicon layer, a first hydrogenated amorphous silicon layer and a first doped layer in sequence on the backlight surface of the silicon wafer;
[0011] Depositing a second intrinsic amorphous silicon layer, a second hydrogenated amorphous silicon layer and a second doped layer in sequence on the light-receiving surface of the silicon wafer;
[0012] Wherein, the deposition of the first intrinsic amorphous silicon layer and / or the second intrinsic amorphous silicon layer comprises:
[0013] Silane is introduced into the deposition equipment to deposit at least two layers of intrinsic amorphous silicon thin films on the backlight side and / or light-receiving side of the silicon wafer from the inside to the outside, and the deposition power of the inner layer of the two adjacent intrinsic amorphous silicon thin films is smaller than the deposition power of the outer layer during the deposition process.
[0014] In one embodiment, three layers of intrinsic amorphous silicon thin films are deposited on the backlight surface and / or the light-receiving surface of the silicon wafer from the inside to the outside, the deposition power of the innermost layer of intrinsic amorphous silicon thin film is less than the deposition power of the middle layer of intrinsic amorphous silicon thin film, and the deposition power of the middle layer of intrinsic amorphous silicon thin film is less than the deposition power of the outermost layer of intrinsic amorphous silicon thin film.
[0015] In one embodiment, a first intrinsic amorphous silicon thin film, a second intrinsic amorphous silicon thin film, and a third intrinsic amorphous silicon thin film are deposited on the backlight surface of the silicon wafer from the inside to the outside, wherein the deposition power during the deposition of the first intrinsic amorphous silicon thin film is 100W to 200W, the deposition power during the deposition of the second intrinsic amorphous silicon thin film is 200W to 300W, and the deposition power during the deposition of the third intrinsic amorphous silicon thin film is 300W to 500W.
[0016] In one embodiment, during the deposition of the first intrinsic amorphous silicon layer, the flow rate of silane is 800 sccm to 1000 sccm, the chamber pressure is 0.4 Torr to 0.6 Torr, the deposition temperature is 200° C. to 220° C., and the deposition thickness is 2 nm to 3 nm.
[0017] In one embodiment, CO 2 is also introduced during the deposition of the first intrinsic amorphous silicon layer, and the flow rate of CO 2 is 20 sccm to 50 sccm.
[0018] In one embodiment, a fourth intrinsic amorphous silicon thin film, a fifth intrinsic amorphous silicon thin film and a sixth intrinsic amorphous silicon thin film are deposited on the light-receiving surface of the silicon wafer from the inside to the outside, wherein the deposition power during the deposition of the fourth intrinsic amorphous silicon thin film is 100W to 200W, the deposition power during the deposition of the fifth intrinsic amorphous silicon thin film is 250W to 350W, and the deposition power during the deposition of the sixth intrinsic amorphous silicon thin film is 300W to 400W.
[0019] In one embodiment, during the deposition of the second intrinsic amorphous silicon layer, the flow rate of silane is 800 sccm to 1000 sccm, the chamber pressure is 0.4 Torr to 0.6 Torr, the deposition temperature is 190° C. to 210° C., and the deposition thickness is 3 nm to 4 nm.
[0020] In one embodiment, CO 2 is further introduced during the deposition of the second intrinsic amorphous silicon layer, and the flow rate of CO 2 is 50 sccm to 100 sccm.
[0021] In one embodiment, the preparation method further comprises:
[0022] The first intrinsic amorphous silicon layer is subjected to hydrogen plasma treatment.
[0023] In one embodiment, hydrogen plasma treatment is performed in a PECVD device, with an H2 flow rate of 1000 sccm to 5000 sccm, a RF power of 800 W to 1200 W, a treatment time of 5 s to 10 s, a chamber pressure of 0.4 Torr to 0.6 Torr, and a treatment temperature of 200° C. to 220° C.
[0024] In one embodiment, the preparation method further comprises:
[0025] The second intrinsic amorphous silicon layer is subjected to hydrogen plasma treatment.
[0026] In one embodiment, hydrogen plasma treatment is performed in a PECVD device, with an H2 flow rate of 3000 sccm to 5000 sccm, a RF power of 1000 W to 1500 W, a treatment time of 5 s to 15 s, a chamber pressure of 0.4 Torr to 0.6 Torr, and a treatment temperature of 190° C. to 210° C.
[0027] In one embodiment, the flow ratio of silane and hydrogen introduced during the deposition of the first hydrogenated amorphous silicon layer and / or the second hydrogenated amorphous silicon layer is 1:(5-10).
[0028] In one embodiment, during the deposition of the first intrinsic hydrogenated amorphous silicon layer, the flow rate of silane is 500 sccm to 800 sccm, and the flow rate of hydrogen is 4000 sccm to 8000 sccm; and / or,
[0029] During the deposition of the first intrinsic hydrogenated amorphous silicon layer, the deposition power is 100W to 200W, the chamber pressure is 0.4 Torr to 0.6 Torr, the deposition temperature is 200° C. to 220° C., and the deposition thickness is 3 nm to 4 nm; and / or,
[0030] During the deposition of the second intrinsic hydrogenated amorphous silicon layer, the flow rate of silane is 800 sccm to 1000 sccm, and the flow rate of hydrogen is 5000 sccm to 8000 sccm; and / or,
[0031] During the deposition process of the second intrinsic hydrogenated amorphous silicon layer, the deposition power is 200W-300W, the chamber pressure is 0.4Torr-0.6Torr, the deposition temperature is 190°C-210°C, and the deposition thickness is 2.5nm-3.5nm.
[0032] In one embodiment, the first doped layer is a boron-doped microcrystalline silicon layer, and the deposition method includes: introducing hydrogen, silane, CO2, and borane into a deposition apparatus, with a flow ratio of hydrogen to silane of (300-350):1, and depositing a boron-doped microcrystalline silicon layer with a thickness of 25 nm to 30 nm on the first intrinsic hydrogenated amorphous silicon layer; and / or,
[0033] The second doped layer is a phosphorus-doped microcrystalline silicon layer, and the deposition method includes: introducing hydrogen, silane, CO2 and phosphine into the deposition equipment, with the flow ratio of hydrogen to silane being (200~300):1, and depositing a phosphorus-doped microcrystalline silicon layer with a thickness of 25nm~30nm on the second intrinsic hydrogenated amorphous silicon layer.
[0034] The technical solution provided by one embodiment of the present invention is as follows:
[0035] A heterojunction battery is prepared by the above-mentioned preparation method.
[0036] Compared with the prior art, the present invention has the following beneficial effects:
[0037] The intrinsic amorphous silicon layer with a gradient low-density structure and the intrinsic hydrogenated amorphous silicon layer with a high density in the present invention can achieve an excellent passivation effect, significantly improve the battery efficiency, and at the same time have stable performance and greatly reduce power attenuation. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments described in the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.
[0039] Figure 1 Schematic diagram of the structure of the heterojunction battery in the present invention;
[0040] Figure 2 Schematic diagram of the structure of the heterojunction battery in Example 1 of the present invention;
[0041] Figure 3 Schematic diagram of the structure of the heterojunction battery in the comparative example of the present invention. DETAILED DESCRIPTION
[0042] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.
[0043] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.
[0044] Ginseng Figure 1 The figure shows a schematic structural diagram of a heterojunction battery in the present invention, which includes:
[0045] The silicon wafer 10 includes a light-receiving surface (i.e., the front surface or the upper surface) and a light-receiving surface (i.e., the back surface or the lower surface) that are oppositely disposed;
[0046] A first intrinsic amorphous silicon layer 11, a first hydrogenated amorphous silicon layer 21 and a first doped layer 31 are sequentially stacked on the backlight surface of the silicon wafer;
[0047] The second intrinsic amorphous silicon layer 12 , the second hydrogenated amorphous silicon layer 22 and the second doped layer 32 are sequentially stacked on the light-receiving surface of the silicon wafer.
[0048] Among them, the first intrinsic amorphous silicon layer 11 is sequentially deposited with at least two layers of intrinsic amorphous silicon films from the inside to the outside, and the second intrinsic amorphous silicon layer 12 is sequentially deposited with at least two layers of intrinsic amorphous silicon films from the inside to the outside, and the deposition power of the inner layer of the two adjacent intrinsic amorphous silicon films is less than the deposition power of the outer layer during the deposition process.
[0049] The present invention also discloses a method for preparing a heterojunction battery, comprising the following steps:
[0050] Providing a silicon wafer 10;
[0051] On the backlight side of the silicon wafer, a first intrinsic amorphous silicon layer 11, a first hydrogenated amorphous silicon layer 21 and a first doped layer 31 are sequentially deposited;
[0052] On the light-receiving surface of the silicon wafer, a second intrinsic amorphous silicon layer 12, a second hydrogenated amorphous silicon layer 22 and a second doped layer 32 are sequentially deposited;
[0053] Wherein, the deposition of the first intrinsic amorphous silicon layer and / or the second intrinsic amorphous silicon layer comprises:
[0054] Silane is introduced into the deposition equipment to deposit at least two layers of intrinsic amorphous silicon thin films on the backlight side and / or light-receiving side of the silicon wafer from the inside to the outside, and the deposition power of the inner layer of the two adjacent intrinsic amorphous silicon thin films is smaller than the deposition power of the outer layer during the deposition process.
[0055] For example, Figure 1 In the heterojunction cell shown, two layers of intrinsic amorphous silicon films are deposited sequentially from the inside to the outside on the backlight side and the light-receiving side of the silicon wafer, namely, an inner intrinsic amorphous silicon film and an outer intrinsic amorphous silicon film. The deposition power during the deposition of the two layers of intrinsic amorphous silicon films adopts a gradient design, and the deposition power of the inner intrinsic amorphous silicon film is less than the deposition power of the outer intrinsic amorphous silicon film.
[0056] Of course, three layers of intrinsic amorphous silicon thin films can also be deposited in sequence from the inside to the outside on both the backlight side and the light-receiving side of the silicon wafer. The deposition power during the deposition of the three layers of intrinsic amorphous silicon thin films adopts a gradient design, and the deposition power of the innermost layer of intrinsic amorphous silicon thin film is less than the deposition power of the middle layer of intrinsic amorphous silicon thin film, and the deposition power of the middle layer of intrinsic amorphous silicon thin film is less than the deposition power of the outermost layer of intrinsic amorphous silicon thin film.
[0057] In the present invention, the porosity and density of each intrinsic amorphous silicon film in the intrinsic amorphous silicon layer can be regulated by the gradient design of deposition power, and finally an intrinsic amorphous silicon layer with a gradient low-density structure is obtained, which can well promote the diffusion of hydrogen to the interface between the silicon wafer and the amorphous silicon film.
[0058] The present invention is further described below with reference to specific examples.
[0059] Example 1:
[0060] Ginseng Figure 2 The figure shows a schematic structural diagram of a heterojunction battery in a specific embodiment of the present invention, which includes:
[0061] The silicon wafer 10 includes a light-receiving surface (i.e., the front surface or the upper surface) and a light-receiving surface (i.e., the back surface or the lower surface) that are oppositely disposed;
[0062] A first intrinsic amorphous silicon layer 11, a first hydrogenated amorphous silicon layer 21 and a first doped layer 31 are sequentially stacked on the backlight surface of the silicon wafer;
[0063] The second intrinsic amorphous silicon layer 12 , the second hydrogenated amorphous silicon layer 22 and the second doped layer 32 are sequentially stacked on the light-receiving surface of the silicon wafer.
[0064] Among them, the first intrinsic amorphous silicon layer 11 includes a first intrinsic amorphous silicon film 111, a second intrinsic amorphous silicon film 112 and a third intrinsic amorphous silicon film 113 deposited sequentially from the inside to the outside, and the second intrinsic amorphous silicon layer 21 includes a fourth intrinsic amorphous silicon film 121, a fifth intrinsic amorphous silicon film 122 and a sixth intrinsic amorphous silicon film 123 deposited sequentially from the inside to the outside.
[0065] Preferably, the silicon wafer 10 in this embodiment is an N-type silicon wafer; the first doped layer 31 is an N-type doped amorphous silicon layer or a microcrystalline silicon layer; and the second doped layer 32 is a P-type doped amorphous silicon layer or a microcrystalline silicon layer.
[0066] The deposition order of each layer on the silicon wafer in this embodiment is as follows: first, the first intrinsic amorphous silicon layer 11 and the first hydrogenated amorphous silicon layer 21 are deposited on the backlight surface, then the second intrinsic amorphous silicon layer 12 and the second hydrogenated amorphous silicon layer 22 are deposited on the light-receiving surface, and finally the second doped layer 32 on the light-receiving surface and the first doped layer 31 on the backlight surface are deposited.
[0067] The following is a detailed description of the deposition process of each layer:
[0068] 1. Deposition of the first intrinsic amorphous silicon layer 11
[0069] Silane is introduced into the PECVD equipment, the flow rate of silane is 800 sccm to 1000 sccm, the chamber pressure is 0.4 Torr to 0.6 Torr, the deposition temperature is 200° C. to 220° C., and the deposition thickness is 2 nm to 3 nm.
[0070] The deposition power during the deposition of the first intrinsic amorphous silicon film 111 is 100 W to 200 W, the deposition power during the deposition of the second intrinsic amorphous silicon film 112 is 200 W to 300 W, and the deposition power during the deposition of the third intrinsic amorphous silicon film 113 is 300 W to 500 W. For example, in this embodiment, the deposition powers are 150 W, 250 W, and 400 W, respectively. By designing the deposition power gradient, a first intrinsic amorphous silicon layer 11 with a gradient low-density structure can be prepared.
[0071] Furthermore, CO 2 is introduced during the deposition of the first intrinsic amorphous silicon layer 11 , and the flow rate of CO 2 is 20 sccm to 50 sccm, preferably 35 sccm.
[0072] By introducing CO2 to dope the first intrinsic amorphous silicon layer 11 with oxygen, the band gap of the amorphous silicon film can be widened and the light transmittance can be improved. In addition, the intrinsic amorphous silicon film becomes more stable and the attenuation is slowed down.
[0073] Optionally, in this embodiment, after the first intrinsic amorphous silicon layer 11 is deposited, hydrogen plasma treatment (HPT) is performed on the first intrinsic amorphous silicon layer 11 .
[0074] Exemplarily, hydrogen plasma treatment is carried out in a PECVD device, with an H2 flow rate of 1000 sccm to 5000 sccm, a RF power of 800 W to 1200 W, a treatment time of 5 s to 10 s, a chamber pressure of 0.4 Torr to 0.6 Torr, and a treatment temperature of 200° C. to 220° C.
[0075] Hydrogen plasma treatment can make the amorphous phase of the amorphous silicon film more disordered, improve the diffusion of hydrogen from the silicon wafer to the interface, and the transformation of the film from amorphous to microcrystalline, thereby increasing the crystallization rate of the amorphous silicon film.
[0076] 2. Deposition of the first hydrogenated amorphous silicon layer 21
[0077] The first hydrogenated amorphous silicon layer 21 is deposited in a PECVD device using a silane to hydrogen flow ratio of 1:(5-10). The first hydrogenated amorphous silicon layer 21 is an amorphous silicon film deposited under conditions of a high hydrogen dilution ratio. This film has a high density, allowing hydrogen to concentrate more on the silicon wafer surface.
[0078] Illustratively, during the deposition of the first intrinsic hydrogenated amorphous silicon layer, the flow rate of silane is 500 sccm to 800 sccm, the flow rate of hydrogen is 4000 sccm to 8000 sccm, the deposition power is 100 W to 200 W, the chamber pressure is 0.4 Torr to 0.6 Torr, the deposition temperature is 200°C to 220°C, and the deposition thickness is 3 nm to 4 nm.
[0079] 3. Deposition of the second intrinsic amorphous silicon layer 12
[0080] Silane is introduced into the PECVD equipment, the flow rate of silane is 800 sccm to 1000 sccm, the chamber pressure is 0.4 Torr to 0.6 Torr, the deposition temperature is 190° C. to 210° C., and the deposition thickness is 3 nm to 4 nm.
[0081] The deposition power during the deposition of the fourth intrinsic amorphous silicon film 121 is 100 W to 200 W, the deposition power during the deposition of the fifth intrinsic amorphous silicon film 122 is 250 W to 350 W, and the deposition power during the deposition of the sixth intrinsic amorphous silicon film 123 is 300 W to 400 W. For example, in this embodiment, the deposition powers are 150 W, 300 W, and 350 W, respectively. By designing the deposition power gradient, a second intrinsic amorphous silicon layer 12 with a gradient low-density structure can be prepared.
[0082] Furthermore, CO 2 is introduced during the deposition of the second intrinsic amorphous silicon layer 12 , and the flow rate of CO 2 is 50 sccm to 100 sccm, preferably 75 sccm.
[0083] The second intrinsic amorphous silicon layer 12 is doped with oxygen by introducing CO2, which can widen the band gap of the amorphous silicon film and improve the light transmittance. In addition, the intrinsic amorphous silicon film becomes more stable and the attenuation is slowed down.
[0084] Optionally, in this embodiment, after the second intrinsic amorphous silicon layer 12 is deposited, hydrogen plasma treatment (HPT) is performed on the second intrinsic amorphous silicon layer 12 .
[0085] Exemplarily, hydrogen plasma treatment is carried out in a PECVD device, with an H2 flow rate of 3000 sccm to 5000 sccm, a RF power of 1000 W to 1500 W, a treatment time of 5 s to 15 s, a chamber pressure of 0.4 Torr to 0.6 Torr, and a treatment temperature of 190° C. to 210° C.
[0086] Hydrogen plasma treatment can make the amorphous phase of the amorphous silicon film more disordered, improve the diffusion of hydrogen from the silicon wafer to the interface, and the transformation of the film from amorphous to microcrystalline, thereby increasing the crystallization rate of the amorphous silicon film.
[0087] 4. Deposition of the Second Hydrogenated Amorphous Silicon Layer 22
[0088] The second hydrogenated amorphous silicon layer 22 is deposited in a PECVD device using a silane to hydrogen flow ratio of 1:(5-10). This second hydrogenated amorphous silicon layer 22 is an amorphous silicon film deposited under conditions of a high hydrogen dilution ratio. This film has a high density, allowing hydrogen to concentrate more on the silicon wafer surface.
[0089] Illustratively, during the deposition of the second hydrogenated amorphous silicon layer, the flow rate of silane is 800 sccm to 1000 sccm, the flow rate of hydrogen is 5000 sccm to 8000 sccm, the deposition power is 200 W to 300 W, the chamber pressure is 0.4 Torr to 0.6 Torr, the deposition temperature is 190°C to 210°C, and the deposition thickness is 2.5 nm to 3.5 nm.
[0090] 5. Deposition of the second doping layer 32
[0091] The second doped layer is a phosphorus-doped microcrystalline silicon layer, and the deposition method includes: introducing hydrogen, silane, CO2 and phosphine into the PECVD equipment, with the flow ratio of hydrogen to silane being (200~300):1, and depositing a phosphorus-doped microcrystalline silicon layer with a thickness of 25nm~30nm on the second intrinsic hydrogenated amorphous silicon layer.
[0092] Preferably, the flow rate of hydrogen is 10,000 to 15,000 sccm, the flow rate of silane is 80 sccm to 100 sccm, the flow rate of CO2 is 50 sccm to 100 sccm, and the flow rate of phosphine is 300 sccm to 500 sccm; the chamber pressure is 4 Torr to 5 Torr, and the deposition power is 3,000 W to 5,000 W.
[0093] 6. Deposition of the first doping layer 31
[0094] The first doped layer is a boron-doped microcrystalline silicon layer, and the deposition method includes: introducing hydrogen, silane, CO2 and borane into the PECVD equipment, with the flow ratio of hydrogen to silane being (300~350):1, and depositing a boron-doped microcrystalline silicon layer with a thickness of 25nm~30nm on the first intrinsic hydrogenated amorphous silicon layer.
[0095] Preferably, the flow rate of hydrogen is 20,000 to 25,000 sccm, the flow rate of silane is 50 sccm to 80 sccm, the flow rate of CO2 is 10 sccm to 30 sccm, and the flow rate of borane is 20 sccm to 60 sccm; the chamber pressure is 4 Torr to 5 Torr, and the deposition power is 3,000 W to 7,000 W.
[0096] Example 2:
[0097] The structure of the light-receiving surface of the heterojunction cell in this embodiment is exactly the same as that in embodiment 1, while the backlight surface adopts the structure of intrinsic amorphous silicon layer + P-type doping layer in conventional heterojunction cells.
[0098] Example 3:
[0099] The structure on the backlight surface of the heterojunction cell in this embodiment is exactly the same as that in embodiment 1, while the light-receiving surface adopts the structure of intrinsic amorphous silicon layer + N-type doping layer in conventional heterojunction cells.
[0100] Comparative Example:
[0101] Ginseng Figure 3 The figure shows a schematic structural diagram of a heterojunction battery in a pair of ratios of the present invention, which includes:
[0102] The silicon wafer 10' comprises a light-receiving surface and a backlight surface that are arranged opposite to each other;
[0103] A first hydrogenated amorphous silicon layer 21' and a first doped layer 31' are sequentially stacked on the backlight surface of the silicon wafer;
[0104] The second hydrogenated amorphous silicon layer 22 ′ and the second doped layer 32 ′ are sequentially stacked on the light-receiving surface of the silicon wafer.
[0105] The first hydrogenated amorphous silicon layer 21' includes a first hydrogenated amorphous silicon film 211' and a second hydrogenated amorphous silicon film 212' deposited sequentially from the inside out, and the second hydrogenated amorphous silicon layer 22' includes a third hydrogenated amorphous silicon film 221' and a fourth hydrogenated amorphous silicon film 222' deposited sequentially from the inside out.
[0106] In this comparative example, the hydrogen dilution ratio of the first hydrogenated amorphous silicon film 211' and the second hydrogenated amorphous silicon film 212' is increased, and the flow ratios of silane and hydrogen are 1:2 and 1:10 respectively. The other process conditions are the same as those for the deposition of the first hydrogenated amorphous silicon layer 21 in the above-mentioned embodiment 1.
[0107] Similarly, the hydrogen dilution ratio of the third hydrogenated amorphous silicon film 221 ′ and the fourth hydrogenated amorphous silicon film 222 ′ is increased gradually, and the flow ratios of silane and hydrogen are 1:2 and 1:10 respectively. The other process conditions are the same as those for the deposition of the second hydrogenated amorphous silicon layer 22 in the above-mentioned embodiment 1.
[0108] The deposition of the first doping layer 31 ′ and the second doping layer 32 ′ in this comparative example is exactly the same as that of the first doping layer 31 and the second doping layer 32 in the above embodiment 1, and will not be further described here.
[0109] The following table shows the effects of different deposition powers on the deposition of intrinsic amorphous silicon thin films on the backlight surface in Example 1 or 3:
[0110] film Deposition power Microstructure factor (R*) The first intrinsic amorphous silicon film 111 100W~200W 0.58～0.62 The second intrinsic amorphous silicon film 112 200W~300W 0.5～0.55 The third intrinsic amorphous silicon film 113 300W~500W 0.4～0.5
[0111] The following table shows the effects of different hydrogen dilution ratios on the deposition of the first intrinsic hydrogenated amorphous silicon layer on the backlight surface in Example 1 or 3:
[0112] Hydrogen dilution ratio Microstructure factor (R*) <![CDATA[SiH4:H2=1:(2~5)]]> 0.3～0.4 <![CDATA[SiH4:H2=1:(5~10)]]> 0.15～0.2
[0113] Among them, the larger the R* value, the greater the porosity of the film and the lower the density, and the smaller the R* value, the higher the density of the film.
[0114] In this way, by designing the gradient of deposition power, an intrinsic amorphous silicon layer with a gradient low-density structure can be prepared, and by controlling the hydrogen dilution ratio, a high-density intrinsic hydrogenated amorphous silicon layer can be prepared.
[0115] The electrical performance data of Example 3 and the comparative example are shown in the following table:
[0116]
[0117] The electrical performance data of Example 2 and Example 3 are similar and will not be described again here.
[0118] It can be seen that the intrinsic amorphous silicon layer with a gradient low-density structure and the high-density intrinsic hydrogenated amorphous silicon layer in the present invention can achieve excellent passivation effect, significantly improve battery efficiency, and at the same time have stable performance and greatly reduce power attenuation.
[0119] It should be understood that the intrinsic amorphous silicon layer in the above embodiment is illustrated by taking three layers of intrinsic amorphous silicon thin films as an example. In other embodiments, the number of layers of the intrinsic amorphous silicon thin film can also be set to two inner and outer layers, or to four layers or more. Any technical solution for preparing an intrinsic amorphous silicon layer with a gradient low-density structure by regulating the deposition power falls within the scope of protection of the present invention.
[0120] The deposition equipment in the above embodiments is illustrated by taking PECVD (plasma enhanced chemical vapor deposition) equipment as an example. In other embodiments, the deposition of each layer can adopt other types of deposition equipment (such as thermal evaporation deposition equipment, sputtering deposition equipment, etc.), which will not be described one by one here.
[0121] The advantage of using PECVD equipment to deposit the film layer is that the PECVD equipment can perform hydrogen plasma treatment (HPT), so the deposition of the film layer and the HPT treatment of the intrinsic amorphous silicon layer can be performed in the same equipment, simplifying the battery preparation process.
[0122] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.
[0123] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.
Claims
1. A method for preparing a heterojunction battery, characterized in that: The preparation method comprises the following steps: providing a silicon wafer; Depositing a first intrinsic amorphous silicon layer, a first hydrogenated amorphous silicon layer and a first doped layer in sequence on the backlight surface of the silicon wafer; Depositing a second intrinsic amorphous silicon layer, a second hydrogenated amorphous silicon layer and a second doped layer in sequence on the light-receiving surface of the silicon wafer; The deposition of the first intrinsic amorphous silicon layer and / or the second intrinsic amorphous silicon layer comprises: Silane is introduced into the deposition equipment to deposit at least two layers of intrinsic amorphous silicon thin films on the backlight side and / or light-receiving side of the silicon wafer from the inside to the outside, and the deposition power of the inner layer of the two adjacent intrinsic amorphous silicon thin films is smaller than the deposition power of the outer layer during the deposition process.
2. The method for preparing a heterojunction battery according to claim 1, wherein: Three layers of intrinsic amorphous silicon thin films are deposited on the backlight surface and / or the light-receiving surface of the silicon wafer from the inside to the outside, the deposition power of the innermost layer of intrinsic amorphous silicon thin film is less than the deposition power of the middle layer of intrinsic amorphous silicon thin film, and the deposition power of the middle layer of intrinsic amorphous silicon thin film is less than the deposition power of the outermost layer of intrinsic amorphous silicon thin film.
3. The method for preparing a heterojunction battery according to claim 1, wherein: A first intrinsic amorphous silicon film, a second intrinsic amorphous silicon film and a third intrinsic amorphous silicon film are deposited on the backlight surface of the silicon wafer from the inside to the outside, wherein the deposition power during the deposition of the first intrinsic amorphous silicon film is 100W to 200W, the deposition power during the deposition of the second intrinsic amorphous silicon film is 200W to 300W, and the deposition power during the deposition of the third intrinsic amorphous silicon film is 300W to 500W.
4. The method for preparing a heterojunction battery according to claim 3, wherein: During the deposition of the first intrinsic amorphous silicon layer, the flow rate of silane is 800 sccm to 1000 sccm, the chamber pressure is 0.4 Torr to 0.6 Torr, the deposition temperature is 200° C. to 220° C., and the deposition thickness is 2 nm to 3 nm.
5. The method for preparing a heterojunction battery according to claim 4, wherein: During the deposition of the first intrinsic amorphous silicon layer, CO2 is also introduced, and the flow rate of CO2 is 20 sccm to 50 sccm.
6. The method for preparing a heterojunction battery according to claim 1, wherein: A fourth intrinsic amorphous silicon thin film, a fifth intrinsic amorphous silicon thin film and a sixth intrinsic amorphous silicon thin film are deposited on the light-receiving surface of the silicon wafer from the inside to the outside, wherein the deposition power during the deposition of the fourth intrinsic amorphous silicon thin film is 100W to 200W, the deposition power during the deposition of the fifth intrinsic amorphous silicon thin film is 250W to 350W, and the deposition power during the deposition of the sixth intrinsic amorphous silicon thin film is 300W to 400W.
7. The method for preparing a heterojunction battery according to claim 6, wherein: During the deposition of the second intrinsic amorphous silicon layer, the flow rate of silane is 800 sccm to 1000 sccm, the chamber pressure is 0.4 Torr to 0.6 Torr, the deposition temperature is 190° C. to 210° C., and the deposition thickness is 3 nm to 4 nm.
8. The method for preparing a heterojunction battery according to claim 7, wherein: During the deposition of the second intrinsic amorphous silicon layer, CO2 is also introduced, and the flow rate of CO2 is 50 sccm to 100 sccm.
9. The method for preparing a heterojunction battery according to claim 3, wherein: The preparation method further comprises: The first intrinsic amorphous silicon layer is subjected to hydrogen plasma treatment.
10. The method for preparing a heterojunction battery according to claim 9, wherein: The hydrogen plasma treatment is carried out in a PECVD device, with an H2 flow rate of 1000 sccm to 5000 sccm, a radio frequency power of 800 W to 1200 W, a treatment time of 5 s to 10 s, a chamber pressure of 0.4 Torr to 0.6 Torr, and a treatment temperature of 200°C to 220°C.
11. The method for preparing a heterojunction battery according to claim 6, wherein: The preparation method further comprises: The second intrinsic amorphous silicon layer is subjected to hydrogen plasma treatment.
12. The method for preparing a heterojunction battery according to claim 11, wherein: The hydrogen plasma treatment is carried out in a PECVD device with an H2 flow rate of 3000 sccm to 5000 sccm, a radio frequency power of 1000 W to 1500 W, a treatment time of 5 s to 15 s, a chamber pressure of 0.4 Torr to 0.6 Torr, and a treatment temperature of 190°C to 210°C.
13. The method for preparing a heterojunction battery according to claim 1, wherein: The flow ratio of silane and hydrogen introduced during the deposition of the first hydrogenated amorphous silicon layer and / or the second hydrogenated amorphous silicon layer is 1:(5-10).
14. The method for preparing a heterojunction battery according to claim 13, wherein: During the deposition of the first intrinsic hydrogenated amorphous silicon layer, the flow rate of silane is 500 sccm to 800 sccm, and the flow rate of hydrogen is 4000 sccm to 8000 sccm; and / or, During the deposition of the first intrinsic hydrogenated amorphous silicon layer, the deposition power is 100W to 200W, the chamber pressure is 0.4 Torr to 0.6 Torr, the deposition temperature is 200° C. to 220° C., and the deposition thickness is 3 nm to 4 nm; and / or, During the deposition of the second intrinsic hydrogenated amorphous silicon layer, the flow rate of silane is 800 sccm to 1000 sccm, and the flow rate of hydrogen is 5000 sccm to 8000 sccm; and / or, During the deposition process of the second intrinsic hydrogenated amorphous silicon layer, the deposition power is 200W-300W, the chamber pressure is 0.4Torr-0.6Torr, the deposition temperature is 190°C-210°C, and the deposition thickness is 2.5nm-3.5nm.
15. The method for preparing a heterojunction battery according to claim 1, wherein: The first doped layer is a boron-doped microcrystalline silicon layer, and the deposition method includes: introducing hydrogen, silane, CO2 and borane into a deposition device, with a flow ratio of hydrogen to silane being (300-350):1, and depositing a boron-doped microcrystalline silicon layer with a thickness of 25 nm to 30 nm on the first intrinsic hydrogenated amorphous silicon layer; and / or, The second doped layer is a phosphorus-doped microcrystalline silicon layer, and the deposition method includes: introducing hydrogen, silane, CO2 and phosphine into the deposition equipment, with the flow ratio of hydrogen to silane being (200~300):1, and depositing a phosphorus-doped microcrystalline silicon layer with a thickness of 25nm~30nm on the second intrinsic hydrogenated amorphous silicon layer.
16. A heterojunction battery, characterized in that: The heterojunction battery is prepared by the preparation method according to any one of claims 1 to 15.