Crystalline silicon / perovskite laminated solar cell and preparation method thereof

Abstract

The invention provides a crystalline silicon / perovskite laminated solar cell and a preparation method thereof, the crystalline silicon / perovskite laminated solar cell is applied to the perovskite / crystalline silicon laminated solar cell, the first edge passivation layer and the second edge passivation layer are respectively prepared after the buffer layer and the transparent electrode layer are prepared, the protection effect of the edge cutting surface of the laminated cell can be improved, and the service life of the cell is prolonged. The risk that a thin film in the crystalline silicon / perovskite laminated cell is easily eroded, damaged or permeated by impurities is reduced; the obtained edge protection structure can also improve the coverage uniformity and continuity of the deposited transparent conductive layer and the metal grid line in the edge region, reduce the potential electric leakage risk of the thin film layer, reduce the parallel resistance loss, and improve the fill factor and open-circuit voltage of the device; the two edge passivation layers are arranged for protection, so that the negative influence of the deposition of each transparent electrode and the preparation process step of the metal grid line on the sensitive edge area can be reduced, and the stability and the photoelectric conversion efficiency of the device are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of perovskite tandem solar cells, and in particular to a crystalline silicon / perovskite tandem solar cell and a preparation method thereof. Background Art

[0002] Crystalline silicon solar cells are currently the dominant technology in the photovoltaic market, accounting for over 90% of the global market. However, the photoelectric conversion efficiency of crystalline silicon cells has a theoretical limit (the Shockley-Queisser limit), which is approximately 29%. Currently, the efficiency of commercial crystalline silicon cells is typically around 20%, and the efficiency of leading laboratory cells is only around 26%, which is relatively close to the theoretical limit. To break through this efficiency bottleneck, researchers have begun exploring tandem cell technology. Crystalline silicon-perovskite tandem solar cells have attracted widespread attention in the photovoltaic field in recent years due to the excellent photoelectric properties of their perovskite materials, such as high absorption coefficient, adjustable band gap, and simple manufacturing process.

[0003] In the traditional production of crystalline silicon perovskite tandem solar cells, the edge passivation treatment is often performed on the finished tandem cells. Although this can reduce the carrier recombination rate in the edge area to improve the photoelectric efficiency and stability of the device, the passivation process does not take into account the physical damage to the bottom film and its edge area during the preparation of the transparent electrode and metal grid line, as well as the electrical protection issues, which affects the effect of edge passivation.

[0004] For example, during the preparation of transparent electrodes, the deposition of transparent electrode layers (such as ITO, AZO, etc.) will form a new, continuous conductive layer edge above the edge of the original structure (perovskite cell / buffer layer), which can easily cause serious leakage problems with subsequent metal grid lines or other parts of the cell. In addition, the deposition process of the transparent electrode layer (especially sputtering) can easily cause serious sputtering damage to the bottom film layer and its edges or generate new defects.

[0005] Moreover, in the existing laminated battery production process, laser cutting is often used to cut the finished batteries, which greatly increases the possibility of water and oxygen corrosion and carrier recombination defects on the cut surface. The damage to sensitive areas such as the perovskite film layer and the edge surface of the device caused by the transparent electrode layer and metal grid line preparation process can easily lead to increased carrier recombination defects at the film interface and edge, thereby reducing the overall life and reliability of the device.

[0006] Therefore, an edge passivation process is urgently needed to solve the film interface and edge recombination defects and commercialization problems of existing stacked solar cells. Summary of the Invention

[0007] In order to solve the problem that traditional edge passivation processes are difficult to apply to tandem solar cells, the present invention provides a crystalline silicon / perovskite tandem solar cell and a preparation method, which are applied to perovskite / crystalline silicon tandem solar cells. After the buffer layer and the transparent electrode layer are prepared, the edge passivation process is performed separately. The two layers of passivation work together to effectively reduce the carrier recombination loss at the thin film interface and the edge area of ​​the device, thereby improving the conversion efficiency and stability of the battery component.

[0008] To achieve the above object, the specific solutions provided by the present invention are as follows:

[0009] On the one hand, the present application provides a crystalline silicon / perovskite tandem solar cell, comprising a crystalline silicon bottom cell, a perovskite top cell, a buffer layer and a transparent electrode layer stacked in sequence from bottom to top, wherein a first edge passivation layer and a second edge passivation layer are sequentially arranged on the four sides of the crystalline silicon bottom cell, the perovskite top cell and the buffer layer, and the second edge passivation layer also covers the four sides of the transparent electrode layer. Metal grid lines are also prepared on the top and bottom surfaces of the tandem solar cell.

[0010] Furthermore, the buffer layer of the crystalline silicon / perovskite tandem solar cell can be removed, and the first edge passivation layer covers the four side extension surfaces of the crystalline silicon bottom cell and the perovskite top cell.

[0011] Furthermore, the first edge passivation layer and the second edge passivation layer can be selected from thin films such as aluminum oxide, silicon oxide, aluminum nitride, and tin oxide, and have a thickness of 5-100 nm.

[0012] In one embodiment, the buffer layer may be made of oxide materials such as SnO2, Yb2O3, TiO2, Al2O3, etc., with a thickness of 5 to 30 nm.

[0013] In one embodiment, the transparent electrode layer can be composed of one transparent material including ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), IWO (tungsten-doped indium oxide), etc., with a thickness of 20~140nm.

[0014] In one embodiment, the metal grid lines can be made of materials such as Ag, Cu, Al, metal alloys, multi-layer metal composite grid lines, silver-clad metal layers, silver-clad metal oxide grid lines, etc. The metal grid lines include main grid lines and fine grid lines. The main grid lines have a thickness of 5~40um and a width of 20~1500um. The fine grid lines have a thickness of 5~30um and a width of 10~100um.

[0015] In one embodiment, the perovskite top cell includes a hole transport layer, a perovskite layer, and an electron transport layer disposed on a crystalline silicon bottom cell.

[0016] The hole transport layer is made of poly [bis (4 phenyl) (2,4,6 trimethylphenyl) amine] (PTAA), poly -3 hexylthiophene (P3HT), nickel oxide (NiO x ), molybdenum trioxide (MoO3), cuprous iodide (CuI), and cuprous thiocyanate (CuSCN).

[0017] In this embodiment, the composition of the perovskite layer may be an ABX3 structure, wherein:

[0018] A position is an organic cation, including CH3NH3 + (MA + ), NH2CH=NH2 + (FA + ), CH3CH2NH3 + or Cs + One or more of the following;

[0019] The B position is a metal cation, including Pb 2+ 、Sn 2+ One or more of the following;

[0020] The X position is a halogen anion, including F - 、Cl - Br - , I - One or more of the .

[0021] In this embodiment, the components of the electron transport layer are zinc oxide (ZnO), tin dioxide (SnO2), titanium dioxide (TiO2), [6,6]-phenyl C 61 Methyl butyrate (PC 61 BM), carbon 60 (C 60 ), one or more of 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP).

[0022] In another embodiment, the perovskite top cell further includes a perovskite passivation layer disposed between the perovskite layer and the electron transport layer, wherein the perovskite passivation layer is composed of at least one of two-dimensional perovskite, phenylethylamine iodide (PEAI), polymethyl methacrylate (PMMA), ammonium halide (NH4X), cesium halide (CsX) and lead halide (PbX2), and has a thickness of 5 to 80 nm.

[0023] Furthermore, the crystalline silicon / perovskite stacked solar cell also includes a third edge passivation layer, which is arranged on the side of the first edge passivation layer away from the second edge passivation layer; the third edge passivation layer covers the four edge surfaces of the crystalline silicon bottom cell, the hole transport layer, and the perovskite layer, or the third edge passivation layer covers the four edge surfaces of the crystalline silicon bottom cell, the hole transport layer, the perovskite layer and the perovskite passivation layer; the third edge passivation layer can be selected from thin films such as aluminum oxide, silicon oxide, aluminum nitride, and tin oxide, with a thickness of 5-100nm.

[0024] In one embodiment, the crystalline silicon bottom cell can be selected from one of the crystalline silicon cell structures such as a PERC cell, a topcon cell or an HJT cell.

[0025] Furthermore, the PERC cell includes a passivation film, an aluminum back surface field, a P-type silicon wafer, and an N+ emitter from bottom to top;

[0026] Furthermore, the topcon cell includes, from bottom to top, a p+ emitter passivation film, a p+ emitter, an N-type silicon substrate, an ultra-thin tunneling oxide layer, and a phosphorus-doped polysilicon layer;

[0027] Furthermore, the HJT cell includes, from bottom to top, a first transparent electrode layer, a P-type base doping layer, a base passivation layer, a silicon substrate, a base surface passivation layer, and an N-type base doping layer.

[0028] In one embodiment, a tunneling layer is further provided between the crystalline silicon bottom cell and the perovskite top cell, and is composed of oxide materials such as ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), and IWO (tungsten-doped indium oxide), with a thickness of 1 to 80 nm. The tunneling layer realizes efficient recombination and tunneling transmission of carriers in the series cells while minimizing optical and electrical losses.

[0029] On the other hand, the present application also provides a method for preparing the above-mentioned crystalline silicon / perovskite tandem solar cell, comprising the steps of:

[0030] A stacked cell structure is provided, comprising a crystalline silicon bottom cell and a perovskite top cell thereon, a buffer layer being prepared on the surface of the perovskite top cell on the stacked cell structure, several stacked cell structures being stacked with their surfaces facing in the same direction and subjected to a deposition process, a first edge passivation layer being formed on the four extended side surfaces of the several stacked cell structures, which are removed after deposition and split, a transparent electrode layer being prepared on the surface of the buffer layer, several stacked cells being stacked again with their surfaces facing in the same direction and subjected to a deposition process, a second edge passivation layer being formed on the four extended side surfaces of the several stacked cell structures, which are removed after deposition and split, and metal grid lines being prepared on the top and bottom surfaces of the stacked cell structures.

[0031] In one embodiment, the buffer layer preparation step is removed, and the first edge passivation layer is deposited on the four edge surfaces of the crystalline silicon bottom cell and the perovskite top cell thereon.

[0032] In one embodiment, the first edge passivation layer and the second edge passivation layer can be composed of a thin film selected from aluminum oxide, silicon oxide, aluminum nitride, tin oxide, etc., with a thickness of 5-100 nm; and are prepared by deposition methods such as atomic layer deposition, evaporation, chemical vapor deposition, and magnetron sputtering.

[0033] Optionally, when atomic layer deposition is used for deposition, the deposition temperature is controlled to be 150~250°C; the deposition pressure is 0.5~3 torr; the flow rate of the passivation gas is 5000~20000sccm, the flow rate of the water vapor is 5000~20000sccm, and the flow rate of the nitrogen is 20000~40000sccm, to form a first edge passivation layer / a second edge passivation layer on the four side extension surfaces of the stacked battery structure.

[0034] Optionally, when magnetron sputtering is used for deposition, a passivation material target is set, the chamber pressure is controlled at 0.3~0.6pa, the deposition power is 1000~2500W, working gases such as Ar and O2 are introduced, and the gas flow rate is controlled at 500~1500sccm to form a first edge passivation layer / a second edge passivation layer on the four side extension surfaces of the stacked battery structure.

[0035] In this embodiment, an annealing process is performed after the first and second edge passivation layers are deposited. The stacked battery structure after the first edge passivation layer / second edge passivation layer is deposited is placed in an annealing device for annealing. The temperature is set to 80-200°C and the annealing time is 10min~30min. After the annealing is completed, the subsequent preparation steps are carried out.

[0036] In one embodiment, the buffer layer can be prepared by sputtering, atomic layer deposition, etc., with a thickness of 5 to 30 nm.

[0037] Optionally, the buffer layer is prepared by sputtering, setting a metal / metal oxide target, introducing an Ar / O2 mixed gas with an O2 partial pressure of 0.5~3%, controlling the gas flow rate to 400~1500sccm, controlling the sputtering power to 1000~2500W, and the vacuum degree to 0.3~0.8Pa, to form a buffer layer on the laminated battery structure.

[0038] Optionally, the buffer layer is prepared by atomic layer deposition. When atomic layer deposition is used, the deposition temperature is controlled to be 80~200°C; the deposition pressure is controlled to be 0.1~1.5 torr; the flow rate of metal / metal oxide gas is controlled to be 500~1500sccm, the flow rate of water vapor is controlled to be 500~1500sccm, and the flow rate of nitrogen is controlled to be 1000~3000sccm, to form a buffer layer on the stacked battery structure.

[0039] In one embodiment, the transparent electrode layer can be prepared by at least one process such as magnetron sputtering, atomic layer deposition, etc., and has a thickness of 20-140 nm.

[0040] Optionally, the transparent electrode layer is prepared by a magnetron sputtering process, a metal oxide target is set, an Ar / O2 mixed gas is introduced, the O2 partial pressure is 0.5~5%, the gas flow rate is controlled to be 400~1500sccm, the sputtering power is controlled to be 1000~2500W, the vacuum degree is 0.3~0.8Pa, and a transparent electrode layer is formed on the laminated battery structure.

[0041] In one embodiment, the metal grid lines can be prepared by at least one process such as screen printing, electroplating, inkjet printing, nanoimprinting, etc., and the metal grid lines include main grid lines and fine grid lines. The main grid lines have a thickness of 5~40um and a width of 20~1500um, and the fine grid lines have a thickness of 5~30um and a width of 10~100um.

[0042] Preferably, the metal grid lines are prepared by a screen printing process. Specifically, the laminated battery structure to be printed is placed on a printing base, a screen is placed on it, a scraper is used to scrape the printing paste to cover the screen, the screen is removed, and the metal grid lines are obtained on the laminated battery structure. The metal grid lines are arranged on the surface of the transparent electrode layer and the bottom surface of the crystalline silicon bottom battery.

[0043] In one embodiment, the perovskite top cell includes a hole transport layer, a perovskite layer, and an electron transport layer sequentially prepared on a crystalline silicon bottom cell; optionally, a perovskite passivation layer is further provided between the perovskite layer and the electron transport layer.

[0044] Furthermore, the preparation method further includes a third edge passivation layer, which is prepared after the perovskite layer or the perovskite passivation layer is prepared, and the preparation process adopted is consistent with that of the first and second edge passivation layers.

[0045] The present application provides a crystalline silicon / perovskite tandem solar cell and a preparation method, which are applied to the perovskite / crystalline silicon tandem solar cell. After preparing the buffer layer and the transparent electrode layer, the first and second edge passivation layers are prepared respectively, which can improve the protection effect of the edge cutting surface of the tandem cell and reduce the risk of the thin film in the crystalline silicon / perovskite tandem cell being easily corroded, damaged or penetrated by impurities; the obtained edge protection structure can also improve the coverage uniformity and continuity of the deposited transparent conductive layer and metal grid line in the edge area, reduce the potential leakage risk of the thin film layer, reduce the parallel resistance loss, and improve the fill factor and open circuit voltage of the device; by providing two layers of edge passivation layers for protection, the negative impact of each transparent electrode deposition and metal grid line preparation process steps on the sensitive edge area can be reduced, and the device stability and photoelectric conversion efficiency can be significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Schematic diagram of the structure of the crystalline silicon / perovskite tandem solar cell of the present invention;

[0047] Figure 2 Schematic diagram of the structure of the crystalline silicon / perovskite tandem solar cell of the present invention;

[0048] Figure 3 A diagram showing the steps for preparing the crystalline silicon / perovskite tandem solar cell of the present invention;

[0049] Figure 4 This is a flow chart for preparing the crystalline silicon / perovskite tandem solar cell of the present invention;

[0050] Figure 5 Schematic diagram of the structure of a crystalline silicon / perovskite tandem solar cell using a PERC silicon bottom structure in the present invention;

[0051] Figure 6 Schematic diagram of the structure of a crystalline silicon / perovskite tandem solar cell using a TOPcon silicon bottom structure in the present invention;

[0052] Figure 7 Schematic diagram of the structure of a crystalline silicon / perovskite tandem solar cell using an HJT silicon bottom structure in the present invention;

[0053] Figure 8 Schematic diagram of the structure of a crystalline silicon / perovskite tandem solar cell using three edge passivation layers in the present invention.

[0054] The labels in the figure are:

[0055] 10, crystalline silicon bottom cell; 20, perovskite top cell; 30, tunneling layer; P1, first edge passivation layer; P2, second edge passivation layer; P3, third edge passivation layer; 11 / 23, metal grid line; 21, buffer layer; 22, transparent electrode layer;

[0056] 101, passivation film; 102, aluminum back surface field; 103, P-type silicon wafer; 104, N+ emitter;

[0057] 111. P+ emitter passivation film; 112. P+ emitter; 113. N-type silicon substrate; 114. Ultra-thin tunneling oxide layer; 115. Phosphorus-doped polysilicon layer;

[0058] 121, first transparent electrode; 122, P-type base doping layer; 123, base passivation layer; 124, silicon substrate; 125, base surface passivation layer; 126, N-type base doping layer;

[0059] 201, hole transport layer; 202, perovskite layer; 2021, perovskite passivation layer; 203, electron transport layer. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0061] In the description of the present invention, unless otherwise specified, "plurality" means two or more; the terms "center", "longitudinal", "lateral", "upper", "lower", "left", "right", "inner", "outer", "front end", "rear end", "head", "tail", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0062] See also Figures 1-4The present application provides a crystalline silicon / perovskite stacked solar cell, comprising a crystalline silicon bottom cell 10, a perovskite top cell 20, a buffer layer 21 and a transparent electrode layer 22 stacked in sequence from bottom to top, wherein a first edge passivation layer P1 and a second edge passivation layer P2 are sequentially provided on the four side extension surfaces of the crystalline silicon bottom cell 10, the perovskite top cell 20 and the buffer layer 21, and the second edge passivation layer P2 also covers the four side extension surfaces of the transparent electrode layer 22, and the top and bottom surfaces of the stacked solar cell are also prepared with metal grid lines 23 (11).

[0063] This application mainly applies to the crystalline silicon / perovskite thin film stacked battery structure. In the crystalline silicon / perovskite thin film stacked battery structure and the preparation process, the perovskite thin film layer is a sensitive material and is very sensitive to the physical / chemical effects of water vapor, oxygen, and solvents, especially in the edge area of ​​the perovskite thin film battery. After laser cutting, its rough cut surface is very susceptible to erosion and penetration by impurities such as water vapor and oxygen, thereby reducing the stability and performance of the film; secondly, in the process of preparing the device, if the edge of the perovskite film is not protected, during the subsequent processes, especially the transparent electrode deposition and metallization processes, the deposited transparent electrode layer and metal grid lines will easily form discontinuous, lateral conductive paths on the rough edges of the film, resulting in device leakage problems. The deposition process used will also easily cause erosion and damage to the underlying battery edge layer, thereby reducing the overall performance and long-term reliability of the device.

[0064] This embodiment uses a first edge passivation layer P1 and a second edge passivation layer P2 for passivation protection, which can improve the protection effect of the edge cutting surface of the stacked battery and reduce the risk of the thin film in the crystalline silicon / perovskite stacked battery being easily corroded, damaged or penetrated by impurities; the obtained edge protection structure can also improve the coverage uniformity and continuity of the deposited transparent conductive layer and metal grid line in the edge area, reduce the potential leakage risk of the thin film layer, reduce the parallel resistance loss, and improve the fill factor and open circuit voltage of the device; by setting two layers of edge passivation layers for protection, the negative impact of each transparent electrode deposition and metal grid line preparation process steps on the sensitive edge area can be reduced, significantly improving the device stability and photoelectric conversion efficiency.

[0065] Furthermore, the buffer layer 21 can be removed from the crystalline silicon / perovskite tandem solar cell, and the first edge passivation layer P1 covers the four edges of the crystalline silicon bottom cell 10 and the perovskite top cell 20 .

[0066] Furthermore, the first edge passivation layer P1 and the second edge passivation layer P2 can be selected from thin films such as aluminum oxide, silicon oxide, aluminum nitride, and tin oxide, and have a thickness of 5-100 nm.

[0067] In one embodiment, the buffer layer 21 may be made of oxide materials such as SnO 2 , Yb 2 O 3 , TiO 2 , and Al 2 O 3 , and may have a thickness of 5 to 30 nm.

[0068] In one embodiment, the transparent electrode layer 22 can be made of one transparent material including ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), IWO (tungsten-doped indium oxide), etc., with a thickness of 20~140nm.

[0069] In one embodiment, the metal grid lines 23 (11) can be made of materials such as Ag, Cu, Al, metal alloys, multi-layer metal composite grid lines, silver-coated metal layers, and silver-coated metal oxide grid lines. The metal grid lines include main grid lines and fine grid lines. The main grid lines have a thickness of 5 to 40 μm and a width of 20 to 1500 μm, and the fine grid lines have a thickness of 5 to 30 μm and a width of 10 to 100 μm.

[0070] In one embodiment, the perovskite top cell 20 includes a hole transport layer 201 , a perovskite layer 202 , and an electron transport layer 203 disposed on a crystalline silicon bottom cell.

[0071] The hole transport layer 201 is made of one or more of poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA), poly-3-hexylthiophene (P3HT), nickel oxide (NiOx), molybdenum trioxide (MoO3), cuprous iodide (CuI), and cuprous thiocyanate (CuSCN).

[0072] In this embodiment, the composition of the perovskite layer 202 may be an ABX3 structure, wherein:

[0073] A position is an organic cation, including CH3NH3 + (MA + ), NH2CH=NH2 + (FA + ), CH3CH2NH3 + or Cs + One or more of the following;

[0074] The B position is a metal cation, including Pb 2+ 、Sn 2+ One or more of the following;

[0075] The X position is a halogen anion, including F - 、Cl - Br - , I - One or more of the .

[0076] In this embodiment, the components of the electron transport layer 203 are zinc oxide (ZnO), tin dioxide (SnO2), titanium dioxide (TiO2), [6,6]-phenyl C 61 Methyl butyrate (PC 61 BM), carbon 60 (C 60 ), one or more of 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP).

[0077] See also Figure 8 In another embodiment, the perovskite top cell 20 further includes a perovskite passivation layer 2021 disposed between the perovskite layer 202 and the electron transport layer 203. The perovskite passivation layer 2021 is composed of at least one of a two-dimensional perovskite, phenylethylamine iodide (PEAI), polymethyl methacrylate (PMMA), ammonium halide (NH4X), cesium halide (CsX), and lead halide (PbX2), and has a thickness of 5 to 80 nm. The perovskite passivation layer can passivate iodide and bromide ion defects on the surface of the perovskite layer, reducing surface carrier recombination and improving photoelectric conversion efficiency.

[0078] Furthermore, the crystalline silicon / perovskite tandem solar cell also includes a third edge passivation layer P3, which is arranged on the side of the first edge passivation layer P1 away from the second edge passivation layer P2; the third edge passivation layer P3 covers the four edges of the crystalline silicon bottom cell 10, the hole transport layer 201, and the perovskite layer 202, or the third edge passivation layer P3 covers the four edges of the crystalline silicon bottom cell 10, the hole transport layer 201, the perovskite layer 202, and the perovskite passivation layer 2021; the third edge passivation layer P3 can be selected from a thin film such as aluminum oxide, silicon oxide, aluminum nitride, and tin oxide, with a thickness of 5-100nm. The third edge passivation layer P3 is mainly set to take into account the characteristics of the perovskite film that is easy to penetrate and decompose. An edge protection structure is first formed at its edge, which can reduce water and oxygen penetration when preparing the electron transport layer and inhibit the interface migration of ions.

[0079] In one embodiment, a tunneling layer 30 is further provided between the crystalline silicon bottom cell 10 and the perovskite top cell 20. The tunneling layer 30 is composed of oxide materials such as ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), and IWO (tungsten-doped indium oxide), with a thickness of 1 to 80 nm. The tunneling layer 30 enables efficient recombination and tunneling transmission of carriers in the series cells while minimizing optical and electrical losses.

[0080] In one embodiment, the crystalline silicon bottom cell 10 can be selected from a crystalline silicon cell structure such as a PERC cell, a topcon cell or an HJT cell.

[0081] For further information, see Figure 5 The PERC cell includes a passivation film 101, an aluminum back surface field 102, a P-type silicon wafer 103, and an N+ emitter 104 from bottom to top;

[0082] For further information, see Figure 6 The topcon cell includes, from bottom to top, a p+ emitter passivation film 111, a p+ emitter 112, an N-type silicon substrate 113, an ultra-thin tunneling oxide layer 114, and a phosphorus-doped polysilicon layer 115;

[0083] For further information, see Figure 7 The HJT cell includes, from bottom to top, a first transparent electrode layer 121 , a P-type base doping layer 122 , a base passivation layer 123 , a silicon substrate 124 , a base surface passivation layer 125 , and an N-type base doping layer 126 .

[0084] The different crystalline silicon bottom cells 10 used above are all prepared by conventional technical means, or by recycling existing scrapped crystalline silicon cells.

[0085] On the other hand, the present application also provides a method for preparing the above-mentioned crystalline silicon / perovskite tandem solar cell, comprising the steps of:

[0086] A stacked cell structure is provided, wherein the stacked cell structure includes a crystalline silicon bottom cell 10 and a perovskite top cell 20 thereon, a buffer layer 21 is prepared on the surface of the perovskite top cell 20 on the stacked cell structure, a plurality of stacked cell structures prepared as above are stacked with their faces facing the same direction and placed in a carrier, and then sent to a deposition device, a first edge passivation layer P1 is formed on the four side extension surfaces of the plurality of stacked cell structures, after deposition is completed, the cells are taken out and split, a transparent electrode layer 22 is prepared on the surface of the buffer layer 21, the plurality of stacked cells prepared are stacked again with their faces facing the same direction and placed in a carrier, and then sent to a deposition device, a second edge passivation layer P2 is formed on the four side extension surfaces of the plurality of stacked cell structures, after deposition is completed, the cells are taken out and split, and metal grid lines 23 (11) are prepared on the top and bottom surfaces of the stacked cell structures.

[0087] The stacked cell structure can be prepared using conventional processes, by providing a crystalline silicon bottom cell 10 and sequentially preparing the various film layers of the perovskite top cell 20 thereon, which will not be described in detail here.

[0088] In one embodiment, the buffer layer 21 step can be removed, that is, the first edge passivation layer P1 is prepared on the four edge surfaces of the crystalline silicon bottom cell 10 and the perovskite top cell 20. The main function is to protect the perovskite thin film layer, reduce the risk of water and oxygen corrosion, and improve the coverage uniformity and continuity of the deposited transparent conductive layer and metal grid line in the edge area, thereby reducing the potential leakage risk of the thin film layer.

[0089] In one embodiment, the first edge passivation layer P1 and the second edge passivation layer P2 can be composed of a thin film selected from aluminum oxide, silicon oxide, aluminum nitride, tin oxide, etc., with a thickness of 5-100 nm; and are prepared by deposition methods such as atomic layer deposition, evaporation, chemical vapor deposition, and magnetron sputtering.

[0090] Optionally, when atomic layer deposition is used for deposition, the deposition temperature is controlled to be 150~250°C; the deposition pressure is 0.5~3 torr; the flow rate of the passivation gas is 5000~20000sccm, the flow rate of the water vapor is 5000~20000sccm, and the flow rate of the nitrogen is 20000~40000sccm, to form a first edge passivation layer P1 / a second edge passivation layer P2 on the four side extension surfaces of the stacked battery structure.

[0091] Optionally, when magnetron sputtering is used for deposition, a passivation material target is set, the chamber pressure is controlled at 0.3~0.6pa, the deposition power is 1000~2500W, working gases such as Ar and O2 are introduced, and the gas flow rate is controlled at 500~1500sccm to form a first edge passivation layer P1 / a second edge passivation layer P2 on the four side extension surfaces of the stacked battery structure.

[0092] In this embodiment, an annealing process is performed after the first and second edge passivation layers P1 (P2) are deposited. The stacked battery structure after the first edge passivation layer P1 / second edge passivation layer P2 is placed in an annealing device for annealing. The temperature is set at 80-200°C and the annealing time is 10 minutes to 30 minutes. After the annealing is completed, the subsequent preparation steps are carried out.

[0093] In one embodiment, the buffer layer 21 can be prepared by sputtering, atomic layer deposition, etc., with a thickness of 5-30 nm.

[0094] Optionally, the buffer layer 21 is prepared by sputtering, setting a metal / metal oxide target, introducing an Ar / O2 mixed gas, controlling the O2 partial pressure to 0.5~3%, controlling the gas flow rate to 400~1500sccm, controlling the sputtering power to 1000~2500W, and the vacuum degree to 0.3~0.8pa, to form a buffer layer 21 on the laminated battery structure.

[0095] Optionally, the buffer layer 21 is prepared by atomic layer deposition. When atomic layer deposition is used for deposition, the deposition temperature is controlled to be 80~200; the deposition pressure is controlled to be 0.1~1.5 torr; the flow rate of metal / metal oxide gas is controlled to be 500~1500sccm, the flow rate of water vapor is controlled to be 500~1500sccm, and the flow rate of nitrogen is controlled to be 1000~3000sccm, to form a buffer layer on the laminated battery structure.

[0096] In one embodiment, the transparent electrode layer 22 can be prepared by at least one process such as magnetron sputtering, atomic layer deposition, etc., and has a thickness of 20-140 nm.

[0097] Optionally, the transparent electrode layer 22 is prepared by a magnetron sputtering process, a metal oxide target is set, and an Ar / O2 mixed gas is introduced. The transparent electrode layer is prepared by a magnetron sputtering process, a metal oxide target is set, and an Ar / O2 mixed gas is introduced, the O2 partial pressure is 0.5~5%, the gas flow rate is controlled to be 400~1500sccm, the sputtering power is controlled to be 1000~2500W, the vacuum degree is 0.3~0.8Pa, and a transparent electrode layer 22 is formed on the laminated battery structure.

[0098] In one embodiment, the metal grid lines 23 (11) can be prepared by at least one process such as screen printing, electroplating, inkjet printing, nano-imprinting, etc., and the metal grid lines include main grid lines and fine grid lines. The main grid lines have a thickness of 5~40um and a width of 20~1500um, and the fine grid lines have a thickness of 5~30um and a width of 10~100um.

[0099] Preferably, the metal grid lines 23 (11) are prepared by a screen printing process. Specifically, the laminated battery structure to be printed is placed on a printing base, a screen is placed on it, a scraper is used to scrape the printing paste to cover the screen, and the screen is removed to obtain the metal grid lines 23 (11) on the laminated battery structure.

[0100] The following specific embodiments and comparative examples are provided to clearly and completely describe the technical solutions of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0101] Example 1

[0102] Step 1: Prepare several prepared stacked cell structures, wherein the stacked cell includes a crystalline silicon bottom cell 10 and a perovskite top cell 20 thereon, and prepare a buffer layer 21 on the surface of the perovskite top cell 20 of the stacked cell structure.

[0103] In this embodiment, a stacked cell structure with an area of ​​M6 can be selected according to production needs, and a cell structure of corresponding size can be obtained by laser cutting. The crystalline silicon bottom cell 10 adopts a TOPcon cell structure, including SiN x / Si:B / n-Si / SiO2 / n⁺-poly-Si structure. The perovskite top cell 20 includes NIO prepared in sequence on the crystalline silicon bottom cell 10. x / CH3NH3PbI3 / C 60 composition.

[0104] In this embodiment, the buffer layer 21 is prepared by sputtering. A SnO2 target is set, an Ar / O2 mixed gas is introduced, the gas flow rate is controlled to 1000sccm, the sputtering power is controlled to 2000W, the vacuum degree is controlled to 0.5pa, and the buffer layer 21 is formed on the laminated battery structure.

[0105] Step 2: Stack the multiple stacked battery structures prepared in the previous step with their surfaces facing the same direction and place them in a carrier, which is then sent to a deposition device to form a first edge passivation layer P1 on the four edges of the multiple stacked battery structures. After deposition, the layers are taken out and split.

[0106] In this embodiment, the first edge passivation layer P1 is deposited by atomic layer deposition, and the deposition temperature is controlled to 200°C; the deposition pressure is 1 torr; the flow rate of trimethylaluminum (TMA) is controlled to 15000 sccm, the flow rate of the water vapor is 15000 sccm, and the flow rate of the nitrogen is 30000 sccm, and the first edge passivation layer P1 is formed on the four side extension surfaces of the stacked battery structure.

[0107] After the first edge passivation layer P1 is deposited, an annealing process is performed. The stacked battery structure with the first edge passivation layer P1 deposited is placed in an annealing device for annealing. The temperature is set at 150° C. and the annealing time is 15 minutes. After the annealing is completed, subsequent preparation steps are performed.

[0108] Step 3: preparing a transparent electrode layer 22 on the surface of the buffer layer 21 .

[0109] In this embodiment, the transparent electrode layer 22 is prepared by a magnetron sputtering process. An ITO target is set, an Ar / O2 mixed gas is introduced, the O2 partial pressure is 1.5%, the gas flow rate is controlled to 1000sccm, the sputtering power is controlled to 1500W, the vacuum degree is 0.5pa, and a transparent electrode layer 22 is formed on the laminated battery structure.

[0110] Step 4: Stack the multiple stacked cells obtained in the previous step with their faces facing the same direction and place them in a carrier, which is then sent to a deposition device to form a second edge passivation layer P2 on the four edges of the multiple stacked cell structures. After deposition, the cells are taken out and split.

[0111] In this embodiment, the second edge passivation layer P2 is deposited by atomic layer deposition, and the deposition temperature is controlled to 200°C; the deposition pressure is 1 torr; the flow rate of trimethylaluminum (TMA) is controlled to 15000 sccm, the flow rate of the water vapor is 15000 sccm, and the flow rate of the nitrogen is 30000 sccm, and the second edge passivation layer P2 is formed on the four side extension surfaces of the stacked battery structure.

[0112] After the second edge passivation layer P2 is deposited, an annealing process is performed. The stacked battery structure with the second edge passivation layer P2 deposited is placed in an annealing device for annealing. The temperature is set at 150° C. and the annealing time is 20 minutes. After the annealing is completed, subsequent preparation steps are performed.

[0113] Step 5: Prepare metal grid lines 23 (11) on the top and bottom surfaces of the laminated battery structure.

[0114] In this embodiment, the metal grid lines 23 (11) are prepared by a screen printing process. Specifically, the laminated battery structure to be printed is placed on a printing base, a screen is placed on it, a scraper is used to scrape the printing paste to cover the screen, and the screen is removed to obtain the metal grid lines 23 (11) on the laminated battery structure.

[0115] Example 2

[0116] This embodiment provides a crystalline silicon / perovskite tandem solar cell prepared by applying this process, wherein a buffer layer 21 is prepared on a tandem cell structure having a crystalline silicon bottom cell 10 and a perovskite top cell 20, and then a first edge passivation layer P1, a transparent electrode layer 22 and metal grid lines 23 (11) are deposited on the bottom and top surfaces of the tandem cell structure in sequence. The difference from Example 1 is that this embodiment does not perform a second edge passivation on the tandem cell structure.

[0117] Example 3

[0118] This embodiment provides a crystalline silicon / perovskite tandem solar cell prepared by applying this process, wherein a buffer layer 21 is prepared on a tandem cell structure having a crystalline silicon bottom cell 10 and a perovskite top cell 20, and then a transparent electrode layer 22, a second edge passivation layer P2 and metal grid lines 23 (11) are deposited on the bottom and top surfaces of the tandem cell structure in sequence. The difference from Example 1 is that this embodiment does not perform the first edge passivation on the tandem cell structure.

[0119] Example 4

[0120] This embodiment provides a crystalline silicon / perovskite tandem solar cell prepared by applying this process, wherein a buffer layer 21 is prepared on a tandem structure having a crystalline silicon bottom cell 10 and a perovskite top cell 20, and then a transparent electrode layer 22 and metal grid lines 23 (11) are deposited on the bottom and top surfaces of the tandem cell structure in sequence. The difference from Example 1 is that this embodiment does not perform the first and second edge passivation on the tandem cell structure.

[0121] The laminated solar cells obtained in Examples 1-4 were tested under the following conditions: a solar simulator was used to calibrate a standard solar intensity and a solar cell with an area of ​​1.0 cm was used. 2 The device of the embodiment was subjected to a long-term IV test, with the starting voltage set to 1.95V, the cut-off voltage set to 0V, and the range set to 100mA. The results were rounded to one decimal place. The test results are shown in Table 1 below.

[0122] Table 1. Performance test results of solar cells obtained in Examples 1 to 4

[0123] Performance indicators EFF (%) Voc (V) <![CDATA[ Isc(mA / cm 2 )]]> FF (%) Example 1 26.15 1.865 18.363 76.36 Example 2 25.83 1.827 18.331 77.13 Example 3 25.06 1.815 18.325 75.35 Example 4 23.82 1.796 18.257 72.65

[0124] In Table 1, EFF refers to the battery conversion efficiency, Voc is the open circuit voltage of the battery cell, Isc is the short circuit current of the battery cell, and FF refers to the fill factor.

[0125] It can be seen from the table that the edge-passivated perovskite crystalline silicon stacked solar cell shows obvious advantages. Examples 1-3 all carried out a two-layer edge passivation or one-layer edge passivation preparation process, which effectively protected the edge film of the perovskite solar cell, and its photoelectric conversion efficiency and open-circuit voltage were significantly improved, thereby improving the stability and performance of the device. In Example 4, since there was no protection of at least one edge passivation layer, it was greatly affected by the physical / chemical effects of water vapor, oxygen and subsequent processes, and its photoelectric conversion efficiency and open-circuit voltage were reduced, resulting in poor device performance.

[0126] The design of performing edge passivation in steps as described in the embodiment of the present invention has significant advantages in stacked perovskite / crystalline silicon cells, which are mainly reflected in the following aspects: 1. It can improve the protection effect of the edges of sensitive layers such as perovskite, and reduce the influence of water vapor, oxygen, solvents and physical / chemical effects of subsequent processes; 2. It can reduce the discontinuous and lateral conductive paths formed at the edge of the device by transparent electrode deposition and metallization processes, which cause leakage risks; 3. The two layers of edge passivation layer can have a good passivation effect on the edge of the device, reduce the recombination loss of carriers in the edge area, and improve the open circuit voltage.

[0127] The above embodiments are only preferred implementation modes of the present invention. It should be pointed out that for ordinary technicians in this technical field, various changes, modifications, replacements and deformations can be made to these embodiments without departing from the principles of the present invention. These technical solutions that are equivalent to the claims of the present invention all fall within the scope of protection of the present invention, and the scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A crystalline silicon / perovskite tandem solar cell, characterized in that: The following steps are involved: A crystalline silicon bottom cell, a perovskite top cell, a buffer layer and a transparent electrode layer are stacked in sequence from bottom to top. A first edge passivation layer and a second edge passivation layer are sequentially arranged on the four sides of the crystalline silicon bottom cell, the perovskite top cell and the buffer layer. The second edge passivation layer also covers the four sides of the transparent electrode layer. Metal grid lines are also prepared on the top and bottom surfaces of the stacked solar cell.

2. The crystalline silicon / perovskite tandem solar cell according to claim 1, characterized in that: The buffer layer of the crystalline silicon / perovskite stacked solar cell is removed, and the first edge passivation layer covers the four side extension surfaces of the crystalline silicon bottom cell and the perovskite top cell.

3. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that: The first edge passivation layer and the second edge passivation layer are composed of a thin film selected from one of aluminum oxide, silicon oxide, aluminum nitride, and tin oxide, and have a thickness of 5-100 nm.

4. The crystalline silicon / perovskite tandem solar cell according to claim 1, characterized in that: The buffer layer is made of one oxide material among SnO2, Yb2O3, TiO2 and Al2O3, and has a thickness of 5-30 nm.

5. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that: The transparent electrode layer is composed of one transparent material of ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), and IWO (tungsten-doped indium oxide), and has a thickness of 20~140nm.

6. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that: The metal grid lines are made of one of the materials of Ag, Cu, Al, metal alloy, multi-layer metal composite grid lines, silver-clad metal layer, and silver-clad metal oxide grid lines. The metal grid lines include main grid lines and fine grid lines. The main grid lines have a thickness of 5~40um and a width of 20~1500um. The fine grid lines have a thickness of 5~30um and a width of 10~100um.

7. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that: The perovskite top cell includes a hole transport layer, a perovskite layer, and an electron transport layer disposed on a crystalline silicon bottom cell.

8. The crystalline silicon / perovskite tandem solar cell according to claim 7, characterized in that: A perovskite passivation layer is provided between the perovskite layer and the electron transport layer. The perovskite passivation layer is composed of at least one of two-dimensional perovskite, phenylethylamine iodide (PEAI), polymethyl methacrylate (PMMA), ammonium halide (NH4X), cesium halide (CsX) and lead halide (PbX2), and has a thickness of 5~80nm.

9. The crystalline silicon / perovskite tandem solar cell according to claim 8, characterized in that: It also includes a third edge passivation layer, which is arranged on the side of the first edge passivation layer away from the second edge passivation layer; the third edge passivation layer covers the four edge surfaces of the crystalline silicon bottom battery, the hole transport layer, and the perovskite layer, or the third edge passivation layer covers the four edge surfaces of the crystalline silicon bottom battery, the hole transport layer, the perovskite layer and the perovskite passivation layer; the third edge passivation layer is selected from one of the thin films of aluminum oxide, silicon oxide, aluminum nitride, and tin oxide, and has a thickness of 5-100nm.

10. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that: The crystalline silicon bottom cell is selected from one of the crystalline silicon cell structures of a PERC cell, a topcon cell or a HJT cell.

11. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that: A tunneling layer is also provided between the crystalline silicon bottom cell and the perovskite top cell, and is composed of one of the oxide materials of ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), and IWO (tungsten-doped indium oxide), with a thickness of 1 to 80 nm.

12. A method for preparing a crystalline silicon / perovskite tandem solar cell, applied to the crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 11, characterized in that: Including steps: A stacked cell structure is provided, comprising a crystalline silicon bottom cell and a perovskite top cell thereon, a buffer layer being prepared on the surface of the perovskite top cell on the stacked cell structure, the plurality of stacked cell structures being stacked and deposited with their surfaces facing in the same direction, a first edge passivation layer being formed on the four side extension surfaces of the plurality of stacked cell structures, the plurality of cells being removed and split after deposition, a transparent electrode layer being prepared on the surface of the buffer layer, the plurality of stacked cells being stacked again with their surfaces facing in the same direction and deposited, a second edge passivation layer being formed on the four side extension surfaces of the plurality of stacked cell structures, the plurality of cells being removed and split after deposition, and metal grid lines being prepared on the top and bottom surfaces of the stacked cell structures.

13. The method for preparing a crystalline silicon / perovskite tandem solar cell according to claim 12, wherein: The first edge passivation layer and the second edge passivation layer are composed of a thin film selected from aluminum oxide, silicon oxide, aluminum nitride, and tin oxide, with a thickness of 5-100nm; and are prepared by one of the deposition methods of atomic layer deposition, evaporation, chemical vapor deposition, and magnetron sputtering.

14. The method for preparing a crystalline silicon / perovskite tandem solar cell according to claim 12, wherein: After the first and second edge passivation layers are deposited, an annealing process is performed. The stacked battery structure with the first edge passivation layer / second edge passivation layer deposited is placed in an annealing device for annealing. The temperature is set at 80-200°C and the annealing time is 10min~30min. After the annealing is completed, the subsequent preparation steps are carried out.

15. The method for preparing a crystalline silicon / perovskite tandem solar cell according to claim 12, wherein: The buffer layer is prepared by at least one of sputtering and atomic layer deposition, and has a thickness of 5 to 30 nm.

16. The method for preparing a crystalline silicon / perovskite tandem solar cell according to claim 12, wherein: The transparent electrode layer is prepared by at least one process of magnetron sputtering and atomic layer deposition, and has a thickness of 20-140 nm.

17. The method for preparing a crystalline silicon / perovskite tandem solar cell according to claim 12, wherein: The metal grid lines are prepared by at least one process of screen printing, electroplating, inkjet printing, and nanoimprinting. The metal grid lines include main grid lines and fine grid lines. The main grid lines have a thickness of 5~40um and a width of 20~1500um. The fine grid lines have a thickness of 5~30um and a width of 10~100um.

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