Power supply noise test structure and chip packaging structure

Abstract

The invention provides a power supply noise test structure and a chip packaging structure, the power supply noise test structure comprises a test substrate, and one side surface of the test substrate is provided with a first observation point and a second observation point; the first observation point is electrically connected to a power supply end in the to-be-tested chip through a first preset salient point, the first preset salient point is arranged on a packaging substrate of the to-be-tested chip, and the first preset salient point and the first observation point are correspondingly arranged; the second observation point is electrically connected to a grounding end in the to-be-tested chip through a second preset salient point, the second preset salient point is arranged on a packaging substrate of the to-be-tested chip, and the second preset salient point and the second observation point are correspondingly arranged; the first observation point and the second observation point are used for carrying out noise testing on the internal power supply of the chip to be tested.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power supply noise test structure and a chip packaging structure. Background Art

[0002] With the growing development of technologies such as the Internet of Things, artificial intelligence, and autonomous driving, data traffic and computing speed are increasing, and the requirements for the performance and computing power of chip products are also becoming higher and higher. The power supply noise generated by the chip during operation is an important factor affecting the signal transmission quality in the chip. Therefore, chip power supply noise testing is crucial to improving chip design effects and improving chip product quality.

[0003] However, in the related art, the noise testing method cannot actually accurately test the power supply noise situation inside the chip, and the accuracy of the chip power supply noise test is low. Summary of the Invention

[0004] The present application provides a power supply noise test structure and a chip packaging structure.

[0005] The present invention provides a power supply noise test structure, which includes a test substrate, wherein a surface of one side of the test substrate has a first observation point and a second observation point;

[0006] The first observation point is electrically connected to a power supply terminal inside the chip to be tested through a first preset bump, the first preset bump is provided on a packaging substrate of the chip to be tested, and the first preset bump is provided corresponding to the first observation point;

[0007] The second observation point is electrically connected to the ground terminal inside the chip to be tested through a second preset bump, the second preset bump is provided on the packaging substrate of the chip to be tested, and the second preset bump is provided corresponding to the second observation point;

[0008] The first observation point and the second observation point are used to perform noise testing on the internal power supply of the chip under test.

[0009] The embodiment of the present application further provides a chip packaging structure, the chip packaging structure comprising a chip to be tested, a packaging substrate and a power supply noise test structure, wherein the power supply noise test structure comprises the power supply noise test structure provided in the embodiment of the present application;

[0010] There are multiple connection bumps on one side surface of the packaging substrate, and the multiple connection bumps include the first preset bump and the second preset bump. The first preset bump is electrically connected to the power supply terminal inside the chip to be tested, and the second preset bump is electrically connected to the ground terminal inside the chip to be tested.

[0011] According to the power supply noise test structure and chip packaging structure of the embodiment of the present application, the first observation point and the second observation point are independently arranged on the surface of one side of the test substrate, and are electrically connected to the power supply terminal and the ground terminal inside the chip to be tested through the first preset bump and the second preset bump on the packaging substrate respectively. The signal for testing the power supply noise inside the chip to be tested can be accurately drawn out for power supply noise testing. The first observation point and the second observation point on the test substrate and the first preset bump and the second preset bump on the packaging substrate are not connected to any other signals, but are directly electrically connected to the power supply terminal and the ground terminal inside the chip to be tested respectively, for power supply noise testing inside the chip to be tested. They are not easily affected by other signal noise between the chip to be tested and the packaging substrate, and other signal noise between the packaging substrate and the test substrate, so that the power supply noise situation inside the chip to be tested can be accurately tested, effectively improving the accuracy of the power supply noise test inside the chip to be tested.

[0012] With respect to the above embodiments and other aspects of the present application and their implementation, further description is provided in the accompanying drawings, detailed description and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In the accompanying drawings of the embodiments of the present application:

[0014] Figure 1 A schematic diagram of the composition of a power supply noise test structure provided in an embodiment of the present application is shown.

[0015] Figure 2 A schematic diagram of the composition structure of another power supply noise test structure provided in an embodiment of the present application is shown.

[0016] Figure 3 A schematic diagram of the circuits connecting the first preset solder ball and the second preset solder ball on the test substrate to the first observation point and the second observation point respectively in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0018] The present application will be described more fully hereinafter with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms, and the present application should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided to make this application thorough and complete and to enable those skilled in the art to fully understand the scope of this application.

[0019] The accompanying drawings of the embodiments of the present application are intended to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present application and do not constitute a limitation of the present application. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the accompanying drawings.

[0020] The present application may be described with reference to plan views and / or cross-sectional views by way of ideal schematic views of the present application. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0021] In the absence of conflict, the various embodiments of the present application and the various features therein may be combined with each other.

[0022] The terms used in this application are only used to describe specific embodiments and are not intended to limit this application. As used in this application, the term "and / or" includes any and all combinations of one or more related enumerated items. As used in this application, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. As used in this application, the terms "comprising" and "made of" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used in this application have the same meaning as commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this application.

[0024] The present application is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0025] In order to effectively improve the technical problems existing in the above-mentioned related technologies, the embodiments of the present application provide a power supply noise test structure and a chip packaging structure.

[0026] Figure 1 A schematic diagram of the structure of a power supply noise test structure provided in an embodiment of the present application is shown in FIG. Figure 1As shown, an embodiment of the present application provides a power supply noise test structure 100, which includes a test substrate 101. One side surface of the test substrate 101 has a first observation point OBS1 and a second observation point OBS2; the first observation point OBS1 is electrically connected to the power supply end inside the chip to be tested 200 through a first preset bump Bu1, and the first preset bump Bu1 is arranged on the package substrate (PKG substrate) 300 of the chip to be tested 200, and the first preset bump Bu1 is arranged corresponding to the first observation point OBS1; the second observation point OBS2 is electrically connected to the ground end inside the chip to be tested 200 through a second preset bump Bu2, and the second preset bump Bu2 is arranged on the package substrate 300 of the chip to be tested 200, and the second preset bump Bu2 is arranged corresponding to the second observation point OBS2; the first observation point OBS1 and the second observation point OBS2 are used to perform noise testing on the internal power supply of the chip to be tested 200.

[0027] In the embodiments of this application, Figure 1 As shown, the first observation point OBS1 on the test substrate 101 is electrically connected to the first preset bump Bu1 on the packaging substrate 300, and the first preset bump Bu1 on the packaging substrate 300 is electrically connected to the power supply terminal inside the chip to be tested 200, thereby realizing an electrical connection between the first observation point OBS1 on the test substrate 101 and the power supply terminal inside the chip to be tested 200; the second observation point OBS2 on the test substrate 101 is electrically connected to the second preset bump Bu2 on the packaging substrate 300, and the second preset bump Bu2 on the packaging substrate 300 is electrically connected to the ground terminal inside the chip to be tested 200, thereby realizing an electrical connection between the second observation point OBS2 on the test substrate 101 and the ground terminal inside the chip to be tested 200.

[0028] In actual applications, when conducting a power supply noise test on a chip, the test pins or probes of a test device (such as an oscilloscope) can be electrically connected to the first observation point OBS1 and the second observation point OBS2 on the test substrate 101, respectively. The first observation point OBS1 and the second observation point OBS2 are used to lead out and read the signal for testing the internal power supply noise of the chip under test, thereby achieving noise testing on the internal power supply of the chip under test 200.

[0029] According to the power supply noise test structure provided in the embodiment of the present application, the first observation point and the second observation point are independently arranged on the surface of one side of the test substrate, and are electrically connected to the power supply terminal and the ground terminal inside the chip to be tested through the first preset bump and the second preset bump on the packaging substrate respectively. The signal for testing the power supply noise inside the chip to be tested can be accurately drawn out to perform power supply noise testing. The first observation point and the second observation point on the test substrate and the first preset bump and the second preset bump on the packaging substrate are not connected to any other signals, but are directly electrically connected to the power supply terminal and the ground terminal inside the chip to be tested respectively, for power supply noise testing inside the chip to be tested. They are not easily affected by other signal noise between the chip to be tested and the packaging substrate, and other signal noise between the packaging substrate and the test substrate, so that the power supply noise situation inside the chip to be tested can be accurately tested, effectively improving the accuracy of the power supply noise test inside the chip to be tested.

[0030] In actual applications, during the chip design process, developers usually use simulation model simulation to guide chip design, power supply design, power supply device selection and PCB board plane design. By using the power supply noise test structure of the embodiment of the present application, accurate chip internal power supply noise testing is performed through the first observation point and the second observation point to obtain accurate power supply noise test results. By comparing and analyzing the power supply noise test results obtained by the test with the simulation results of the simulation model, the cause of the power supply noise can be accurately analyzed and determined, so that the simulation model can be trimmed by adjusting the filter circuit or power supply switching frequency in the chip to improve the accuracy of the simulation model, which is conducive to better guiding chip design, power supply design, power supply device selection and PCB board plane design, etc., and is conducive to determining the correctness of the chip power supply circuit design. The filter circuit or power supply switching frequency in the chip can be adjusted more accurately according to the power supply noise test results, which is conducive to improving chip working efficiency, signal transmission quality and product quality.

[0031] In the embodiment of the present application, the chip to be tested 200 can be a bare die, which refers to an unpackaged semiconductor chip unit cut from a wafer, containing the complete circuit structure of the chip; the packaging substrate 300 is a carrier for semiconductor chip packaging, which can provide electrical connection, protection, support, heat dissipation, assembly and other functions for the chip to be tested 200, so as to achieve multi-pin, reduce the volume of the packaged product, improve electrical performance and heat dissipation, ultra-high density or multi-chip modularization.

[0032] In an embodiment of the present application, the chip to be tested 200 has a plurality of chip pins, and the packaging substrate 300 has connection bumps (Bump) electrically connected to the chip pins of the chip to be tested 200. The embodiment of the present application does not impose any special restrictions on the connection method between the chip pins of the chip to be tested 200 and the connection bumps (Bump) of the packaging substrate 300. For example, the connection can be achieved by bonding or welding.

[0033] In some embodiments, an interposer is further provided between the chip to be tested 200 and the packaging substrate 300. The interposer is an intermediate layer technology for connecting chips, usually made of silicon material, and is used to provide electrical connection and signal redistribution between the chip to be tested 200 and the packaging substrate 300. For example, the interposer is a redistributed layer (RDL) layer, which electrically connects the chip pins of the chip to be tested 200 to the corresponding connection bumps on the packaging substrate 300 after rearranging the positions of the chip pins.

[0034] Figure 2 A schematic diagram showing the composition of another power supply noise test structure provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, in some embodiments, one side surface of the packaging substrate 300 has multiple connection bumps Bu, and the multiple connection bumps Bu can be arranged between the packaging substrate 300 and the chip to be tested 200. The connection bumps Bu are used to achieve electrical connection between the chip to be tested 200 and the packaging substrate 300.

[0035] In some embodiments, the plurality of connection bumps Bu on the packaging substrate 300 include a first preset bump Bu1 and a second preset bump Bu2. The first preset bump Bu1 and the second preset bump Bu2 are two connection bumps between the packaging substrate 300 and the chip under test 200 specifically used for power supply noise testing. The two connection bumps can be two connection bumps Bu selected from a plurality of connection bumps Bu already provided on one side surface of the packaging substrate 300 to serve as the first preset bump Bu1 and the second preset bump Bu2, respectively, or two connection bumps Bu added to a plurality of connection bumps Bu already provided on one side surface of the packaging substrate 300 to serve as the first preset bump Bu1 and the second preset bump Bu2, respectively.

[0036] In an embodiment of the present application, the power supply terminal inside the chip to be tested 200 is electrically connected to the first preset bump B1 on the packaging substrate 300 by leading out a dedicated power supply line, and the first preset bump B1 is then electrically connected to the corresponding first observation point OBS1 through the internal lines of the packaging substrate 300 and the internal lines of the test substrate 101; the ground terminal inside the chip to be tested 200 is electrically connected to the second preset bump B2 on the packaging substrate 300 by leading out a dedicated grounding line, and the second preset bump B2 is then electrically connected to the corresponding second observation point OBS2 through the internal lines of the packaging substrate 300 and the internal lines of the test substrate 101.

[0037] In some embodiments, the first preset bump B1 and the second preset bump B2 on the packaging substrate 300 are insulated and isolated from other bumps, other traces, and components, and the corresponding traces of the first preset bump B1 and the second preset bump B2 inside the packaging substrate 300 are also insulated and isolated from the traces and components of any other signals, so that the first preset bump B1 and the second preset bump B2 are not connected to any other signals, which helps to avoid the first preset bump B1 and the second preset bump B2 being interfered with by other signal noise during the power supply noise test and affecting the accuracy of the power supply noise test.

[0038] In some embodiments, the test substrate 101 is a printed circuit board (PCB), which is a circuit board used to connect and support the chip under test. It can provide physical support for the chip under test and various electronic components, and realize the electrical connection and signal transmission function between the chip under test and various electronic components. The packaging substrate 300 is a carrier for packaging the chip under test 200. The packaging substrate 300 plays the role of electrical interconnection and transition between the different circuits of the chip under test 200 and the test substrate 101. It is a bridge connecting the test substrate 101 and the chip under test 200, transmitting the signal of the chip under test 200 to the test substrate 101, and realizing the interconnection and communication between the chip under test 200 and various electronic components.

[0039] In some embodiments, as Figure 1 As shown, the test substrate 101 has a first surface facing the package substrate 300 and a second surface facing away from the first surface. The first observation point OBS1 and the second observation point OBS2 can be set on the second surface of the test substrate 101 to facilitate connecting external test equipment for power supply noise testing.

[0040] In some embodiments, as Figure 2 As shown, the test substrate 101 serves as a PCB board of the chip under test 200 and is electrically connected to the package substrate 300 of the chip under test 200 via connecting solder balls.

[0041] In some embodiments, as Figure 2As shown, a plurality of connecting solder balls Ba are provided on the first surface of the test substrate 101, that is, the surface facing the packaging substrate 300. The plurality of connecting solder balls Ba include a first preset solder ball Ba1 and a second preset solder ball Ba2. The first preset solder ball Ba1 and the second preset solder ball Ba2 are two connecting solder balls between the packaging substrate 300 and the test substrate 101 that are dedicated to power supply noise testing. The two connecting solder balls can be two connecting solder balls Ba selected from a plurality of connecting solder balls Ba on the basis of a plurality of connecting solder balls Ba already provided on one side surface of the test substrate 101, to serve as the first preset solder ball Ba1 and the second preset solder ball Ba2 respectively, or two connecting solder balls Ba are added on the basis of a plurality of connecting solder balls Ba already provided on one side surface of the test substrate 101, to serve as the first preset solder ball Ba1 and the second preset solder ball Ba2 respectively.

[0042] In some embodiments, as Figure 2 As shown, the first observation point OBS1 on the second surface of the test substrate 101 is electrically connected to the first preset solder ball Ba1 on the first surface, and the first preset solder ball Ba1 is electrically connected to the power supply terminal inside the chip to be tested 200 through the first preset bump Bu1, so that the first observation point OBS1 is electrically connected to the power supply terminal inside the chip to be tested 200; the second observation point OBS2 is electrically connected to the second preset solder ball Ba2, and the second preset solder ball Ba2 is electrically connected to the ground terminal inside the chip to be tested 200 through the second preset bump Bu2, so that the second observation point OBS2 is electrically connected to the ground terminal inside the chip to be tested 200.

[0043] In some embodiments, a wiring connecting the first predetermined bump Bu1 and the first predetermined solder ball Ba1 , and a wiring connecting the second predetermined bump Bu2 and the second predetermined solder ball Ba2 are provided inside the package substrate 300 .

[0044] In some embodiments, on the test substrate 101, the first preset solder ball Ba1, the first observation point OBS1 and the wiring inside the test substrate 101 connecting the first preset solder ball Ba1 and the first observation point OBS1, the second preset solder ball Ba2, the second observation point OBS2 and the wiring inside the test substrate 101 connecting the second preset solder ball Ba2 and the second observation point OBS2 are all insulated and isolated from other solder balls, other wirings and components on the test substrate, so that the first preset solder ball Ba1, the second preset solder ball Ba2, the first observation point OBS1 and the second observation point OBS2 are not connected to any other signals, which is beneficial to avoid the first preset solder ball Ba1, the second preset solder ball Ba2, the first observation point OBS1 and the second observation point OBS2 being interfered by other signal noise during the power supply noise test, thereby affecting the accuracy of the power supply noise test.

[0045] In some embodiments, the test substrate 101 is provided with a first metal trace and a second metal trace; the first observation point OBS1 is electrically connected to the first preset solder ball Ba1 through the first metal trace; the second observation point OBS2 is electrically connected to the second preset solder ball Ba2 through the second metal trace.

[0046] In some embodiments, inside the test substrate 101, the first metal trace and the second metal trace have the same length, and the first metal trace and the second metal trace are arranged in parallel and close to each other, where close arrangement means that the distance between the first metal trace and the second metal trace is within a preset distance range, and the preset distance range can be set according to actual needs.

[0047] In some embodiments, the line from the power supply terminal inside the chip under test 200 to the first preset bump Bu1 on the packaging substrate 300, then to the first preset solder ball Ba1 on the test substrate 101, and then to the first observation point OBS1 on the test substrate 101, and the line from the ground terminal inside the chip under test 200 to the second preset bump Bu2 on the packaging substrate 300, then to the second preset solder ball Ba2 on the test substrate 101, and then to the second observation point OBS2 on the test substrate 101 can be arranged in parallel and closely.

[0048] It should be noted that Figure 1 and Figure 2 The schematic diagram only shows an example of a line from the power supply terminal inside the chip under test 200 to the first observation point OBS1 on the test substrate 101, and a line from the ground terminal inside the chip under test 200 to the second observation point OBS2 on the test substrate 101, and does not constitute a limitation on the line layout design of the embodiment of the present application for the line from the power supply terminal inside the chip under test 200 to the first observation point OBS1 on the test substrate 101 and the ground terminal inside the chip under test 200 to the second observation point OBS2 on the test substrate 101, and can also be any other suitable line layout design.

[0049] In an embodiment of the present application, the test circuit from the power supply terminal and the ground terminal inside the chip to be tested 200, through the packaging substrate 300 to the connecting solder ball Ba on the test substrate 101, and then through the routing inside the test substrate 101 to the first observation point OBS1 and the second observation point OBS2 on the test substrate 101 needs to meet the impedance requirements of the test pin or probe of the test equipment (such as an oscilloscope) to avoid introducing new signal noise due to the discontinuity or mismatch of the impedance of the test circuit and the test pin or probe.

[0050] In some embodiments, the impedance of the first observation point OBS1 and the second observation point OBS2 and the impedance of the test pin or probe of the test device meet a preset impedance condition, which can be configured according to actual conditions. For example, the preset impedance condition includes the impedance of the first observation point OBS1 and the second observation point OBS2 being the same as the impedance of the test pin or probe of the test device, or the difference between the impedance of the first observation point OBS1 and the second observation point OBS2 and the impedance of the test pin or probe of the test device being within a preset impedance range, which can be set according to actual needs.

[0051] In some embodiments, a first impedance adjustment device corresponding to the first observation point OBS1 may also be provided on the test substrate 101. The first impedance adjustment device can be connected to the first metal trace between the first preset solder ball Ba1 and the first observation point OBS1. The impedance of the first observation point OBS1 can be adjusted through the first impedance adjustment device so that the impedance of the first observation point OBS1 can meet the required impedance requirements.

[0052] In some embodiments, a second impedance adjustment device corresponding to the second observation point OBS2 may also be provided on the test substrate 101. The second impedance adjustment device can be connected to the second metal trace between the second preset solder ball Ba2 and the second observation point OBS2. The impedance of the second observation point OBS2 can be adjusted through the second impedance adjustment device so that the impedance of the second observation point OBS2 can meet the required impedance requirements.

[0053] In some embodiments, the first impedance adjustment device and the second impedance adjustment device may include resistor-capacitor devices, that is, capacitor and resistor devices.

[0054] In some embodiments, the first impedance adjustment device and the second impedance adjustment device can be set on a side surface of the test substrate 101. For example, the first impedance adjustment device and the second impedance adjustment device can be set on the same side surface (second surface) of the test substrate 101 as the first observation point OBS1 and the second observation point OBS2.

[0055] Figure 3 A schematic diagram showing a circuit diagram of connecting the first preset solder ball and the second preset solder ball on the test substrate in an embodiment of the present application to the first observation point and the second observation point, respectively. In some embodiments, combined with Figure 2 and Figure 3As shown, a first impedance adjustment device is further provided on the second surface of the test substrate 101, and the first impedance adjustment device includes a first resistor R1 and a first capacitor C1. The first preset solder ball Ba1 is electrically connected to the first observation point OBS1 through a first metal trace L1. One end of the first resistor R1 and one end of the first capacitor C1 are respectively electrically connected to the first metal trace L1, and the other end of the first resistor R1 and the other end of the first capacitor C1 are respectively electrically connected to the ground end inside the test substrate 101.

[0056] In some embodiments, combined Figure 2 and Figure 3 As shown, a second impedance adjustment device is also provided on the second surface of the test substrate 101, and the second impedance adjustment device includes a second resistor R2 and a second capacitor C2. The first preset solder ball Ba2 is electrically connected to the second observation point OBS2 through a second metal trace L2. One end of the second resistor R2 and one end of the second capacitor C2 are respectively electrically connected to the second metal trace L2, and the other end of the second resistor R2 and the other end of the second capacitor C2 are respectively electrically connected to the ground end inside the test substrate 101.

[0057] In some embodiments, the first resistor R1 and the second resistor R2 have the same resistance value, and the first capacitor C1 and the second capacitor C2 have the same capacitance value. The present embodiment of the application does not impose any particular limitation on the resistance values ​​of the first resistor R1 and the second resistor R2, and they can be set according to actual needs. For example, the resistance values ​​of the first resistor R1 and the second resistor R2 are both configured to be 49.9 ohms.

[0058] In some embodiments, the first metal trace L1 and the second metal trace L2 are a pair of differential traces, being two parallel traces of equal length. The reference plane for either the first metal trace L1 or the second metal trace L2 is the ground plane (the ground terminal within the test substrate 101). The characteristic impedance of either the first metal trace L1 or the second metal trace L2 is 50 ohms, and the differential impedance between the first metal trace L1 and the second metal trace L2 is 100 ohms. This routing method and configuration can help reduce interference from other signal noise on the test substrate 101 during power supply noise testing.

[0059] In some embodiments, a preset grounding point is further provided on the second surface of the test substrate 101 , and a ground terminal inside the test substrate 101 is electrically connected to the preset grounding point. The preset grounding point is used to assist in noise testing.

[0060] In some embodiments, as Figure 3As shown, the preset grounding points include a first preset grounding point GND1 and a second preset grounding point GND2. The first preset grounding point GND1 is arranged on one side of the first observation point OBS1, and the second preset grounding point GND2 is arranged on one side of the second observation point OBS2.

[0061] In some embodiments, the first observation point OBS1 is connected to the first preset ground point GND1 through a corresponding first impedance adjustment device, and the second observation point OBS2 is connected to the second preset ground point GND2 through a corresponding second impedance adjustment device. By configuring the first preset ground point GND1 and the second preset ground point GND2 to assist in power supply noise testing, it is helpful to reduce the interference of the ground plane on the noise test.

[0062] In actual applications, since some types of test equipment have built-in differential impedance function, while some types of test equipment do not have differential impedance function, by adding a first preset ground point GND1 and a second preset ground point GND2 to assist in noise testing, it can better adapt to more types of test equipment. During actual testing, the test pin or probe of the test equipment can be connected to one or more of the first observation point OBS1, the second observation point OBS2, the first preset ground point GND1 and the second preset ground point GND2 according to test needs to perform noise testing.

[0063] In some embodiments, on the second surface of the test substrate 101, the center distance between the first observation point OBS1 and the second observation point OBS2 is 150 mils, the center distance between the first observation point OBS1 and the first preset ground point GND1 is 150 mils, and the center distance between the second observation point OBS2 and the second preset ground point GND2 is 150 mils. The embodiment of the present application does not impose any special restrictions on the center distances between the first observation point OBS1, the second observation point OBS2, the first preset ground point GND1, and the second preset ground point GND2, and can be set according to actual needs.

[0064] In some embodiments, the first observation point OBS1, the second observation point OBS2, the first preset grounding point GND1 and the second preset grounding point GND2 can use dedicated SMA (SubMiniature version A, a spiral connector) connector or copper foil, etc. The embodiment of the present application does not impose any special restrictions on the specific implementation form of the first observation point OBS1, the second observation point OBS2, the first preset grounding point GND1 and the second preset grounding point GND2, and can be configured according to actual needs.

[0065] In the embodiment of the present application, the test substrate 101 , which serves as the PCB board of the chip under test 200 , is generally further provided with electronic components required for the normal operation of the chip under test 200 , such as power supply devices.

[0066] In some embodiments, the test substrate 101 serves as the PCB board of the chip under test 200. The first observation point OBS1, the second observation point OBS2, the first preset ground point GND1, the second preset ground point GND2, the first impedance adjustment device, and the second impedance adjustment device on the test substrate 101 are not located on the same side surface of the test substrate 101 as the power supply device on the test substrate 101. This helps prevent power supply noise generated by the power supply device on the test substrate 101 from interfering with power supply noise testing within the chip under test. For example, if the power supply device on the test substrate 101 is disposed on the first surface of the test substrate 101, then the first observation point OBS1, the second observation point OBS2, the first preset ground point GND1, the second preset ground point GND2, the first impedance adjustment device, and the second impedance adjustment device need to be disposed on the second surface of the test substrate 101.

[0067] In one application scenario, the noise at the chip die typically comes from the load current noise at the connection bumps between the chip and the package substrate, and the noise at the connection solder balls between the package substrate and the PCB. The noise at the connection solder balls between the package substrate and the PCB typically comes from the noise of the power supply on the PCB, the power plane on the PCB, and other surrounding power supplies or devices. Therefore, the noise at the chip die and the noise at the connection solder balls are different noises. If the noise at the chip die is directly tested through the connection solder balls between the package substrate and the PCB, the noise at the chip die cannot be accurately measured, and the test results may not meet actual requirements. To this end, the embodiment of the present application constructs a first observation point and a second observation point on the PCB board of the chip, and electrically connects the first observation point and the second observation point to the power supply terminal and the ground terminal inside the chip through preset solder balls on the PCB board and preset bumps on the packaging substrate, respectively. The first observation point and the second observation point are connected through the test equipment, which can directly and accurately lead out the power supply signal and ground signal inside the chip to perform internal power supply noise testing of the chip, thereby accurately testing the power supply noise situation inside the chip, effectively improving the accuracy of the internal power supply noise testing of the chip, and improving the problem of sensitive power supply noise testing of the chip.

[0068] The present application also provides a chip packaging structure, such as Figure 2 As shown, the chip packaging structure includes a chip to be tested 200, a packaging substrate 300 and a power supply noise test structure 100. The power supply noise test structure 100 includes the power supply noise test structure of any of the above embodiments.

[0069] like Figure 2 As shown, there are multiple connection bumps Bu on the surface of one side of the packaging substrate 300, and the multiple connection bumps Bu include the first preset bump Bu1 and the second preset bump Bu2. The first preset bump Bu1 is electrically connected to the power supply end inside the chip to be tested 200, and the second preset bump Bu2 is electrically connected to the ground end inside the chip to be tested 200.

[0070] In some embodiments, as Figure 2 As shown, the package substrate 300 is disposed between the chip under test 200 and the test substrate 101 of the power noise test structure 100 .

[0071] In the embodiment of the present application, for the detailed description of the chip under test 200, the packaging substrate 300 and the power supply noise test structure 100, reference may be made to the relevant description in the above embodiment, which will not be repeated here.

[0072] In some application scenarios, the chip 200 to be tested may be a high-speed, high-power chip, such as a Serdes (Serializer / Deserializer) chip or other Ethernet chip with a rate of 50G or above. The chip itself cannot filter out low-frequency noise with a frequency below 5M. This low-frequency noise is mainly generated by the internal power supply of the chip, and will be transmitted through the power plane and interfere with the high-speed Serdes signal quality. By using the power supply noise test structure of the embodiment of the present application, the chip can be tested for internal power supply noise, and the internal power supply noise of the chip can be accurately tested, which is conducive to analyzing power supply noise changes through power supply noise test results, and is conducive to guiding and improving chip design, thereby improving the signal transmission quality and product quality of chip products.

[0073] In some embodiments, the selection of the first predetermined bump Bu1 and the second predetermined bump Bu2, and the first predetermined solder ball Ba1 and the second predetermined solder ball Ba2 can be determined by the following method:

[0074] 1. After the chip die is designed, obtain the power simulation model of the sensitive power supply or high-standard power supply inside the chip die.

[0075] 2. Design the power supply and ground according to the chip Die's power requirements at the connection bumps, and extract the S parameters of the package substrate power supply.

[0076] 3. Design the PCB board (test substrate) according to the chip requirements and extract the S parameters of the PCB board power supply.

[0077] 4. Combine the die internal power simulation model, the S parameters of the package substrate power supply, and the S parameters of the PCB board power supply to simulate the chip power supply as a whole.

[0078] 5. According to the simulation results, two connection bumps with the largest noise at the chip Die are selected on the package substrate, or two appropriate connection bumps are added as the first preset bump Bu1 and the second preset bump Bu2 respectively.

[0079] 6. Lead the first preset bump Bu1 and the second preset bump Bu2 directly to the connecting solder ball Ball through the package substrate through routing, and the obtained two connecting solder balls are respectively used as the first preset solder ball Ba1 and the second preset solder ball Ba2.

[0080] In practical applications, a coaxial cable may be used to connect the first observation point OBS1 and the second observation point OBS2 on the test substrate 101 to perform a power supply noise test.

[0081] First, since the coaxial cable has been impedance matched, it is not necessary to connect resistors and capacitors at the first observation point OBS1 and the second observation point OBS2, that is, the first resistor R1, the first capacitor C1, the second resistor R2, and the second capacitor C2 are not soldered; then, use two coaxial cables (Cable), solder the test pins of the two coaxial cables to the first observation point OBS1 and the second observation point OBS2 respectively, and connect the ground pins of the two coaxial cables to the first preset ground point GND1 and the second preset ground point GND2 respectively; then, connect the other ends of the two coaxial cables to the two channels of the oscilloscope respectively, the oscilloscope is set to an impedance of 50 ohms, and the two channels need to be skew calibrated; finally, read the internal power supply signal and ground signal of the chip from the first observation point OBS1 and the second observation point OBS2 through the oscilloscope to obtain the power supply noise test results.

[0082] The above description of exemplary embodiments of the present application has been provided by way of exemplary and non-limiting examples. However, various modifications and adaptations to the above embodiments will be apparent to those skilled in the art, when considered in conjunction with the accompanying drawings and the appended claims, without departing from the scope of the present application. Therefore, the proper scope of the present application will be determined by reference to the appended claims.

Claims

1. A power supply noise test structure, comprising a test substrate, wherein a first observation point and a second observation point are provided on a surface of the test substrate; The first observation point is electrically connected to a power supply terminal inside the chip to be tested through a first preset bump, the first preset bump is provided on a packaging substrate of the chip to be tested, and the first preset bump is provided corresponding to the first observation point; The second observation point is electrically connected to the ground terminal inside the chip to be tested through a second preset bump, the second preset bump is provided on the packaging substrate of the chip to be tested, and the second preset bump is provided corresponding to the second observation point; The first observation point and the second observation point are used to perform noise testing on the internal power supply of the chip under test.

2. The power supply noise test structure according to claim 1, wherein: The test substrate has a first surface facing the package substrate and a second surface facing away from the first surface. The first observation point and the second observation point are set on the second surface.

3. The power supply noise test structure according to claim 2, wherein: The first surface of the test substrate has a plurality of connection solder balls, the plurality of connection solder balls including a first preset solder ball and a second preset solder ball, the first observation point on the second surface is electrically connected to the first preset solder ball, and the second observation point is electrically connected to the second preset solder ball; The first preset solder ball is electrically connected to the power supply terminal inside the chip to be tested through the first preset bump; The second preset solder ball is electrically connected to a ground terminal inside the chip to be tested through the second preset bump.

4. The power supply noise test structure according to claim 3, wherein: A first metal trace and a second metal trace are provided inside the test substrate; The first observation point is electrically connected to the first preset solder ball through the first metal trace; The second observation point is electrically connected to the second preset solder ball through the second metal trace.

5. The power supply noise test structure according to claim 4, wherein: Inside the test substrate, the first metal trace and the second metal trace have the same length and are arranged in parallel.

6. The power supply noise test structure according to claim 4, wherein: A first resistor and a first capacitor are also provided on the second surface of the test substrate, one end of the first resistor and one end of the first capacitor are electrically connected to the first metal trace, respectively, and the other end of the first resistor and the other end of the first capacitor are electrically connected to the ground terminal inside the test substrate, respectively.

7. The power supply noise test structure according to claim 4, wherein: A second resistor and a second capacitor are also provided on the second surface of the test substrate, one end of the second resistor and one end of the second capacitor are electrically connected to the second metal trace, respectively, and the other end of the second resistor and the other end of the second capacitor are electrically connected to the ground terminal inside the test substrate, respectively.

8. The power supply noise test structure according to claim 6 or 7, wherein: A preset grounding point is further provided on the second surface of the test substrate. The grounding end inside the test substrate is electrically connected to the preset grounding point. The preset grounding point is used to assist in the noise test.

9. The power supply noise test structure according to claim 1, wherein: The test substrate is a PCB board.

10. A chip packaging structure, comprising a chip to be tested, a packaging substrate, and a power supply noise test structure, wherein the power supply noise test structure comprises the power supply noise test structure according to any one of claims 1 to 9; There are multiple connection bumps on one side surface of the packaging substrate, and the multiple connection bumps include the first preset bump and the second preset bump. The first preset bump is electrically connected to the power supply terminal inside the chip to be tested, and the second preset bump is electrically connected to the ground terminal inside the chip to be tested.

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