Beidou PTP master clock device based on chip atomic clock timekeeping

Abstract

The invention discloses a Beidou PTP master clock device based on chip atomic clock timekeeping, which integrates a chip atomic clock and a Beidou satellite time service signal, and comprises the following steps: firstly, receiving a Beidou satellite signal through a satellite receiving module, and generating an accurate 1PPS signal, a TOD signal and a 10MHz frequency signal based on the satellite signal; high-precision time-frequency reference is provided for equipment, and the problem that clock precision is insufficient in a traditional clock synchronization system is solved through the design. Secondly, the first clock board and the second clock board carry chip atomic clocks, and the high stability and low power consumption characteristics of the chip atomic clocks enable the equipment to maintain high precision of clock signals during long-time operation, so that clock errors caused by crystal oscillator frequency drift and aging in a traditional system are avoided. Moreover, the communication core board is connected with the upper computer, so that instructions can be received in real time, and the clock board and the logic control board can be controlled to work, and therefore, the system can quickly respond to the instructions of the upper computer, and accurate time control can be realized.

Description

Technical Field

[0001] The present application relates to the field of clock synchronization technology, and in particular to a Beidou PTP master clock device based on chip atomic clock timekeeping. Background Art

[0002] With technological advancements, precise clock synchronization technology is playing an increasingly important role in modern communications, control systems, and scientific research experiments. This is especially true in experiments and applications involving multiple subsystems and complex devices. Clock synchronization requires not only high-precision time alignment but also precise coordination of event triggering and data acquisition between various systems. The BeiDou satellite timing system and PTP (Precision Time Protocol) have been widely used in various fields, including motor control, power management, and heating systems, to achieve high-precision time synchronization and event triggering. They have become a crucial technical foundation for modern automated control and precision scientific research experiments.

[0003] However, in practical applications, existing clock synchronization technologies still face some challenges. Although the time synchronization system based on Beidou and PTP protocols has significantly improved in accuracy compared to the traditional NTP (Network Time Protocol) system, some key issues still exist. The existing hardware trigger mechanism has not been able to fully utilize its advantages in high-precision time synchronization applications. Traditional devices usually use crystal oscillators as clock sources, but crystal oscillators will experience problems such as frequency aging and phase drift after long-term operation, resulting in the lack of an accurate reference source for the generated hardware timestamps. In addition, due to the limitations of hardware architecture design and program implementation, the output stability and accuracy of the clock frequency and control pulses are difficult to meet the needs of some demanding applications.

[0004] Therefore, in the precise clock synchronization system based on Beidou satellite timing and PTP time synchronization, the accuracy of clock frequency output and the stability of control pulses, as well as how to solve the problem of insufficient timestamp accuracy in the traditional hardware trigger mechanism, have become urgent issues that need to be addressed. Summary of the Invention

[0005] To this end, the present application provides a BeiDou PTP master clock device based on chip atomic clock timekeeping to solve the problem of insufficient timestamp accuracy in traditional hardware triggering mechanisms.

[0006] In order to achieve the above objectives, this application provides the following technical solutions:

[0007] A Beidou PTP master clock device based on chip atomic clock timekeeping, the device includes a satellite receiving module, a communication core board, a first clock board, a second clock board, a logic control board, a PTP output network card and a display module;

[0008] The satellite receiving module is used to receive Beidou satellite signals;

[0009] The input end of the communication core board is electrically connected to the host computer, and the output end of the communication core board is electrically connected to the control end of the first clock board, the second clock board and the logic control board respectively; the communication core board is used to receive instructions sent by the host computer, and control the operation of the first clock board, the second clock board and the logic control board based on the instructions;

[0010] The input ends of the first clock board and the second clock board are electrically connected to the output end of the satellite receiving module, respectively. The first clock board and the second clock board are respectively equipped with a chip atomic clock. The first clock board and the second clock board are used to generate a time-frequency signal based on the output signal of the satellite receiving module. The time-frequency signal includes a 1PPS signal, a TOD signal, and a 10 MHz frequency signal.

[0011] The input end of the logic control board is electrically connected to the output end of the first clock board and the output end of the second clock board respectively, and the logic control board is used to receive the time-frequency signal and generate a clock frequency signal and a trigger pulse signal through the FPGA control circuit;

[0012] The input end of the PTP output network card is electrically connected to the output end of the logic control board, and the PTP output network card is used to receive the clock frequency signal and the trigger pulse signal, and generate two PTP synchronization signals based on the clock frequency signal and the trigger pulse signal;

[0013] The input end of the display module is electrically connected to the output end of the logic control board, and the display module is used to display the clock frequency signal and the trigger pulse signal.

[0014] Optionally, one of the two PTP synchronization signals is an optical fiber output signal, and the other PTP synchronization signal is a standard Ethernet output signal.

[0015] Optionally, the input end of the communication core board is electrically connected to the host computer via an Ethernet interface or an optical fiber interface.

[0016] Optionally, the device further includes a button module;

[0017] The key module is electrically connected to the logic control board, and the key module is used to manually control the operation and state switching of the device.

[0018] Optionally, the device further includes an LED indicator light, which is electrically connected to the logic control board.

[0019] Optionally, the logic control board includes a built-in phase-locked loop circuit, and the phase-locked loop circuit is used to accurately modulate the clock frequency signal according to the time-frequency signal.

[0020] Optionally, the communication core board communicates with the first clock board, the second clock board and the logic control board via UART.

[0021] Optionally, the device supports an event-controlled pulse signal generation mechanism, and the event-controlled pulse signal includes an immediate execution command and an event-relative time execution command, and the event-relative time execution command includes absolute zero point configuration, output single pulse, output equally spaced multiple pulses, and output unequally spaced multiple pulses functions.

[0022] Optionally, the absolute zero point configuration generates an absolute zero point timestamp by receiving UTC day and second number and TOD information; the output single pulse generates a single pulse signal according to the configuration command; the output equally spaced multiple pulses generates an equally spaced multiple pulse signal according to the configuration command; the output unequally spaced multiple pulses generates unequally spaced multiple pulse signals according to the configuration command.

[0023] Optionally, the event control pulse signal is generated based on the clock frequency signal output by the chip atomic clock, through the host computer configuration command, and the configuration command includes channel number, mode, T time delay, number of pulses, pulse width, pulse interval and unequal interval pulse parameters.

[0024] Compared with the prior art, this application has at least the following beneficial effects:

[0025] The present application provides a Beidou PTP master clock device based on chip atomic clock punctuality. By integrating chip atomic clock and Beidou satellite timing signal, it solves the problems of insufficient clock accuracy, frequency drift and synchronization delay in traditional clock synchronization technology. In this device, first, Beidou satellite signal is received by satellite receiving module, and accurate 1PPS signal, TOD signal and 10MHz frequency signal are generated based on satellite signal, providing high-precision time and frequency reference for the device. This design solves the problem of insufficient clock accuracy in traditional clock synchronization system. Secondly, the first clock board and the second clock board are equipped with chip atomic clock, and its high stability and low power consumption characteristics enable the device to maintain high precision of clock signal during long-term operation, avoiding the clock error caused by crystal oscillator frequency drift and aging in traditional system. Furthermore, the communication core board can receive instructions and control the work of clock board and logic control board in real time through connection with the host computer, thereby ensuring that the system can quickly respond to host computer instructions and achieve accurate time control. Furthermore, the logic control board generates clock frequency signals and control pulse signals through the FPGA control circuit, meeting the requirements of high-precision synchronization and triggering. This solves the problem of inconsistent trigger accuracy and response time in traditional control systems, especially when multiple devices are working together. In this way, the device achieves precise time synchronization and event control, effectively improving system stability and reliability, and is particularly suitable for applications requiring extremely high synchronization accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more intuitively illustrate the prior art and the present application, exemplary drawings are provided below. It should be understood that the specific shapes and structures shown in the drawings should not generally be considered as limiting conditions for implementing the present application; for example, based on the technical concepts disclosed in this application and the exemplary drawings, those skilled in the art are capable of easily making routine adjustments or further optimizations to the addition / reduction / attribution division, specific shapes, positional relationships, connection methods, dimensional ratios, etc. of certain units (components).

[0027] Figure 1 A circuit block diagram of a BeiDou PTP master clock device based on a chip atomic clock for timekeeping, provided in Example 1 of the present application;

[0028] Figure 2 A schematic diagram of the structure of a chip atomic clock taming experimental platform based on TDC time precision measurement provided in Example 1 of the present application;

[0029] Figure 3 A schematic diagram of a frequency division configuration providing embodiment 1 of the present application to generate two 1 MHz clock frequency signals;

[0030] Figure 4 A schematic diagram of an FPGA control relative time command functional architecture provided in Example 1 of the present application;

[0031] Figure 5 A schematic diagram of a single pulse mode setting and output pulse of an event relative time command provided in Example 1 of the present application;

[0032] Figure 6 A schematic diagram of an event-relative time command equal-interval multi-pulse mode setting and output pulses provided in Example 1 of the present application;

[0033] Figure 7 A schematic diagram of an event-relative time command unequal interval multi-pulse mode setting and output pulses provided in Example 1 of the present application. DETAILED DESCRIPTION

[0034] The present application will be further described below in detail through specific embodiments in conjunction with the accompanying drawings.

[0035] In the description of this application: unless otherwise specified, the meaning of "plurality" is two or more. The terms "first", "second", "third", etc. in this application are intended to distinguish the objects referred to and do not have any special meaning in terms of technical connotation (for example, they should not be understood as emphasizing the importance or order, etc.). Expressions such as "including", "comprising", "having", etc. also mean "not limited to" (certain units, components, materials, steps, etc.).

[0036] The terms such as "upper", "lower", "left", "right", "middle", etc. cited in this application are usually used to indicate the general relative position relationship for the convenience of intuitive understanding by referring to the drawings, and are not absolute limitations on the position relationship in the actual product.

[0037] Currently, time and frequency standards are primarily based on cesium, hydrogen, and rubidium clocks. Due to their high cost and strict environmental requirements, they are not widely used in daily life. Research institutions and laboratories require high-precision timekeeping, clock synchronization, and event triggering for scientific research projects, especially those involving multiple subsystems and complex devices. These devices are primarily used to ensure clock and event synchronization between different measurement and control subsystems, ensuring the accuracy of experimental data acquisition and analysis.

[0038] Beidou satellite timing and the PTP precise time synchronization protocol are increasingly being used in fields such as motor control, power management, and heating systems, requiring high-precision clock synchronization and trigger signals between systems. Devices that provide these systems with precise clock signals and enable efficient and stable automated control require stable and secure hardware triggering mechanisms.

[0039] In practical applications, the time synchronization accuracy based on Beidou and PTP precise time synchronization can reach within 100 nanoseconds. Compared with traditional NTP network timing, the time synchronization accuracy is greatly improved. However, due to the limitations of clock punctuality quality, hardware architecture design and program implementation logic, it is difficult for the hardware trigger signal to produce the corresponding effect based on this architecture.

[0040] Existing traditional time synchronization microcontrollers and network timing boards use clock crystal oscillators, which are subject to frequency aging and phase drift, and the generated hardware timestamps lack a reference source. Deploying Beidou and PTP time synchronization applications requires an FPGA board to generate precise clock frequencies and control trigger signals.

[0041] The present invention provides a systematic clock timekeeping, phase locking and trigger signal generation mechanism, which utilizes the low power consumption, high frequency stability characteristics of the chip atomic clock and the precise timing output characteristics of FPGA signal processing to output a trigger mechanism for industry automation and experimental field applications that is adapted to Beidou satellite signals and PTP precise time synchronization.

[0042] like Figure 1 As shown, this embodiment provides a Beidou PTP master clock device based on chip atomic clock punctuality, the device includes a satellite receiving module, a communication core board, a first clock board, a second clock board, a logic control board, a PTP output network card and a display module;

[0043] The satellite receiving module is used to receive Beidou satellite signals;

[0044] The input end of the communication core board is electrically connected to the host computer, and the output end of the communication core board is electrically connected to the control end of the first clock board, the second clock board and the logic control board respectively; the communication core board is used to receive instructions sent by the host computer, and control the operation of the first clock board, the second clock board and the logic control board based on the instructions;

[0045] The input ends of the first clock board and the second clock board are electrically connected to the output end of the satellite receiving module, respectively. The first clock board and the second clock board are respectively equipped with a chip atomic clock. The first clock board and the second clock board are used to generate a time-frequency signal based on the output signal of the satellite receiving module. The time-frequency signal includes a 1PPS signal, a TOD signal, and a 10 MHz frequency signal.

[0046] The input end of the logic control board is electrically connected to the output end of the first clock board and the output end of the second clock board respectively, and the logic control board is used to receive the time-frequency signal and generate a clock frequency signal and a trigger pulse signal through the FPGA control circuit;

[0047] The input end of the PTP output network card is electrically connected to the output end of the logic control board, and the PTP output network card is used to receive the clock frequency signal and the trigger pulse signal, and generate two PTP synchronization signals based on the clock frequency signal and the trigger pulse signal;

[0048] The input end of the display module is electrically connected to the output end of the logic control board, and the display module is used to display the clock frequency signal and the trigger pulse signal.

[0049] In this embodiment, one of the two PTP synchronization signals is an optical fiber output signal, and the other PTP synchronization signal is a standard Ethernet output signal.

[0050] In this embodiment, the input end of the communication core board is electrically connected to the host computer through an Ethernet interface or an optical fiber interface.

[0051] In this embodiment, the device further includes a button module;

[0052] The key module is electrically connected to the logic control board, and the key module is used to manually control the operation and state switching of the device.

[0053] In this embodiment, the device further includes an LED indicator light, which is electrically connected to the logic control board.

[0054] In this embodiment, the logic control board includes a built-in phase-locked loop circuit, and the phase-locked loop circuit is used to accurately modulate the clock frequency signal according to the time-frequency signal.

[0055] In this embodiment, the communication core board communicates with the first clock board, the second clock board and the logic control board through UART.

[0056] In this embodiment, the device supports an event-controlled pulse signal generation mechanism, and the event-controlled pulse signal includes an immediate execution command and an event-relative time execution command. The event-relative time execution command includes absolute zero point configuration, output single pulse, output equally spaced multiple pulses, and output unequally spaced multiple pulses functions.

[0057] In this embodiment, the absolute zero point configuration generates an absolute zero point timestamp by receiving the UTC day and second number and TOD information; the output single pulse generates a single pulse signal according to the configuration command; the output equally spaced multi-pulses generates an equally spaced multi-pulse signal according to the configuration command; the output unequally spaced multi-pulses generates unequally spaced multi-pulse signals according to the configuration command.

[0058] In this embodiment, the generation of the event control pulse signal is based on the clock frequency signal output by the chip atomic clock, and is configured through the host computer command, and the configuration command includes channel number, mode, T time delay, number of pulses, pulse width, pulse interval and unequal interval pulse parameters.

[0059] In this embodiment, the satellite receiving module receives time and frequency signals from Beidou satellites. Beidou satellites provide precise clock reference signals for the device through their high-precision timing system. This module decodes the time and frequency information in the satellite signals and provides the clock board with the required 1PPS (pulse per second), TOD (time of day) signal, and 10 MHz frequency signal.

[0060] The communication core board connects to the host computer through the management network port and receives control commands from the host computer. These commands control the operation of the clock board and logic control board, including the generation of time-frequency signals, the adjustment of clock frequency, and the generation of event-controlled pulse signals. The communication core board is responsible for managing the operation of each module according to the host computer's commands and ensuring signal transmission and data exchange between modules through appropriate communication protocols (such as UART, Ethernet, or fiber optics).

[0061] The first and second clock boards are each equipped with a chip-based atomic clock. These chip-based atomic clocks are characterized by low power consumption, high precision, and high stability, providing high-quality clock signals. These clock boards generate a 1PPS signal, a TOD signal, and a 10MHz frequency signal based on the time and frequency signals received from the satellite receiver module. These time and frequency signals serve as reference signals within the device, ensuring the synchronization accuracy of the entire system.

[0062] The clock board not only generates time-frequency signals, but also provides a reference frequency source, which is crucial for subsequent signal modulation and pulse generation.

[0063] The logic control board is the device's core control unit, responsible for receiving time-frequency signals and processing them through the internal FPGA control circuit. The FPGA circuit generates the required clock frequency signal and control pulse signal based on the time-frequency signals. The FPGA circuit's primary function is to modulate the time-frequency signals and generate precise clock output signals and trigger pulse signals. These signals are used for subsequent data synchronization, event triggering, and other control tasks.

[0064] The control board can flexibly adjust the parameters of the output signal, such as pulse width, delay time and frequency, according to the configuration commands sent by the host computer, ensuring precise control in different application scenarios.

[0065] The PTP output network card receives the clock frequency and control pulse signals generated by the logic control board and generates multiple PTP synchronization signals based on these signals. This output network card supports two output channels: one for standard Ethernet and the other for fiber optics, adapting to the needs of various network environments. The output PTP synchronization signals not only provide precise time synchronization for external devices but also ensure interoperability and synchronization accuracy between different devices.

[0066] The display module is connected to the logic control board and displays the status of the clock frequency signal and control pulse signal in real time on an LCD screen. This display module can provide operators with feedback on key information such as clock synchronization status and trigger signal status, enhancing the device's operability and user experience.

[0067] This embodiment utilizes the high-precision time and frequency signals provided by a chip atomic clock, enabling the device to achieve extremely precise clock synchronization. Chip atomic clocks offer the advantages of low power consumption, long-term stability, and high frequency accuracy, effectively eliminating time errors caused by crystal oscillator aging, phase drift, and other issues in traditional clock synchronization systems.

[0068] Beidou satellite timing signals serve as the benchmark for clock synchronization, ensuring high precision and stability of the clock frequency signal. Compared to traditional Network Time Protocol (NTP) or other clock synchronization systems, this device significantly improves synchronization accuracy, achieving synchronization accuracy of hundreds of nanoseconds through the combined use of PTP (Precision Time Protocol) and Beidou satellite signals. The device provides a flexible event-controlled pulse signal generation mechanism that can generate immediate execution commands or event-based execution commands based on relative time according to host computer instructions. These pulse signals can be used for precise trigger control, ensuring the accuracy of the system in fields such as precision experiments and control systems. Through the FPGA control circuit, it can generate precise event-controlled pulse signals, including absolute zero point configuration, single pulse output, equal-interval multi-pulse, and unequal-interval multi-pulse functions. This mechanism solves the problems of traditional trigger signal generation delay, low precision, and lack of flexibility in the background art, and can be adjusted in real time according to actual needs. Through the connection between the communication core board and the host computer, the device can flexibly receive instructions and adjust the operating status of each module. This function makes the device highly adaptable in complex experimental or control environments, and can adjust the operating mode and output parameters in real time according to different control requirements. The design of the button module and LED indicator light makes the device operation more intuitive. Users can easily operate and monitor the status and understand the working status of the device in a timely manner.

[0069] The device's dual clock board design and multi-channel output capabilities provide redundant support in the event of a failure, ensuring system stability and high availability. In critical applications, even if a hardware failure occurs, the device maintains stable operation and provides precise clock synchronization and event control pulse signals. The device supports multiple output signal modes, including standard Ethernet and fiber optic output, to meet the needs of diverse application scenarios. In high-speed network environments, the device provides highly accurate clock synchronization signals and ensures compatibility and efficient collaboration with external systems.

[0070] The Beidou PTP master clock device based on chip atomic clock timekeeping in this embodiment effectively solves multiple problems in the existing technology through a high-precision clock synchronization mechanism, flexible event control function and perfect redundancy design, especially in terms of clock synchronization accuracy, trigger signal flexibility, system reliability and ease of operation. It has significant technical advantages.

[0071] In this embodiment, the BeiDou PTP time source device is equipped with two clock boards (equipped with chip atomic clocks), a satellite receiving module, a communication core board, a gigabit PTP output network card, an LCD display screen / buttons, and a set of LED indicators; the satellite receiving module: receives satellite signals and analyzes the time and frequency signals via the clock board; clock boards 1 & 2: generate 1PPS+TOD signals and 10MHz based on the chip clock analysis, and transmit the time and frequency signals via the communication line; the logic control core board: receives host computer instructions based on the management network port and uses UART communication to complete the tasks specified by the clock board and logic control board; the LCD display screen / buttons: displays time information, clock / trigger information; the logic control board: receives time and frequency information and control words, generates clock, trigger, and PPS signal outputs, and controls the LED indicator output; the PTP output card: receives time information and generates two PTP outputs (one of which can be optical port), supporting a one-key recovery function. The clock frequency output and control pulse output implemented by the device software function are realized by the logic control board equipped with FPGA through digital signal processing related algorithms.

[0072] This embodiment provides a fast control signal triggering mechanism based on existing clock timekeeping and PTP clock synchronization technologies. The master clock device can provide a pulse output signal, such as 1PPS (one pulse per second), typically generated by controlling a high-precision oscillator and timer circuit. This pulse signal can be synchronized with other devices and applied in various applications, such as measurement, triggering, and control.

[0073] This embodiment integrates a chip clock and satellite receiving module to receive instructions from the communication core board. The clock frequency output is traced back to the Beidou satellite time and frequency reference. The clock frequency output of the chip atomic clock after satellite training is used as the reference, and a stable frequency output is generated through FPGA integer multiplication and division.

[0074] like Figure 2 As shown in the figure, the internal hardware architecture of the Beidou PTP time source device consists of two clock boards equipped with chip atomic clocks, a satellite receiving module, a communication core board, a gigabit PTP output network card, an LCD display screen / buttons and LED indicators.

[0075] Satellite receiving module: receives satellite signals and analyzes time and frequency signals through the clock board;

[0076] Clock boards 1 & 2: Generate 1PPS+TOD signals and 10MHz based on chip atomic clock analysis, and transmit time and frequency signals via communication lines;

[0077] Communication core board: receives host computer instructions based on the management network port and uses UART communication to complete the tasks specified by the clock board and logic control board;

[0078] LCD display screen / buttons: time information, clock / trigger information display;

[0079] Logic control board: receives time-frequency information and control words, and generates precise clock frequency through FPGA, such as Figure 3 As shown, control triggering, such as Figure 4 、 5 , 6, 7, and PPS signal output to control the LED indicator output;

[0080] PTP output card: Receives time information, generates two-way PTP output (one of which can be optical port) and supports one-key recovery function.

[0081] In this embodiment, the clock frequency output signal triggering mechanism is as follows: the clock frequency output is based on the chip atomic clock clock frequency output frequency, and the FPGA is used for integer multiplication and division to generate a stable frequency output. The chip atomic clock is used to provide high-precision, low-power time and frequency output signals, and is generally used in higher-precision time synchronization systems;

[0082] The FPGA signal processing module uses the internal phase-locked loop and atomic clock source reference combined with the configuration command, which is sent to the FPGA for modulation to generate the clock frequency signal output required by the user; the communication core board: management network port, used to communicate with the host computer to generate the appropriate clock frequency configuration signal.

[0083] The event control output is also based on the chip atomic clock output frequency. The control word is generated by the host computer program and forwarded to the logic control board through the communication core board. The FPGA on the board generates the corresponding event control pulse signal through the control word and outputs it.

[0084] Chip atomic clock: used to provide high-precision, low-power time and frequency output signals, usually used in higher-precision time synchronization systems.

[0085] Communication core board: Management network port, used to communicate with the host computer and generate appropriate event pulse output configuration signals. Logic control board: Uses the internal phase-locked loop and atomic clock source reference combined with event control pulse configuration commands, sends them to the FPGA for modulation to generate the user's required event control pulse signal output.

[0086] Event control pulse signals are divided into event immediate execution commands and event relative time execution commands. The time immediate execution commands include functions such as immediate output of high / low levels and immediate output of single pulses. The output phase has little correlation with this mechanism. The FPGA control relative time command output includes four parts: absolute zero point timestamp, output of single pulse, output of multiple pulses with equal intervals, and output of multiple pulses with unequal intervals.

[0087] Absolute zero point configuration: The UTC day and second TOD information time reference sent by the clock board is sent to the FPGA signal processing module according to the custom protocol. The FPGA converts the absolute zero point information configured by the host computer into a control word generated by the communication core board and compares it with UTC_Second to determine the absolute zero time of the device.

[0088] Event relative time command: The functions include setting the absolute zero time stamp, outputting a single pulse, outputting multiple pulses at equal intervals, and outputting multiple pulses at unequal intervals. The host computer software includes seven parameter configurations: channel number, mode, T time delay in ns, quantity, pulse width in ns, pulse interval and pulse width in ns, and unequal interval pulses.

[0089] like Figure 5 As shown, the waveform is a single pulse output with a pulse width of 2us (2000ns). After the absolute zero point is issued, the PPS rising edge delay relative to the second where the absolute zero point is located is 1us (1000ns).

[0090] like Figure 6 As shown in the figure, the PPS delay of equal interval multi-pulse (@OUTREP) is 2000ns relative to the absolute zero point, and six groups of equal interval multi-pulse waveforms with high level of 400ns and low level of 300ns are output. The function setting of outputting unequal interval multi-pulse (@OUTRUP) needs to be configured in the relative time setting, such as Figure 7As shown in the example, set the channel number to 1, the mode to unequal-interval multi-pulse, and the unequal-interval multi-pulse settings to 200, 2, 600, 4, 1200, 6, 2000, and 4. The unequal-interval multi-pulse setting parameters are the D1-Dn and W1-Wn input control words converted to decimal. For example, if D1 is 200, the delay between the first pulse and time T is 200ns; if W1 is 2, the width of the first pulse is 2*100us. According to the protocol pulse interval requirements, Dn+1 must be greater than Dn+Wn*100+200. For example, if D1 is 200, or 200us, and W1 is 2, the first pulse width is 200us, then W2 must be greater than or equal to D1+W1+200, or 600us.

[0091] The technical features of the above embodiments can be combined arbitrarily (as long as there is no contradiction in the combination of these technical features). In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described; these embodiments that are not explicitly written should also be considered to be within the scope of this specification.

Claims

1. A BeiDou PTP master clock device based on chip atomic clock timekeeping, characterized in that: The device includes a satellite receiving module, a communication core board, a first clock board, a second clock board, a logic control board, a PTP output network card and a display module; The satellite receiving module is used to receive Beidou satellite signals; The input end of the communication core board is electrically connected to the host computer, and the output end of the communication core board is electrically connected to the control end of the first clock board, the second clock board and the logic control board respectively; The communication core board is used to receive instructions sent by the host computer and control the work of the first clock board, the second clock board and the logic control board based on the instructions; The input ends of the first clock board and the second clock board are electrically connected to the output end of the satellite receiving module, respectively. The first clock board and the second clock board are respectively equipped with a chip atomic clock. The first clock board and the second clock board are used to generate a time-frequency signal based on the output signal of the satellite receiving module. The time-frequency signal includes a 1PPS signal, a TOD signal, and a 10 MHz frequency signal. The input end of the logic control board is electrically connected to the output end of the first clock board and the output end of the second clock board respectively, and the logic control board is used to receive the time-frequency signal and generate a clock frequency signal and a trigger pulse signal through the FPGA control circuit; The input end of the PTP output network card is electrically connected to the output end of the logic control board, and the PTP output network card is used to receive the clock frequency signal and the trigger pulse signal, and generate two PTP synchronization signals based on the clock frequency signal and the trigger pulse signal; The input end of the display module is electrically connected to the output end of the logic control board, and the display module is used to display the clock frequency signal and the trigger pulse signal.

2. A BeiDou PTP master clock device based on chip atomic clock punctuality according to claim 1, characterized in that, One of the two PTP synchronization signals is an optical fiber output signal, and the other PTP synchronization signal is a standard Ethernet output signal.

3. A BeiDou PTP master clock device based on chip atomic clock punctuality according to claim 1, characterized in that, The input end of the communication core board is electrically connected to the host computer via an Ethernet interface or an optical fiber interface.

4. A BeiDou PTP master clock device based on chip atomic clock punctuality according to claim 1, characterized in that, The device also includes a key module; The key module is electrically connected to the logic control board, and the key module is used to manually control the operation and state switching of the device.

5. A BeiDou PTP master clock device based on chip atomic clock punctuality according to claim 1, characterized in that, The device further includes an LED indicator light, which is electrically connected to the logic control board.

6. A BeiDou PTP master clock device based on chip atomic clock punctuality according to claim 1, characterized in that, The logic control board includes a built-in phase-locked loop circuit, which is used to accurately modulate the clock frequency signal according to the time-frequency signal.

7. A BeiDou PTP master clock device based on chip atomic clock timekeeping according to claim 1, characterized in that, The communication core board communicates with the first clock board, the second clock board and the logic control board through UART.

8. A BeiDou PTP master clock device based on chip atomic clock timekeeping according to claim 1, characterized in that, The device supports an event-controlled pulse signal generation mechanism, wherein the event-controlled pulse signal includes an immediate execution command and an event-relative time execution command, wherein the event-relative time execution command includes absolute zero point configuration, output single pulse, output equally spaced multiple pulses, and output unequally spaced multiple pulses functions.

9. A BeiDou PTP master clock device based on chip atomic clock timekeeping according to claim 8, characterized in that, The absolute zero configuration generates an absolute zero time stamp by receiving UTC day and second and TOD information; The output single pulse generates a single pulse signal according to the configuration command; the output equally spaced multiple pulses generates an equally spaced multiple pulse signal according to the configuration command; the output unequally spaced multiple pulses generates an unequally spaced multiple pulse signal according to the configuration command.

10. A BeiDou PTP master clock device based on chip atomic clock timekeeping according to claim 9, characterized in that, The event control pulse signal is generated based on the clock frequency signal output by the chip atomic clock, through the host computer configuration command, and the configuration command includes channel number, mode, T time delay, number of pulses, pulse width, pulse interval and unequal interval pulse parameters.

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