Circuit, method, apparatus, medium and product for simulating speed sensor

Abstract

The invention provides a circuit, a method, equipment, a medium and a product for simulating a speed sensor, and relates to the technical field of speed sensors, the circuit comprises a first timer, a second timer and an MOS tube, the second timer is connected with the first timer and the MOS tube, the first timer is used for simulating the speed sensor based on the frequency dividing ratio of a first counter in the first timer, and the second timer is used for simulating the speed sensor based on the frequency dividing ratio of a second counter in the second timer. Determining a pulse signal frequency corresponding to the vehicle simulation speed; the second timer is used for receiving different pulse signals according to pulse signal frequencies and simulating corresponding initial pulse signals of the vehicle in different directions based on the pulse signals; and the MOS tube is used for performing level conversion on the initial pulse signal and simulating a target pulse signal when the speed sensor collects the speed. According to the invention, through software and components such as the first timer, the second timer and the MOS tube, a speed sensor is simulated to acquire a target pulse signal of the speed, so that the vehicle-mounted control system can be tested and researched in a laboratory.

Description

Technical Field

[0001] The present invention relates to the technical field of speed sensors, and in particular to a circuit, method, device, medium and product of an analog speed sensor. Background Art

[0002] The on-board control system is the infrastructure to ensure the safe operation of trains. Building a semi-physical train simulation system including speed sensors in the laboratory to test the on-board control system is an indispensable step in the research of on-board control systems.

[0003] However, using real speed sensors to build a simulation system in the laboratory is expensive and bulky, and simulating the functions of real speed sensors requires the use of train wheels, making it impossible to test and study the on-board control system in the laboratory. Summary of the Invention

[0004] The present invention provides a circuit, method, device, medium and product for simulating a speed sensor, which is used to solve the defect in the prior art that the speed sensor is high in cost and large in size and cannot be used for testing and researching the vehicle control system in the laboratory. The circuit achieves the target pulse signal of the speed sensor for collecting the speed through software and components such as a first timer, a second timer and a MOS tube, and uses a low-cost and small-volume speed sensor to build a simulation system speed sensor, thereby realizing the testing and research of the vehicle control system in the laboratory.

[0005] The present invention provides a circuit for simulating a speed sensor, comprising: a first timer, a second timer, and a MOS transistor, wherein the second timer is connected to the first timer and the MOS transistor respectively, wherein: The first timer is configured to determine a pulse signal frequency corresponding to a simulated vehicle speed based on a frequency division ratio of a first counter in the first timer; The second timer is configured to receive different pulse signals according to the pulse signal frequency, and simulate initial pulse signals corresponding to different directions of the vehicle based on the pulse signals; The MOS tube is used to perform level conversion on the initial pulse signal to simulate the target pulse signal when the speed sensor collects the speed.

[0006] According to the present invention, a circuit of an analog speed sensor further includes a logic processing module, which is connected to the first timer and the second timer respectively, wherein: the logic processing module is used to determine the division ratio of the first counter based on the vehicle simulation speed, the vehicle wheel circumference and the value of the reload counter.

[0007] According to a circuit simulating a speed sensor provided by the present invention, the second timer includes a second counter, a comparator module and a level flip module, the second counter is respectively connected to the first timer and the comparator module, and the level flip module is respectively connected to the comparator module and the MOS tube, wherein: the second counter is used to determine the number of received pulse signals to obtain the output value of the second counter; the comparator module is used to compare the output value of the second counter with a fixed value in the comparator module; the level flip module is used to perform a level flip on the pulse signal corresponding to the output value of the second counter when the output value of the second counter is the same as the fixed value in the comparator module, so as to simulate the initial pulse signal.

[0008] According to a circuit of an analog speed sensor provided by the present invention, the comparator module includes a first comparator, a second comparator, and a third comparator; the level flip module includes a first level flip unit, a second level flip unit, and a third level flip unit; the MOS transistor includes a first MOS transistor, a second MOS transistor, and a third MOS transistor; the first level flip unit is connected to the first comparator and the first MOS transistor respectively; the second level flip unit is connected to the second comparator and the second MOS transistor respectively; the third level flip unit is connected to the third comparator and the third MOS transistor respectively; the fixed value includes a first fixed value, a second fixed value, and a third fixed value; the initial pulse signal includes a first initial pulse signal, a second initial pulse signal, and a third initial pulse signal; the target pulse signal includes a first target pulse signal, a second target pulse signal, and a third target pulse signal; wherein: the first comparator is used to compare the first output value of the second counter with the first fixed value; the second comparator is used to compare the second output value of the second counter with the second fixed value; the third comparator is used to compare the third output value of the second counter with the third fixed value; and wherein the first fixed value, the second fixed value, and the third fixed value are determined according to the reload counter value of the second counter and the range of the vehicle rotation angle; the first level flipping unit is configured to, when the first output value is equal to the first fixed value, flip the level of the pulse signal corresponding to the first output value to simulate the first initial pulse signal; the second level flipping unit is configured to, when the second output value is equal to the second fixed value, flip the level of the pulse signal corresponding to the second output value to simulate the second initial pulse signal; the third level flipping unit is configured to, when the third output value is equal to the third fixed value, flip the level of the pulse signal corresponding to the third output value to simulate the third initial pulse signal; the first MOS transistor is configured to, when conducting, perform level conversion on the first initial pulse signal to simulate the first target pulse signal; the second MOS transistor is configured to, when conducting, perform level conversion on the second initial pulse signal to simulate the second target pulse signal; and the third MOS transistor is configured to, when conducting, perform level conversion on the third initial pulse signal to simulate the third target pulse signal.

[0009] According to the present invention, a circuit of an analog speed sensor further includes a switch group, which is respectively connected to the first level flip unit, the second level flip unit, the third level flip unit and the MOS tube, wherein: the switch group is used to control the output of one or more pulse signals among the first target pulse signal, the second target pulse signal and the third target pulse signal.

[0010] According to a circuit of an analog speed sensor provided by the present invention, the logic processing module is further configured to control the increase or decrease of the output value of the second counter based on the running direction of the vehicle.

[0011] The present invention further provides a method for simulating a speed sensor, which is applied to the circuit of the above-mentioned simulating speed sensor, comprising: determining, by a first timer and based on a frequency division ratio of a first counter in the first timer, a pulse signal frequency corresponding to a simulated vehicle speed; receiving different pulse signals according to the pulse signal frequency by a second timer, and simulating initial pulse signals corresponding to different directions of the vehicle based on the pulse signals; The initial pulse signal is level-converted by the MOS tube to simulate the target pulse signal when the speed sensor collects the speed.

[0012] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-described methods for simulating a speed sensor when executing the computer program.

[0013] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for simulating a speed sensor as described above is implemented.

[0014] The present invention further provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above methods for simulating a speed sensor.

[0015] The circuit of the simulated speed sensor provided by the present invention determines the pulse signal frequency corresponding to the simulated vehicle speed based on the frequency division ratio of the first counter in the first timer through a first timer, receives the pulse signal according to the pulse signal frequency, determines the initial pulse signals corresponding to different directions of the vehicle from different pulse signals, and performs level conversion on the obtained initial pulse signal by a MOS tube to obtain a target pulse signal to drive a speed acquisition module to collect speed. In this way, the target pulse signal of the speed sensor is simulated by software and components such as the first timer, the second timer, and the MOS tube, and a simulation system speed sensor is constructed using a low-cost, small-volume speed sensor, thereby realizing testing and research of the vehicle control system in the laboratory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 This is one of the structural schematic diagrams of the circuit of the analog speed sensor provided by the present invention.

[0018] Figure 2 This is the second structural schematic diagram of the circuit of the analog speed sensor provided by the present invention.

[0019] Figure 3 This is the third structural schematic diagram of the circuit of the analog speed sensor provided by the present invention.

[0020] Figure 4 It is a flow chart of the method for simulating a speed sensor provided by the present invention.

[0021] Figure 5 It is a structural schematic diagram of the electronic device provided by the present invention.

[0022] Reference numerals: 100: Circuit of analog speed sensor; 110: First timer; 120: Second timer; 130: MOS transistor; 140: Logic processing module; 121: Second counter; 122: First comparator; 123: Second comparator; 124: Third comparator; 125: First level flip unit; 126: Second level flip unit; 127: Third level flip unit; 131: First MOS transistor; 132: Second MOS transistor; 133: Third MOS transistor. DETAILED DESCRIPTION

[0023] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0024] The following combination Figure 1-Figure 3 The circuit of the analog speed sensor of the present invention is described. The circuit of the analog speed sensor provided by the present invention can collect the speed of vehicles including but not limited to trains, vehicles and the like.

[0025] Figure 1This is one of the structural diagrams of the circuit of the analog speed sensor provided by the present invention, such as Figure 1 As shown, the circuit 100 of the analog speed sensor includes: a first timer 110, a second timer 120 and a MOS transistor 130, wherein the second timer is connected to the first timer and the MOS transistor respectively, wherein: The first timer is configured to determine a pulse signal frequency corresponding to a simulated vehicle speed based on a frequency division ratio of a first counter in the first timer; The second timer is configured to receive different pulse signals according to the pulse signal frequency, and simulate initial pulse signals corresponding to different directions of the vehicle based on the pulse signals; The MOS tube is used to perform level conversion on the initial pulse signal to simulate the target pulse signal when the speed sensor collects the speed.

[0026] Here, the pulse signal frequency means the number of pulse signals acquired per second.

[0027] It should be noted that different simulated vehicle speeds correspond to different frequency division ratios, wherein the frequency division ratio of the first counter can be continuously set through code. In other words, the frequency of the pulse signal output by the first timer can be adjusted according to the frequency division ratio, and the first timer can generate a clock source with adjustable frequency.

[0028] Here, the pulse signal frequency determined by the first timer is used as the input signal of the second timer, that is, the second timer receives unused pulse signals according to the pulse signal frequency.

[0029] Here, the initial pulse signal is used to indicate the direction of the vehicle. For example, the initial pulse signal includes three pulse signals. One rotation of the vehicle is 360 degrees, and the phase difference between two adjacent pulse signals is 120 degrees.

[0030] Here, the MOS tube is a metal-oxide-semiconductor field-effect transistor (MOS). When the MOS tube is turned on, it performs level conversion on the initial pulse signal and transmits the converted pulse signal to the speed acquisition module.

[0031] It should be noted that the voltage of the initial pulse signal generated in the second timer is relatively small, generally 3.3 volts (V), which cannot drive the speed acquisition module to collect speed. Therefore, level conversion is required to convert the voltage of the initial pulse signal to 24V to drive the speed acquisition module to collect speed.

[0032] In an embodiment of the present invention, a first timer is used to determine the pulse signal frequency corresponding to the simulated speed of the vehicle based on the frequency division ratio of the first counter in the first timer. A second timer receives a pulse signal according to the pulse signal frequency, and determines the initial pulse signals corresponding to different directions of the vehicle from different pulse signals. The MOS tube performs level conversion on the obtained initial pulse signal to obtain a target pulse signal to drive the speed acquisition module to collect the speed. In this way, the target pulse signal of the speed sensor is simulated by software and components such as the first timer, the second timer, and the MOS tube, and a simulation system speed sensor is built with a low-cost, small-volume speed sensor, thereby realizing actual testing and research on the vehicle control system in the laboratory.

[0033] further, Figure 2 This is the second structural diagram of the circuit of the analog speed sensor provided by the present invention, as shown in FIG. Figure 2 As shown, the circuit of the analog speed sensor also includes a logic processing module 140, which is connected to the first timer and the second timer respectively, wherein: the logic processing module is used to determine the division ratio of the first counter based on the vehicle simulation speed, the vehicle wheel circumference and the value of the reload counter.

[0034] Here, the division ratio of the first counter may be determined by any appropriate method, for example, by obtaining the mapping relationship between the vehicle simulation speed, the vehicle wheel circumference, the value of the reload counter and the division ratio, or by calculating the division ratio according to a calculation formula.

[0035] Here, the reload counter value is the number of pulse signals in half a period, and the reload counter value can be any appropriate value, such as 90, 900, 9000, etc.

[0036] Exemplarily, the pulse signal frequency is first determined according to the simulated vehicle speed and the wheel circumference of the vehicle, and then the frequency division ratio is obtained by dividing the pulse signal frequency by the natural frequency of the first timer.

[0037] For example, the pulse signal frequency f The calculation is as follows formula (1): (1) in, Indicates the vehicle simulation speed, Indicates the wheel circumference, It represents the number of pulses in one rotation of the vehicle, which is generally 200. n represents the number of pulses in half a cycle, which is the value of the above-mentioned reload counter.

[0038] It should be noted that the logic processing module first determines the frequency division ratio corresponding to different speeds based on different vehicle simulation speeds, the vehicle's wheel circumference and the value of the reload counter, and then implements different frequency division ratios through code to obtain different pulse signal frequencies, and further adjust the input frequency of the second timer.

[0039] In an embodiment of the present invention, the first timer changes the frequency division ratio according to different simulated vehicle speeds, thereby changing the input frequency of the second timer to simulate the state of the speed sensor at different train speeds. At the same time, the problem of discontinuous output phase caused by resetting the pre-allocated counter of the second timer is avoided.

[0040] Furthermore, the second timer includes a second counter, a comparator module and a level flip module, the second counter is respectively connected to the first timer and the comparator module, and the level flip module is respectively connected to the comparator module and the MOS tube, wherein: the second counter is used to determine the number of received pulse signals to obtain the output value of the second counter; the comparator module is used to compare the output value of the second counter with the fixed value in the comparator module; the level flip module is used to perform a level flip on the pulse signal corresponding to the output value of the second counter when the output value of the second counter is the same as the fixed value in the comparator module, so as to simulate the initial pulse signal.

[0041] The initial pulse signal can also turn on the MOS transistor to perform level conversion on the initial pulse signal.

[0042] It should be noted that when a pulse signal is received, the output value of the second counter may increase by 1 or decrease by 1. For example, when the vehicle is moving forward and a pulse signal is received, the output value of the second counter increases by 1. When the vehicle is moving backward and a pulse signal is received, the output value of the second counter decreases by 1. The wheel rotation directions corresponding to the vehicle moving forward and backward are opposite.

[0043] Here, the fixed value in the comparator module may be preset.

[0044] Here, pin level flipping refers to converting a high level into a low level, or converting a low level into a high level. After the level flipping, the initial pulse signal can be obtained and the MOS tube can be turned on.

[0045] It should be noted that the number of comparators in the comparator module can be any appropriate number, for example, three comparators, each of which has a corresponding fixed value, and each path has a corresponding pulse signal transmission.

[0046] It should be noted that the circuit of the simulated speed sensor can simulate both normal state pulse signals and fault state pulse signals. For example, when simulating the normal state, there are three comparators, and the phase difference of the pulse signals in adjacent comparators is 120 degrees, and the speed acquisition module collects the speed in the normal state; when simulating the broken line fault state, there can be two comparators, and the speed acquisition module collects the speed under the fault pulse, or, when simulating the pulse error fault, there can be three comparators and the phase difference of the pulse signals in adjacent comparators is not 120 degrees.

[0047] Specifically, each time a pulse signal is received, the second counter has a corresponding output value. When the output value in the counter is equal to the fixed value in the comparator, a pulse signal corresponding to the output value of the second counter is output, and the pin level in the second timer is flipped to turn on the MOS tube transmission to perform level conversion on the initial pulse signal, and the initial pulse signal after level conversion is transmitted to the speed acquisition module to drive the speed acquisition module to collect speed.

[0048] In the embodiment of the present invention, a low-cost, small-volume speed sensor is realized by using the first timer, the second counter, the comparator module, the level flip module and the MOS tube, meeting the laboratory's demand for speed sensor signal simulation.

[0049] For example, three comparators are used as an embodiment for description.

[0050] Exemplarily, the comparator module includes a first comparator, a second comparator, and a third comparator, the level flip module includes a first level flip unit, a second level flip unit, and a third level flip unit, the MOS tube includes a first MOS tube, a second MOS tube, and a third MOS tube, the first level flip unit is connected to the first comparator and the first MOS tube respectively, the second level flip unit is connected to the second comparator and the second MOS tube respectively, the third level flip unit is connected to the third comparator and the third MOS tube respectively, the fixed value includes a first fixed value, a second fixed value, and a third fixed value, the initial pulse signal includes a first initial pulse signal, a second initial pulse signal, and a third initial pulse signal, and the target pulse signal includes a first target pulse signal, a second target pulse signal, and a third target pulse signal, wherein: the first comparator is used to compare the first output value of the second counter with the first fixed value; the second comparator is used to compare the second output value of the second counter with the second fixed value; the third comparator is used to compare the third output value of the second counter with the third fixed value; wherein the first fixed The first level flipping unit is configured to flip the level of the pulse signal corresponding to the first output value when the first output value is equal to the first fixed value, so as to simulate the first initial pulse signal; the second level flipping unit is configured to flip the level of the pulse signal corresponding to the second output value when the second output value is equal to the second fixed value, so as to simulate the second initial pulse signal; the third level flipping unit is configured to flip the level of the pulse signal corresponding to the third output value when the third output value is equal to the third fixed value, so as to simulate the third initial pulse signal; the first MOS transistor is configured to, when conducting, perform level conversion on the first initial pulse signal to simulate the first target pulse signal; the second MOS transistor is configured to, when conducting, perform level conversion on the second initial pulse signal to simulate the second target pulse signal; and the third MOS transistor is configured to, when conducting, perform level conversion on the third initial pulse signal to simulate the third target pulse signal.

[0051] It should be noted that each comparator corresponds to a channel, and each channel has a corresponding level flip unit and MOS tube.

[0052] It should be noted that the range of the vehicle's rotation angle is 360, and the overload counter value is 900. In order to ensure that the phase difference of the three pulse signals is 120 degrees, the first fixed value is 0, the second fixed value is 600, and the third fixed value is 300. During the counting process of the second counter, when the output value of the second counter is equal to the fixed value, the pin level of the corresponding channel is flipped to turn on the corresponding MOS tube.

[0053] For example, Figure 3 This is the third structural diagram of the circuit of the analog speed sensor provided by the present invention, as shown in FIG. Figure 3 As shown, the circuit of the analog speed sensor includes a first timer 110, a second timer 120, a logic processing module 140, and a MOS transistor 130. The second timer 120 includes a second counter 121, a first comparator 122, a second comparator 123, a third comparator 124, a first level flip unit 125, a second level flip unit 126, and a third level flip unit 127. The MOS transistor 130 includes a first MOS transistor 131, a second MOS transistor 132, and a third MOS transistor 133. The working principle of the circuit of the analog speed sensor is that the logic processing module sets different frequency division ratios of the first timer according to different speeds, and the first timer sets different frequency division ratios according to the natural frequency (50 MHz) and different The frequency division ratio determines different pulse frequencies, and the second timer determines the output value of the second counter according to the pulse frequency. During the counting process of the second counter, when the output value of the second counter is equal to the fixed value 0 in the first comparator, the first level flip unit flips the pin level on the channel to turn on the first MOS transistor. When the output value of the second counter is equal to the fixed value 600 in the second comparator, the second level flip unit flips the pin level on the channel to turn on the second MOS transistor. When the output value of the second counter is equal to the fixed value 300 in the third comparator, the third level flip unit flips the pin level on the channel to turn on the third MOS transistor, thereby simulating three pulse signals with a phase difference of 120 degrees.

[0054] In an embodiment of the present invention, a laboratory speed measurement test of an on-board control system using three comparators, three level flipping units, and three MOS tubes is performed to reduce costs while accurately generating three pulse signals with a phase difference of 120 degrees, meeting the laboratory's needs for speed sensor signal simulation.

[0055] Furthermore, the circuit of the analog speed sensor also includes a switch group, which is respectively connected to the first level flip unit, the second level flip unit, the third level flip unit and the MOS tube, wherein: the switch group is used to control the output of one or more pulse signals among the first target pulse signal, the second target pulse signal and the third target pulse signal.

[0056] It should be noted that the purpose of providing the switch group is to enable simulation of a fault state in the case of three comparators.

[0057] Exemplarily, the switch group may include three switches, with one switch connected between each level flip unit and the MOS tube. When simulating a line break fault, one or two switches may be closed to turn on the corresponding MOS tube to transmit a pulse signal. When simulating a normal state, the three switches may be closed to turn on the three MOS tubes to transmit three pulse signals.

[0058] In the embodiment of the present invention, the level of a certain output is controlled by a switch group to simulate sensor pulses, simulating normal status, disconnection, pulse error and other faults, thereby meeting the laboratory's demand for speed sensor signal simulation.

[0059] Furthermore, the logic processing module is further configured to control the increase or decrease of the output value of the second counter based on the running direction of the vehicle.

[0060] It should be noted that the vehicle's running direction includes forward and backward. For example, when the vehicle is moving forward, each time a pulse signal is received, the logic processing module controls the second counter to add 1. When the vehicle is moving backward, each time a pulse signal is received, the logic processing module controls the second counter to subtract 1. As long as the vehicle's running direction and the direction of the counter correspond to each other, the present invention does not make any specific limitations on this.

[0061] In an embodiment of the present invention, the logic processing part can simulate the forward and reverse rotation (i.e., the running direction) of the wheel by controlling the direction of the counter, thereby increasing the diversity of simulated speed sensor working conditions, meeting the laboratory's needs for speed sensor signal simulation, and further improving the accuracy and practicality of the test.

[0062] The method for simulating a speed sensor provided by the present invention is described below. The method for simulating a speed sensor described below and the circuit for simulating a speed sensor described above can refer to each other.

[0063] Figure 4 FIG. 1 is a flow chart of a method for simulating a speed sensor provided by the present invention, as shown in FIG. Figure 4 As shown, the circuit applied to the above analog speed sensor includes: S201 : Determine, by a first timer and based on a frequency division ratio of a first counter in the first timer, a pulse signal frequency corresponding to a simulated vehicle speed.

[0064] S202 : Receive different pulse signals according to the pulse signal frequency through a second timer, and simulate initial pulse signals corresponding to the vehicle in different directions based on the pulse signals.

[0065] S203 , performing level conversion on the initial pulse signal through a MOS tube to simulate a target pulse signal when a speed sensor collects speed.

[0066] Figure 5 Schematic diagram of the structure of the electronic device provided by the present invention, such as Figure 5 As shown, the electronic device may include: a processor 810, a communications interface 820, a memory 830, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 830 communicate with each other via the communications bus 840. The processor 810 may call logic instructions in the memory 830 to execute a method for simulating a speed sensor, which includes: determining, by a first timer and based on the frequency division ratio of a first counter in the first timer, a pulse signal frequency corresponding to a simulated vehicle speed; receiving, by a second timer, different pulse signals according to the pulse signal frequency, and simulating, based on the pulse signals, initial pulse signals corresponding to different vehicle directions; and performing level conversion on the initial pulse signal by a MOS transistor to simulate a target pulse signal when the speed sensor collects speed.

[0067] Furthermore, the logic instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product, stored in a storage medium, includes instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0068] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the method of simulating a speed sensor provided by the above methods, the method including: determining the pulse signal frequency corresponding to the simulated speed of the vehicle based on the division ratio of the first counter in the first timer through a first timer; receiving different pulse signals according to the pulse signal frequency through a second timer, and simulating the initial pulse signals corresponding to the vehicle in different directions based on the pulse signals; performing level conversion on the initial pulse signal through a MOS tube to simulate the target pulse signal when the speed sensor collects the speed.

[0069] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the method of simulating a speed sensor provided by the above methods, the method comprising: determining the pulse signal frequency corresponding to the simulated speed of the vehicle based on the division ratio of the first counter in the first timer through a first timer; receiving different pulse signals according to the pulse signal frequency through a second timer, and simulating the initial pulse signals corresponding to the vehicle in different directions based on the pulse signals; performing level conversion on the initial pulse signal through a MOS tube to simulate the target pulse signal when the speed sensor collects the speed.

[0070] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0071] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A circuit for simulating a speed sensor, characterized in that: include: A first timer, a second timer, and a MOS transistor, wherein the second timer is connected to the first timer and the MOS transistor respectively, wherein: The first timer is configured to determine a pulse signal frequency corresponding to a simulated vehicle speed based on a frequency division ratio of a first counter in the first timer; The second timer is configured to receive different pulse signals according to the pulse signal frequency, and simulate initial pulse signals corresponding to different directions of the vehicle based on the pulse signals; The MOS tube is used to perform level conversion on the initial pulse signal to simulate the target pulse signal when the speed sensor collects the speed.

2. The circuit of the analog speed sensor according to claim 1, characterized in that: It also includes a logic processing module, which is connected to the first timer and the second timer respectively, wherein: The logic processing module is used to determine the frequency division ratio of the first counter based on the simulated vehicle speed, the wheel circumference of the vehicle and the value of the heavy load counter.

3. The circuit of the analog speed sensor according to claim 2, characterized in that: The second timer includes a second counter, a comparator module and a level flip module, the second counter is connected to the first timer and the comparator module respectively, and the level flip module is connected to the comparator module and the MOS tube respectively, wherein: The second counter is used to determine the number of received pulse signals and obtain an output value of the second counter; The comparator module is configured to compare the output value of the second counter with a fixed value in the comparator module; The level flip module is used to flip the level of the pulse signal corresponding to the output value of the second counter when the output value of the second counter is the same as the fixed value in the comparator module, so as to simulate the initial pulse signal.

4. The circuit of the analog speed sensor according to claim 3, characterized in that: The comparator module includes a first comparator, a second comparator, and a third comparator; the level flip module includes a first level flip unit, a second level flip unit, and a third level flip unit; the MOS transistor includes a first MOS transistor, a second MOS transistor, and a third MOS transistor; the first level flip unit is connected to the first comparator and the first MOS transistor, respectively; the second level flip unit is connected to the second comparator and the second MOS transistor, respectively; the third level flip unit is connected to the third comparator and the third MOS transistor, respectively; the fixed value includes a first fixed value, a second fixed value, and a third fixed value; the initial pulse signal includes a first initial pulse signal, a second initial pulse signal, and a third initial pulse signal; the target pulse signal includes a first target pulse signal, a second target pulse signal, and a third target pulse signal, wherein: The first comparator is configured to compare the first output value of the second counter with the first fixed value; The second comparator is configured to compare the second output value of the second counter with the second fixed value; The third comparator is configured to compare the third output value of the second counter with the third fixed value; wherein the first fixed value, the second fixed value, and the third fixed value are determined according to the reload counter value of the second counter and the range of the vehicle rotation angle; The first level flipping unit is configured to flip the level of the pulse signal corresponding to the first output value to simulate the first initial pulse signal when the first output value is equal to the first fixed value; The second level flipping unit is configured to flip the level of the pulse signal corresponding to the second output value when the second output value is equal to the second fixed value, so as to simulate the second initial pulse signal; The third level flipping unit is configured to flip the level of the pulse signal corresponding to the third output value to simulate the third initial pulse signal when the third output value is equal to the third fixed value; The first MOS transistor is used to perform level conversion on the first initial pulse signal to simulate the first target pulse signal when it is turned on; The second MOS transistor is used to perform level conversion on the second initial pulse signal to simulate the second target pulse signal when it is turned on; The third MOS transistor is used to perform level conversion on the third initial pulse signal to simulate the third target pulse signal when it is turned on.

5. The circuit of the analog speed sensor according to claim 4, characterized in that: It also includes a switch group, which is respectively connected to the first level flip unit, the second level flip unit, the third level flip unit and the MOS tube, wherein: The switch group is used to control the output of one or more pulse signals among the first target pulse signal, the second target pulse signal and the third target pulse signal.

6. The circuit of the analog speed sensor according to claim 3, characterized in that: The logic processing module is further configured to control the increase or decrease of the output value of the second counter based on the running direction of the vehicle.

7. A method for simulating a speed sensor, characterized in that: The circuit for the analog speed sensor of claim 1 comprises: determining, by a first timer and based on a frequency division ratio of a first counter in the first timer, a pulse signal frequency corresponding to a simulated vehicle speed; receiving different pulse signals according to the pulse signal frequency by a second timer, and simulating initial pulse signals corresponding to different directions of the vehicle based on the pulse signals; The initial pulse signal is level-converted by the MOS tube to simulate the target pulse signal when the speed sensor collects the speed.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the method for simulating a speed sensor according to claim 7 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for simulating a speed sensor according to claim 7 is implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method for simulating a speed sensor according to claim 7 is implemented.

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