Register renaming method, system and storage medium for vector processor

Abstract

The application belongs to the technical field of processors, and particularly relates to a register renaming method and system of a vector processor and a storage medium. The instruction fetching unit of the register renaming system of the vector processor is used for fetching instructions from a memory and sending the instructions to a decoding unit; the decoding unit is used for decoding the received instructions; the renaming unit is used for renaming the destination registers corresponding to the decoded scalar instructions and vector instructions into physical registers; the reordering buffer unit is used for storing the vector instructions, the scalar instructions and the renaming information of the scalar instructions; and the vector history stack unit is used for recording the renaming information of the vector instructions in microinstruction granularity. Compared with the prior art, the application can simultaneously rename the vector instructions and the scalar instructions, effectively reduces blocking, optimizes transmission bandwidth, and further improves the performance of the processor.

Description

TECHNICAL FIELD

[0001] The application is suitable for the field of processor technology, and particularly relates to a register renaming method, system and storage medium of a vector processor. BACKGROUND

[0002] With the development of reduced instruction set computer technology, modern processors increasingly adopt superscalar architecture, i.e., multiple instructions are executed in one clock cycle, to meet high computing requirements and complex application scenarios. Register renaming is a key technology in superscalar processors, which usually renames logical registers to physical registers to eliminate false data dependencies and thus improve instruction-level parallelism (ILP). In order to improve data-level parallelism (DLP), modern processors further evolve into vector architecture, so that one instruction can process multiple data. In order to improve the execution efficiency of vector instructions, the processor also needs to perform register renaming on the vector instructions. Unlike scalar instructions, a vector instruction will write the execution result to multiple destination registers, so multiple registers need to be renamed at one time. Therefore, the processor needs a large enough renaming bandwidth to support superscalar and vector at the same time.

[0003] The existing vector processor has multiple renaming schemes for vector instructions, as shown in Figure 1 Figure 1 is a schematic diagram of the renaming process of vector instructions in the related art. In the decoding stage, vector instructions are identified from multiple instruction decoding channels and are processed one by one by the vector decoding unit. The vector decoding unit splits a vector instruction into several micro-ops (micro-operations) in the granularity of vector registers, and then the renaming unit renames these micro-ops according to its processing bandwidth. The re-order buffer is a hardware structure in out-of-order processors that ensures that instructions are submitted in order, which saves the renaming information of each instruction in the execution process until the instruction is finally submitted. In a superscalar-vector processor, the re-order buffer allocates a table entry for each scalar instruction or vector micro-op to save its information.

[0004] ​Because the instructions must be renamed in a sequential order, the above superscalar-vector register renaming manner has a blocking problem. Firstly, because of the bandwidth limitation of the reorder buffer, a vector instruction cannot be renamed in the same clock cycle as several scalar instructions. The vector instruction can only start to be renamed after all the scalar instructions before it are renamed. Secondly, the vector decode unit can need multiple cycles to split and rename a vector instruction, during which the subsequent scalar instructions cannot start to be renamed. Thirdly, the micro-instructions split from the vector instruction can occupy too much reorder buffer, and the insufficient remaining space of the reorder buffer can cause the subsequent instructions to be unable to be received. In the working scenario of mixed emission of scalar and vector instructions, the register renaming manner can cause insufficient emission bandwidth. The insufficient emission bandwidth cannot be compensated by the subsequent execution stage, and finally performance loss is caused.

[0005] Therefore, there is an urgent need for a new register renaming method, system and storage medium of a vector processor to solve the above technical problems. SUMMARY

[0006] The present application provides a register renaming method, system and storage medium of a vector processor, aiming to enable scalar instructions and vector instructions to be simultaneously subjected to register renaming, so that the processor can meet higher performance and frequency requirements.

[0007] In a first aspect, the present application provides a register renaming system of a vector processor, comprising a fetch unit, a decode unit, a rename unit, a reorder buffer unit and a vector history table unit.

[0008] The fetch unit is configured to read instructions from a memory and send the instructions to the decode unit.

[0009] The decode unit is configured to decode the received instructions and send the decoded scalar instructions and vector instructions to the rename unit and the reorder buffer unit.

[0010] The rename unit is configured to rename the destination registers corresponding to the decoded scalar instructions and vector instructions to physical registers, and send the renaming information of the scalar instructions to the reorder buffer unit and the renaming information of the vector instructions to the vector history table unit.

[0011] The reorder buffer unit is configured to store the vector instructions, the scalar instructions and the renaming information of the scalar instructions.

[0012] The vector history table unit is configured to record the renaming information of the vector instructions in a micro-instruction granularity.

[0013] Preferably, each of the vector instructions only occupies a single entry in the reorder buffer unit.

[0014] Preferably, when the renamed vector instruction fails to commit, the vector history table unit is further configured to modify the physical registers mapped by the renamed vector instruction back to the physical registers mapped before renaming according to the renaming information.

[0015] In a second aspect, the present application provides a register renaming method of a vector processor, which is based on the register renaming system of the vector processor as described in the above embodiments. The register renaming method comprises the following steps:

[0016] S1, reading instructions from a memory by a fetch unit and sending the instructions to a decode unit;

[0017] S2, decoding the received instructions by the decode unit and sending scalar instructions and vector instructions decoded out to a rename unit;

[0018] S3, renaming the destination registers corresponding to the decoded scalar instructions and vector instructions to physical registers by the rename unit, sending the renaming information corresponding to the scalar instructions to a reorder buffer unit, and sending the renaming information corresponding to the vector instructions to a vector history table unit and the reorder buffer unit;

[0019] S4, when the scalar instruction successfully commits, deleting the entry corresponding to the scalar instruction in the reorder buffer unit; when the vector instruction successfully commits, deleting the entry corresponding to the vector instruction in the reorder buffer unit and deleting the entry corresponding to the vector instruction in the vector history table unit. Preferably, each of the vector instructions only occupies a single entry in the reorder buffer unit.

[0020] Preferably, when the vector instruction fails to commit, the physical registers mapped by the renamed vector instruction are modified back to the physical registers mapped before renaming according to the renaming information.

[0021] In a third aspect, the present application provides a computer device, which comprises a memory, a processor, and a register renaming program of a vector processor stored in the memory and executable in the processor. When the processor executes the register renaming program of the vector processor, the steps in the register renaming method of the vector processor as described in any one of the above embodiments are implemented.

[0022] In a fourth aspect, the present application provides a computer readable storage medium having stored thereon a register renaming program for a vector processor, the register renaming program for a vector processor being executed by a processor to implement the steps of the register renaming method for a vector processor as described in any of the above embodiments.

[0023] Compared with the prior art, the present application enables the vector instruction and the scalar instruction to be simultaneously renamed by the instruction fetch unit, the decoding unit, the renaming unit, the reordering buffer unit and the vector history stack unit, effectively reduces the blocking, optimizes the transmission bandwidth, and further improves the processor performance. Since the renaming information of the vector instruction is recorded by the vector history stack unit in microinstruction granularity, a vector instruction can be completely renamed in one clock cycle without splitting each vector instruction into microinstructions during the renaming for several clock cycles. Meanwhile, the single vector instruction only occupies a single entry in the reordering buffer unit, thereby avoiding the problem that the remaining space of the reordering buffer is insufficient due to the excessive occupation of the reordering buffer by the microinstructions split from the vector instruction, and the subsequent instructions cannot be received. BRIEF DESCRIPTION OF DRAWINGS

[0024] The above and other aspects of the present application will become more apparent and more readily appreciated from the following detailed description of the application, taken in conjunction with the accompanying drawings in which:

[0025] Figure 1 is a schematic diagram of the renaming process of the vector instruction in the related art;

[0026] Figure 2 is a schematic diagram of the structure of the register renaming system of the vector processor provided by the embodiment of the present application;

[0027] Figure 3 is a schematic diagram of the process of renaming the vector instruction of the register renaming system of the vector processor provided by the embodiment of the present application;

[0028] Figure 4 is a flowchart of the register renaming method of the vector processor provided by the embodiment of the present application;

[0029] Figure 5 is a schematic diagram of the structure of the computer device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0031] Embodiment one

[0032] The embodiment of the present application provides a register renaming system 100 of a vector processor, please refer to Figure 2 , Figure 2 The embodiment of the present application provides a register renaming system 100 of a vector processor, please refer to

[0033] The instruction fetching unit 1 is used for reading instructions from a memory, and sending the instructions to the decoding unit 2.

[0034] The decoding unit 2 is used for decoding the received instructions, and sending scalar instructions and vector instructions decoded out to the renaming unit 3 and the reorder buffer unit 4; specifically, the decoding unit 2 does not split the vector instructions into microinstructions when decoding the vector instructions.

[0035] The renaming unit 3 is used for renaming the destination registers corresponding to the decoded scalar instructions and the vector instructions into physical registers, and sending the renaming information corresponding to the scalar instructions to the reorder buffer unit 4 and sending the renaming information corresponding to the vector instructions to the vector history table unit 5; specifically, the renaming unit 3 can simultaneously perform the renaming operation on one vector instruction and multiple scalar instructions.

[0036] The reorder buffer unit 4 is used for storing the vector instructions, the scalar instructions and the renaming information of the scalar instructions.

[0037] The vector history table unit 5 is used for recording the renaming information of the vector instructions in microinstruction granularity; specifically, since the renaming information storage units of the vector instructions and the scalar instructions are different, the renaming processing of the scalar instructions and the vector instructions is decoupled to a certain extent, the blocking problem possibly caused by the prior scheme is avoided, and the overall performance is improved. The microinstruction granularity refers to that the vector instructions are split into a plurality of microinstructions in the vector register granularity and stored in the vector history table unit 5. For example, the destination registers of the vector instruction vadd include two continuous registers starting from the vector register 4 (v4), such as v4 and v5, so the renaming information corresponding to v4 and v5 is stored in two table entries of the vector history table unit 5 respectively.

[0038] In the embodiment of the present application, a single vector instruction only occupies a single entry in the reorder buffer unit 4. A vector instruction updates multiple entries in the vector register rename table and the vector history stack unit 5, but only occupies one entry in the reorder buffer unit 4, so that the reorder buffer unit 4 can also receive several scalar instructions at the same time, thereby improving the overall instruction issue bandwidth.

[0039] In the embodiment of the present application, when the renamed vector instruction cannot be committed, the vector history stack unit 5 is also used to modify the physical registers mapped by the renamed vector instruction back to the physical registers mapped before renaming according to the renaming information.

[0040] Specifically, reference can be made to Figure 3 , Figure 3 is a flowchart of the process of renaming a vector instruction of the register renaming system 100 of the vector processor provided in the embodiment of the present application. When a vector instruction is renamed by the register renaming system 100 of the vector processor, the process is completed within one clock cycle. Taking a vector addition (vadd) instruction as an example, the vector instruction writes the calculation result into two destination registers, and it is to be noted that other numbers of destination registers are also feasible, which are only used for illustration. The vector instruction writes the calculation result into the two consecutive registers v4 and v5 starting from the 4th vector register (v4). The free register list in the processor allocates a physical register for each destination register of the vector instruction, which is used to store the real calculation result of the vector instruction in the subsequent execution stage. At the same time, the mapping of v4 and v5 in the register rename table is also modified to the newly allocated physical registers P8 and P11 by the renaming unit 3.

[0041] The vector history stack unit 5 records the renaming information (i.e. the modification history of the vector register rename table) of the vector instruction, which is used for physical register release and state rollback. As shown in Figure 3 , the vector history stack unit 5 records that the mapping of the destination registers v4 and v5 before renaming of the vector instruction is modified, and records the previously mapped physical registers, i.e. physical registers P6 and P7. After the subsequent execution and commitment of the vector instruction, P6 and P7 will be released and returned to the free register list. If an abnormal condition (such as branch misprediction) occurs subsequently, causing the vector instruction to be unable to be committed, then according to the renaming information recorded in the vector history stack unit 5, the register rename table is restored to the original state before being modified by the vector instruction (i.e. P6 and P7).

[0042] Compared with the prior art, the application makes the vector instruction and the scalar instruction can be simultaneously renamed by the instruction fetching unit, the decoding unit, the renaming unit, the reordering buffer unit and the vector history stack unit, effectively reduces the blocking, optimizes the transmission bandwidth, and further improves the processor performance. Since the renaming information of the vector instruction is recorded by the vector history stack unit in microinstruction granularity, a vector instruction does not need to be split and renamed for multiple cycles. Meanwhile, the single vector instruction only occupies a single entry in the reordering buffer unit, thereby avoiding the problem that the reordering buffer is occupied by too many microinstructions split from the vector instruction, and the remaining space of the reordering buffer is insufficient to receive subsequent instructions.

[0043] Embodiment two

[0044] Please refer to Figure 4 The application further provides a register renaming method of a vector processor, which is based on the register renaming system 100 of the vector processor as described in the above embodiments, and comprises the following steps:

[0045] S1, reading an instruction from a memory by the instruction fetching unit 1, and sending the instruction to the decoding unit 2;

[0046] S2, decoding the received scalar instruction and vector instruction by the decoding unit 2, and sending the decoded scalar instruction and vector instruction to the renaming unit 3;

[0047] S3, renaming the destination registers corresponding to the decoded scalar instruction and vector instruction to physical registers by the renaming unit 3, and sending the renaming information corresponding to the scalar instruction to the reordering buffer unit 4 and the renaming information corresponding to the vector instruction to the vector history stack unit 5 and the reordering buffer unit 4;

[0048] S4, when the scalar instruction is successfully submitted, deleting the entry corresponding to the scalar instruction in the reordering buffer unit 4; and when the vector instruction is successfully submitted, deleting the entry corresponding to the vector instruction in the reordering buffer unit 4 and deleting the entry corresponding to the vector instruction in the vector history stack unit 5.

[0049] In the embodiment of the application, the single vector instruction only occupies a single entry in the reordering buffer unit 4. A vector instruction updates multiple entries in the vector register renaming table and the vector history stack unit 5, but only occupies one entry in the reordering buffer unit 4, so that the reordering buffer unit 4 can simultaneously receive another several scalar instructions, thereby improving the overall instruction transmission bandwidth.

[0050] In the embodiment of the present application, when the renamed vector instruction cannot be committed, the vector history table unit 5 is further configured to modify the physical register mapped by the renamed vector instruction back to the physical register mapped before the renaming according to the renaming information.

[0051] The register renaming method of the vector processor is based on the modules in the register renaming system 100 of the vector processor in the above embodiment, and can achieve the same technical effects. For details, refer to the description in the above embodiment, which will not be repeated here.

[0052] Embodiment Three

[0053] The embodiment of the present application also provides a computer device, please refer to Figure 5 , Figure 5 is a structural schematic diagram of the computer device provided by the embodiment of the present application, the computer device 200 comprises a memory 202, a processor 201 and a register renaming program of a vector processor stored in the memory 202 and capable of running on the processor 201.

[0054] The processor 201 invokes the register renaming program of a vector processor stored in the memory 202, and executes the steps in the register renaming method of a vector processor provided by the embodiment of the present application. Please refer to Figure 4 , which specifically comprises the following steps:

[0055] S1, reading an instruction from the memory by the instruction fetching unit 1, and sending the instruction to the decoding unit 2;

[0056] S2, decoding the received instruction by the decoding unit 2, and sending the scalar instruction and the vector instruction decoded out to the renaming unit 3;

[0057] S3, renaming the destination register corresponding to the decoded scalar instruction and the vector instruction to a physical register by the renaming unit 3, and sending the renaming information corresponding to the scalar instruction to the reordering buffer unit 4 and sending the renaming information corresponding to the vector instruction to the vector history table unit 5 and the reordering buffer unit 4;

[0058] S4, when the scalar instruction is successfully committed, deleting the entry corresponding to the scalar instruction in the reordering buffer unit 4; when the vector instruction is successfully committed, deleting the entry corresponding to the vector instruction in the reordering buffer unit 4 and deleting the entry corresponding to the vector instruction in the vector history table unit 5.

[0059] In the embodiment of the present application, the single vector instruction only occupies a single entry in the reorder buffer unit 4. One vector instruction updates multiple entries in the vector register renaming table and the vector history table unit 5, but only occupies one entry in the reorder buffer unit 4, so that the reorder buffer unit 4 can also receive several scalar instructions at the same time, thereby improving the overall instruction transmission bandwidth.

[0060] In the embodiment of the present application, when the renamed vector instruction cannot be submitted, the vector history table unit 5 is further configured to modify the physical register mapped by the renamed vector instruction back to the physical register mapped before the renaming according to the renaming information.

[0061] The computer device 200 provided by the embodiment of the present application can implement the steps in the register renaming method of the vector processor in the above-described embodiment, and can achieve the same technical effects. For details, refer to the description in the above-described embodiment, which will not be described here again.

[0062] Embodiment Four

[0063] The embodiment of the present application further provides a computer readable storage medium, which stores a register renaming program of a vector processor. The register renaming program of the vector processor, when executed by a processor, implements each process and step in the register renaming method of the vector processor provided by the embodiment of the present application, and can achieve the same technical effects. To avoid repetition, details will not be described here again.

[0064] Those skilled in the art can understand that all or part of the processes in the above-described embodiments can be completed by a computer program instructing related hardware. The program can be stored in a computer readable storage medium. When the program is executed, the processes of the above-described embodiments can be included. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM).

[0065] It should be noted that, in this document, the term "comprising" or "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0066] Those skilled in the art can clearly understand the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, also can be through hardware, but many cases the former is the better embodiment. Based on such understanding, the technical solutions of the present application essentially or say the part of contribution to the prior art can be embodied in the form of software product, the computer software product is stored in a storage medium (such as ROM / RAM, disk, optical disc), including several instructions to make a terminal (may be mobile phone, computer, server, air conditioner, or network equipment, etc.) executes the method described in various embodiments of the present application.

[0067] The above describes the embodiments of the present application in conjunction with the drawings, the disclosed is only the preferred embodiment of the present application, but the present application is not limited to the above-mentioned specific embodiments, the above-mentioned specific embodiments are only illustrative, but not limited, those skilled in the art can make a lot of forms under the inspiration of the present application, such as equivalent changes, without departing from the scope of the present application and the claims, all belong to the protection of the present application.

Claims

1. A register renaming system for a vector processor, characterized in that, It includes an instruction fetch unit, a decoding unit, a renaming unit, a reordering buffer unit, and a vector history heap unit; The instruction fetching unit is used to read instructions from the memory and send the instructions to the decoding unit; The decoding unit is used to decode the received instructions and send the decoded scalar instructions and vector instructions to the renaming unit and the reordering buffer unit. The renaming unit is used to rename the destination registers corresponding to the decoded scalar instructions and vector instructions to physical registers, and to send the renaming information corresponding to the scalar instructions to the reordering buffer unit and the renaming information corresponding to the vector instructions to the vector history heap unit; the renaming unit performs renaming operations on one vector instruction and multiple scalar instructions at the same time. The reordering buffer unit is used to store the vector instruction, the scalar instruction, and the renaming information of the scalar instruction; The vector history stack unit is used to record the renaming information of the vector instruction at the microinstruction granularity; the microinstruction granularity refers to splitting the vector instruction into several microinstructions and storing them in the vector history stack unit at the granularity of the vector register. A single vector instruction occupies only a single entry in the reordering buffer unit; When the renamed vector instruction cannot be submitted, the vector history stack unit is also used to modify the physical register mapped by the renamed vector instruction back to the physical register mapped before the renaming, based on the renaming information.

2. A method for renaming registers in a vector processor, characterized in that, The register renaming method is based on the register renaming system of the vector processor as described in claim 1, and the register renaming method includes the following steps: S1. Read the instruction from the memory through the instruction fetch unit and send the instruction to the decoding unit; S2. The received instruction is decoded by the decoding unit, and the decoded scalar instruction and vector instruction are sent to the renaming unit. S3. The destination registers corresponding to the decoded scalar instructions and vector instructions are renamed to physical registers by the renaming unit, and the renaming information corresponding to the scalar instructions is sent to the reordering buffer unit and the renaming information corresponding to the vector instructions is sent to the vector history heap unit and the reordering buffer unit. S4. When the scalar instruction is successfully submitted, the entry corresponding to the scalar instruction in the reordering buffer unit is deleted; when the vector instruction is successfully submitted, the entry corresponding to the vector instruction in the reordering buffer unit and the entry corresponding to the vector instruction in the vector history heap unit are also deleted.

3. A computer device, characterized in that, include: The system includes a memory, a processor, and a register renaming program for a vector processor stored in the memory and executable on the processor. When the processor executes the register renaming program for the vector processor, it implements the steps in the register renaming method for a vector processor as described in claim 2.

4. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a register renaming program for the vector processor, which, when executed by the processor, implements the steps of the register renaming method for the vector processor as described in claim 2.

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