Data prefetching method, device and processor

Abstract

This application provides a data prefetching method, apparatus, and processor. The method includes: acquiring a target memory access stream, which includes multiple executed memory access instructions, each carrying cache address identification information; using the cache address identification information carried by each memory access instruction to read the virtual address corresponding to each memory access instruction from the target cache region; determining the address access pattern based on the virtual address corresponding to each memory access instruction; and initiating data prefetching based on the address access pattern. This method enables the prefetcher to determine the address access pattern based on consecutive virtual addresses, reducing the difficulty of monitoring address access patterns and improving the accuracy of data prefetching.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a data prefetching method, apparatus and processor. Background Technology

[0002] A prefetcher is a hardware or software mechanism in computer architecture that performs prefetching training by monitoring memory access patterns and cache hit information. This allows it to predict data or instructions that a program might access in the future and load them into the internal cache in advance, thereby reducing performance latency caused by the processor waiting for data. Currently, prefetching training and data prefetching in prefetchers have shortcomings. Summary of the Invention

[0003] In view of this, embodiments of this application provide a data prefetching method, apparatus, and processor to at least partially solve the above-mentioned problems.

[0004] According to a first aspect of the embodiments of this application, a data prefetching method is provided, the method being applied to a data prefetching apparatus, the data prefetching apparatus including a prefetcher and a target cache region, the method comprising:

[0005] The prefetcher obtains the target memory access stream, which includes multiple executed memory access instructions, each of which carries cache address identification information.

[0006] The prefetcher uses the cache address identification information carried by each memory access instruction to read the virtual address corresponding to each memory access instruction from the target cache area;

[0007] The prefetcher determines the memory access pattern based on the virtual address corresponding to each memory access instruction;

[0008] The prefetcher initiates data prefetching based on the address access patterns.

[0009] According to a second aspect of the embodiments of this application, a data prefetching apparatus is provided, which can be used to perform the method as described in the first aspect.

[0010] According to a third aspect of the embodiments of this application, a processor is provided, including: a data prefetching device as described in the second aspect.

[0011] According to a fourth aspect of the embodiments of this application, a computer storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect.

[0012] Through the technical solution of the embodiments of this application, the prefetcher can determine the address access pattern based on continuous virtual addresses, which reduces the difficulty of the prefetcher monitoring the address access pattern and helps to improve the accuracy of subsequent data prefetching. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0014] Figure 1 This is a schematic diagram of a data prefetching device in related technologies;

[0015] Figure 2 A schematic diagram of the data prefetching device provided in the embodiments of this application;

[0016] Figure 3 A schematic flowchart of a data prefetching method provided in an embodiment of this application;

[0017] Figure 4 Another flowchart illustrating the data prefetching method provided in this application embodiment;

[0018] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0020] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0021] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0022] It should also be noted that the terms "first, second, and third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, and third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0023] Furthermore, in the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0024] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies of the embodiments of this application are described below. The following relevant technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and they all fall within the protection scope of the embodiments of this application.

[0025] A prefetcher is a hardware or software mechanism in computer architecture that performs prefetch training by monitoring memory access patterns and cache hit information. This allows it to predict the data or instructions that a program may access in the future and load them from slow storage (such as main memory) into the internal cache in advance, thereby reducing the performance latency caused by the processor waiting for data.

[0026] In the field of data storage, data storage addresses are divided into virtual addresses and physical addresses. Virtual addresses are contiguous, while physical addresses are discontinuous. The operating system's memory management maps contiguous virtual address spaces to discontinuous physical address spaces and accesses internal caches and external storage through physical addresses. Therefore, memory access streams and instruction cache queues are usually configured with only physical addresses and not virtual addresses.

[0027] For the reasons mentioned above, prefetchers currently typically monitor memory access patterns based on the physical addresses in the memory access stream to achieve prefetch training and data prefetching. However, due to the discontinuous nature of physical addresses, this increases the difficulty for the prefetcher to determine memory access patterns, reducing the efficiency and accuracy of prefetch training and data prefetching.

[0028] To facilitate understanding, the following will explain the functional implementation and shortcomings of prefetchers in related technologies, with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic diagram of a data prefetching device in related technologies. For example... Figure 1As shown, the data prefetching device may include an issue queue, an address generation unit (AGU), a data translation lookaside buffer (DTLB), an instruction cache queue (including a first instruction cache queue and a second instruction cache queue), a cache, miss-status handling registers (MSHR), and a prefetcher.

[0030] To facilitate understanding of how the data prefetching device works, the functions of each functional unit in the data prefetching device will be introduced and explained first.

[0031] The instruction issuance queue can be used to store decoded but not yet executed memory access instructions, dynamically selecting executable memory access instructions based on operand readiness status and hardware resource availability. In this embodiment, memory access instructions may include data read instructions (load instructions) and data write instructions (store instructions). Load instructions load data from memory or cache into processor registers, while store instructions store data from processor registers into memory or cache. The address generation unit can be used to calculate the effective address for memory access to support the execution of load and store instructions. The data translation back buffer can be used to accelerate the translation from virtual address to physical address, avoiding page table lookups for each memory access and thus reducing address translation overhead. The instruction cache queue may include a first instruction cache queue and a second instruction cache queue. The first instruction cache queue can store load instructions waiting to be executed and their corresponding physical addresses, while the second instruction cache queue can store store store store store store store and their corresponding physical addresses. The cache miss request handling register can be used to manage cache miss requests.

[0032] The following is combined with, for example Figure 1 The data prefetching device with the structure shown above, and the functions of each functional unit in the device, are as follows: Figure 1 The functional implementation of the data prefetching device with the structure shown will be explained.

[0033] like Figure 1As shown, the instruction issue queue can be used to sequentially send each memory access instruction to the address generation unit. The address generation unit can be used to calculate the virtual address corresponding to each memory access instruction according to the addressing mode. Then, the data translation backup buffer can be used to translate the virtual address corresponding to each memory access instruction into the physical address corresponding to each memory access instruction. Finally, each memory access instruction and its corresponding physical address can be sequentially stored in the instruction cache queue to await execution. Specifically, each load instruction and its corresponding physical address can be sequentially stored in the first instruction cache queue, and each store instruction and its corresponding physical address can be sequentially stored in the second instruction cache queue.

[0034] Once the execution conditions for memory access instructions are met, memory access operations can be performed on the cache memory sequentially based on each memory access instruction and its carried physical address. Furthermore, the prefetcher can retrieve the physical addresses of each memory access instruction from the instruction cache queue, and based on the physical addresses of each executed memory access instruction, as well as the hit information (Hit information) or miss information (Miss information) corresponding to each executed memory access instruction, it obtains address access patterns for prefetch training, thereby predicting the processor's memory access addresses and performing data prefetching. Specifically, the Hit information can be used to describe that the requested data was successfully found in the current cache level, without needing to access lower-level storage (such as main memory or lower-level cache). The Miss information can be used to describe that the required data is not in the current cache level, requiring a request to lower-level storage (such as main memory or lower-level cache).

[0035] Specifically, after the prefetcher predicts the memory access address, it can send a miss request to the lower-level storage in advance based on the predicted memory access address, so that the data that may be accessed in the future can be loaded from the lower-level storage level into the current cache.

[0036] As can be seen, in the above process, the memory access instruction only carries the physical address, and the instruction cache queue also stores the physical address. The prefetcher performs prefetch training and data prefetching based on the physical addresses of each memory access instruction obtained from the instruction cache queue. Since the physical address has a non-contiguous characteristic, it increases the difficulty for the prefetcher to monitor the address memory access pattern and affects the accuracy of data prefetching.

[0037] This application is submitted to address the aforementioned issues.

[0038] In one embodiment of this application, Figure 1Based on the data prefetching device with the structure shown, the physical address and virtual address corresponding to the memory access instruction can be stored simultaneously in the instruction cache queue. Specifically, each load instruction and its corresponding physical address and virtual address can be stored simultaneously in the first instruction cache queue, and each store instruction and its corresponding physical address and virtual address can be stored simultaneously in the second instruction cache queue.

[0039] On the one hand, memory access operations can be performed on the cache memory based on the physical address corresponding to the memory access instruction. On the other hand, the prefetcher can obtain the virtual address corresponding to each memory access instruction in the memory access stream from the instruction cache queue, determine the address access pattern based on the virtual address, predict the processor's memory access address based on the address access pattern, and perform data prefetching.

[0040] The technical solutions described above can reduce the difficulty of the prefetcher monitoring address access patterns, which is beneficial to improving the accuracy of subsequent data prefetching.

[0041] However, the above technical solution requires adding virtual addresses to each instruction cache queue, which will result in a significant consumption of cache resources.

[0042] To address the aforementioned problems, in another embodiment of this application, in Figure 1 Based on the data prefetching device with the structure shown, a target cache region can be added. This target cache region differs from the instruction cache queue described above; it can be specifically used to store the virtual addresses corresponding to memory access instructions. Then, the prefetcher can obtain the virtual addresses corresponding to each memory access instruction in the memory access stream based on the target cache region, determine the address access pattern based on the virtual addresses, thereby predicting the processor's memory access address and performing data prefetching.

[0043] Through the above-described technical solution of this application, on the one hand, the prefetcher can determine the address access pattern based on consecutive virtual addresses, reducing the difficulty of the prefetcher monitoring the address access pattern and improving the accuracy of subsequent data prefetching. On the other hand, by adding the aforementioned target cache area to store virtual addresses, compared with the implementation method of storing virtual addresses in each instruction cache queue, the technical solution of this application embodiment can reduce the consumption of cache resources.

[0044] The specific implementation of the embodiments of this application will be described below with reference to the accompanying drawings.

[0045] Figure 2 This is a schematic diagram of a data prefetching device provided in an embodiment of this application. Figure 1 Compared to the data prefetching device with the structure shown, in this embodiment, the data prefetching device can add a target cache area for storing the virtual addresses of each memory access instruction. The following refers to... Figure 2 The data prefetching apparatus with the structure shown will be used to explain the implementation process of the data prefetching method provided in the embodiments of this application.

[0046] Figure 3 This is a schematic flowchart of a data prefetching method provided in an embodiment of this application. (Reference) Figure 3 The data prefetching method provided in this application embodiment may include the following steps:

[0047] Step 101: The address generation unit stores the virtual addresses corresponding to each memory access instruction into the target cache area.

[0048] Step 102: The address generation unit generates cache address identification information corresponding to each memory access instruction based on the storage location of the virtual address corresponding to each memory access instruction in the target cache area.

[0049] In this embodiment, the address generation unit can receive memory access instructions sent by the instruction issuance queue and calculate the virtual address corresponding to each memory access instruction according to the addressing mode. Then, the address generation unit can access the target cache area and store the virtual addresses corresponding to each memory access instruction into the target cache area. After storing the virtual addresses corresponding to each memory access instruction into the target cache area, the address generation unit can also generate cache address identification information corresponding to each memory access instruction. The cache address identification information can be used to identify the storage location of the virtual address corresponding to the memory access instruction in the target cache area. In this way, each memory access instruction can carry a cache address identification information.

[0050] Furthermore, the address generation unit can be used to send each memory access instruction carrying the aforementioned cache address identification information and its corresponding virtual address to the data translation backup buffer. The data translation backup buffer can be used to convert the virtual address corresponding to each memory access instruction into the physical address corresponding to each memory access instruction, and then sequentially store each memory access instruction, its corresponding physical address, and the cache address identification information into the instruction cache queue for execution. It should be understood that the amount of data in the cache address identification information corresponding to the virtual address is smaller than the virtual address itself.

[0051] Step 103: The prefetcher obtains the target memory access stream, which includes multiple executed memory access instructions, each of which carries cache address identification information.

[0052] In this embodiment, once the memory access instructions in the instruction cache queue meet the execution conditions, memory access operations can be performed on the cache memory sequentially based on each memory access instruction and its carried physical address. Furthermore, after each memory access instruction has been executed and corresponding hit or miss information has been generated, the prefetcher can obtain the target memory access stream from the instruction cache queue. The target memory access stream may include multiple executed memory access instructions, each carrying cache address identification information.

[0053] Step 104: The prefetcher uses the cache address identification information carried by each memory access instruction to read the virtual address corresponding to each memory access instruction from the target cache area.

[0054] Step 105: The prefetcher determines the memory access pattern based on the virtual address corresponding to each memory access instruction.

[0055] Step 106: The prefetcher initiates data prefetching based on address access patterns.

[0056] The prefetcher can query the corresponding storage location in the target cache region based on the cache address identifier information carried by each memory access instruction, thereby obtaining the virtual address corresponding to each memory access instruction. Furthermore, based on the virtual address corresponding to each memory access instruction, as well as the hit or miss information corresponding to each memory access instruction, the prefetcher can learn the address access pattern. Then, based on the address access pattern, the prefetcher can predict the memory access address and initiate data prefetching based on the predicted memory access address.

[0057] In the above technical solution, an additional target cache area can be set up to store the virtual addresses corresponding to each memory access instruction. Then, the prefetcher can query the virtual addresses corresponding to each memory access instruction from the target cache area and perform prefetch training and data prefetching based on the virtual addresses. This helps to improve the accuracy of data prefetching. Furthermore, storing virtual addresses in a dedicated cache area reduces the consumption of cache resources compared to storing virtual addresses in each instruction cache queue.

[0058] Figure 4 This is another schematic flowchart illustrating the data prefetching method provided in an embodiment of this application. (See reference...) Figure 4 The data prefetching method provided in this application embodiment may include the following steps:

[0059] Step 201: The address generation unit stores the first part of the virtual address corresponding to each memory access instruction into the target cache area.

[0060] Step 202: The address generation unit generates cache address identification information corresponding to each memory access instruction based on the storage location of the first part of the virtual address corresponding to each memory access instruction within the target cache area.

[0061] In this embodiment, the address generation unit can be used to receive various memory access instructions sent by the instruction issuance queue, and calculate the virtual address corresponding to each memory access instruction according to the addressing mode. Furthermore, the address generation unit can be used to access the target cache area and store the first part of the virtual address corresponding to each memory access instruction into the target cache area. The first part of the virtual address can be, for example, any part of the virtual address.

[0062] After the address generation unit stores the first part of the virtual address corresponding to each memory access instruction into the target cache area, it can also generate cache address identification information corresponding to each memory access instruction. The cache address identification information can be used to identify the storage location of the first part of the virtual address corresponding to the memory access instruction in the target cache area. In this way, each memory access instruction can carry a cache address identification information.

[0063] Furthermore, the address generation unit can send each memory access instruction carrying the aforementioned cache address identifier information and its corresponding virtual address to the data translation backup buffer. The data translation backup buffer can convert the virtual address corresponding to each memory access instruction to the physical address corresponding to each memory access instruction, and sequentially store each memory access instruction, its corresponding physical address, and the cache address identifier information into the instruction cache queue. Simultaneously, the data translation backup buffer can also store the second part of the virtual address corresponding to each memory access instruction into the instruction cache queue, awaiting execution. The second part of the virtual address is the portion other than the first part.

[0064] Step 203: The prefetcher obtains the target memory access stream, which includes multiple executed memory access instructions, each of which carries cache address identification information.

[0065] In this embodiment, once the memory access instructions in the instruction cache queue meet the execution conditions, memory access operations can be performed on the cache memory sequentially based on each memory access instruction and its carried physical address. Furthermore, after each memory access instruction has been executed and corresponding hit or miss information has been generated, the prefetcher can obtain the target memory access stream from the instruction cache queue. The target memory access stream may include multiple executed memory access instructions, each carrying cache address identification information and a second part of the virtual address.

[0066] Step 204: The prefetcher uses the cache address identification information carried by each memory access instruction to read the first part of the virtual address corresponding to each memory access instruction from the target cache area.

[0067] Step 205: The prefetcher determines the virtual address corresponding to each memory access instruction based on the first part and the second part of the virtual address corresponding to each memory access instruction.

[0068] Step 206: The prefetcher determines the memory access pattern based on the virtual address corresponding to each memory access instruction.

[0069] Step 207: The prefetcher initiates data prefetching based on address access patterns.

[0070] The prefetcher can query the corresponding storage location in the target cache region based on the cache address identifier information carried by each memory access instruction, thereby obtaining the first part of the virtual address corresponding to each memory access instruction. Then, based on the first and second parts of the virtual address corresponding to each memory access instruction, the prefetcher can determine the complete virtual address. Furthermore, based on the complete virtual address and the hit or miss information corresponding to each memory access instruction, the prefetcher learns the address access pattern. Finally, based on the address access pattern, the prefetcher can predict the memory access address and initiate data prefetching based on the predicted memory access address.

[0071] In the above technical solution, the target cache region can be used to store only a portion of the virtual address, while the other portion of the virtual address is stored by the instruction cache queue. The prefetcher can obtain different portions of the virtual address from the target cache region and the instruction cache queue respectively to generate a complete virtual address for prefetch training and data prefetching. The technical solution of this application embodiment can also improve the accuracy of prefetch training and data prefetching.

[0072] In another embodiment of this application, only the high-order part of the virtual address corresponding to each memory access instruction may be stored in the target cache area, without storing the low-order part of the virtual address.

[0073] Specifically, under paging, the lower-order bits (page offset) of the virtual and physical addresses are used to locate the data's position within the page; their values ​​are the same and no conversion is needed. However, the higher-order bits are different. The higher-order bits of the virtual address (virtual page number) need to be converted to the higher-order bits of the physical address (physical page frame number) through the page table.

[0074] Therefore, in this embodiment of the application, only the high-order part of the virtual address corresponding to each memory access instruction can be stored in the target cache area. Then, the prefetcher can obtain the high-order part of the virtual address corresponding to each memory access instruction from the target cache area, and determine the low-order part of each virtual address according to the physical address of each memory access instruction stored in the instruction cache queue, thereby determining the complete virtual address, and completing the subsequent prefetch training and data prefetching based on the complete virtual address.

[0075] By implementing the above methods, the consumption of cache resources can be further reduced while maintaining functionality.

[0076] In another embodiment of this application, such as Figure 2 As shown, the data prefetching device may also include a translation lookaside buffer (TLB).

[0077] Specifically, since the prefetcher in the above embodiments obtains virtual addresses, while data access operations require physical addresses, the prefetcher can also be connected to the aforementioned TLB to complete the virtual address to physical address translation, and then use the physical address to access the cache memory. Alternatively, the data prefetching device may not include the aforementioned TLB; the prefetcher can multiplex the DTLB to complete the virtual address to physical address translation.

[0078] In another embodiment of this application, the prefetcher may also use both virtual addresses and physical addresses for prefetch training.

[0079] Specifically, in real-world scenarios, physical addresses within the same physical page are contiguous. Therefore, in one possible implementation, when the data to be accessed by various memory access instructions resides on different physical pages, the prefetcher can determine the address access pattern based on the virtual addresses corresponding to each memory access instruction. Conversely, when the data to be accessed by various memory access instructions resides on the same physical page, the prefetcher can determine the address access pattern based on the physical addresses corresponding to each memory access instruction.

[0080] Figure 5 A schematic diagram of an electronic device according to an embodiment of this application is shown. The electronic device may be configured with a data prefetching device provided in the embodiment of this application. The data prefetching device can be used to execute the data prefetching method provided in the embodiment of this application. The specific embodiments of this application do not limit the specific implementation of the electronic device.

[0081] like Figure 5 As shown, the electronic device may include: a processor 502, a communications interface 504, a memory 506, and a communications bus 508.

[0082] The processor 502, communication interface 504, and memory 506 communicate with each other via communication bus 508. Communication interface 504 is used to communicate with other electronic devices or servers. The processor 502 may include a data prefetching device, which can be used to execute program 510, specifically performing the relevant steps in the above-described data prefetching method embodiment.

[0083] Specifically, program 510 may include program code that includes computer operation instructions.

[0084] Processor 502 may be a CPU, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The smart device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0085] Memory 506 is used to store program 510. Memory 506 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0086] Specifically, program 510 can be used to cause processor 502 to perform the following operations: In an optional implementation, program 510 is further used to cause processor 502 to perform the following operations. The specific implementation of each step in program 510 can be found in the corresponding steps and system descriptions in the above-described data prefetching method embodiments, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0087] This application also provides a computer program product, including computer instructions that instruct a computing device to perform an operation corresponding to any of the data prefetching methods in the above-described plurality of method embodiments. It should be noted that, depending on implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0088] This application also provides a computer-readable storage medium in which the methods described in this application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the data prefetching methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the data prefetching methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the data prefetching methods shown herein.

[0089] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0090] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0091] Furthermore, it should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Moreover, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0092] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0093] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0094] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0095] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0096] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A data prefetching method, characterized in that, The method is applied to a data prefetching device, the data prefetching device including a prefetcher and a target buffer region, the method comprising: The prefetcher acquires the target memory access stream, which includes multiple executed memory access instructions. Each memory access instruction carries cache address identification information. The cache address identification information is used to identify the storage location of the virtual address corresponding to the memory access instruction in the target cache area. The prefetcher uses the cache address identification information carried by each memory access instruction to read the virtual address corresponding to each memory access instruction from the target cache area; The prefetcher determines the memory access pattern based on the virtual address corresponding to each memory access instruction; The prefetcher initiates data prefetching based on the address access patterns.

2. The method according to claim 1, characterized in that, The data prefetching device further includes an address generation unit; before the prefetcher acquires the target memory access stream, the method further includes: The address generation unit stores the virtual addresses corresponding to each memory access instruction into the target cache area respectively; The address generation unit generates cache address identification information corresponding to each memory access instruction based on the storage location of the virtual address corresponding to each memory access instruction within the target cache area.

3. The method according to claim 2, characterized in that, The address generation unit stores the virtual addresses corresponding to each memory access instruction into the target cache area, including: The address generation unit stores the first part of the virtual address corresponding to each memory access instruction into the target cache area.

4. The method according to claim 3, characterized in that, The prefetcher uses the cache address identification information carried by each memory access instruction to read the virtual address corresponding to each memory access instruction from the target cache region, including: The prefetcher uses the cache address identification information carried by each memory access instruction to read the first part of the virtual address corresponding to each memory access instruction from the target cache region.

5. The method according to claim 4, characterized in that, The first part is the high-order part of the virtual address.

6. The method according to claim 5, characterized in that, Each memory access instruction also carries a physical address; before the prefetcher determines the address access pattern based on the virtual address corresponding to each memory access instruction, the method further includes: The prefetcher determines the virtual address corresponding to each memory access instruction based on the high-order part of the virtual address corresponding to each memory access instruction and the physical address.

7. The method according to claim 4, characterized in that, The first part can be any part of the virtual address.

8. The method according to claim 7, characterized in that, The data prefetching device further includes an instruction cache queue; the method further includes: When each memory access instruction is in a pending execution state, each memory access instruction and the second part of the virtual address corresponding to each memory access instruction are sequentially stored in the instruction cache queue, wherein the second part is the part of the virtual address other than the first part.

9. The method according to claim 8, characterized in that, Before the prefetcher determines the address access pattern based on the virtual addresses corresponding to each memory access instruction, the method further includes: The prefetcher obtains the second part of the virtual address corresponding to each memory access instruction based on the instruction cache queue; The prefetcher determines the virtual address corresponding to each memory access instruction based on the second part and the first part of the virtual address.

10. The method according to claim 1, characterized in that, The prefetcher determines the memory access pattern based on the virtual address corresponding to each memory access instruction, including: When the memory access data to be accessed by each memory access instruction is located in different physical pages, the prefetcher determines the address access pattern based on the virtual address corresponding to each memory access instruction. When the memory access data to be accessed by each memory access instruction is located in the same physical page, the prefetcher determines the address access pattern based on the physical address corresponding to each memory access instruction.

11. A data prefetching device, characterized in that, include: Prefetcher and target cache area; The target cache area is used to store the virtual addresses corresponding to each memory access instruction in the target memory access stream; The prefetcher is used to acquire a target memory access stream, which includes multiple executed memory access instructions, each of which carries cache address identification information; the cache address identification information is used to identify the storage location of the virtual address corresponding to the memory access instruction in the target cache area. The prefetcher is also used to read the virtual address corresponding to each memory access instruction from the target cache area using the cache address identification information carried by each memory access instruction; The prefetcher is also used to determine the address access pattern based on the virtual address corresponding to each memory access instruction; The prefetcher is also used to initiate data prefetching based on the address access patterns.

12. A processor, characterized in that, include: The data prefetching apparatus as described in claim 11.

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