A method for data transfer within the Pxie platform

Abstract

This invention discloses a data transmission method for use within a Pxie platform. The method includes: obtaining unique SPI addresses corresponding to all registers and all SPI devices; parsing a first protocol used between the main FPGA and the secondary FPGA to obtain multiple AXI addresses, and constructing an address mapping table after selecting one AXI address for each SPI address; constructing a control code based on the address mapping table and the data to be transmitted; and sending the control code through the main FPGA to the corresponding secondary FPGA, so that the secondary FPGA sends the data to be transmitted to the target register or target SPI device. This method enables more accurate and clear data transmission within the Pxie platform and avoids excessively long host waiting times or even system crashes when data transmission errors occur.

Description

Technical Field

[0001] This invention belongs to the field of computer technology, specifically relating to an internal data transmission method for the Pxie platform. Background Technology

[0002] The PXIE (PCI Extensions for Instrumentation Express) platform is a standardized instrumentation platform based on PCIe (Peripheral Component Interconnect Express) extensions. Its architecture typically consists of a host, a main FPGA, and multiple secondary FPGAs. The secondary FPGAs are connected to the main FPGA, and the main FPGA is connected to the host. Each secondary FPGA has multiple internal registers and also connects to multiple SPI (Serial Peripheral Interface) devices. Currently, data or signal transmission within the PXIE platform requires the use of IP provided by the FPGA manufacturer for protocol conversion. For example, in a Xilinx FPGA design, the control architecture within the main FPGA is implemented using Xilinx's PCIe-AXI Bridge + AXI-SPI Bridge IPs. A custom protocol, such as SPI, is then used to determine the control of the remaining registers in the secondary FPGAs and the peripheral SPI devices. However, this approach now achieves a one-to-one correspondence between PCIe and AXI addresses, meaning that AXI addresses can be mapped to the host's memory via corresponding PCIe addresses. However, the IP address between AXI and a group of SPIs is fixed, meaning the secondary FPGA (a group of SPIs) can only be mapped as a whole into the host memory. All registers in the secondary FPGA and the external SPI devices share a single PCIe address, which can only be mapped to the same address in the host memory—the address of the secondary FPGA. Different devices are distinguished by the content transmitted via the protocol. This means the host software cannot directly see all the lowest-level registers and devices in memory, making control inconvenient and unclear.

[0003] In existing control schemes, handshakes are required in the secondary FPGA to ensure that each transmission is successful, which results in excessively long transmission times and causes the host to wait for too long or freeze when transmission errors occur.

[0004] Therefore, how to perform data transmission more accurately and clearly within the Pxie platform, and avoid excessive waiting time or even freezing of the host when data transmission errors occur, is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to solve the technical problems in the prior art where data transmission within the Pxie platform is not accurate and clear enough, and the host waits for too long or even freezes when data transmission errors occur.

[0006] To achieve the above technical objectives, in one aspect, the present invention provides a data transmission method for an internal Pxie platform. The Pxie platform includes at least a host, a main FPGA, and multiple secondary FPGAs, all of which are connected to the main FPGA. Each secondary FPGA includes multiple registers and is also connected to multiple SPI devices. The method includes:

[0007] Obtain all registers and the unique SPI address corresponding to all SPI devices;

[0008] The first protocol used between the main FPGA and the secondary FPGA is parsed to obtain multiple AXI addresses, and an address mapping table is constructed after selecting an AXI address for each SPI address.

[0009] A control code is constructed based on the address mapping table and the data to be transmitted;

[0010] The control code is sent from the main FPGA to the corresponding secondary FPGA, so that the secondary FPGA sends the data to be transmitted to the target register or the target SPI device.

[0011] Furthermore, the step of sending the control code to the corresponding secondary FPGA via the main FPGA specifically includes:

[0012] The control code is read through the first state machine and written into the first first-in-first-out queue in the main FPGA through the first state machine.

[0013] The first FIFO queue is detected by the second state machine. When the second state machine detects a control code in the first FIFO queue, it parses the control codes in the first FIFO queue in sequence and sends them to the corresponding secondary FPGA via the SPI protocol.

[0014] Furthermore, the maximum capacity of the first first-in-first-out queue is greater than the number of control codes required for a complete control operation.

[0015] Furthermore, the secondary FPGA sends the data to be transmitted to the target register or the target SPI device, specifically including:

[0016] When the secondary FPGA receives the control code, it decodes the control code through the SPI routing control component to obtain the target SPI address;

[0017] The secondary FPGA sends the data to be transmitted to the target register or the target SPI device according to the target SPI address.

[0018] Furthermore, when the secondary FPGA sends the data to be transmitted to the target register or the target SPI device according to the target SPI address, the target SPI address needs to be removed so that the secondary FPGA only sends the data to be transmitted to the target register or the target SPI device.

[0019] Furthermore, the data to be transmitted specifically refers to data to be written or data to be read.

[0020] This invention provides a data transmission method for use within a Pxie platform. Compared with existing technologies, this method includes: obtaining the unique SPI addresses corresponding to all registers and all SPI devices; parsing the first protocol used between the main FPGA and the secondary FPGA to obtain multiple AXI addresses, and constructing an address mapping table after selecting an AXI address for each SPI address; constructing a control code based on the address mapping table and the data to be transmitted; and sending the control code through the main FPGA to the corresponding secondary FPGA, so that the secondary FPGA sends the data to be transmitted to the target register or target SPI device. This method enables more accurate and clear data transmission within the Pxie platform and avoids excessively long host waiting times or even system crashes when data transmission errors occur. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 The diagram shown is a flowchart illustrating a data transmission method for the Pxie platform provided in an embodiment of this specification.

[0023] Figure 2 The diagram shown is a data transmission schematic of a specific application scenario using existing technical solutions in the embodiments of this specification;

[0024] Figure 3 The diagram shown is a data transmission schematic of the technical solution of this application used in a specific application scenario in the embodiments of this specification. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] like Figure 1 The diagram illustrates a data transmission method for the Pxie platform provided in an embodiment of this specification. While this specification provides the method operation steps or device structure shown in the embodiments or accompanying drawings, based on conventional methods or without creative effort, the method or device may include more or fewer operation steps or module units after partial merging. In steps or structures where there is no logically necessary causal relationship, the execution order of these steps or the module structure of the device are not limited to the execution order or module structure shown in the embodiments or accompanying drawings. When the method or module structure is applied in actual devices, servers, or terminal products, it can be executed sequentially or in parallel according to the method or module structure shown in the embodiments or accompanying drawings (e.g., in a parallel processor or multi-threaded processing environment, or even in a distributed processing or server cluster implementation environment).

[0027] The data transmission method for the Pxie platform provided in the embodiments of this specification can be applied to various systems that include the Pxie platform, such as... Figure 1 As shown, the method specifically includes the following steps:

[0028] Step S101: Obtain the unique SPI address corresponding to all registers and all SPI devices.

[0029] Specifically, in the SPI protocol, each lowest-level register and SPI device has a corresponding SPI address, which is appended to the beginning of an SPI data transmission, so that the unique SPI address corresponding to all registers and all SPI devices can be obtained.

[0030] Step S102: Parse the first protocol used between the main FPGA and the secondary FPGA to obtain multiple AXI addresses, and construct an address mapping table after selecting an AXI address for each SPI address.

[0031] Specifically, the protocol used between the host and the main FPGA is the PE protocol, and the primary protocol used between the main FPGA and the secondary FPGA is the AXI protocol. It should be noted that the solution in this application is not limited to the AXI protocol. For other usable protocols, the corresponding protocol is parsed to obtain multiple corresponding addresses, which are then mapped to the registers and SPI device addresses. In the current embodiment, the AXI protocol is parsed first, and then the corresponding SPI address is mapped according to the parsed AXI address. This forms a PCi-AXI-SPI address mapping relationship, which can map all register addresses and SPI device addresses to the host memory, that is, the address mapping table is stored in the host memory.

[0032] Step S103: Construct a control code based on the address mapping table and the data to be transmitted.

[0033] Specifically, in order for the data to be transmitted, i.e., AXI data, to successfully reach the target register or target SPI device, it is necessary to construct a control code by mapping the target SPI address of the target register or target SPI device to the data to be transmitted, so that the data to be transmitted can accurately reach the target register or target SPI device.

[0034] Step S104: Send the control code to the corresponding secondary FPGA through the main FPGA, so that the secondary FPGA sends the data to be transmitted to the target register or the target SPI device.

[0035] Specifically, the data to be transmitted is either write data or read data. When constructing the address mapping table, because the AXI address is obtained through parsing based on the first protocol used between the main FPGA and the secondary FPGA, the main FPGA can clearly know which secondary FPGA to send the control code to after receiving it. It then adds the corresponding SPI address to the data according to the mapping table. The secondary FPGA receives the data and decodes it according to the SPI address before forwarding it to the corresponding device. In this embodiment, sending the control code from the main FPGA to the corresponding secondary FPGA specifically includes:

[0036] The control code is read through the first state machine and written into the first first-in-first-out queue in the main FPGA through the first state machine.

[0037] The first FIFO queue is detected by the second state machine. When the second state machine detects a control code in the first FIFO queue, it parses the control codes in the first FIFO queue in sequence and sends them to the corresponding secondary FPGA via the SPI protocol.

[0038] The maximum capacity of the first first-in-first-out queue is greater than the number of control codes required for a complete control operation.

[0039] Specifically, the FIFO is located in the main FPGA, ensuring smooth communication between the AXI and SPI bus clock rates. The first state machine reads the control code sent by the host and writes it into the first FIFO queue. Then, the second state machine detects the first FIFO queue. When the second state machine detects the presence of a control code in the first FIFO queue, it parses the control codes in the queue sequentially and sends them to the corresponding secondary FPGA via the SPI protocol. Both the first and second state machines are located in the main FPGA. The secondary FPGA can simply forward the corresponding data. The transmission process is controlled by the state machines. After detecting the presence of a control code in the FIFO, the data is read out and then sent according to the SPI protocol. After the data is sent, the above operation is repeated until there are no remaining control codes in the FIFO.

[0040] In this embodiment, the secondary FPGA sends the data to be transmitted to the target register or the target SPI device, specifically including:

[0041] When the secondary FPGA receives the control code, it decodes the control code through the SPI routing control component to obtain the target SPI address;

[0042] The secondary FPGA sends the data to be transmitted to the target register or the target SPI device according to the target SPI address.

[0043] Specifically, after receiving the control code from the second state machine, the secondary FPGA decodes the control code through the SPI routing control component to obtain the target SPI address. The control code is constructed based on the address mapping table and the data to be transmitted. During construction, the target SPI address of the target register or target SPI device is obtained through the address mapping table. Then, this target SPI address and the data to be transmitted are combined to form the control code. Since the SPI address also has a corresponding secondary FPGA address when the address mapping table is constructed, when the master FPGA sends the control code, it simultaneously informs the master FPGA which secondary FPGA to forward it to. Alternatively, the corresponding secondary FPGA address can be... The address of the secondary FPGA is added to the control code, which is sent collaboratively by the first and second state machines. Specifically, when the second state machine parses the control code, it sends the control code to the corresponding secondary FPGA based on the secondary FPGA address in the control code. When the secondary FPGA receives the control code, it decodes the control code to obtain the target SPI address. Then, the secondary FPGA sends the data to be transmitted to the target register or target SPI device based on the target SPI address. When sending to the target register or target SPI device, only the corresponding data to be transmitted is sent to the corresponding target register or target SPI device, without sending the address information along with it.

[0044] This application's solution maps all underlying registers and devices into the host memory, which greatly helps to simplify resource management and control of the host software. At the same time, the entire control architecture is clearer, and it also solves the problems of slow speed and easy freezing in high-speed control applications (such as frequency sweep mode of signal source, multi-item automatic test process of automatic test machine, etc.).

[0045] like Figure 2 The diagram illustrates data transmission using existing technologies in a specific application scenario. A complete control flow in the existing technology is shown below:

[0046] (1) The host, i.e. the pc in the figure, finds the corresponding ranges of AXI address 0x10000 and 0x20000 in memory respectively, and creates the corresponding IP at the software level (if a group of SPI corresponds to a secondary FPGA, then the one created is the secondary FPGA), and prepares to operate on the Xilinx IP.

[0047] (2) Reset the TX RX FIFO and disable the SPI transmission function of the SPI IP:

[0048] Write 0x1E6 to AXI address 0x10070.

[0049] (3) Fill the SPI address + write data into the FIFO (only one valid byte is filled at a time, and multiple transmissions are made according to different control code lengths. Assume that the control code corresponding to all SPI addresses is 4 bytes of 0x1234ABCD):

[0050] Write 0x01 (SPI address) to AXI address 0x10068

[0051] Write 0x12 (valid data) to AXI address 0x10068.

[0052] Write 0x34 (valid data) to AXI address 0x10068.

[0053] Write 0xAB (valid data) to AXI address 0x10068.

[0054] Write 0xCD (valid data) to AXI address 0x10068.

[0055] (4) Enable SPI CS signal:

[0056] Write 0x00 to AXI address 0x10070

[0057] (5) Enable the SPI transmission function of the SPI IP Core

[0058] Write 0x86 to AXI address 0x10060

[0059] (6) Check if the sending is complete:

[0060] Read the AXI address 0x10020. If the read value is 0x04, it means the transmission is complete and proceed to the next step. Otherwise, read again until the system-set timeout period.

[0061] (7) Disable the SPI CS signal:

[0062] Write 0x1 to AXI address 0x10070

[0063] (8) Disable the SPI transmission function of the SPI IP:

[0064] Write 0x186 to AXI address 0x10060

[0065] Repeat steps 2-8 above until all control signals required for SPI addresses 0x01 to SPI address 0x05 have been sent.

[0066] If the solution proposed in this application is adopted, such as Figure 3 The diagram shown illustrates data transmission using the technical solution of this application. The specific process is as follows:

[0067] (1) Find the corresponding ranges of AXI addresses 0x10000, 0x10004, 0x10008, 0x20000, and 0x20004 in memory respectively, and create the corresponding registers or devices at the software level to prepare for direct operation on the underlying layer.

[0068] (2) Write 0x1234ABCD to AXI address 0x10000 (no SPI address required)

[0069] (3) Write 0x1234ABCD to AXI address 0x10004 (no SPI address required)

[0070] (4) Write 0x1234ABCD to AXI address 0x10008 (no SPI address required)

[0071] (5) Write 0x1234ABCD to AXI address 0x20000 (no SPI address required)

[0072] (6) Write 0x1234ABCD to AXI address 0x20004 (no SPI address required)

[0073] As can be seen from the above, the operation steps omit many cumbersome operations involving IP interaction, and the entire process involves only writing without reading or waiting operations, greatly shortening the control flow completion time. Furthermore, when the software creates the corresponding device, it can directly map the underlying device to memory, instead of only showing one set of SPIs (i.e., one secondary FPGA) corresponding to one IP, as was the case with the original IP.

[0074] Based on the above-described data transmission method for the Pxie platform, one or more embodiments of this specification also provide a platform or terminal for data transmission within the Pxie platform. This platform or terminal may include devices, software, modules, plug-ins, servers, clients, etc., using the methods described in the embodiments of this specification, combined with necessary hardware implementation devices. Based on the same innovative concept, the systems in one or more embodiments provided in this specification are as described in the following embodiments. Since the implementation schemes and methods for solving the system problem are similar, the specific system implementation in the embodiments of this specification can refer to the implementation of the aforementioned methods. Repeated descriptions will not be repeated. The terms "unit" or "module" used below can refer to a combination of software and / or hardware that achieves a predetermined function. Although the systems described in the following embodiments are preferably implemented in software, hardware implementations, and a combination of software and hardware, are also possible and contemplated.

[0075] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0076] The methods or apparatus described in the embodiments provided in this specification can implement business logic through a computer program and record it on a storage medium. The storage medium can be read and executed by a computer to achieve the effects of the solutions described in the embodiments of this specification, such as:

[0077] Obtain all registers and the unique SPI address corresponding to all SPI devices;

[0078] The first protocol used between the main FPGA and the secondary FPGA is parsed to obtain multiple AXI addresses, and an address mapping table is constructed after selecting an AXI address for each SPI address.

[0079] A control code is constructed based on the address mapping table and the data to be transmitted;

[0080] The control code is sent from the main FPGA to the corresponding secondary FPGA, so that the secondary FPGA sends the data to be transmitted to the target register or the target SPI device.

[0081] The storage medium can include physical devices for storing information, typically digitizing the information and then storing it using electrical, magnetic, or optical methods. The storage medium can include: devices that store information using electrical energy, such as various types of memory, like RAM and ROM; devices that store information using magnetic energy, such as hard disks, floppy disks, magnetic tapes, magnetic core memory, bubble memory, and USB flash drives; and devices that store information using optical methods, such as CDs or DVDs. Of course, there are other readable storage media, such as quantum memories and graphene memories.

[0082] The embodiments in this specification are not limited to conforming to industry communication standards, standard computer resource data update and data storage rules, or the situations described in one or more embodiments of this specification. Slightly modified implementations based on certain industry standards or custom methods or embodiments can also achieve the same, equivalent, or similar, or predictable, implementation effects as described above. Embodiments that utilize these modified or modified methods for data acquisition, storage, judgment, and processing still fall within the scope of optional implementations of the embodiments in this specification.

[0083] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, ASICs, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0084] The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or plug-ins may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between devices or units, and may be electrical, mechanical, or other forms.

[0085] These computer program instructions can also be loaded onto a computer or other programmable resource data updating device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0086] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, system embodiments are basically similar to method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0087] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A data transmission method for use in a Pxie platform, the Pxie platform comprising at least a host, a master FPGA and a plurality of secondary FPGAs, each of the secondary FPGAs being connected to the master FPGA, each of the secondary FPGAs comprising a plurality of registers and each of the secondary FPGAs being further connected to a plurality of SPI devices, the method comprising: The method comprises: ​ acquiring unique SPI addresses corresponding to all registers and all SPI devices; parsing a first protocol used between the master FPGA and the secondary FPGA to obtain a plurality of AXI addresses, selecting an AXI address for each SPI address, and constructing an address mapping table; constructing a control code based on the address mapping table and the data to be transmitted; sending the control code through the master FPGA to the corresponding secondary FPGA, so that the secondary FPGA sends the data to be transmitted to the target register or the target SPI device; wherein the sending of the control code through the master FPGA to the corresponding secondary FPGA specifically comprises: reading the control code through a first state machine and writing the control code into a first first-in-first-out queue in the master FPGA through the first state machine; detecting the first first-in-first-out queue through a second state machine, and when the second state machine detects the control code in the first first-in-first-out queue, sequentially parsing the control code in the first first-in-first-out queue and sending it to the corresponding secondary FPGA through the SPI protocol.

2. The method for data transfer inside a PXE platform of claim 1, wherein, The maximum capacity of the first first-in-first-out queue is greater than the number of complete control of all control codes at a time.

3. The method for data transfer inside a PXE platform as recited in claim 1, wherein, The secondary FPGA sends the data to be transmitted to the target register or the target SPI device, specifically comprising: after the secondary FPGA receives the control code, decoding the control code through an SPI routing control component to obtain a target SPI address; sending the data to be transmitted to the target register or the target SPI device according to the target SPI address through the secondary FPGA.

4. The method for data transfer inside a PXE platform of claim 3, wherein, When the data to be transmitted is sent to the target register or the target SPI device according to the target SPI address through the secondary FPGA, the target SPI address needs to be removed so that the secondary FPGA only sends the data to be transmitted to the target register or the target SPI device.

5. The method for data transfer inside a PXE platform as recited in claim 1, wherein, The data to be transmitted is specifically write data or read data.

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