PCIe interface implementation method and device for FPGA high-speed data transmission

Abstract

The embodiment of the application provides a PCIe interface implementation method and device for FPGA high-speed data transmission, which realizes safe and efficient transmission of data through innovative design of a direct memory access mechanism, registration and descriptor queue management of a physically continuous cache area. A timestamp-based data block organization strategy is constructed, combined with a burst transmission channel and a state tracker, to establish a reliable data transmission control system. State registers and an interrupt mechanism are introduced to ensure the integrity of the transmission process and the security of the information through real-time state monitoring and data synchronization. This method effectively solves the deficiencies of traditional technologies in transmission efficiency, data management, and state monitoring, etc., while protecting data security, significantly improving the performance and reliability of the PCIe interface.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data processing, specifically to a PCIe interface implementation method and device for FPGA high-speed data transmission. BACKGROUND

[0002] The existing PCIe interface implementation method for FPGA high-speed data transmission has obvious deficiencies. Traditional systems perform poorly in terms of data transmission efficiency, failing to fully utilize the bandwidth advantage of PCIe bus, affecting the overall performance of the system.

[0003] In addition, the existing technology has bottlenecks in data management and control. Most systems lack effective descriptor queue management mechanisms and direct memory access strategies, resulting in insufficient data transmission reliability.

[0004] The existing system has technical shortcomings in state monitoring. Lack of real-time tracking ability of data block transmission state, difficult to realize accurate data synchronization through status register, affecting the stability of transmission. The solution of these problems has important significance for improving the performance of PCIe interface. SUMMARY

[0005] In view of the problems in the prior art, the present application provides a PCIe interface implementation method and device for FPGA high-speed data transmission, which can effectively solve the deficiencies of traditional technology in transmission efficiency, data management and state monitoring, etc., and significantly improve the performance and reliability of PCIe interface.

[0006] In order to solve at least one of the above problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a PCIe interface implementation method for FPGA high-speed data transmission, comprising:

[0008] allocating a host physical continuous cache area and registering the physical continuous cache area as a direct memory access buffer area, establishing a descriptor queue in the direct memory access buffer area, the descriptor queue recording data source address, target address and length information, mapping the descriptor queue to user space through memory mapping, configuring burst transmission length and address alignment mode, binding task identification and interrupt processing function;

[0009] Converting image data into gray scale values and dividing them into multiple data blocks according to a preset size, adding boundary pixels to each data block and setting a timestamp, writing the data block into the DMA buffer, triggering the doorbell register to send a task signal to the FPGA, the FPGA pre-fetches descriptors from the descriptor queue to the FIFO cache, and writes the data block into the specified location in the DRAM through the burst transfer channel based on the descriptor information;

[0010] Building a two-dimensional cache array and writing the processed data block to the corresponding position according to the timestamp, the FPGA writes the data block state to the status register and triggers an interrupt signal, the status tracker detects the absence and duplication of the data block, and the host reads the data block from the DRAM according to the content of the status register, and the host sends a data read completion signal to the FPGA.

[0011] Further, it also includes: traversing the system physical address space through the kernel module to obtain a continuous physical address segment, establishing a mapping table of physical address to virtual address, allocating the physical address segment to the host as a physically continuous cache area, marking the properties of the physically continuous cache area in the host memory management unit as non-swap, and registering the start address and length information of the physically continuous cache area to the DMA controller;

[0012] The DMA controller is configured in master mode, the data area and descriptor area are divided in the DMA buffer, the descriptor linked list structure is established in the descriptor area, the source address points to the start position of the data area, the target address points to the internal storage space of the FPGA, and the length information and direction control bit of data transmission are recorded in the descriptor linked list.

[0013] Further, it also includes: mapping the physical page where the descriptor queue is located to the process virtual address space through the memory management unit at system startup, establishing a page table entry and setting the access permission flag bit, allocating a virtual address interval in the user space as the mapping area of the descriptor queue, writing the start address and length information of the mapping area to the device base address register, configuring the burst transfer length parameter according to the bus bit width, and setting the mask value of address boundary alignment;

[0014] Creating an interrupt descriptor table and setting an interrupt gate descriptor, writing the entry address of the interrupt service program to the interrupt vector table, establishing a mapping relationship between the task identifier and the interrupt number, configuring the trigger mode and priority of the interrupt controller, writing the status update and notification logic after data transfer in the interrupt handling function, and registering the interrupt handling function to the system interrupt handling chain table.

[0015] Further, it also includes: extracting red, green and blue three-channel pixel values according to the original format of the image data, calculating the corresponding gray value of each pixel point by using the weighted average method, writing the gray value into the preprocessing buffer, determining the data block size based on the image resolution, calculating the number of data blocks in the horizontal and vertical directions, establishing a data block index table in the preprocessing buffer, and recording the starting position and size information of each data block;

[0016] Padding the border pixels around each of the data blocks to form an overlapping area, generating a globally monotonically increasing timestamp count value, writing the timestamp count value into the data block header, establishing a mapping relationship table between the data block and the timestamp, calculating the offset address of the data block in the direct memory access buffer according to the spatial position information of the data block, and writing the data block with the border pixels and the timestamp information into the storage location pointed by the offset address.

[0017] Further, it also includes: locating the physical address of the doorbell register in the base address register space, writing the task start flag bit into the specified position of the doorbell register, configuring the trigger mode of the doorbell register as edge trigger, creating a task state register to record the execution stage of the current task, establishing an associated mapping between the doorbell register and the task state register, and monitoring the value of the task state register to confirm whether the field programmable gate array responds to the task signal;

[0018] After receiving the task signal, the field programmable gate array reads a preset number of descriptors from the descriptor queue, temporarily stores the descriptors in the first-in-first-out cache, configures the source address and target address of the burst transmission channel according to the address information in the descriptor, divides the data transmission unit according to the burst transmission length parameter, writes the data blocks into the continuous storage space of the dynamic random access memory in sequence, and updates the values of the memory address pointer and the data counter.

[0019] Further, it also includes: dividing the two-dimensional cache array space inside the field programmable gate array, calculating the storage position in the two-dimensional cache array according to the row and column coordinates of the data block, parsing the timestamp information in the data block header to obtain the processing order, establishing a mapping table between the timestamp and the storage position, writing the processed data blocks into the corresponding position of the two-dimensional cache array according to the timestamp order, maintaining a bitmap table of the data block writing state, and recording the spatial distribution of the written data blocks;

[0020] The field programmable gate array writes the processing state of the data block into the state field of the state register, generates an interrupt request signal and sends it to the host through the interrupt controller, the state tracker reads the bitmap table to check the writing of the data block, calculates the interval value between adjacent timestamps to determine whether the data block is missing, scans the timestamp identifier in the two-dimensional cache array to determine whether the data block is repeatedly written, and updates the detection result to the error flag bit of the state register.

[0021] Further, the host reads the status field of the status register through an interrupt service program, parses the address pointer in the status register to obtain the storage position of the data block in the dynamic random access memory, configures the transmission parameter of the host-side direct memory access controller, establishes a descriptor chain table for data block reading, points the target address to the receiving buffer of the host side, starts the direct memory access controller to execute data reading operation, and judges whether the data block is read completely according to the transmission completion flag;

[0022] The host writes the reading completion flag bit into the command register, sends the content of the command register to the FPGA through the bus interface, the FPGA clears the status flag bit of the corresponding data block after receiving the data reading completion signal, releases the storage space in the two-dimensional cache array, updates the value of the data block counter, and resets the related status bit in the status register.

[0023] In a second aspect, the application provides a PCIe interface implementation device for FPGA high-speed data transmission, comprising:

[0024] A task mapping module is configured to allocate a physically continuous cache area on the host side and register the physically continuous cache area as a direct memory access buffer, establish a descriptor queue in the direct memory access buffer, record data source address, target address and length information in the descriptor queue, map the descriptor queue to the user space through memory mapping, configure burst transmission length and address alignment mode, and bind task identification and interrupt processing function;

[0025] A data cache module is configured to convert image data into gray value and divide the image data into a plurality of data blocks according to a preset size, add boundary pixels to each data block and set a timestamp, write the data blocks into the direct memory access buffer, trigger a doorbell register to send a task signal to the FPGA, the FPGA pre-fetches descriptors from the descriptor queue to a first-in-first-out cache, and writes the data blocks into a specified position in the dynamic random access memory through a burst transmission channel based on the descriptor information;

[0026] A data writing module is configured to construct a two-dimensional cache array and write the data blocks processed to the corresponding position according to the timestamp, the FPGA writes the data block status into a status register and triggers an interrupt signal, a status tracker detects the absence and repetition of the data blocks, the host reads the data blocks from the dynamic random access memory according to the content of the status register, and the host sends a data reading completion signal to the FPGA.

[0027] In a third aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for implementing a PCIe interface for high-speed data transmission of an FPGA when executing the program.

[0028] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program, wherein the computer program is executable on a processor to implement the steps of the method for implementing a PCIe interface for high-speed data transmission of an FPGA.

[0029] In a fifth aspect, the present application provides a computer program product, comprising computer programs / instructions, wherein the computer programs / instructions are executable on a processor to implement the steps of the method for implementing a PCIe interface for high-speed data transmission of an FPGA.

[0030] According to the above technical solution, the present application provides a method and device for implementing a PCIe interface for high-speed data transmission of an FPGA, which realizes safe and efficient transmission of data by innovatively designing a direct memory access mechanism, registering and describing a physical continuous cache area, and managing a descriptor queue. A data block organization strategy based on a timestamp is constructed, combined with a burst transmission channel and a state tracker, to establish a reliable data transmission control system. A state register and an interrupt mechanism are introduced, and real-time state monitoring and data synchronization are performed to ensure the integrity of the transmission process and the information security. The method effectively solves the deficiencies of traditional technologies in transmission efficiency, data management, and state monitoring, while protecting data security, and significantly improves the performance and reliability of the PCIe interface. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0032] Figure 1 A flowchart of the method for implementing a PCIe interface for high-speed data transmission of an FPGA in the embodiments of the present application;

[0033] Figure 2 A structural diagram of the device for implementing a PCIe interface for high-speed data transmission of an FPGA in the embodiments of the present application;

[0034] Figure 3 A structural diagram of the electronic device in the embodiments of the present application.

[0035] Reference signs:

[0036] The electronic device 9600, the central processor 9100, the memory 9140, the communication module 9110, the input unit 9120, the audio processor 9130, the display 9160, the power supply 9170, the buffer memory 9141, the application / function storage unit 9142, the data storage unit 9143, the driver program storage unit 9144, the antenna 9111, the speaker 9131, and the microphone 9132. DETAILED DESCRIPTION

[0037] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0038] The acquisition, storage, use, processing and the like of data in the technical solutions of the present application comply with relevant provisions of laws and regulations.

[0039] In view of the problems in the prior art, the present application provides a PCIe interface implementation method and device for FPGA high-speed data transmission. By innovatively designing a direct memory access mechanism, through physical continuous cache area registration and descriptor queue management, safe and efficient transmission of data is achieved. A data block organization strategy based on timestamps is constructed, combined with burst transmission channels and state trackers, to establish a reliable data transmission control system. State registers and interrupt mechanisms are introduced to ensure the integrity of the transmission process and information security through real-time state monitoring and data synchronization. This method effectively solves the deficiencies of traditional technologies in transmission efficiency, data management, and state monitoring, significantly improving the performance and reliability of the PCIe interface while protecting data security.

[0040] In order to effectively solve the deficiencies of traditional technologies in transmission efficiency, data management, and state monitoring, and significantly improve the performance and reliability of the PCIe interface, an embodiment of a PCIe interface implementation method for FPGA high-speed data transmission is provided in the present application, as shown in Figure 1 , which specifically includes the following contents:

[0041] Step S101: allocate a host-side physically continuous buffer area and register the physically continuous buffer area as a direct memory access buffer, establish a descriptor queue in the direct memory access buffer, the descriptor queue records data source address, target address and length information, map the descriptor queue to a user space through memory mapping, configure burst transmission length and address alignment mode, bind task identification and interrupt processing function;

[0042] Optionally, the embodiment solves key problems such as physical memory dispersion, address mapping complexity and interrupt response delay in FPGA data transmission through a deeply optimized memory management and DMA transmission mechanism. In the system initialization stage, an efficient physical memory allocation mechanism needs to be established first. The embodiment innovatively designs a physical address continuity score formula: PMA_Score = (Block_Size × Continuity_Factor) / (Fragment_Count + Address_Gap), wherein Block_Size represents a memory block size, Continuity_Factor represents a continuity coefficient, Fragment_Count represents a fragment quantity, and Address_Gap represents an address gap. A DMA transmission efficiency score formula: DMA_Efficiency = (Burst_Length × Alignment_Quality) / (Setup_Time + Transfer_Latency) is introduced simultaneously, which is used for optimizing data transmission performance.

[0043] The embodiment first realizes allocation of a physically continuous buffer area through a kernel state memory management mechanism. By traversing a system physical address space, a buddy algorithm is used to find a continuous physical page meeting a size requirement. In order to avoid memory fragmentation, the embodiment adopts a reserved memory area mode, and a dedicated physical memory space is divided at the time of system startup. These physical pages are marked as non-swapable, ensuring that the memory address remains stable during data transmission. When allocating physical memory, the system considers memory alignment requirements and selects an address boundary suitable for DMA transmission. For large-scale data transmission scenarios, the system reserves sufficient continuous physical space to avoid runtime memory reallocation overhead. This optimized memory allocation mechanism provides a reliable physical basis for subsequent DMA transmission.

[0044] The embodiment innovatively realizes a descriptor queue management mechanism. In the direct memory access buffer, the system uses a ring queue structure to organize DMA descriptors. Each descriptor contains complete transmission information, including source address, target address, transmission length, and control flags. The organization of descriptors uses a linked list method, supporting dynamic expansion and contraction. In order to improve the access efficiency of the descriptor, the system establishes a multi-level index structure in the buffer, which can quickly locate the descriptor at any position. When processing high-speed data streams, the system reduces the runtime resource allocation overhead by pre-allocating descriptors. This flexible descriptor management mechanism significantly improves the scheduling efficiency of DMA transmission.

[0045] The embodiment realizes direct access of the user space through an optimized address mapping mechanism. By mapping the physically continuous buffer area to the virtual address area of the user space through the page table, frequent kernel mode switching is avoided. During the mapping process, the system sets appropriate access permissions and cache attributes to ensure the safety and efficiency of data access. Especially for the descriptor queue that needs to be frequently accessed, the system uses a write-merge buffer technology to reduce the number of PCIe bus transactions. This direct address mapping mechanism significantly reduces the data access delay.

[0046] The embodiment establishes a complete interrupt handling framework. A flexible mapping relationship is established between the interrupt handling function and the task identifier, supporting multi-task parallel processing. When the interrupt is triggered, the system can quickly locate the corresponding processing function, reducing the interrupt handling delay. The interrupt handling process adopts a lightweight design, mainly completing the necessary state update and notification operation, and the complex data processing is postponed to the non-interrupt context for execution. This optimized interrupt handling mechanism ensures the real-time response capability of the system.

[0047] The embodiment provides an innovative solution for PCIe data transmission. Through optimized memory management and transmission control mechanism, the system can efficiently handle large-scale data transmission tasks. This reliable transmission mechanism significantly improves the data exchange efficiency between FPGA and host.

[0048] The embodiment realizes transmission acceleration through full-process optimization. From memory allocation to interrupt handling, each link is carefully designed and optimized to ensure efficient operation of the entire transmission process. This systematic optimization strategy provides a reliable data transmission solution for FPGA application development.

[0049] The transmission method adopted in the embodiment has good scalability. By adjusting the buffer configuration and transmission parameters, the system can adapt to different scales and types of data transmission requirements. This flexible transmission framework provides a general technical solution for FPGA application development. This adaptive transmission method not only improves the processing efficiency of the system, but also enhances the practical value of the solution.

[0050] Step S102: converting the image data into gray scale values and dividing them into multiple data blocks according to a preset size, adding boundary pixels to each data block and setting a timestamp, writing the data blocks into the direct memory access buffer, triggering the doorbell register to send a task signal to the field programmable gate array, the field programmable gate array pre-fetching descriptors from the descriptor queue to the first-in-first-out cache, and writing the data blocks into a specified location in the dynamic random access memory through the burst transfer channel based on the descriptor information;

[0051] Optionally, the embodiment innovatively designs a set of data organization scheme based on timestamps to solve the problems of unreasonable data blocking, low boundary processing efficiency, and complex transmission synchronization in image data processing. In terms of image conversion evaluation, the embodiment designs a gray scale conversion quality score formula: Gray_Quality = α × (RGB_Weight_Balance) + β × (Detail_Preservation) + γ × (Noise_Reduction), where α, β, and γ are weight coefficients, respectively representing RGB weight balance, detail preservation, and noise reduction. At the same time, a data block division score formula: Block_Efficiency = (Block_Size × Processing_Speed) / (Memory_Usage + Transfer_Overhead) is introduced to optimize the data block size configuration.

[0052] The embodiment first realizes efficient gray scale conversion through an optimized image processing flow. For input RGB image data, a weighted average method is used for gray scale conversion, and the weight coefficients are optimized according to the sensitivity of the human eye to different colors. During conversion, the system uses a pipeline method to process multiple pixels in parallel, significantly improving processing efficiency. Especially for high-resolution images, the system dynamically adjusts the processing batch according to the cache size to avoid frequent data movement between memories. In the data block division stage, the system considers the PCIe transmission efficiency and FPGA processing capacity to select the optimal block size. This adaptive data organization method provides a good foundation for subsequent parallel processing.

[0053] The embodiment innovatively realizes the boundary processing mechanism. When processing the data block boundary, the system adopts an intelligent pixel filling strategy. For the data block of the image edge, the system supplements the boundary pixels through mirror copying; for the internal data block, the processing continuity is ensured through the overlapping area. The generation of the timestamp adopts a monotonically increasing counter, and the unique identifier is generated in combination with the spatial position information of the data block. This accurate timing control mechanism ensures the sequence and integrity of data processing. When writing data to the buffer, the system realizes the parallel execution of data preparation and transmission through the double buffering mechanism, which significantly improves the data throughput.

[0054] The embodiment realizes efficient data transmission through an optimized transmission control mechanism. The trigger of the doorbell register adopts an edge trigger mode to ensure reliable signal transmission. After receiving the task signal, the FPGA immediately prefetches multiple descriptors from the descriptor queue, and realizes the caching and queuing of the descriptors through the first-in-first-out cache. This prefetching mechanism effectively reduces the transmission start delay. During data transmission, the system optimizes the burst transmission parameters according to the PCIe bus characteristics, and selects the most suitable transmission length and address alignment mode. By reasonably organizing the transmission request, the system significantly improves the bus utilization rate.

[0055] The embodiment establishes a complete storage management framework. In the dynamic random access memory, the system manages the storage location of the data block through the address mapping table. The allocation of the storage space considers the data access mode, and stores the related data blocks in adjacent positions to improve the access efficiency. During data writing, the system monitors the transmission progress in real time through the state tracking mechanism to ensure reliable storage of data. This fine storage management mechanism provides reliable storage support for data processing.

[0056] The embodiment provides an innovative solution for image data processing. Through optimized data organization and transmission mechanism, the system can efficiently process large-scale image data. This reliable processing mechanism significantly improves the real-time performance and reliability of image processing.

[0057] The embodiment realizes processing acceleration through full-process optimization. From image conversion to data storage, each link is carefully designed and optimized to ensure efficient operation of the entire processing process. This systematic optimization strategy provides reliable technical support for FPGA image processing.

[0058] The processing method adopted in the embodiment has good scalability. By adjusting the processing parameters and transmission strategy, the system can adapt to different scales and types of image processing requirements. This flexible processing framework provides a general technical solution for FPGA application development. This adaptive processing method not only improves the processing efficiency of the system, but also enhances the practical value of the scheme.

[0059] Step S103: constructing a two-dimensional cache array and writing the processed data block to the corresponding position according to the timestamp, the field programmable gate array writes the data block state to the state register and triggers an interrupt signal, the absence and repetition of the data block are detected by the state tracker, and the host reads the data block from the dynamic random access memory according to the content of the state register, and the host sends a data read completion signal to the field programmable gate array.

[0060] Optionally, the embodiment innovatively designs a set of data management scheme based on two-dimensional cache to solve the problems of complex cache organization, difficult state tracking and unreliable data synchronization in data management. In terms of cache efficiency evaluation, the embodiment designs a cache performance score formula: Cache_Score = α × (Access_Speed / Max_Speed) + β × (Space_Utilization) + γ × (Data_Consistency), wherein α, β and γ are weight coefficients, respectively representing access speed, space utilization and data consistency. At the same time, a state tracking score formula: Track_Efficiency = (Detection_Accuracy × Response_Speed) / (Resource_Usage + Detection_Delay) is introduced to optimize the state monitoring efficiency.

[0061] The embodiment first realizes efficient data organization through a deeply optimized cache management mechanism. The design of the two-dimensional cache array fully considers the spatial locality of data blocks and organizes data in a row-first storage manner. The division of cache space is based on the actual size of data blocks, and a dynamic allocation algorithm is used to ensure space utilization. During data writing, the system adopts a multi-level cache structure, including a write buffer and a main cache area. The write buffer is used to temporarily store newly arrived data blocks, and the main cache area saves confirmed data. This layered cache structure effectively reduces data writing conflicts and improves storage efficiency. For timestamp management, the system establishes a timestamp-to-storage location mapping table to support fast positioning of data blocks corresponding to any timestamp.

[0062] The embodiment innovatively realizes the state management mechanism. The state register adopts a multi-field design, not only recording the basic state of the data block, but also containing detailed error flags and processing progress information. The state information of each data block is stored compactly in bitmap mode, supporting efficient state query and update. In terms of interrupt triggering, the system adopts a configurable interrupt strategy, which can adjust the interrupt triggering conditions according to actual needs. For example, you can choose to trigger an interrupt only after a certain number of data blocks are processed, reducing interrupt processing overhead. The state tracker monitors the data block state through a periodic scanning mechanism and uses a sliding window to detect the continuity of the data sequence.

[0063] The embodiment realizes reliable data integrity verification through an optimized detection algorithm. When detecting data block loss, the state tracker not only compares the difference between adjacent timestamps, but also considers the spatial position relationship of the data block. For possible data loss, the system will immediately start the recovery program, including re-requesting data transmission or using backup data. When detecting data duplication, the system ensures the accuracy of detection by comparing timestamps and data content. For detected abnormal conditions, the system updates the error flags in the state register and triggers the corresponding processing flow. This complete detection mechanism ensures the reliability of data processing.

[0064] The embodiment establishes an efficient data reading framework. After receiving the interrupt signal, the host first reads the state register to obtain the data state. The data reading process uses a batch method, and the continuous data blocks are transmitted to the host memory through DMA transmission. After reading is completed, the host notifies the FPGA to update the state by writing to the command register. This coordinated reading mechanism significantly improves data transmission efficiency. Especially when processing a large number of data blocks, the system reduces the waiting time through predictive reading, improving overall processing efficiency.

[0065] The embodiment provides an innovative solution for data management. Through optimized cache organization and state management mechanism, the system can efficiently process complex data streams. This reliable management mechanism significantly improves the reliability and efficiency of data processing.

[0066] The embodiment realizes management acceleration through full-process optimization. From data organization to state tracking, each link is carefully designed and optimized to ensure efficient operation of the entire management process. This systematic optimization strategy provides a reliable data management solution for FPGA application development.

[0067] The management method used in this embodiment has good scalability. By adjusting the cache parameters and detection strategies, the system can adapt to different sizes and types of data processing requirements. This flexible management framework provides a general technical solution for FPGA application development. This adaptive management method not only improves the processing efficiency of the system, but also enhances the practical value of the solution.

[0068] From the above description, the PCIe interface implementation method for FPGA high-speed data transmission provided by the embodiments of the application can achieve safe and efficient transmission of data by innovatively designing a direct memory access mechanism, through physical continuous cache area registration and descriptor queue management. A data block organization strategy based on timestamps is constructed, combined with burst transmission channels and state trackers, to establish a reliable data transmission control system. State registers and interrupt mechanisms are introduced to ensure the integrity of the transmission process and information security through real-time state monitoring and data synchronization. This method effectively solves the deficiencies of traditional technologies in transmission efficiency, data management, and state monitoring, etc., while protecting data security, significantly improving the performance and reliability of the PCIe interface.

[0069] In an embodiment of the PCIe interface implementation method for FPGA high-speed data transmission of the application, the following content can be specifically included:

[0070] Step S201: Obtain a continuous physical address segment by traversing the system physical address space through a kernel module, establish a mapping table of physical addresses to virtual addresses, allocate the physical address segment to a host end as a physically continuous cache area, mark the attribute of the physically continuous cache area as non-swap in the host memory management unit, and register the start address and length information of the physically continuous cache area to a direct memory access controller.

[0071] Step S202: Configure the direct memory access controller as a master device mode, divide a data region and a descriptor region in the direct memory access buffer, establish a descriptor linked list structure in the descriptor region, point a source address to the start position of the data region, point a target address to the internal storage space of the FPGA, and record the length information and direction control bit of data transmission in the descriptor linked list.

[0072] Optionally, the embodiment is directed to the low efficiency of memory management, complex address mapping and unreasonable configuration of DMA controller in FPGA data transmission, and a set of DMA transmission scheme based on physically continuous memory is innovatively designed. In the aspect of memory management evaluation, the embodiment designs a memory allocation score formula: Memory_Score = α × (Continuous_Size / Total_Size) + β × (Address_Alignment) + γ × (Fragment_Reduction), wherein α, β and γ are weight coefficients, respectively representing the continuity ratio, address alignment degree and fragment reduction degree. At the same time, a DMA control score formula: DMA_Control = (Transfer_Speed × Channel_Efficiency) / (Setup_Time + Switch_Overhead) is introduced to optimize the transmission control efficiency.

[0073] The embodiment first realizes the allocation of physically continuous memory through a deeply optimized memory management mechanism. The kernel module records the available physical page information by traversing the system physical address space and using a multi-level page table structure. During the traversal process, the system uses a bitmap to mark the allocated and idle pages, and quickly locates the continuous physical address segment that meets the size requirement through a continuous page tracking algorithm. For large-scale data transmission scenarios, the system reserves enough continuous physical space to avoid frequent allocation and release at runtime. When establishing the address mapping, the system uses a multi-level mapping table structure to support fast address conversion and access permission management. This optimized memory management mechanism provides a reliable physical basis for DMA transmission.

[0074] The embodiment innovatively realizes the memory attribute management mechanism. In the host memory management unit, the system marks the physically continuous cache area as non-swap by modifying the attribute bit of the page table entry. This marking ensures that the cache area always maintains physical address continuity during system operation, avoiding the address discontinuity problem caused by page swapping. Especially when handling high-speed data streams, this fixed memory allocation strategy significantly improves the stability of data access. When registering the DMA controller, the system writes the start address and length information of the physically continuous cache area into the configuration register of the controller to establish a reliable data transmission channel.

[0075] The embodiment realizes efficient data transmission through an optimized DMA controller configuration. In the host device mode, the DMA controller can autonomously initiate data transmission requests, reducing CPU intervention. The division of the buffer uses a dynamic proportional strategy to adjust the size of the data area and the descriptor area according to actual transmission requirements. In the data area, the system uses a circular buffer structure to support continuous data write and read operations. The descriptor area organizes transmission descriptors in a linked list, and each descriptor contains complete transmission control information. This flexible buffer management mechanism significantly improves transmission efficiency.

[0076] The embodiment establishes a complete descriptor management framework. The descriptor linked list uses a bidirectional link structure to support flexible descriptor insertion and deletion operations. Each descriptor not only contains basic address and length information, but also sets detailed control flags to indicate transmission direction, interrupt enable, and other attributes. The setting of the source address and the target address considers the data flow direction to ensure the optimization of the transmission path. This fine descriptor management mechanism provides reliable control support for data transmission.

[0077] The embodiment provides an innovative solution for DMA transmission. Through optimized memory management and transmission control mechanisms, the system can efficiently handle large-scale data transmission tasks. This reliable transmission mechanism significantly improves the data exchange efficiency between the FPGA and the host.

[0078] The embodiment realizes transmission acceleration through full-process optimization. From memory allocation to descriptor management, each link is carefully designed and optimized to ensure efficient operation of the entire transmission process. This systematic optimization strategy provides a reliable data transmission solution for FPGA application development.

[0079] The transmission method used in the embodiment has good scalability. By adjusting the buffer configuration and transmission parameters, the system can adapt to different sizes and types of data transmission requirements. This flexible transmission framework provides a general technical solution for FPGA application development. This adaptive transmission method not only improves the processing efficiency of the system, but also enhances the practical value of the solution.

[0080] In an embodiment of the PCIe interface implementation method for FPGA high-speed data transmission in the present application, the following contents can be specifically included:

[0081] Step S301: When the system starts, map the physical page where the descriptor queue is located to the process virtual address space through the memory management unit, establish a page table entry and set the access permission flag bit, allocate a virtual address interval in the user space as the mapping area of the descriptor queue, write the start address and length information of the mapping area to the device base address register, configure the burst transmission length parameter according to the bus bit width, and set the mask value of address boundary alignment;

[0082] Step S302: Create an interrupt descriptor table and set an interrupt gate descriptor, write an entry address of an interrupt service program into an interrupt vector table, establish a mapping relationship between a task identification and an interrupt number, configure a triggering mode and a priority of an interrupt controller, write a state update and a notification logic after data transfer in an interrupt processing function, and register the interrupt processing function to a system interrupt processing chain table.

[0083] Optionally, the embodiment innovatively designs a set of interrupt management schemes based on memory mapping to solve the problems of low address mapping efficiency, large interrupt processing delay, and unreasonable system resource configuration in FPGA data transmission. In the aspect of mapping efficiency evaluation, the embodiment designs a mapping performance score formula: Map_Score = α × (Access_Speed / Direct_Speed) + β × (TLB_Hit_Rate) + γ × (Page_Efficiency), wherein α, β, and γ are weight coefficients, respectively representing an access speed ratio, a TLB hit rate, and a page utilization rate. Meanwhile, an interrupt processing score formula: IRQ_Efficiency = (Response_Time × Priority_Weight) / (Context_Switch + Handler_Execution) is introduced to optimize interrupt response efficiency.

[0084] The embodiment first realizes efficient descriptor access through a deeply optimized memory mapping mechanism. In the system startup phase, a memory management unit establishes a mapping relationship between a physical page and a virtual address space through a multi-level page table structure. In order to improve access efficiency, the system adopts a large page mapping technology to reduce the number of page table entries and the TLB miss rate. When establishing a page table entry, the system not only sets basic read-write permissions, but also configures cache attributes and access modes. For example, for frequently accessed descriptor regions, write-merge cache attributes are set to improve data write efficiency. When mapping a user space, the system realizes zero-copy access through a memory mapping file operation, avoiding data copy overhead between the kernel mode and the user mode. This optimized mapping mechanism provides an efficient access channel for descriptor queue management.

[0085] The embodiment innovatively realizes the transmission parameter configuration mechanism. The configuration of the device base address register adopts a segmented manner, which not only records the basic information of the mapping area, but also contains the access control parameters. The setting of the burst transmission length is based on the PCIe bus characteristics, and the optimal transmission unit size is determined through performance modeling. The address alignment requirement is forcibly realized through the mask value, ensuring that all transmission operations are performed on the legal address boundary. Especially in the processing of large-scale data transmission, this fine parameter configuration significantly improves the transmission efficiency. The system also establishes a parameter adaptive mechanism, which can dynamically adjust the configuration parameters according to the actual transmission situation.

[0086] The embodiment realizes efficient task synchronization through an optimized interrupt management mechanism. The interrupt descriptor table adopts a hierarchical structure, supporting interrupt priority management and nested processing. Each interrupt gate descriptor contains complete control information, including privilege level, stack switching parameters and handler entry address. When configuring the interrupt vector table, the system adopts a vectorized interrupt handling method to reduce interrupt distribution overhead. The mapping of task identification and interrupt number is realized by using a hash table, supporting fast interrupt association query. This efficient interrupt organization mechanism significantly reduces the task synchronization overhead.

[0087] The embodiment establishes a complete interrupt handling framework. The configuration of the interrupt controller fully considers the real-time requirements, and adopts an edge trigger method to avoid interrupt loss. The priority setting is based on the importance of the task, ensuring that critical tasks can respond in time. The interrupt handling function adopts a lightweight design, mainly completing state update and notification operations, and complex data processing is postponed to non-interrupt context for execution. This optimized processing mechanism ensures the real-time response capability of the system.

[0088] The embodiment provides an innovative solution for data transmission. Through optimized memory mapping and interrupt handling mechanisms, the system can efficiently manage complex data transmission tasks. This reliable management mechanism significantly improves the communication efficiency between FPGA and host.

[0089] The embodiment realizes transmission acceleration through full-process optimization. From address mapping to interrupt handling, each link is carefully designed and optimized to ensure efficient operation of the entire transmission process. This systematic optimization strategy provides reliable system support for FPGA application development.

[0090] The management method adopted in the embodiment has good scalability. By adjusting the mapping parameters and interrupt configuration, the system can adapt to different sizes and types of transmission requirements. This flexible management framework provides a general technical solution for FPGA application development. This adaptive management method not only improves the processing efficiency of the system, but also enhances the practical value of the solution.

[0091] In the embodiment of the FPGA high-speed data transmission PCIe interface implementation method of the application, the following contents can be further included:

[0092] Step S401: Extracting red, green and blue three-channel pixel values according to the original format of the image data, calculating the corresponding gray value of each pixel point by using the weighted average method, writing the gray value into a preprocessing buffer, determining the data block size based on the image resolution, calculating the number of data blocks in the horizontal and vertical directions, establishing a data block index table in the preprocessing buffer, and recording the starting position and size information of each data block;

[0093] Step S402: Filling the boundary pixels around each data block to form an overlapping area, generating a globally monotonically increasing timestamp count value, writing the timestamp count value into the data block header, establishing a mapping relationship table between the data block and the timestamp, calculating the offset address of the data block in the direct memory access buffer according to the spatial position information of the data block, and writing the data block with the boundary pixels and the timestamp information into the storage position pointed by the offset address.

[0094] Optionally, the embodiment innovatively designs a data preprocessing scheme based on multi-level cache to solve the problems of inaccurate color conversion, low data block efficiency and unreasonable boundary processing in image data preprocessing. In the aspect of color conversion evaluation, the embodiment designs a gray conversion score formula: Gray_Quality = a x (R_Weight x R + G_Weight x G + B_Weight x B) / (R + G + B) + b x (Edge_Preservation) + g x (Contrast_Enhancement), wherein a, b and g are weight coefficients, R, G and B represent red, green and blue channel values respectively, and the formula is used to evaluate the gray conversion quality. Meanwhile, a block division score formula: Block_Efficiency = (Processing_Speed x Memory_Usage) / (Block_Size + Overlap_Cost) is introduced to optimize the data block size.

[0095] The embodiment first realizes high-quality color conversion through a deeply optimized image processing mechanism. For different image formats, the system uses a special channel extraction algorithm to ensure accurate separation of RGB data. When performing grayscale conversion, the system not only considers the sensitivity of the human eye to different colors, but also dynamically adjusts the weight coefficients according to the local features of the image. For example, for high-light areas, the system will reduce the weight of the green channel to avoid overexposure; for dark areas, it will increase the weight of the red channel to maintain details. The converted grayscale values are written to the preprocessing buffer through a multi-level cache mechanism, and continuous pixel data is processed in a pipeline manner. This optimized color processing mechanism significantly improves the quality of image conversion.

[0096] The embodiment innovatively realizes a data block division mechanism. Based on image resolution and processing requirements, the system uses an adaptive block size calculation method. The determination of block size not only considers processing efficiency, but also takes into account data transmission and storage characteristics. For example, for high-resolution images, the system will choose a larger block size to reduce management overhead; for complex texture areas, a smaller block size will be used to improve processing accuracy. When calculating the number of data blocks, the system handles boundary conditions through an optimized integer division algorithm to ensure coverage of the entire image area. The data block index table uses a multi-level hash structure to support fast location queries and update operations. This flexible division mechanism provides a reliable data organization foundation for subsequent processing.

[0097] The embodiment realizes high-quality data overlap through optimized boundary processing. When performing boundary padding, the system uses different padding strategies based on the position of the data block. For data blocks at the image edge, the system generates padding pixels through mirror copying or boundary extension; for internal data blocks, the system calculates the optimal overlap area size to ensure processing continuity. The generation of timestamps uses atomic operations to ensure uniqueness in parallel processing environments. The system establishes a timestamp mapping table to realize accurate tracking and management of data blocks. This complete boundary processing mechanism significantly improves the quality of data processing.

[0098] The embodiment establishes an efficient storage management framework. When calculating the storage offset address, the system considers data alignment and access efficiency, and uses an optimized addressing algorithm to quickly locate the storage position. Data block writing uses batch transmission, and DMA mechanism is used to realize efficient data transfer. Especially for the processing of a large number of data blocks, the system reduces waiting time through predictive writing to improve overall processing efficiency. This optimized storage mechanism provides reliable storage support for data processing.

[0099] The embodiment provides an innovative solution for image preprocessing. Through optimized data processing and management mechanisms, the system can efficiently process various image data. This reliable processing mechanism significantly improves the quality and efficiency of image processing.

[0100] This embodiment realizes processing acceleration through full-process optimization. From color conversion to data storage, each link is carefully designed and optimized to ensure efficient operation of the entire preprocessing process. This systematic optimization strategy provides a reliable data preparation scheme for FPGA image processing.

[0101] The preprocessing method adopted in this embodiment has good scalability. By adjusting the processing parameters and storage strategy, the system can adapt to different scales and types of image processing requirements. This flexible processing framework provides a general technical solution for FPGA application development. This adaptive processing method not only improves the processing efficiency of the system, but also enhances the practical value of the solution.

[0102] In an embodiment of the PCIe interface implementation method for FPGA high-speed data transmission of the present application, the following contents can be specifically included:

[0103] Step S501: Locate the physical address of the doorbell register in the base address register space, write the task start flag bit to the specified position of the doorbell register, configure the trigger mode of the doorbell register as edge trigger, create a task status register to record the execution phase of the current task, establish an associated mapping between the doorbell register and the task status register, and monitor the value of the task status register to confirm whether the field programmable gate array responds to the task signal;

[0104] Step S502: After the field programmable gate array receives the task signal, it reads a preset number of descriptors from the descriptor queue, temporarily stores the descriptors in the first-in-first-out cache, configures the source address and target address of the burst transmission channel according to the address information in the descriptor, divides the data transmission unit according to the burst transmission length parameter, writes the data blocks into the continuous storage space of the dynamic random access memory in turn, and updates the values of the memory address pointer and the data counter.

[0105] Optionally, the embodiment is directed to the problem of unreliable FPGA task triggering, low data transmission efficiency and frequent storage access conflicts, and innovatively designs a task control scheme based on the doorbell mechanism. In terms of task control evaluation, the embodiment designs a trigger efficiency score formula: Trigger_Score = a x (Response_Time / Max_Time) + β x (Signal_Stability) + γ x (Status_Accuracy), wherein a, β, and γ are weight coefficients, respectively representing response time ratio, signal stability, and status accuracy. At the same time, a transmission efficiency score formula: Transfer_Efficiency = (Burst_Length x Channel_Utilization) / (Setup_Overhead + Memory_Latency) is introduced to optimize data transmission performance.

[0106] The embodiment first realizes reliable task triggering through a deeply optimized register management mechanism. In the base address register space, the system organizes various control registers in a segmented mapping manner. The physical address of the doorbell register is calculated by base address offset to ensure the accuracy of access. When writing the task flag, the system uses atomic operation to avoid flag confusion caused by multi-task concurrency. The edge trigger configuration of the doorbell register ensures the reliable detection of the signal, and the system improves the accuracy of triggering through double-edge sampling technology. In terms of task state recording, the status register is designed with multiple fields, which not only contains the basic execution state, but also records detailed progress information. This fine state management mechanism provides a reliable monitoring means for task control.

[0107] The embodiment innovatively realizes the state association mechanism. A close mapping relationship is established between the doorbell register and the task status register, and the state synchronization is realized through shared control bits. The system manages the task execution process in a state machine manner, and each state transition is accompanied by corresponding register update operation. Especially when dealing with complex task sequences, this association mechanism can accurately track the task execution process. The system also realizes the state readback mechanism, which monitors the response of the FPGA through polling to ensure correct task startup.

[0108] The embodiment realizes efficient storage access through an optimized data transmission mechanism. After receiving a task signal, the FPGA first pre-fetches descriptors in batches from the descriptor queue, reducing queue access overhead. The pre-fetched descriptors are temporarily stored in a first-in-first-out cache, and multiple transmission requests are processed through a pipeline. When configuring the transmission channel, the system sets the source address and target address according to the descriptor information, and optimizes the burst transmission parameters. The data transmission adopts a block strategy, dividing large blocks of data into data units suitable for burst transmission, improving bus utilization. This optimized transmission mechanism significantly improves data throughput.

[0109] The embodiment establishes a complete storage management framework. In dynamic random access memory, the system uses a continuous storage strategy to organize data blocks, reducing address translation overhead. The allocation of storage space takes into account the data access pattern, avoiding fragmentation problems at runtime through a pre-allocation mechanism. The update of address pointers and data counters uses atomic operations to ensure data consistency during multi-channel access. This reliable storage management mechanism provides stable storage support for data transmission.

[0110] The embodiment provides an innovative solution for task control. Through an optimized trigger mechanism and transmission control, the system can efficiently manage complex data processing tasks. This reliable control mechanism significantly improves the efficiency of FPGA data processing.

[0111] The embodiment realizes task acceleration through full-process optimization. From task triggering to data storage, each link is carefully designed and optimized to ensure efficient operation of the entire processing process. This systematic optimization strategy provides a reliable task management solution for FPGA application development.

[0112] The control method used in the embodiment has good scalability. By adjusting trigger parameters and transmission strategies, the system can adapt to different sizes and types of processing requirements. This flexible control framework provides a general technical solution for FPGA application development. This adaptive control method not only improves the processing efficiency of the system, but also enhances the practical value of the solution.

[0113] In an embodiment of the PCIe interface implementation method for FPGA high-speed data transmission of the present application, the following contents can be specifically included:

[0114] Step S601: Divide the two-dimensional cache array space inside the field programmable gate array, calculate the storage location in the two-dimensional cache array according to the row and column coordinates of the data block, parse the timestamp information in the data block header to obtain the processing order, establish a mapping table of the timestamp and the storage location, write the processed data block into the corresponding position of the two-dimensional cache array according to the timestamp order, maintain a bitmap table of the data block writing state, and record the spatial distribution of the written data block;

[0115] Step S602: The field programmable gate array writes the processing status of the data block into the status field of the status register, generates an interrupt request signal and sends it to the host through the interrupt controller, the status tracker reads the bitmap table to check the writing of the data block, calculates the interval value between adjacent timestamps to determine whether the data block is missing, scans the timestamp identifier in the two-dimensional cache array to determine whether the data block is repeatedly written, and updates the detection result to the error flag bit of the status register.

[0116] Optionally, the embodiment innovatively designs a data management scheme based on two-dimensional cache to solve the problems of complex cache management, difficult status tracking and unreliable data integrity verification in FPGA data processing. In terms of cache efficiency evaluation, the embodiment designs a storage score formula: Cache_Score = α × (Access_Speed / Max_Speed) + β × (Space_Utilization) + γ × (Data_Locality), wherein α, β and γ are weight coefficients, respectively representing access speed, space utilization and data locality. At the same time, an integrity verification score formula: Validation_Quality = (Detection_Accuracy × Processing_Speed) / (Missing_Count + Duplicate_Count) is introduced to evaluate the data verification effect.

[0117] The embodiment first realizes efficient data organization through a deeply optimized cache management mechanism. The division of the two-dimensional cache array fully considers the spatial characteristics of the data block and organizes the data in a row-first storage manner. The size of the cache space is dynamically adjusted according to actual processing requirements to ensure resource utilization. When positioning the data block, the system uses an optimized coordinate mapping algorithm to convert two-dimensional coordinates into linear addresses. This conversion considers the efficiency of hardware implementation and uses displacement and addition operations instead of complex multiplication operations. For frequently accessed data regions, the system reserves a fast access channel to reduce access delay. Especially when processing large-scale data, the system avoids high resource occupation through a block processing mechanism to ensure the stability of processing. This optimized cache management mechanism provides a reliable storage foundation for data processing.

[0118] The embodiment innovatively realizes a timestamp management mechanism. Efficient bit operation is adopted for parsing timestamp information to quickly extract processing order information. The system establishes a bidirectional mapping relationship from timestamp to storage location, supporting fast lookup based on timestamp and reverse tracking based on location. During data writing, the system strictly organizes data according to timestamp order to ensure the orderliness of processing. The bitmap table is maintained in a compressed storage mode, and each bit represents the state of the corresponding data block. This compact state representation not only saves storage space but also supports fast state query and update. For parallel processing scenarios, the system ensures the consistency of bitmap table update through atomic operations. This complete management mechanism significantly improves the reliability of data processing.

[0119] The embodiment realizes reliable data verification through optimized state tracking. The state register adopts a multi-field design, recording not only the basic processing state but also detailed error information. The generation of interrupt requests adopts an edge-triggered mode to avoid loss of interrupt signals. The state tracker checks data integrity through an efficient scanning algorithm, including calculating timestamp intervals to judge data loss and comparing timestamp identifiers to detect repeated writing. This multi-dimensional verification mechanism ensures the accuracy of data processing. In particular, when handling abnormal situations, the system can quickly locate the problem and start the recovery process, improving the fault tolerance of the system.

[0120] The embodiment establishes a complete error handling framework. The error flag bit of the state register adopts a hierarchical design, supporting independent marking of different types of errors. When data loss is detected, the system records the missing location and timestamp information to facilitate subsequent data recovery. For repeated writing, the system determines which version of data to keep by comparing data content. This fine error handling mechanism ensures the reliability of data processing.

[0121] The embodiment provides an innovative solution for data management. Through optimized cache organization and state management mechanism, the system can efficiently process complex data streams. This reliable management mechanism significantly improves the quality and efficiency of FPGA data processing.

[0122] The embodiment realizes management acceleration through full-process optimization. From data organization to error handling, each link is carefully designed and optimized to ensure efficient operation of the entire management process. This systematic optimization strategy provides a reliable data management solution for FPGA application development.

[0123] The management method adopted in this embodiment has good scalability. By adjusting the cache parameters and verification strategies, the system can adapt to different scales and types of data processing requirements. This flexible management framework provides a general technical solution for FPGA application development. This adaptive management method not only improves the processing efficiency of the system, but also enhances the practical value of the solution.

[0124] In an embodiment of the PCIe interface implementation method for FPGA high-speed data transmission of the present application, the following contents can be specifically included:

[0125] Step S701: The host reads the status field of the status register through the interrupt service program, parses the address pointer in the status register to obtain the storage position of the data block in the dynamic random access memory, configures the transmission parameters of the host-side direct memory access controller, establishes the descriptor chain table for data block reading, points the target address to the receiving buffer of the host side, starts the direct memory access controller to perform data reading operation, and judges whether the data block is read according to the transmission completion flag;

[0126] Step S702: The host writes the read completion flag bit into the command register, sends the content of the command register to the field programmable gate array through the bus interface, and the field programmable gate array clears the status flag bit of the corresponding data block after receiving the data read completion signal, releases the storage space in the two-dimensional cache array, updates the value of the data block counter, and resets the related status bits in the status register.

[0127] Optionally, the embodiment innovatively designs a set of data read-back scheme based on interruption to solve the problems of state analysis delay, transmission control complexity and resource release delay in FPGA data read-back. In the aspect of data read-back evaluation, the embodiment designs a read-back efficiency scoring formula: Read_Score = α × (Response_Speed / Max_Speed) + β × (Buffer_Utilization) + γ × (Resource_Recovery), wherein α, β and γ are weight coefficients, respectively representing response speed ratio, buffer utilization and resource recovery efficiency. At the same time, the release efficiency scoring formula: Release_Efficiency = (Memory_Recovery × Status_Update_Speed) / (Clear_Overhead + Sync_Delay) is introduced to optimize the resource release performance.

[0128] The embodiment first realizes efficient state management through a deeply optimized interrupt handling mechanism. The interrupt service program adopts a lightweight design and mainly completes the reading and analysis of the state register. The state field is organized in a bit field structure to support fast state extraction and judgment. When analyzing the address pointer, the system uses bitmap indexing technology to quickly locate the position of the data block in the memory. This efficient state analysis mechanism significantly reduces the data positioning time. Especially when processing a large number of data blocks, the system uses a batch state checking mechanism to obtain the state information of multiple data blocks at a time, avoiding frequent register access operations.

[0129] The embodiment innovatively realizes a transmission configuration mechanism. The configuration of the host-side DMA controller adopts a parameter preset method to select the optimal transmission parameters according to the characteristics of the data block. The construction of the descriptor chain table considers the continuity of the data, and uses aggregated transmission for continuously stored data blocks to reduce descriptor overhead. The management of the receiving buffer adopts a circular buffer strategy to support continuous data reception operations. The system monitors the data reading progress in real time through the establishment of a transmission completion flag detection mechanism. This optimized transmission mechanism significantly improves the data readback efficiency.

[0130] The embodiment realizes reliable state synchronization through an optimized command delivery mechanism. The writing of the completion flag adopts atomic operations to ensure the atomicity of operations in a multi-task environment. The command register design supports multi-field combination, which can deliver multiple control information at the same time. The transmission through the bus interface adopts a high-priority channel to ensure timely delivery of command information. After receiving the completion signal, the FPGA controls a series of cleaning operations through the state machine. This reliable command delivery mechanism ensures the state synchronization between the host and the FPGA.

[0131] The embodiment establishes a complete resource release framework. The clearing of the state flag bit adopts a batch operation method to support the simultaneous release of multiple data blocks. The space recycling of the two-dimensional cache array is managed through the free block chain table to ensure the effective use of storage space. The update of the data block counter adopts atomic operations to avoid counting errors caused by concurrent access. The reset of the state register adopts a mask operation to only update the relevant state bits and keep other control information unchanged. This fine release mechanism provides reliable protection for the continuous operation of the system.

[0132] The embodiment provides an innovative solution for data readback. Through the optimized state management and resource release mechanism, the system can efficiently handle data readback tasks. This reliable readback mechanism significantly improves the integrity of FPGA data processing.

[0133] This embodiment realizes readback acceleration through full-process optimization. From state checking to resource release, each link is carefully designed and optimized to ensure efficient operation of the entire readback process. This systematic optimization strategy provides a reliable data readback solution for FPGA application development.

[0134] The readback method adopted in this embodiment has good scalability. By adjusting the processing parameters and release strategy, the system can adapt to different scales and types of data readback requirements. This flexible readback framework provides a general technical solution for FPGA application development. This adaptive readback method not only improves the processing efficiency of the system, but also enhances the practical value of the solution.

[0135] In order to effectively solve the deficiencies of traditional technology in transmission efficiency, data management and state monitoring, and significantly improve the performance and reliability of the PCIe interface, the present application provides an embodiment of a PCIe interface implementation device for FPGA high-speed data transmission, which implements all or part of the content of the PCIe interface implementation method for FPGA high-speed data transmission, as shown in Figure 2 , The FPGA high-speed data transmission PCIe interface implementation device specifically includes the following contents:

[0136] The task mapping module 10 is used to allocate a host physical continuous cache area and register the physical continuous cache area as a direct memory access buffer, establish a descriptor queue in the direct memory access buffer, the descriptor queue records data source address, target address and length information, maps the descriptor queue to user space through memory mapping, configures burst transmission length and address alignment mode, binds task identification and interrupt processing function;

[0137] The data cache module 20 is used to convert image data into gray value and divide it into multiple data blocks according to the preset size, add boundary pixels to each data block and set a timestamp, write the data block into the direct memory access buffer, trigger the doorbell register to send a task signal to the field programmable gate array, the field programmable gate array prefetches descriptors from the descriptor queue to the first-in-first-out cache, and writes the data block into the specified position in the dynamic random access memory through the burst transmission channel based on the descriptor information;

[0138] The data writing module 30 is used to construct a two-dimensional cache array and write the processed data block into the corresponding position according to the timestamp, the field programmable gate array writes the data block state into the state register and triggers the interrupt signal, the state tracker detects the absence and repetition of the data block, the host reads the data block from the dynamic random access memory according to the content of the state register, and the host sends a data read completion signal to the field programmable gate array.

[0139] From the above description, the FPGA high-speed data transmission PCIe interface implementation device provided by the embodiment of the application can realize safe and efficient transmission of data by innovatively designing a direct memory access mechanism, registering and describing a physical continuous cache area, and managing a descriptor queue. A timestamp-based data block organization strategy is constructed, a burst transmission channel and a state tracker are combined, and a reliable data transmission control system is established. A state register and an interrupt mechanism are introduced, real-time state monitoring and data synchronization are performed, and the integrity of the transmission process and the information security are ensured. The method effectively solves the deficiencies of the traditional technology in transmission efficiency, data management, and state monitoring, and significantly improves the performance and reliability of the PCIe interface while protecting the data security.

[0140] From the hardware level, in order to effectively solve the deficiencies of the traditional technology in transmission efficiency, data management, and state monitoring, and significantly improve the performance and reliability of the PCIe interface, the application provides an embodiment of an electronic device for implementing all or part of the contents of the FPGA high-speed data transmission PCIe interface implementation method, which specifically includes the following contents:

[0141] A processor, a memory, a communications interface, and a bus; wherein the processor, the memory, and the communications interface complete mutual communication through the bus; the communications interface is used to realize information transmission between the FPGA high-speed data transmission PCIe interface implementation device and related devices such as a core business system, a user terminal, and a related database; the logic controller can be a desktop computer, a tablet computer, a mobile terminal, and the like, and the embodiment is not limited thereto. In the embodiment, the logic controller can be implemented by referring to the embodiments of the FPGA high-speed data transmission PCIe interface implementation method and the FPGA high-speed data transmission PCIe interface implementation device, the contents of which are incorporated herein, and the repeated parts will not be described herein.

[0142] It can be understood that the user terminal can include a smart phone, a tablet electronic device, a network set-top box, a portable computer, a desktop computer, a personal digital assistant (PDA), a vehicle-mounted device, a smart wearable device, and the like. The smart wearable device can include smart glasses, a smart watch, a smart bracelet, and the like.

[0143] In actual application, part of the PCIe interface implementation method of FPGA high-speed data transmission can be executed on the electronic device as described above, or all operations can be completed in the client device. Specifically, the processing capacity of the client device and the use scenario of the user can be selected. The present application does not limit this. If all operations are completed in the client device, the client device can further include a processor.

[0144] The client device described above can have a communication module (i.e., a communication unit) and can be communicatively connected with a remote server to realize data transmission with the server. The server can include a server of a task scheduling center, and can also include a server of an intermediate platform in other implementation scenarios, such as a server of a third-party server platform communicatively connected with the server of the task scheduling center. The server can include a single computer device, or a server cluster composed of multiple servers, or a distributed server structure.

[0145] Figure 3 A schematic block diagram of a system configuration of the electronic device 9600 of an embodiment of the present application is shown in FIG. 9. As shown in FIG. 9, the electronic device 9600 can include a central processor 9100 and a memory 9140; the memory 9140 is coupled to the central processor 9100. It is worth noting that the structure shown in FIG. 9 is exemplary; other types of structures can also be used to supplement or replace the structure to realize telecommunication functions or other functions. Figure 3 Figure 3 The structure shown in FIG. 9 is exemplary; other types of structures can also be used to supplement or replace the structure to realize telecommunication functions or other functions.

[0146] In an embodiment, the PCIe interface implementation method function of FPGA high-speed data transmission can be integrated into the central processor 9100. The central processor 9100 can be configured to perform the following control:

[0147] Step S101: allocating a host physical continuous cache area and registering the physical continuous cache area as a direct memory access buffer, establishing a descriptor queue in the direct memory access buffer, the descriptor queue recording data source address, target address and length information, mapping the descriptor queue to a user space through memory mapping, configuring burst transmission length and address alignment mode, binding task identification and interrupt processing function;

[0148] ​Step S102: converting the image data into gray scale values and dividing the image data into a plurality of data blocks according to a preset size, adding boundary pixels to each of the data blocks and setting a time stamp, writing the data blocks into the DMA buffer, triggering a doorbell register to send a task signal to the FPGA, the FPGA pre-fetching descriptors from the descriptor queue to a FIFO cache, and writing the data blocks into a specified location in the DRAM through a burst transfer channel based on the descriptor information;

[0149] Step S103: constructing a two-dimensional cache array and writing the processed data blocks into corresponding positions according to the time stamp, the FPGA writing the data block state into a state register and triggering an interrupt signal, detecting the absence and repetition of the data blocks through a state tracker, the host reading the data blocks from the DRAM according to the content of the state register, and the host sending a data read completion signal to the FPGA.

[0150] As can be seen from the above description, the electronic device provided by the embodiments of the present application realizes safe and efficient transmission of data by innovatively designing a DMA mechanism, through physical continuous cache area registration and descriptor queue management. A data block organization strategy based on a time stamp is constructed, a burst transfer channel and a state tracker are combined, and a reliable data transmission control system is established. A state register and an interrupt mechanism are introduced, real-time state monitoring and data synchronization are performed, and the integrity of the transmission process and the information security are ensured. The method protects data security while effectively solving the deficiencies of traditional technologies in terms of transmission efficiency, data management and state monitoring, and significantly improves the performance and reliability of the PCIe interface.

[0151] In another embodiment, the PCIe interface implementation device for FPGA high-speed data transmission can be configured separately from the central processor 9100, for example, the PCIe interface implementation device for FPGA high-speed data transmission can be configured as a chip connected with the central processor 9100, and the function of the PCIe interface implementation method for FPGA high-speed data transmission is realized through the control of the central processor.

[0152] As shown in Figure 3 , the electronic device 9600 can further include a communication module 9110, an input unit 9120, an audio processor 9130, a display 9160, and a power supply 9170. It should be noted that the electronic device 9600 does not necessarily include all the components shown in Figure 3 ; in addition, the electronic device 9600 can further include components not shown in Figure 3 , which can be referred to the prior art.

[0153] As shown in Figure 3As shown, the central processing unit 9100, which is sometimes also referred to as a controller or operation control, can include a microprocessor or other processor device and / or logic device, which receives input and controls the operation of the various components of the electronic device 9600.

[0154] The memory 9140, for example, can be one or more of a buffer, a flash memory, a hard drive, a removable media, a volatile memory, a non-volatile memory, or other suitable device. Information relating to failures can be stored, and in addition, programs for executing the information can be stored. The central processing unit 9100 can execute the programs stored in the memory 9140 to achieve information storage or processing, etc.

[0155] The input unit 9120 provides input to the central processing unit 9100. The input unit 9120 is, for example, a key or touch input device. The power supply 9170 is used to provide power to the electronic device 9600. The display 9160 is used to display display objects such as images and text. The display can be, for example, an LCD display, but is not limited thereto.

[0156] The memory 9140 can be a solid state memory such as a read only memory (ROM), a random access memory (RAM), a SIM card, etc. It can also be a memory that retains information even when power is off, can be selectively erased, and is provided with more data, examples of which are sometimes referred to as EPROM, etc. The memory 9140 can also be some other type of device. The memory 9140 includes a buffer memory 9141 (sometimes referred to as a buffer). The memory 9140 can include an application / function storage section 9142 for storing application programs and function programs or for executing the flow of the operation of the electronic device 9600 by the central processing unit 9100.

[0157] The memory 9140 can also include a data storage section 9143 for storing data such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. A driver program storage section 9144 of the memory 9140 can include various driver programs of the electronic device for communication functions and / or for executing other functions of the electronic device such as a messaging application, an address book application, etc.

[0158] The communication module 9110 is a transmitter / receiver that transmits and receives signals via an antenna 9111. The communication module 9110 (transmitter / receiver) is coupled to the central processing unit 9100 to provide input signals and receive output signals, which can be the same as in the case of a conventional mobile communication terminal.

[0159] Based on different communication technologies, multiple communication modules 9110, such as a cellular network module, a Bluetooth module, and / or a wireless local area network module, etc., can be provided in the same electronic device. The communication module 9110 (transmitter / receiver) is also coupled to a speaker 9131 and a microphone 9132 via an audio processor 9130 to provide audio output via the speaker 9131 and to receive audio input from the microphone 9132, thereby enabling typical telecommunication functions. The audio processor 9130 can include any suitable buffers, decoders, amplifiers, etc. In addition, the audio processor 9130 is also coupled to the central processor 9100, thereby enabling recording on-site via the microphone 9132 and playing stored sounds on-site via the speaker 9131.

[0160] The embodiment of the present application further provides a computer readable storage medium capable of implementing all steps of the PCIe interface implementation method for FPGA high-speed data transmission with the execution subject being a server or a client in the above-mentioned embodiment, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement all steps of the PCIe interface implementation method for FPGA high-speed data transmission with the execution subject being a server or a client in the above-mentioned embodiment, for example, the processor executes the computer program to implement the following steps:

[0161] Step S101: allocating a host physical continuous cache region and registering the physical continuous cache region as a direct memory access buffer, establishing a descriptor queue in the direct memory access buffer, recording data source address, target address and length information in the descriptor queue, mapping the descriptor queue to a user space through memory mapping, configuring burst transmission length and address alignment mode, and binding a task identifier and an interrupt processing function;

[0162] Step S102: converting image data into gray value and dividing the image data into multiple data blocks according to a preset size, adding boundary pixels to each data block and setting a timestamp, writing the data block into the direct memory access buffer, triggering a doorbell register to send a task signal to a field programmable gate array, and pre-fetching a descriptor from the descriptor queue to a first-in-first-out cache by the field programmable gate array, and writing the data block into a specified position in a dynamic random access memory through a burst transmission channel based on the descriptor information.

[0163] Step S103: constructing a two-dimensional cache array and writing the processed data block to the corresponding position according to the timestamp, the FPGA writes the data block state to the state register and triggers an interrupt signal, the state tracker detects the absence and repetition of the data block, and the host reads the data block from the DRAM according to the content of the state register, and the host sends a data read completion signal to the FPGA.

[0164] From the above description, the computer readable storage medium provided by the embodiments of the present application realizes safe and efficient transmission of data by innovatively designing a direct memory access mechanism, through physical continuous cache area registration and descriptor queue management. A data block organization strategy based on timestamps is constructed, combined with a burst transmission channel and a state tracker, to establish a reliable data transmission control system. The state register and interrupt mechanism are introduced, and through real-time state monitoring and data synchronization, the integrity of the transmission process and information security are ensured. This method effectively solves the deficiencies of traditional technologies in transmission efficiency, data management and state monitoring, etc., while protecting data security, significantly improving the performance and reliability of the PCIe interface.

[0165] The embodiments of the present application also provide a computer program product capable of implementing all steps of the PCIe interface implementation method for FPGA high-speed data transmission of the server or client in the above-mentioned embodiments. The computer program / instruction is executed by the processor to implement the steps of the PCIe interface implementation method for FPGA high-speed data transmission, for example, the computer program / instruction implements the following steps:

[0166] Step S101: allocating a host physical continuous cache area and registering the physical continuous cache area as a direct memory access buffer, establishing a descriptor queue in the direct memory access buffer, the descriptor queue recording data source address, target address and length information, mapping the descriptor queue to the user space through memory mapping, configuring the burst transmission length and address alignment mode, binding the task identifier and the interrupt processing function;

[0167] Step S102: converting image data into grayscale values and dividing them into multiple data blocks according to a preset size, adding boundary pixels to each data block and setting a timestamp, writing the data block into the direct memory access buffer, triggering the doorbell register to send a task signal to the FPGA, the FPGA pre-fetches descriptors from the descriptor queue to the first-in-first-out cache, and writes the data block into the specified position in the DRAM through the burst transmission channel based on the descriptor information;

[0168] Step S103: constructing a two-dimensional cache array and writing the processed data block to the corresponding position according to the timestamp, the FPGA writing the data block state to the state register and triggering an interrupt signal, detecting the absence and repetition of the data block by the state tracker, and the host reading the data block from the DRAM according to the content of the state register, and the host sending a data read completion signal to the FPGA.

[0169] From the above description, the computer program product provided by the embodiments of the present application realizes safe and efficient transmission of data by innovatively designing a direct memory access mechanism, through physical continuous cache area registration and descriptor queue management. A data block organization strategy based on a timestamp is constructed, a burst transmission channel and a state tracker are combined, and a reliable data transmission control system is established. A state register and an interrupt mechanism are introduced, real-time state monitoring and data synchronization are performed, and the integrity of the transmission process and information security are ensured. While protecting data security, the method effectively solves the deficiencies of traditional technologies in transmission efficiency, data management, and state monitoring, and significantly improves the performance and reliability of the PCIe interface.

[0170] Those skilled in the art will understand that the embodiments of the present application can be provided as a method, device, or computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0171] The present application is described with reference to flowcharts and / or block diagrams of the method, device (apparatus), and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The device that implements the functions specified in one or more flows and / or blocks Figure 1 The device that implements the functions specified in one or more flows and / or blocks

[0172] These computer program instructions can also be stored in a computer-readable memory that can cause the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction devices that implement the functions specified in the flowcharts and / or block diagrams.Figure 1 one or more processes and / or functions described in one or more blocks. Figure 1 one or more blocks.

[0173] These computer program instructions can also be loaded into computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable data processing devices to generate a computer implemented process, so that the instructions executed on the computer or other programmable data processing devices provide steps for implementing the function described in one or more processes and / or functions described in one or more blocks. Figure 1 one or more processes and / or functions described in one or more blocks. Figure 1 one or more blocks.

[0174] The principles and implementation manners of the present application are described in the specific embodiments. The above embodiment description is only used to help understand the method and core idea of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed. In summary, the content of the description should not be understood as a limitation of the present application.

Claims

1. A method for implementing a PCIe interface for high-speed data transmission of an FPGA, characterized in that, The method comprises: allocating a host physical continuous cache area and registering the physical continuous cache area as a direct memory access buffer, establishing a descriptor queue in the direct memory access buffer, the descriptor queue recording data source address, target address and length information, mapping the descriptor queue to a user space through memory mapping, configuring burst transmission length and address alignment mode, and binding task identification and interrupt processing function; converting image data into gray value and dividing into multiple data blocks according to preset size, adding boundary pixels to each data block and setting a timestamp, writing the data block into the direct memory access buffer, triggering a doorbell register to send a task signal to a field programmable gate array, the field programmable gate array pre-fetching a descriptor from the descriptor queue to a first-in-first-out cache, and writing the data block into a specified position in a dynamic random access memory through a burst transmission channel based on the descriptor information; constructing a two-dimensional cache array and writing a processed data block into a corresponding position according to the timestamp, the field programmable gate array writing a data block state into a state register and triggering an interrupt signal, detecting missing and repeated data blocks through a state tracker, the host reading the data block from the dynamic random access memory according to the content of the state register, and the host sending a data reading completion signal to the field programmable gate array.

2. The PCIe interface implementation method for FPGA high-speed data transmission according to claim 1, characterized in that, The allocation of the host physical continuous cache area and the registration of the physical continuous cache area as the direct memory access buffer, and the establishment of the descriptor queue in the direct memory access buffer, the descriptor queue recording data source address, target address and length information, comprise: acquiring a continuous physical address segment through a kernel module to traverse a system physical address space, establishing a mapping table of physical address to virtual address, allocating the physical address segment to a host as a physical continuous cache area, marking the attribute of the physical continuous cache area as non-swap in a host memory management unit, and registering the start address and length information of the physical continuous cache area to a direct memory access controller; configuring the direct memory access controller as a master device mode, dividing a data area and a descriptor area in the direct memory access buffer, establishing a descriptor linked list structure in the descriptor area, pointing a source address to the start position of the data area, pointing a target address to a storage space inside a field programmable gate array, and recording length information and direction control bits of data transmission in the descriptor linked list.

3. The PCIe interface implementation method for FPGA high-speed data transmission according to claim 1, characterized in that, The mapping of the descriptor queue to a user space through memory mapping, the configuration of burst transmission length and address alignment mode, and the binding of task identification and interrupt processing function comprise: The physical page where the descriptor queue is located is mapped to the process virtual address space by the memory management unit at system startup, a page table entry is established and an access permission flag bit is set, a virtual address interval is allocated in the user space as a mapping area of the descriptor queue, the start address and length information of the mapping area are written into the device base address register, a burst transfer length parameter is configured according to the bus bit width, and a mask value for address boundary alignment is set; An interrupt descriptor table is created and an interrupt gate descriptor is set, the entry address of an interrupt service program is written into an interrupt vector table, a mapping relationship between a task identifier and an interrupt number is established, the trigger mode and priority of an interrupt controller are configured, and state updating and notification logic after data carrying is completed is written in an interrupt processing function, and the interrupt processing function is registered in a system interrupt processing linked list.

4. The PCIe interface implementation method for FPGA high-speed data transmission according to claim 1, characterized in that, The image data is converted into gray values and divided into a plurality of data blocks according to a preset size, a boundary pixel is added to each data block, and a timestamp is set, and the data block is written into the direct memory access buffer, comprising: According to the original format of the image data, red, green and blue three-channel pixel values are extracted, a weighted average method is used to calculate the corresponding gray values of each pixel point, the gray values are written into a preprocessing buffer, the data block size is determined based on the image resolution, the number of data blocks in the horizontal and vertical directions is calculated, and a data block index table is established in the preprocessing buffer to record the starting position and size information of each data block; Boundary pixels are filled around each data block to form an overlapping area, a globally monotonically increasing timestamp count value is generated, the timestamp count value is written into the data block header, a mapping relationship table of the data block and the timestamp is established, the offset address of the data block in the direct memory access buffer is calculated according to the spatial position information of the data block, and the data block with the boundary pixel and the timestamp information are written into the storage location pointed by the offset address.

5. The PCIe interface implementation method for FPGA high-speed data transmission according to claim 1, characterized in that, The trigger doorbell register sends a task signal to the field programmable gate array, the field programmable gate array prefetches descriptors from the descriptor queue to the first-in-first-out cache, and writes the data block into the specified position in the dynamic random access memory through the burst transmission channel based on the descriptor information, comprising: The physical address of the doorbell register is located in the base address register space, the task start flag bit is written into the specified position of the doorbell register, the trigger mode of the doorbell register is configured as edge trigger, the task state register is created to record the execution stage of the current task, the association mapping between the doorbell register and the task state register is established, and whether the field programmable gate array responds to the task signal is confirmed by monitoring the value of the task state register; After receiving the task signal, the field programmable gate array reads a preset number of descriptors from the descriptor queue, temporarily stores the descriptors in the first-in-first-out cache, configures the source address and target address of the burst transmission channel according to the address information in the descriptor, divides the data transmission unit according to the burst transmission length parameter, writes the data block into the continuous storage space of the dynamic random access memory in sequence, and updates the values of the memory address pointer and the data counter.

6. The PCIe interface implementation method for FPGA high-speed data transmission according to claim 1, characterized in that, The two-dimensional cache array is constructed and the data block completed by processing is written in the corresponding position according to the timestamp, the field programmable gate array writes the data block state into the state register and triggers the interrupt signal, the absence and repetition of the data block are detected by the state tracker, and the method comprises the following steps: The two-dimensional cache array space is divided inside the field programmable gate array, the storage position in the two-dimensional cache array is calculated according to the row and column coordinates of the data block, the processing order is obtained by analyzing the timestamp information in the data block header, the mapping table of the timestamp and the storage position is established, the data block completed by processing is written in the corresponding position of the two-dimensional cache array according to the timestamp order, and the bitmap table of the data block writing state is maintained to record the spatial distribution of the data block written; The field programmable gate array writes the processing state of the data block into the state field of the state register, generates an interrupt request signal and sends it to the host through the interrupt controller, the state tracker reads the bitmap table to check the writing state of the data block, calculates the interval value between adjacent timestamps to determine whether the data block is absent, and scans the timestamp identifier in the two-dimensional cache array to determine whether the data block is repeatedly written, and the detection result is updated to the error flag bit of the state register.

7. The PCIe interface implementation method for FPGA high-speed data transmission according to claim 1, characterized in that, The host reads the data block from the dynamic random access memory according to the content of the state register, and the host sends a data read completion signal to the field programmable gate array, comprising: The host reads the state field of the state register through the interrupt service program, analyzes the address pointer in the state register to obtain the storage position of the data block in the dynamic random access memory, configures the transmission parameters of the host-side direct memory access controller, establishes the descriptor chain table of the data block reading, points the target address to the receiving buffer of the host side, starts the direct memory access controller to execute the data reading operation, and judges whether the data block is read according to the transmission completion flag; The host writes the read completion flag bit into the command register, sends the content of the command register to the field programmable gate array through the bus interface, the field programmable gate array clears the state flag bit of the corresponding data block after receiving the data read completion signal, releases the storage space in the two-dimensional cache array, updates the value of the data block counter, and resets the related state bits in the state register.

8. A PCIe interface implementation device for FPGA high-speed data transmission, characterized in that, The device comprises: A task mapping module is configured to allocate a physically continuous cache area on the host side and register the physically continuous cache area as a direct memory access buffer area, establish a descriptor queue in the direct memory access buffer area, record data source address, target address and length information in the descriptor queue, map the descriptor queue to the user space through memory mapping, configure burst transmission length and address alignment mode, bind task identification and interrupt processing function, and the like. The data cache module is configured to convert image data into gray values, divide the image data into a plurality of data blocks according to a preset size, add boundary pixels to each data block, set a timestamp for each data block, write the data blocks into the DMA buffer, trigger a doorbell register to send a task signal to the FPGA, and trigger the FPGA to prefetch descriptors from the descriptor queue to a FIFO cache, write the data blocks into a specified location in the DRAM through a burst transfer channel based on the descriptor information, and write data block states into a status register and trigger an interrupt signal. The data write module is configured to construct a two-dimensional cache array and write processed data blocks into corresponding locations according to the timestamps, the FPGA writes data block states into a status register and triggers an interrupt signal, a status tracker detects missing and repeated data blocks, and a host reads the data blocks from the DRAM according to the content of the status register and sends a data read completion signal to the FPGA.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to implement the steps of the PCIe interface implementation method for FPGA high-speed data transmission according to any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the PCIe interface implementation method for FPGA high-speed data transmission according to any one of claims 1 to 7.

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