Method and system for collaborative design of programming radio frequency circuits based on artificial intelligence

Abstract

The present application relates to the technical field of intelligent and industrial software, and particularly relates to a method and system for collaborative design and programming of a radio frequency circuit based on artificial intelligence, which comprises: generating an initial schematic diagram and code; training a circuit generation model; predicting candidate code segments; simulating and screening admitted segments; displaying the admitted segments and counting the operation frequency; adjusting the model based on the operation; and iteratively generating a target until the target is generated, wherein the design indicators are closely combined with the initial circuit schematic diagram and the structured code, the circuit generation model is trained using preprocessed data, intelligent prediction of the radio frequency circuit code segments is realized, high-quality code segments are dynamically screened in combination with the performance simulation results, and an adaptive feedback mechanism is formed based on the drag frequency and parameter modification frequency data in the user interaction. The present application effectively solves the problem of low design efficiency and high error rate caused by weak generalization ability of the circuit design result due to static training of the model and lack of performance closed-loop verification.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of intelligent and industrial software, and particularly relates to a method and system for collaborative design and programming of a radio frequency circuit based on artificial intelligence. BACKGROUND

[0002] With the rapid development of 5G communication, satellite navigation, Internet of Things and other high-frequency and high-speed applications, the position of radio frequency circuits in system integration is increasingly important, and the design complexity and precision requirements are significantly improved. At the same time, the chip development cycle is continuously compressed, which puts forward higher challenges to the efficiency and repeatability of circuit design. The traditional design method relying on human experience gradually shows problems such as low efficiency, high error rate, and limited optimization space when facing a huge design space, multi-dimensional performance constraints, and frequent iteration requirements. Therefore, a new technical path is urgently needed to improve the intelligent level of design, enhance the reliability and scalability of design, and support the continuous evolution of radio frequency systems towards high performance, low power consumption and miniaturization.

[0003] The patent document with the publication number CN113239651A discloses an artificial intelligence implementation method and system for circuit design, which includes: obtaining a circuit design topology graph of a historical stage, the circuit design topology graph being composed of multiple sub-circuit topology graphs; building a convolutional neural network for training the circuit design topology graph; constructing a sample database, the sample database including functional parameters of sub-circuits, names of each circuit element of the sub-circuit topology, and connection relationships between the circuit elements; inputting the sample database into the convolutional neural network to obtain a first feature model; inputting a circuit topology graph in the design into the first feature model to obtain circuit feature parameters; and comparing the circuit feature parameters with expected parameters and obtaining a corresponding determination result.

[0004] It can be seen that the artificial intelligence implementation method and system for circuit design have the following problems: the method is only based on the circuit topology graph for training, and cannot effectively combine circuit performance or simulation data to improve the determination accuracy; the method lacks a dynamic feedback mechanism and cannot adjust model parameters or optimization strategies according to the actual performance in the design process; the method uses a convolutional neural network to process circuit structure information, which is difficult to handle non-Euclidean graph structures and complex dependency relationships in circuit design; the functional parameters are mainly used for classification training and are not used to generate design suggestions or specific circuit structures, and the functional utilization rate is low; the determination result of the method is only a static output of whether it is qualified or not, and lacks guidance for circuit modification direction or optimization suggestions; the sample database built by the method is of static structure and cannot be continuously expanded and optimized as design data accumulates. SUMMARY

[0005] To this end, the application provides a method and system for collaborative design and programming of radio frequency circuits based on artificial intelligence, which introduces a model iteration mechanism combining multi-dimensional collection and circuit performance simulation to overcome the problem of low design efficiency and high error rate caused by weak generalization ability of circuit design results due to static model training and lack of performance closed-loop verification in the prior art.

[0006] To achieve the above-mentioned purpose, in one aspect, the application provides a method for collaborative design and programming of radio frequency circuits based on artificial intelligence, comprising:

[0007] Step S1, generating an initial circuit schematic and a structured code corresponding to a design index in real time according to the design index of the radio frequency circuit received in the visual interface;

[0008] Step S2, inputting the preprocessed initial circuit schematic, the structured code and the design index into a preset artificial intelligence architecture to train a circuit generation model;

[0009] Step S3, based on the real-time input design index, calling the circuit generation model for prediction and generating a plurality of candidate code segments;

[0010] Step S4, performing performance simulation on each of the candidate code segments through a preset simulation engine, and selecting a plurality of to-be-admitted code segments from all candidate code segments according to the simulation results and a preset expected threshold;

[0011] Step S5, displaying all the to-be-admitted code segments in the visual interface, and determining a plurality of prediction segments from all the to-be-admitted code segments according to the real-time drag frequency and real-time parameter modification frequency of each to-be-admitted code segment;

[0012] Step S6, adjusting the circuit generation model based on the proportion of the prediction segments in all to-be-admitted code segments and the preference index of each prediction segment;

[0013] Step S7, based on the adjusted circuit generation model, continue to perform steps S3 to S6 until a target circuit is generated;

[0014] In step S6, the preference index is determined based on the real-time drag frequency and real-time parameter modification frequency in the past preset update period.

[0015] Further, in step S4, the preset expected threshold is the optimal value of a plurality of reference performance values obtained by simulating and calculating each of the initial circuit schematics in the past preset threshold setting period using the preset simulation engine.

[0016] Further, when the radio frequency circuit is a filter, in step S4, the expected threshold includes an S-parameter threshold.

[0017] The S parameter threshold is an optimal S parameter obtained by using a CAE simulation engine to simulate and calculate each of the initial circuit schematics within the preset threshold setting period in the past.

[0018] Further, when the radio frequency circuit is a four-channel clock driver, in step S4, the expected threshold includes a timing parameter threshold;

[0019] The timing parameter thresholds are maximum clock jitter, maximum propagation delay, and maximum output skew obtained by simulating and calculating each of the initial circuit schematics within the past preset threshold setting period using an EDA simulation engine.

[0020] Furthermore, the step S2 includes:

[0021] Step S21: Obtain radio frequency circuit design cases within a preset historical period in the past, and extract their structured code snippets as training samples;

[0022] Step S22: performing random masking processing on the structured code in the training sample at a preset masking ratio to obtain a preprocessed code;

[0023] Step S23: inputting the preprocessed code, its corresponding initial circuit schematic, and design specifications into the preset artificial intelligence architecture to predict the masked code content and obtain a prediction result;

[0024] Step S24: Compare the prediction result with the original structured code snippet to calculate the prediction loss value, and update the model parameters of the real-time preset artificial intelligence architecture through the back propagation algorithm;

[0025] Step S25: When the predicted loss value does not decrease within consecutive preset training rounds, the training is terminated to obtain the circuit generation model.

[0026] Furthermore, in step S3, a preset prediction failure threshold is set. When the number of consecutive predictions exceeds the preset prediction failure threshold and the candidate code snippet that meets the preset expected threshold is still not screened out, a prompt for manual intervention in writing is issued.

[0027] Furthermore, the preset artificial intelligence architecture is a Transformer-based encoder-decoder architecture, including:

[0028] An encoder, composed of a stack of multiple encoder layers, for encoding the input sequence of the structured code and the design indicator into a fixed-length vector through word embedding, position encoding, and a multi-head attention mechanism;

[0029] A decoder stacked by multiple decoder layers, configured to generate a subsequent candidate code snippet by inputting embedding, positional encoding, mask multi-head attention mechanism and a Softmax layer, combining the encoder output and the generated sequence of structured code.

[0030] Further, the step S5 comprises:

[0031] Step S51, in each preset statistical period, the drag times and parameter modification times of each of the to-be-admitted code snippets are counted respectively, to obtain a plurality of real-time drag frequencies and a plurality of real-time parameter modification frequencies;

[0032] Step S52, the real-time drag frequencies and the real-time parameter modification frequencies are weighted and synthesized according to a preset preference weight, to calculate the preference scores of each of the to-be-admitted code snippets;

[0033] Step S53, all the to-be-admitted code snippets are sorted according to the preference scores from high to low, and a plurality of to-be-admitted code snippets with the highest scores are selected according to a preset score threshold as the predicted snippets.

[0034] Further, the step S6 comprises:

[0035] Step S61, in each of the preset update periods, the proportion of the selected predicted snippets in all the to-be-admitted code snippets is counted, to obtain a proportion coefficient of each predicted snippet;

[0036] Step S62, the proportion coefficient of each predicted snippet and its corresponding preference index are weighted and synthesized according to a preset fusion weight, to calculate a comprehensive influence factor of each predicted snippet;

[0037] Step S63, according to the comprehensive influence factor and a preset learning rate, a model parameter update gradient is constructed, and one or more gradient descent iterations are performed on the circuit generation model to adjust the model parameters, to obtain an adjusted circuit generation model.

[0038] On the other hand, the present application also provides a system for collaborative design and programming of radio frequency circuits based on artificial intelligence, comprising:

[0039] A first generation module, configured to generate an initial circuit schematic and a structured code corresponding to the design index in real time according to the design index of the radio frequency circuit received in the visual interface;

[0040] A training module connected with the first generation module, configured to input the preprocessed initial circuit schematic, the structured code and the design index into a preset artificial intelligence architecture to train a circuit generation model;

[0041] a prediction module connected with the training module, configured to invoke the circuit generation model to make a prediction and generate a plurality of candidate code segments based on the design indicators input in real time;

[0042] a screening module connected with the prediction module, configured to perform performance simulation on each of the candidate code segments through a preset simulation engine, and screen a plurality of to-be-admitted code segments from all the candidate code segments according to a simulation result and a preset expected threshold;

[0043] a determination module connected with the screening module, configured to display all the to-be-admitted code segments on a visual interface, and determine a plurality of predicted segments from all the to-be-admitted code segments according to real-time drag frequency and real-time parameter modification frequency of each to-be-admitted code segment;

[0044] an adjustment module connected with the determination module and the training module respectively, configured to adjust the circuit generation model based on a proportion of predicted segments in all the to-be-admitted code segments and a preference index of each of the predicted segments;

[0045] a second generation module connected with the prediction module, the screening module, the determination module and the adjustment module respectively, configured to continuously optimize based on a dynamic update result of the circuit generation model until a target circuit is generated.

[0046] Compared with the prior art, the beneficial effects of the present application are that by closely combining design indicators with initial circuit schematics and structured code, a circuit generation model is trained using preprocessed data to realize intelligent prediction of radio frequency circuit code segments; high-quality code segments are dynamically screened in combination with performance simulation results, and design preferences are accurately identified based on drag frequency and parameter modification frequency data in user interaction, model parameters are further adjusted, and a self-adaptive feedback mechanism is formed. The interaction of various parameters ensures that the model can not only generate code that meets the design indicators, but also continuously optimize the prediction effect according to actual use, improve the matching degree of design efficiency and circuit performance, promote the intelligentization and individualization of the radio frequency circuit design process, and effectively solve the problem of low design efficiency and high error rate caused by weak generalization ability of the circuit design result due to static training of the model and lack of performance closed-loop verification.

[0047] Further, by adopting a Transformer-based encoder-decoder architecture, the model can fully understand the semantic relationship between the structured code sequence and the design indicators. The encoder converts the input sequence into a context-aware high-dimensional representation through word embedding and position encoding, and uses a multi-head attention mechanism to effectively focus on different features, thereby enhancing the expression ability of the input information; the decoder then combines the existing code sequence based on the high-dimensional representation, controls the generation path with the mask mechanism, and outputs the next code fragment with the optimal probability in the Softmax layer. This architecture can improve the model's ability to model complex circuit semantics and the accuracy of code fragment generation, thereby providing high-quality candidates for subsequent simulation screening and optimization, and improving overall design efficiency and engineering applicability of the generated results.

[0048] Further, by introducing structured code fragments based on historical radio frequency circuit design cases during the model training phase and combining a random mask mechanism for self-supervised learning, the model's ability to recognize and complete circuit semantic patterns is effectively enhanced. Specifically, the setting of the mask ratio ensures that the model faces sufficient information missing challenges while retaining necessary context, thereby guiding it to learn the mapping relationship between key structural features and local function expressions; the prediction loss value, as a measure of the model's learning effect, is used in conjunction with a continuous round of descent monitoring mechanism to dynamically control the training convergence process, avoiding overfitting or undertraining. By continuously optimizing model parameters through backpropagation, the circuit generation model constructed has stronger generalization ability and structural completion accuracy in actual applications, and can quickly generate candidate code fragments that meet engineering rules and design intentions when faced with new design tasks, thereby improving the efficiency of collaborative design and the quality of the model from the source.

[0049] Further, by setting a preset prediction failure threshold, the prediction performance of the circuit generation model can be effectively monitored. When the number of consecutive predictions exceeds the threshold and still does not produce a candidate code fragment that meets the preset expected threshold, the system promptly triggers a human intervention prompt to ensure that the design process does not stall due to model prediction failure; this mechanism not only ensures the continuity and accuracy of the design, but also promotes human-machine collaboration, improving overall design efficiency and reliability.

[0050] Further, by dynamically setting the preset expected threshold value based on the historical optimal performance value, high-precision screening of the candidate code fragment performance can be achieved in step S4. By taking all initial circuit schematic simulation results in the past preset threshold setting period as the basis, the optimal reference performance is extracted as the current judgment basis, thereby logically establishing a closed-loop path of "historical performance accumulation-optimal value extraction-current screening optimization", which can effectively improve the matching degree between the simulation results and the target design requirements, avoid excessive screening or false acceptance caused by traditional static threshold setting, and further, the dynamic updating mechanism can continuously optimize the parameter judgment standard as the design progresses, improving the model self-adaptation ability and evolution efficiency.

[0051] Further, by introducing the S-parameter threshold value calculated based on the CAE simulation engine as the expected standard in the application scenario of the radio frequency circuit as a filter, the simulation data of multiple initial circuit schematics in the historical preset threshold setting period can be fully utilized to extract the optimal S-parameter under the target index as the performance reference. By generating a dynamic threshold value based on data, subjective bias caused by human experience setting is avoided, and the response capability and stability of different topological structures in actual application are reflected by aggregating the historical optimal solution, improving the precision and robustness of screening the code fragment to be accepted. Further, the S-parameter threshold value forms a closed-loop feedback relationship with the filter structure, material parameters, frequency range and other design dimensions, providing a quantifiable and traceable performance scale for the iterative optimization and circuit generation of subsequent models, strengthening the coupling mechanism between circuit performance and intelligent recommendation, and thus realizing a more engineering practical collaborative design optimization process.

[0052] Further, by introducing the timing parameter threshold value obtained based on the EDA simulation engine as the expected standard in the design scenario of the radio frequency circuit as a four-way clock driver, the high dependence of this type of circuit on clock accuracy and signal integrity can be fully reflected. Specifically, the maximum clock jitter, maximum propagation delay and maximum output skew are key indicators for measuring the stability and synchronization performance of the driver, and the three have a high coupling relationship: clock jitter directly affects the edge stability, propagation delay affects the consistency of the clock distribution path, and output skew reflects the symmetry control effect between output ports. By simulating a large number of initial schematics in the past preset threshold setting period and extracting the optimal reference performance, a dynamic optimization threshold system is automatically constructed, so that the circuit generation model can take the performance lower bound verified in engineering practice as a target constraint, thereby improving the timing correctness and system integration of the candidate code fragment. At the same time, a closed-loop deduction from the schematic structure to the key performance indicators is realized, significantly enhancing the structure-performance mapping capability of the model for timing circuits, and realizing more reliable and controllable automated collaborative design.

[0053] Further, by carefully counting the number of times of dragging and the number of times of parameter modification of the code fragments to be admitted, and combining the preset preference weight to calculate the preference score, the actual use preference and adjustment demand for each code fragment can be objectively reflected; then, the high-score code fragments are screened out as prediction fragments according to the preference score, which effectively improves the pertinence and accuracy of subsequent model training, thereby continuously optimizing the matching degree of circuit design and promoting the design process to be more efficient and meet the actual demand.

[0054] Further, by counting the proportion of the prediction fragments in all the code fragments to be admitted, combining the preference index corresponding to each prediction fragment, and calculating the comprehensive influence factor according to the preset fusion weight, the parameters of the circuit generation model are dynamically adjusted based on the influence factor and the preset learning rate. This process can effectively reflect the selection preference and use frequency of the user, promote continuous optimization of the model, and improve the accuracy and adaptability of code generation, so that the generated radio frequency circuit design is more in line with the actual demand, and the overall design efficiency and quality are improved.

[0055] Further, by modular construction, intelligent generation and iterative optimization of the radio frequency circuit are realized, and the modules work cooperatively, which not only realizes the generation of a structured circuit driven by design indicators, but also dynamically filters and updates the model based on simulation feedback and user behavior, so as to realize effective identification and continuous optimization of the candidate code fragments, and greatly improve the intelligent level of circuit design, generation efficiency, and controllability and reliability of the design results. BRIEF DESCRIPTION OF DRAWINGS

[0056] Figure 1 The flowchart of the method for programming a radio frequency circuit based on artificial intelligence collaborative design of the present embodiment;

[0057] Figure 2 The flowchart of step S2 of the present embodiment;

[0058] Figure 3 The flowchart of step S5 of the present embodiment;

[0059] Figure 4 The flowchart of step S6 of the present embodiment. DETAILED DESCRIPTION

[0060] In order to make the objects and advantages of the present application clearer, the present application will be further described below with reference to the embodiments; it should be understood that the specific embodiments described herein are only used to explain the present application, and do not limit the present application.

[0061] The preferred embodiments of the present application will be described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are only used to explain the technical principles of the present application, and do not limit the protection scope of the present application.

[0062] Referring to Figure 1 As shown in the flowchart of the method for co-designing and programming a radio frequency circuit based on artificial intelligence according to the present embodiment, the present embodiment provides a method for co-designing and programming a radio frequency circuit based on artificial intelligence, which comprises the following steps:

[0063] Step S1, generating an initial circuit schematic and a structured code corresponding to a design index in real time according to the design index of the radio frequency circuit received in the visual interface;

[0064] Step S2, inputting the preprocessed initial circuit schematic, the structured code and the design index into a preset artificial intelligence architecture to train a circuit generation model;

[0065] Step S3, based on the real-time input of the design index, calling the circuit generation model for prediction and generating a plurality of candidate code segments;

[0066] Step S4, performing performance simulation on each of the candidate code segments through a preset simulation engine, and selecting a plurality of to-be-admitted code segments from all candidate code segments according to the simulation results and a preset expected threshold;

[0067] Step S5, displaying all the to-be-admitted code segments in the visual interface, and determining a plurality of prediction segments from all the to-be-admitted code segments according to the real-time drag frequency and real-time parameter modification frequency of each to-be-admitted code segment;

[0068] Step S6, adjusting the circuit generation model based on the proportion of the prediction segments in all the to-be-admitted code segments and the preference index of each prediction segment;

[0069] Step S7, continuing to execute the steps S3 to S6 based on the adjusted circuit generation model until a target circuit is generated;

[0070] In the step S6, the preference index is determined based on the real-time drag frequency and real-time parameter modification frequency in the past preset update period.

[0071] In this embodiment, the design index is a set of quantitative performance parameters input by the designer in the visual interface, used to guide the generation of the initial circuit schematic and structured code and as a subsequent screening benchmark; the specific content of the index varies under different circuit types: when the radio frequency circuit is a filter, the design index preferably includes but is not limited to the center frequency (such as 2.4 GHz ± 50 MHz), the passband insertion loss (≤ 1.5 dB), the passband return loss (≥ 15 dB), and the out-of-band rejection (≥ 30 dB) S parameters; when the radio frequency circuit is a four-way clock driver, the timing performance index is emphasized, including the maximum clock jitter (≤ 100 fs), the maximum propagation delay (≤ 200 ps), and the maximum output skew (≤ 50 ps); To match this, the preset simulation engine is an electromagnetic / time domain or frequency domain performance evaluation module integrated in the system, the selection of which depends on the trade-off between simulation accuracy and response speed, preferably using a CAE S parameter simulation engine based on the fast multipole algorithm or an EDA simulation tool supporting parasitic parameter extraction and transient analysis, which can complete high-precision (0.01 dB level or picosecond level) parallel simulation of candidate schemes in batches, thereby providing reliable historical optimal thresholds for screening and model iteration.

[0072] The preset update period refers to the time window for triggering parameter update after the model performs several prediction-simulation-screening operations, the length of which depends on factors such as the number of candidate code fragments, simulation time consumption, designer interaction frequency, and system computing resources; it can usually be set to trigger once every 1 minute to every 5 minutes; in this embodiment, the preset update period is preferably set to every 3 minutes, in order to balance the real-time performance of design response and the stability of model convergence, which can ensure smooth human-computer interaction while timely absorbing the latest preference data and accelerating the adaptive direction of the circuit generation model to the optimal direction.

[0073] In this embodiment, first, in step S1, the design indicators of the radio frequency circuit (such as the center frequency, bandwidth, insertion loss of the filter, or jitter and delay of the clock driver, etc.) are received by the visualization interface, and the corresponding initial circuit schematic and its structured code are generated in real time; then, in step S2, the schematic, code and design indicators are input into the preset artificial intelligence architecture for training to obtain a circuit generation model that can predict circuit segments in real time; in step S3, the model outputs a plurality of candidate code segments in real time; in step S4, the system calls a preset simulation engine to perform performance simulation on each candidate segment, and combines the dynamically updated expected threshold to filter out a plurality of to-be-admitted code segments that meet the requirements; in step S5, these segments are displayed side by side on the interface, and the designer generates behavior data through drag-and-drop and parameter fine-tuning operations, and determines the priority prediction segment according to the drag frequency and modification frequency; in step S6, the influence factor is calculated based on the proportion and preference index of the prediction segment, and the circuit generation model is adjusted online combined with the preset learning rate; finally, in step S7, the closed-loop process of prediction-simulation-filtering-feedback-updating is repeatedly executed until the target circuit that meets all design indicators is generated, thereby realizing AI and manual expert collaboration, efficient and adaptive radio frequency circuit design.

[0074] By closely combining the design indicators with the initial circuit schematic and the structured code, the circuit generation model is trained using preprocessed data to realize intelligent prediction of the radio frequency circuit code segments; high-quality code segments are dynamically filtered based on the performance simulation results, and the model parameters are further adjusted based on the drag frequency and parameter modification frequency data in user interaction to form an adaptive feedback mechanism. The interaction of various parameters ensures that the model not only generates code that meets the design indicators, but also continuously optimizes the prediction effect according to the actual use, improves the matching degree of design efficiency and circuit performance, promotes the intelligentization and individualization of the radio frequency circuit design process, and effectively solves the problem of low design efficiency and high error rate caused by weak generalization ability of the circuit design result due to static training of the model and lack of performance closed-loop verification.

[0075] Specifically, in the step S2, the preset artificial intelligence architecture is a Transformer-based encoder-decoder architecture, comprising:

[0076] The encoder is stacked by multiple encoder layers, and is used to encode the sequence of the structured code and the design indicators into fixed-length vectors through word embedding, position encoding and multi-head attention mechanism;

[0077] The decoder is stacked by multiple decoder layers, and is used to generate the subsequent candidate code segments by input embedding, position encoding, mask multi-head attention mechanism and Softmax layer, combined with the encoder output and the generated sequence of the structured code.

[0078] Referring to Figure 2 As shown in the flowchart of step S2 of the embodiment, in the embodiment, the step S2 comprises:

[0079] Step S21, acquire the radio frequency circuit design cases in the past preset historical period, extract the structured code segments as training samples;

[0080] Step S22, randomly mask the structured code in the training sample at a preset masking proportion to obtain a preprocessed code;

[0081] Step S23, input the preprocessed code and its corresponding initial circuit schematic and design indicators into the preset artificial intelligence architecture to predict the masked code content and obtain a prediction result;

[0082] Step S24, compare the prediction result with the original structured code segment to calculate a prediction loss value, and update the model parameters of the real-time preset artificial intelligence architecture through a back propagation algorithm;

[0083] Step S25, terminate the training when the prediction loss value does not decrease within a continuous preset training round, and obtain the circuit generation model.

[0084] The preset historical period refers to the historical time range for collecting radio frequency circuit design cases, which depends on the demand of the target model for sample diversity and novelty, and is usually set between 1 month and 12 months, and is set to 6 months in the embodiment, which can ensure that the training data is representative and timely, thereby improving the model generalization ability.

[0085] The preset masking proportion refers to the masking range proportion when the structured code is randomly masked, which depends on the training demand of the model for context understanding ability, and is usually set between 10% and 30%, and is set to 20% in the embodiment, which can improve the prediction accuracy of the model while maintaining the semantic integrity.

[0086] The preset training round refers to the upper limit of the number of iterations of complete sample traversal performed by the circuit generation model in the training stage, which depends on the model complexity and the convergence speed of the loss function, and is usually set between 50 rounds and 500 rounds, and is set to 200 rounds in the embodiment, which can ensure sufficient learning while avoiding overfitting.

[0087] By introducing structured code snippets based on historical radio frequency circuit design cases during the model training phase and combining a random masking mechanism for self-supervised learning, the model's ability to recognize and complete circuit semantic patterns is effectively enhanced. Specifically, the setting of the masking ratio ensures that the model faces sufficient information missing challenges while retaining the necessary context, thereby guiding it to learn the mapping relationship between key structural features and local function expressions. The prediction loss value, as a measure of the model's learning effectiveness, is used in conjunction with a continuous round of descent monitoring mechanism to dynamically control the training convergence process, avoiding overfitting or undertraining. By continuously optimizing model parameters through backpropagation, the circuit generation model constructed has stronger generalization ability and structural completion accuracy in practical applications, enabling it to quickly generate candidate code snippets that meet engineering rules and design intentions when faced with new design tasks, thereby improving collaborative design efficiency and model quality from the source.

[0088] Specifically, in the step S3, a preset prediction failure threshold is also set. When the number of consecutive predictions exceeds the preset prediction failure threshold and the candidate code snippets that meet the preset expected threshold have not been filtered out, a prompt for manual intervention in writing is issued.

[0089] The preset prediction failure threshold refers to the maximum allowed number of consecutive predictions that fail to produce code snippets that meet the preset expected threshold. It depends on the complexity of the circuit and the stability of the model, and is usually set between 10 and 50 times. In this embodiment, it is set to 30 times, which can effectively balance the timing of automatic prediction and manual intervention, ensuring the continuity and accuracy of the design process.

[0090] By setting the preset prediction failure threshold, the prediction performance of the circuit generation model can be effectively monitored. When the number of consecutive predictions exceeds the threshold and no candidate code snippets that meet the preset expected threshold are produced, the system promptly triggers a prompt for manual intervention, ensuring that the design process does not stall due to model prediction failure. This mechanism not only ensures the continuity and accuracy of the design, but also promotes human-machine collaboration, improving overall design efficiency and reliability.

[0091] Specifically, in the step S3, a visual collaboration interface is also provided to simultaneously display the candidate code snippets and real-time code written by manual intervention.

[0092] By introducing a visual collaboration interface, the automatically generated candidate code snippets and the real-time written code by manual intervention can be displayed side by side, allowing for intuitive comparison and selection of the optimal solution, improving the flexibility and interactivity of the design. This interface supports immediate modification and feedback of the code, promoting the deep integration of artificial intelligence, thereby significantly improving overall design efficiency and accuracy.

[0093] Specifically, in the step S4, the preset expected threshold is an optimal value among a plurality of reference performance values obtained by simulating each of the initial circuit schematics in a preset threshold setting period using the preset simulation engine.

[0094] The preset threshold setting period refers to a historical time period for updating the performance evaluation threshold, which depends on the calculation time of circuit simulation, the real-time requirement of design task, and the complexity of circuit type. It is usually set between 1 hour and 72 hours, and is set to 24 hours in this embodiment, which can sufficiently extract representative performance reference values, thereby ensuring that the screened expected threshold has stability and foresight, and effectively improving the guiding effectiveness of the model in actual design and the accuracy of simulation screening.

[0095] By dynamically setting the preset expected threshold based on the historical optimal performance value, high-precision screening of candidate code fragments can be achieved in step S4. By taking all initial circuit schematic simulation results in the past preset threshold setting period as the basis, the optimal reference performance is extracted as the current judgment basis, thereby logically establishing a closed-loop path of “historical performance accumulation-optimal value extraction-current screening optimization”. This can effectively improve the matching degree between the simulation results and the target design requirements, avoid excessive screening or false acceptance caused by traditional static threshold setting, and further continuously optimize the parameter judgment standard as the design progresses, thereby improving the model adaptability and evolution efficiency.

[0096] Specifically, when the radio frequency circuit is a filter, the expected threshold in step S4 includes an S parameter threshold.

[0097] The S parameter threshold is an optimal S parameter obtained by simulating each of the initial circuit schematics in the past preset threshold setting period using a CAE simulation engine.

[0098] By introducing the S parameter threshold calculated based on the CAE simulation engine as the expected standard in the application scenario where the radio frequency circuit is a filter, the simulation data of a plurality of initial circuit schematics in the historical preset threshold setting period can be fully utilized to extract the optimal S parameter as the performance reference under the target index. A dynamic threshold is generated by data-driven, which not only avoids subjective bias caused by human experience setting, but also reflects the response capability and stability of different topological structures in actual application by aggregating the historical optimal solution, thereby improving the precision and robustness of screening the code fragments to be accepted. Furthermore, the S parameter threshold forms a closed-loop feedback relationship with the filter structure, material parameters, frequency range, and other design dimensions, providing a quantifiable and traceable performance scale for subsequent model iteration optimization and circuit generation, thereby strengthening the coupling mechanism between circuit performance and intelligent recommendation, and realizing a more engineering practical collaborative design optimization process.

[0099] Specifically, when the radio frequency circuit is a four-channel clock driver, in step S4, the expected threshold includes a timing parameter threshold;

[0100] The timing parameter thresholds are maximum clock jitter, maximum propagation delay, and maximum output skew obtained by simulating and calculating each of the initial circuit schematics within the past preset threshold setting period using an EDA simulation engine.

[0101] By introducing timing parameter thresholds derived from an EDA simulation engine as expected standards in the design scenario of a four-channel RF circuit clock driver, the high dependence of this type of circuit on clock accuracy and signal integrity can be fully reflected. Specifically, maximum clock jitter, maximum propagation delay, and maximum output skew, as key indicators for measuring driver stability and synchronization performance, are highly coupled: clock jitter directly affects edge stability, propagation delay affects the consistency of the clock distribution path, and output skew reflects the symmetry control effect between output ports. By simulating and extracting a large number of initial schematics within the preset threshold setting period, a dynamic optimization threshold system is automatically constructed, enabling the circuit generation model to use the performance lower bound verified in engineering practice as the target constraint, thereby improving the timing correctness and system integration of candidate code snippets. At the same time, a closed-loop deduction from schematic structure to key performance indicators is achieved, significantly enhancing the model's structure-performance mapping capabilities for timing-related circuits, enabling more reliable and controllable automated collaborative design.

[0102] See also Figure 3 As shown, it is a flow chart of step S5 of this embodiment. In this embodiment, step S5 includes:

[0103] Step S51: Within each preset statistical period, the number of drags and parameter modifications of each code segment to be accepted is counted to obtain a number of real-time drag frequencies and a number of real-time parameter modification frequencies;

[0104] Step S52: The real-time dragging frequency and the real-time parameter modification frequency are weighted and synthesized according to preset preference weights to calculate the preference score of each code snippet to be accepted, Qi=wd×fi1+wm×fi2, where Qi is the preference score of the i-th code snippet to be accepted, fi1 is the real-time dragging frequency of the i-th code snippet to be accepted, fi2 is the real-time parameter modification frequency of the i-th code snippet to be accepted, wd and wm are the preset preference weights of the real-time dragging frequency and the real-time parameter modification frequency, respectively, and wd+wm=1 is satisfied;

[0105] Step S53, sort all the to-be-admitted code segments according to the preference scores from high to low, and select several highest-score to-be-admitted code segments with the preference scores greater than a preset score threshold as the prediction segments.

[0106] The preset preference weight is a coefficient for balancing the influence of real-time dragging frequency and real-time parameter modification frequency on the preference score, depends on the importance proportion of the two in the specific application scenario, and is usually set between 0 and 1 with the sum of the two weights being 1. In the embodiment, the preset preference weight of the real-time dragging frequency is set as 0.6, and the preset preference weight of the real-time parameter modification frequency is set as 0.4, which can effectively reflect the user operation preference and improve the accuracy of candidate code segment screening.

[0107] The preset score threshold is a minimum score standard for screening high-preference code segments, depends on the system requirements for the quality and quantity of candidate segments, and is usually set between 0 and 1. In the embodiment, it is set as 0.75, which can effectively filter low-quality code and improve the overall performance of the prediction segment and user satisfaction.

[0108] By carefully counting the dragging times and parameter modification times of the to-be-admitted code segments and combining the preset preference weight for weighted calculation of the preference score, the actual use preference and adjustment demand for each code segment can be objectively reflected. Then, the high-score code segments are selected as the prediction segments according to the preference score sorting, which effectively improves the pertinence and accuracy of subsequent model training, thereby continuously optimizing the matching degree of circuit design and promoting the design process to be more efficient and meet the actual demand.

[0109] Please refer to Figure 4 As shown in FIG. 6, which is a flow chart of step S6 of the embodiment, in the embodiment, the step S6 includes:

[0110] Step S61, in each preset update period, count the proportion of the selected prediction segment in all to-be-admitted code segments to obtain the proportion coefficient of each prediction segment;

[0111] Step S62, weight and synthesize the proportion coefficient of each prediction segment and its corresponding preference index according to a preset fusion weight to calculate the comprehensive influence factor of each prediction segment, Yi = α × Pi + (1-α) × Qi', wherein Yi is the i th comprehensive influence factor, α is the weight proportion of the proportion coefficient and the preference score in the comprehensive influence factor, Pi is the proportion coefficient of the i th prediction segment in all to-be-admitted code segments, and Qi' is the preference index of the i th prediction segment;

[0112] Step S63, according to the comprehensive influence factor and a preset learning rate, construct a model parameter update gradient, perform one or more gradient descent iterations on the circuit generation model to adjust the model parameters, and obtain the adjusted circuit generation model.

[0113] By statistically predicting the proportion of the segment in all to-be-admitted code segments, combining the preference index corresponding to each prediction segment, and performing weighted calculation according to a preset fusion weight, a comprehensive influence factor is obtained, and then based on the influence factor and a preset learning rate, the parameters of the circuit generation model are dynamically adjusted. This process can effectively reflect the selection preference and usage frequency of the user, promote continuous optimization of the model, improve the accuracy and adaptability of code generation, so that the generated radio frequency circuit design is more in line with actual needs, and the overall design efficiency and quality are improved.

[0114] On the other hand, the embodiment also provides a system for collaborative design and programming of a radio frequency circuit based on artificial intelligence, comprising:

[0115] A first generation module is configured to generate an initial circuit schematic and a structured code corresponding to a design index in real time according to the design index of the radio frequency circuit received in the visual interface;

[0116] A training module is connected with the first generation module and configured to input the preprocessed initial circuit schematic, the structured code and the design index into a preset artificial intelligence architecture to train a circuit generation model;

[0117] A prediction module is connected with the training module and configured to call the circuit generation model to perform prediction and generate a plurality of candidate code segments based on the real-time input design index;

[0118] A screening module is connected with the prediction module and configured to perform performance simulation on each candidate code segment through a preset simulation engine, and select a plurality of to-be-admitted code segments from all candidate code segments according to the simulation result and a preset expected threshold;

[0119] A determination module is connected with the screening module and configured to display all to-be-admitted code segments in a visual interface, and determine a plurality of prediction segments from all to-be-admitted code segments according to the real-time drag frequency and real-time parameter modification frequency of each to-be-admitted code segment;

[0120] An adjustment module is connected with the determination module and the training module respectively, and configured to adjust the circuit generation model based on the proportion of the prediction segment in all to-be-admitted code segments and the preference index of each prediction segment;

[0121] A second generation module is connected with the prediction module, the screening module, the determination module and the adjustment module respectively, and configured to continuously optimize until a target circuit is generated based on the dynamic update result of the circuit generation model.

[0122] The intelligent generation and iterative optimization of the radio frequency circuit are realized through modular construction, the modules work cooperatively, the structured circuit generation driven by design indexes can be realized, dynamic screening and model adaptive updating can be carried out based on simulation feedback and user behavior, so that effective identification and continuous optimization of the candidate code fragments can be realized, and the intelligent level, generation efficiency, controllability and reliability of the design result of the circuit design are greatly improved.

[0123] The above merely describes the preferred embodiments of the present application, and is not intended to limit the present application; for those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for collaboratively designing and programming radio frequency circuits based on artificial intelligence, characterized in that: include: Step S1: generating an initial circuit schematic and a structured code corresponding to the design indicators in real time according to the design indicators of the radio frequency circuit received on the visual interface; Step S2: inputting the pre-processed initial circuit schematic, the structured code, and the design indicators into a preset artificial intelligence framework to train and obtain a circuit generation model; Step S3: Based on the design indicators input in real time, calling the circuit generation model to perform prediction and generate a number of candidate code snippets; Step S4: performing performance simulation on each of the candidate code snippets using a preset simulation engine, and selecting a number of code snippets to be accepted from all candidate code snippets based on the simulation results and a preset expected threshold; Step S5: displaying all the code snippets to be accepted on a visual interface, and determining a number of predicted snippets from all the code snippets to be accepted based on the real-time dragging frequency and the real-time parameter modification frequency of each code snippet to be accepted; Step S6: adjusting the circuit generation model based on the proportion of the predicted segments in all code segments to be accepted and the preference index of each predicted segment; Step S7, continuing to execute steps S3 to S6 based on the adjusted circuit generation model until a target circuit is generated; In step S6, the preference index is determined based on the real-time dragging frequency and the real-time parameter modification frequency in a past preset update period.

2. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: In step S4, the preset expected threshold is the optimal value among several reference performance values ​​obtained by using the preset simulation engine to perform simulation calculations on each of the initial circuit schematics within a past preset threshold setting period.

3. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: When the radio frequency circuit is a filter, in step S4, the expected threshold value includes an S parameter threshold value; The S parameter threshold is an optimal S parameter obtained by using a CAE simulation engine to simulate and calculate each of the initial circuit schematics within a preset threshold setting period in the past.

4. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: When the radio frequency circuit is a four-channel clock driver, in step S4, the expected threshold includes a timing parameter threshold; The timing parameter thresholds are maximum clock jitter, maximum propagation delay, and maximum output skew obtained by simulating and calculating each of the initial circuit schematics within a past preset threshold setting period using an EDA simulation engine.

5. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: The step S2 comprises: Step S21: Obtain radio frequency circuit design cases within a preset historical period in the past, and extract their structured code snippets as training samples; Step S22: performing random masking processing on the structured code in the training sample at a preset masking ratio to obtain a preprocessed code; Step S23: inputting the preprocessed code, its corresponding initial circuit schematic, and design specifications into the preset artificial intelligence architecture to predict the masked code content and obtain a prediction result; Step S24: Compare the prediction result with the original structured code snippet to calculate the prediction loss value, and update the model parameters of the real-time preset artificial intelligence architecture through the back propagation algorithm; Step S25: When the predicted loss value does not decrease within consecutive preset training rounds, the training is terminated to obtain the circuit generation model.

6. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: In step S3, a preset prediction failure threshold is also set. When the number of consecutive predictions exceeds the preset prediction failure threshold and the candidate code snippet that meets the preset expected threshold is still not screened out, a prompt for manual intervention in writing is issued.

7. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, wherein in step S2, The preset artificial intelligence architecture is a Transformer-based encoder-decoder architecture, including: An encoder, composed of a stack of multiple encoder layers, for encoding the input sequence of the structured code and the design indicator into a fixed-length vector through word embedding, position encoding, and a multi-head attention mechanism; The decoder is composed of multiple decoder layers stacked together to gradually generate the subsequent candidate code fragments by combining the encoder output and the sequence of generated structured codes through input embedding, position encoding, masked multi-head attention mechanism and softmax layer.

8. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: The step S5 comprises: Step S51: Within each preset statistical period, the number of drags and parameter modifications of each code segment to be accepted is counted to obtain a number of real-time drag frequencies and a number of real-time parameter modification frequencies; Step S52: performing weighted synthesis on the real-time dragging frequency and the real-time parameter modification frequency according to a preset preference weight, and calculating a preference score for each of the code snippets to be accepted; Step S53: sort all the code snippets to be accepted from high to low according to the preference scores, and select several code snippets to be accepted with the highest scores as the predicted snippets according to a preset score threshold.

9. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: The step S6 comprises: Step S61: within each of the preset update cycles, calculating the proportion of the selected predicted segments in all the code segments to be accepted, and obtaining a proportion coefficient of each predicted segment; Step S62: weighting and synthesizing the proportion coefficient of each predicted segment and its corresponding preference index according to a preset fusion weight to calculate a comprehensive impact factor of each predicted segment; Step S63: construct a model parameter update gradient based on the comprehensive influencing factor and the preset learning rate, and perform one or more gradient descent iterations on the circuit generation model to adjust the model parameters to obtain the adjusted circuit generation model.

10. A system for collaboratively designing and programming radio frequency circuits based on artificial intelligence, constructed based on the method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to any one of claims 1 to 9, characterized in that: include: A first generation module is used to generate an initial circuit schematic and a structured code corresponding to the design indicators in real time according to the design indicators of the radio frequency circuit received in the visual interface; a training module connected to the first generation module, configured to input the preprocessed initial circuit schematic, the structured code, and the design indicators into a preset artificial intelligence architecture to train and obtain a circuit generation model; a prediction module connected to the training module, configured to call the circuit generation model to perform prediction and generate a plurality of candidate code snippets based on the design indicators input in real time; a screening module, connected to the prediction module, for performing performance simulation on each of the candidate code snippets using a preset simulation engine, and screening a number of code snippets to be accepted from all candidate code snippets based on the simulation results and a preset expected threshold; a determination module connected to the screening module, configured to display all the code snippets to be accepted on a visual interface, and determine a number of predicted snippets from all the code snippets to be accepted based on the real-time dragging frequency and the real-time parameter modification frequency of each code snippet to be accepted; an adjustment module, connected to the determination module and the training module respectively, for adjusting the circuit generation model based on a proportion of the predicted segments in all code segments to be accepted and a preference index of each predicted segment; The second generation module is connected to the prediction module, the screening module, the determination module and the adjustment module respectively, and is used to continuously optimize based on the dynamic update result of the circuit generation model until a target circuit is generated.

Images