Method and device for extracting resistance in integrated circuit and electronic equipment

Abstract

The invention provides a method and device for extracting resistance in an integrated circuit and electronic equipment. The extraction method comprises the steps that a graph of a resistor to be extracted in the integrated circuit is segmented to obtain a first graph, the first graph is different from a second graph, and current in the second graph flows from one port of the second graph to the other port according to a preset direction; dividing an area where the first graph is located to obtain a plurality of target areas; first resistances of at least part of the target areas are extracted respectively; according to the method, the first graph which is obtained by segmenting the graph of the to-be-extracted resistor and has an indefinite current flow direction is divided into the plurality of target areas, and then the first resistor of at least part of the target areas is extracted, so that the resistance between any points in the to-be-extracted resistor can be extracted, and the extraction method can simplify the calculation process and improve the extraction efficiency. The extraction efficiency of the resistor in the integrated circuit is improved, and the calculation problem of a traditional method when a conductor with an indefinite current flow direction is processed is effectively solved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit design, and in particular to a method, device, and electronic device for extracting resistance in an integrated circuit. Background Art

[0002] Resistance calculation is a critical step in integrated circuit design, involving the accurate calculation of parasitic resistance in the circuit. Numerical methods, such as the Finite Element Method (FEM), obtain parasitic parameters by solving the Laplace equation within a region. This method is particularly suitable for complex multi-terminal conductor structures. However, numerical methods face challenges when dealing with large-scale integrated circuits due to the large amount of data involved, the high demand for computing resources, and relatively low computational efficiency. Summary of the Invention

[0003] To solve the problems existing in the related art, the present disclosure provides a method, device and electronic device for extracting resistance in an integrated circuit.

[0004] According to a first aspect of an embodiment of the present disclosure, a method for extracting resistance in an integrated circuit is provided, the method comprising:

[0005] Slicing a pattern of a resistor to be extracted in an integrated circuit to obtain a first pattern, wherein the first pattern is different from a second pattern, and current in the second pattern flows from one port of the second pattern to another port in a preset direction;

[0006] Dividing the area where the first graphic is located to obtain multiple target areas;

[0007] The first resistance of at least a portion of the target area is respectively extracted.

[0008] In some embodiments of the present disclosure, the plurality of target areas are all rectangular areas; and extracting the first resistance of at least part of the target areas respectively includes:

[0009] inserting target points in at least a portion of the rectangular area to form a resistor network of the first pattern;

[0010] The resistance between at least some of the adjacent target points on the resistance network is determined as the first resistance.

[0011] In some embodiments of the present disclosure, inserting a target point in at least a portion of the rectangular area includes:

[0012] In the case where the rectangular area includes a port, inserting the target point between the midpoint of the port of the rectangular area and the center point of the rectangular area;

[0013] In the case where the rectangular area includes a through hole, the through hole in the rectangular area and a corresponding point of the through hole in the center line of the rectangular area are inserted into the target point.

[0014] In some embodiments of the present disclosure, the first graphic is a rectangle and / or a trapezoid including a first number of ports.

[0015] In some embodiments of the present disclosure, the plurality of target areas are triangular areas, and the vertices of the plurality of triangular areas are all located at ports of the first graph; and extracting the first resistance of at least part of the target areas respectively includes:

[0016] determining a second resistance between two vertices located at different ports in each of the triangular regions;

[0017] The first resistor is determined according to each of the second resistors.

[0018] In some embodiments of the present disclosure, determining the second resistance between two vertices located at different ports in each of the triangular regions includes:

[0019] Determine each of the second resistors by a finite element method; and / or,

[0020] The determining the first resistance according to each of the second resistances includes:

[0021] The second resistors are connected in parallel to obtain the first resistor.

[0022] In some embodiments of the present disclosure, the first figure is a parallelogram and / or a trapezoid including a second number of ports.

[0023] In some embodiments of the present disclosure, dividing the area where the first graphic is located to obtain multiple target areas includes:

[0024] In a case where the first graphic is a rectangle including a first number of ports, dividing the area where the rectangle is located into a plurality of rectangular areas;

[0025] In a case where the first figure is a parallelogram including a second number of ports, dividing the area where the parallelogram is located into a plurality of congruent triangular areas;

[0026] In the case where the first graphic is a trapezoid including the second number of ports, dividing the area where the trapezoid is located into a plurality of parallelogram areas and triangular areas; and dividing each of the parallelogram areas into a plurality of triangular areas;

[0027] In a case where the first graphic is a trapezoid including the first number of ports, a polygonal area where the trapezoid is located is divided into a plurality of rectangular areas, where the polygonal areas are associated with the ports of the first graphic.

[0028] According to a second aspect of an embodiment of the present disclosure, a device for extracting resistance in an integrated circuit is provided, the device comprising:

[0029] a slicing module configured to slice a pattern of resistance to be extracted in the integrated circuit to obtain a first pattern, wherein the first pattern is different from a second pattern, and current in the second pattern flows from one port of the second pattern to another port in a preset direction;

[0030] a dividing module, wherein the dividing module is configured to divide the area where the first graphic is located into a plurality of target areas;

[0031] The extraction module is configured to extract the first resistance of at least part of the target area respectively.

[0032] According to a third aspect of an embodiment of the present disclosure, an electronic device is provided, comprising:

[0033] processor;

[0034] a memory for storing instructions executable by the processor;

[0035] The processor is configured to execute the above-mentioned method for extracting resistance in an integrated circuit.

[0036] The beneficial effects of the present disclosure include, but are not limited to, the following: in the method for extracting resistors in an integrated circuit provided by the present disclosure, a first graphic with unclear current flow direction obtained after segmenting the graphic of the resistor to be extracted is divided into multiple target areas, and then the first resistance of at least part of the target areas is extracted respectively. In this way, the resistance between any points in the resistor to be extracted can be extracted. This extraction method can simplify the calculation process, improve the efficiency of extracting resistors in the integrated circuit, and at the same time ensure a certain extraction accuracy, effectively solving the calculation difficulties of traditional methods when processing conductors with unclear current flow direction in the integrated circuit.

[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0039] Figure 1 1 is a flow chart of a method for extracting resistance in an integrated circuit according to an exemplary embodiment of the present disclosure;

[0040] Figure 2 A schematic diagram of dividing a pattern of resistors to be extracted according to an exemplary embodiment of the present disclosure;

[0041] Figure 3 is a schematic diagram of a first figure of an exemplary embodiment of the present disclosure;

[0042] Figure 4 is a schematic diagram of a first figure of another exemplary embodiment of the present disclosure;

[0043] Figure 5 is a schematic diagram of a first figure of another exemplary embodiment of the present disclosure;

[0044] Figure 6 A schematic diagram of a parameter selection method according to an exemplary embodiment of the present disclosure;

[0045] Figure 7 is a schematic diagram of a first figure of another exemplary embodiment of the present disclosure;

[0046] Figure 8 is a schematic diagram of a first figure of another exemplary embodiment of the present disclosure;

[0047] Figure 9 FIG. 1 is a schematic diagram of a resistance extraction device in an integrated circuit according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure will be clearly and completely described below in conjunction with the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0049] Resistance analysis is a critical step in integrated circuit design, involving the accurate calculation of parasitic resistance within a circuit. Numerical methods, such as finite element analysis (FEA), obtain parasitic parameters by solving the Laplace equation for a specific region. This approach is particularly well-suited for complex, multi-terminal conductor structures. However, numerical methods face challenges when dealing with large-scale integrated circuits due to the large amount of data involved, high computational resource requirements, and relatively low computational efficiency.

[0050] To address this problem, an effective strategy is to partition the region containing the resistor shape to be calculated, breaking down the complex resistor geometry into smaller units. This partitioning process captures the relationship between the individual shapes and the overall shape, ultimately transforming the target region into a resistor network. This approach significantly reduces computational complexity and improves solution efficiency.

[0051] For rectangular conductors, their resistance can be calculated using a simple formula: the square resistance multiplied by its aspect ratio, where the aspect ratio refers to the length along the conductor's current flow. However, if the rectangle is cut, the cut represents an internal port, which affects the direction of the current flow. The current flow in the conductor is no longer clear, so the formula cannot be used directly.

[0052] In addition, some circuit structures contain a large number of beveled metal lines and general non-rectangular conductor shapes. These beveled lines result in a large number of additional graphics when dividing the graphics, affecting the extraction efficiency. Therefore, a suitable division method needs to be designed for such graphics.

[0053] To address the above technical problems, the present disclosure provides a method for extracting resistance in an integrated circuit. In this extraction method, a first graphic with unclear current flow direction obtained by segmenting the graphic of the resistor to be extracted is divided into multiple target areas, and then the first resistance of at least part of the target areas is extracted respectively. In this way, the resistance between any points in the resistor to be extracted can be extracted. This extraction method can simplify the calculation process, improve the extraction efficiency of the resistor in the integrated circuit, and at the same time ensure a certain extraction accuracy, effectively solving the calculation difficulties of traditional methods when processing conductors with unclear current flow direction in the integrated circuit.

[0054] The embodiment of the present disclosure provides a method for extracting resistance in an integrated circuit, such as Figure 1 As shown, the extraction method includes:

[0055] S100 , dividing a pattern of a resistor to be extracted in an integrated circuit to obtain a first pattern, wherein the first pattern is different from a second pattern, and current in the second pattern flows from one port of the second pattern to another port in a preset direction.

[0056] S200: Divide the area where the first graphic is located to obtain multiple target areas.

[0057] S300 , extracting first resistances of at least a portion of the target area.

[0058] The resistor to be extracted in the integrated circuit can be a multi-port resistor or a resistor with a complex pattern (such as Figure 2 The resistor shown in the figure can also be a multi-port resistor with a complex shape. That is, the resistor to be extracted in the integrated circuit has the problem of unclear current flow direction. Therefore, the simple rectangular resistor formula R = Rs(L / W) cannot be used to calculate the resistance value of the resistor to be extracted. In the rectangular resistor formula, Rs is the square resistance value, which represents the resistance value per unit thickness and unit area of ​​the conductive material. L is the length of the conductor in the direction of current flow, and W is the length of the conductor perpendicular to the direction of current flow.

[0059] refer to Figure 2 The image of the resistor to be extracted in the integrated circuit is segmented to obtain a first pattern 10. The first pattern 10 is different from the second pattern 20. The current in the second pattern 20 flows from one port of the second pattern 20 to the other port in a predetermined direction. That is, the second pattern 20 can be a two-port rectangle with a clear current flow direction, while the first pattern 10 is a pattern with an unclear current flow direction. It may be a rectangle with three or more ports, or a non-rectangular pattern such as a trapezoid 11, a parallelogram 12, or a triangle. The current flow direction of the first pattern 10 is unclear, and the simple rectangular resistance formula R = Rs(L / W) cannot be used to calculate the resistance of the first pattern 10. Therefore, in this embodiment, the area where the first pattern 10 is located is divided into multiple target areas. The target areas can be sub-areas that are convenient for direct resistance calculation. The first resistance of at least part of the target area is extracted from each target area. In this way, the resistance between any points in the resistance to be extracted can be extracted. The extraction method provided in this embodiment can simplify the calculation process, improve the efficiency of resistance extraction in integrated circuits, and ensure a certain extraction accuracy. It effectively solves the calculation difficulties of traditional methods when dealing with conductors with unclear current flow directions in integrated circuits.

[0060] It should be noted that if Figure 2 As shown, when the pattern of the resistor to be extracted in the integrated circuit is divided, in addition to the first pattern 10, a second pattern 20 may also be obtained. The current in the second pattern 20 flows from one port of the second pattern to the other port in a predetermined direction. Therefore, the current flow direction of the second pattern 20 is clear, and the resistance of the second pattern 20 can be directly calculated according to the simple rectangular resistance formula R = Rs (L / W), without the need for further division and calculation. If the pattern of the resistor to be extracted in the integrated circuit is divided, resulting in both the first pattern 10 and the second pattern 20, the resistor to be extracted can be determined based on the first resistance of each target area after the first pattern 10 is divided and the resistance of the second pattern 20.

[0061] In one embodiment, the plurality of target areas are all rectangular areas. Step S300 of extracting the first resistance of at least a portion of the target area includes:

[0062] S301 , inserting target points into at least a portion of a rectangular area to form a resistor network of a first pattern.

[0063] like Figure 2 As shown, after the complex figure is cut, it is trapezoidalized in the x and y directions respectively, and the long-side figure (i.e., the second figure 20) and the non-long-side figure (i.e., the first figure 10) are cut out. The current flow direction in the long-side figure is clear, its length is significantly greater than its width, and the inflow and outflow points of the current are located at both ends of the length direction. This kind of figure meets the conditions required by the rectangular resistance formula, and it can be directly calculated according to the rectangular resistance formula R=Rs(L / W). For non-long-side figures, it will contain two parallel sides (parallelogram or trapezoid) or be cut into triangles ( Figure 2 not shown).

[0064] like Figure 3-Figure 4 As shown, for the first graphic 10 after segmentation, there are several ports 30 at the segmentation point (the bold line segments in the figure represent the ports). The direction of the current in the first graphic 10 is no longer determined, and the use condition of the rectangular resistance formula R = Rs (L / W) is not satisfied. Therefore, the first graphic 10 is divided into multiple target areas 40, each of which is a rectangular area. Target points 50 (the cross in the figure represents the target point) are inserted in at least part of the rectangular area, and according to the position of the target point 50, the following is formed. Figure 4 A first diagram 10 of a resistor network is shown.

[0065] S302: Determine the resistance between at least some adjacent target points on the resistance network as a first resistance.

[0066] After forming the resistor network of the first pattern 10 , the resistance between at least some adjacent target points 50 on the resistor network can be determined as the first resistor according to the rectangular resistor formula R=Rs(L / W).

[0067] In this embodiment, the target region obtained after dividing the region containing the first pattern is a rectangular region, and target points are inserted into at least a portion of the rectangular region to form a resistor network of the first pattern. The resistance between at least a portion of adjacent target points on the resistor network is determined as the first resistance. In this way, the complex resistance calculation problem is transformed into a simple resistance network construction problem, thereby significantly reducing the computational complexity of resistance in integrated circuits, avoiding the complex partial differential equation solution process in traditional numerical methods for solving resistance, and improving computational efficiency.

[0068] In one embodiment, after constructing the resistor network of the first graph, the connection relationship between each first resistor (for example, a parallel relationship or a series relationship) can be determined based on the resistor network. Then, the resistor to be extracted can be determined based on the connection relationship between each first resistor and the first resistor.

[0069] In one embodiment, inserting a target point in at least a portion of the rectangular area in step S301 includes:

[0070] S3011 . When the rectangular area includes a port, insert a target point between the midpoint of the port of the rectangular area and the center point of the rectangular area.

[0071] S3012: When the rectangular area includes a through hole, insert a target point at the through hole in the rectangular area and a corresponding point of the through hole in the midline of the rectangular area.

[0072] For example, in combination Figure 3-Figure 4 As shown, the first figure 10 is divided into a plurality of target areas 40 (i.e., rectangular areas) according to the position of the port 30, and the target area 40 is divided into an area including the port 30 and an area not including the port 30. In the case where the rectangular area includes the port 30, a target point 50 is inserted at the midpoint of the port 30 in the rectangular area and the center point of the rectangular area. In the case where the rectangular area includes a through hole 60 (the small square in the figure represents a through hole), a target point 50 is inserted at the through hole 60 in the rectangular area and at the corresponding point of the through hole 60 on the midline of the rectangular area. In the case where the rectangular area does not include the port 30, in order to simplify the calculation, the target point 50 is no longer inserted on the midline. When calculating the first resistance, the point closest to the midline is used as the reference point to construct the resistance network.

[0073] These target points and their corresponding IDs are stored in a map container and sorted by the primary direction (x or y) of the first graphic area. If the x-direction is greater than the y-direction, the graphic is in the x-direction, and the target points are sorted from smallest to largest x-coordinate. Conversely, if the graphic is in the y-direction, the target points are sorted from smallest to largest y-coordinate. This sorting method facilitates subsequent resistance calculations.

[0074] The first graphic resistance calculation includes the resistance from the target point to the port, the resistance between vertical points, and the resistance between horizontal points. Different L and W parameters are used for each case. For the x-axis rectangle, for the target point to port resistance calculation, L is the distance from the target point to the port midpoint, and W is the width of the rectangular area. For the vertical resistance calculation between target points, L is the difference in y coordinates between the two target points, and W is the width of the rectangular area. For the horizontal resistance calculation between target points, L is the distance between two adjacent target points at the midline, and W is the height of the rectangular area.

[0075] In addition, the resistance between rectangular areas needs to be calculated. After calculating the resistance of a rectangular area, set the last point of the rectangular area. If the first graph is in the x-direction, for a rectangular area with a port, the x-coordinate of the last point is the same as the x-coordinate of the last inserted target point, and the y-coordinate is the height at the center line. For a rectangular area without a port, the last point is represented by the last target point closest to the center line. When calculating the resistance of the next rectangular area, the resistance between the first point of the next rectangular area and the last point of the previous rectangular area is calculated to ensure the continuity and accuracy of the resistance network. In addition, since the current on the port can be considered to be 0, the points on the port can be regarded as equipotential points.

[0076] The extraction method provided in this embodiment constructs a resistor network by inserting target points into a rectangular area in a standardized manner, thereby enhancing the consistency and repeatability of the resistor extraction method and being suitable for the automated extraction of resistors in integrated circuits.

[0077] In one embodiment, the first graphic is a rectangle and / or a trapezoid including a first number of ports. The first number can be any number, that is, the first graphic can include any number of ports.

[0078] like Figure 4 As shown in FIG, the first graphic 10 is a rectangle including four ports. Figure 5 As shown in FIG, the first graph 10 is a trapezoid including three ports. The method for extracting resistance in an integrated circuit provided by the exemplary embodiment of the present disclosure supports extraction of resistances of different numbers of ports and can be applied to extraction of resistances in complex integrated circuits.

[0079] It should be noted that the extraction of multi-port ladder resistance is similar to the calculation of rectangular multi-port resistance, except that the method of selecting W is different. In the extraction of multi-port ladder resistance, the midline of the ladder where the two target points are located is selected as W, such as Figure 6 As shown, the resistance is calculated, and finally the equivalent resistance network of the entire multi-port ladder is obtained, as shown in Figure 5 As shown in the figure, for a trapezoid, the sum of the target areas is greater than the area where the trapezoid is located.

[0080] In one embodiment, the plurality of target areas are triangular areas, and the vertices of the plurality of triangular areas are all located at the ports of the first graph. The step S300 of extracting the first resistance of at least part of the target area includes:

[0081] S310 , determining a second resistance between two vertices located at different ports in each triangular area.

[0082] S320 : Determine the first resistor according to each second resistor.

[0083] like Figure 7 As shown, the first figure after cutting may be a hypotenuse figure (such as a trapezoid or a parallelogram), then the multiple target areas into which the first figure is divided may be triangular areas, and the vertices of the triangular areas are all located on the ports of the first figure. Before dividing the first figure into multiple triangular areas, a target point (not shown in the figure) can also be inserted on the port of the first figure. Since one side of the divided triangular area is located on the port, the current in the triangular area flows on the other two sides of the triangular area. Therefore, by determining the resistance of the other two sides of the triangular area except on the port, that is, by determining the second resistance between the two vertices of the triangular area located at different ports, the first resistance of the target area (triangular area) can be determined.

[0084] The method for extracting resistance in an integrated circuit provided in this embodiment effectively solves the computational difficulties of traditional methods when dealing with non-rectangular conductors by dividing a figure with oblique sides (such as a trapezoid and a parallelogram) into multiple triangular regions, where the current flow direction is unclear, and determining the first resistance based on the resistance of each triangular region.

[0085] It should be noted that the number of triangular regions obtained by dividing the first graph can be selected according to the shape of the first graph, for example, 3-20. If the number of triangular regions is too small, it will not be sufficient to simulate the current flow direction of the first graph. If the number of triangular regions is too large, the calculation accuracy will be reduced.

[0086] In one embodiment, determining the second resistance between two vertices located at different ports in each triangular region in step S310 includes:

[0087] Each second resistor is determined by a finite element method.

[0088] The first figure after segmentation may be a hypotenuse figure including two ports (such as a trapezoid or a parallelogram), and the resistance of the two-port hypotenuse figure can be calculated using the conductance matrix formula derived by the finite element method.

[0089] The core idea of ​​the finite element method is to discretize the continuous solution domain into a finite number of small units, assume the approximate form of the unknown function in each unit, and then transform the partial differential equation into a set of algebraic equations through the variational principle or weighted residual method. In electromagnetics, Poisson's equation or Laplace's equation are usually used to describe the distribution of electric potential. For a steady-state current field, the electric potential Satisfies Laplace's equation:

[0090]

[0091] where σ is the conductivity.

[0092] The weighted residual method is a common method in the finite element method for transforming partial differential equations into a system of algebraic equations. The basic idea is to substitute the approximate solution into the original equation to obtain a residual, which is then minimized through weighted integration. For the Laplace equation, a residual can be defined as:

[0093]

[0094] In order to minimize the residual, a weighting function w is selected and the residual is weightedly integrated over the entire solution domain Ω:

[0095] ∫wRdΩ=0

[0096] Substituting R into the above formula, we get:

[0097]

[0098] To simplify the above integral, we can use integration by parts:

[0099]

[0100] in, Where Γ is the boundary of the solution domain, n is the unit external normal vector on the boundary, and assuming the boundary condition is homogeneous (i.e., the value of φ on the boundary is zero), the boundary integral term is zero. Therefore, the above formula simplifies to:

[0101]

[0102] Substituting the above results into the weighted residual equation, we get:

[0103]

[0104] The above formula is the variational form of Laplace's equation. To further simplify, the weighting function can be selected as a shape function:

[0105] w=N m

[0106] Therefore, the variational form becomes:

[0107]

[0108] In the two-dimensional case, triangular elements are often used to discretize the solution domain. For each triangular element, we define a shape function (also called basis function) to approximate the potential distribution within the element. Suppose there is a triangular element with three nodes i, j, and k, and the corresponding coordinates are (x i ,y i ), (x j ,y j ), (x k ,y k), shape function N i , N j , N k Defined as:

[0109]

[0110] Where A is the area of ​​the triangle, a i , b i , c i The equal coefficients are determined by the node coordinates:

[0111] a i =x i y k -x k y i

[0112] b i =y j -y k

[0113] c=x k -x j

[0114] Similarly, other coefficients can be defined.

[0115] In the triangular unit, the electric potential It can be approximated as a linear combination of shape functions:

[0116]

[0117] in is the potential value at node i, j, k.

[0118] Right now:

[0119]

[0120] Substituting the approximate potential into the variational form, we obtain

[0121]

[0122] The above formula can be written in matrix form:

[0123] Kφ=0

[0124] The conductivity matrix K describes the influence of the material conductivity on the potential distribution. Therefore, the element K of the conductivity matrix in the triangular area is mn Defined as:

[0125]

[0126] because is a constant, the integral can be further simplified to: Where A is the area of ​​the triangular integration unit, and the gradient of the shape function can be obtained through the coefficient of the shape function:

[0127]

[0128] Therefore, the elements of the conductance matrix can be expressed as:

[0129]

[0130] For each triangular unit, its local conductivity matrix can be calculated. Since each matrix element K corresponds to the interaction between nodes m and n, it can be obtained through K mn Calculate the conductance between any two points of the triangle.

[0131] The core idea of ​​finite element triangulation is to discretize complex geometric structures into simple triangular units. The physical quantities within each unit are approximately described by shape functions. This discretization method has geometric flexibility and numerical stability. Figure 7 In the two-port parallelogram shown, the current mainly flows from one port to the other along the hypotenuse. By dividing the parallelogram into multiple identical triangular areas, each triangular area has two vertices located on the same port (equipotential point, conductivity is 0), and the current is mainly concentrated between the two sides of the non-port of the triangular area. The current inside the triangular area simulates the current distribution of the two-port parallelogram. The conductance between the two vertices of the non-port side of the triangular area can be calculated using the element formula of the conductance matrix, and two resistors R1 and R2, i.e., two second resistors, can be obtained. For a two-port trapezoid, as shown in Figure 8 As shown in the figure, as the current approaches the hypotenuse of the trapezoid, its direction gradually deviates from the vertical direction, tending to flow along the hypotenuse. Based on the direction of the hypotenuse, the current is divided into parallelogram regions (the resistance of the parallelogram region is further divided into triangular regions for resistance calculation) and triangular regions. The finite element method is then used to calculate the second resistance between the two vertices of different ports in each parallelogram and triangular region. This division method simulates the current path of the two-port hypotenuse graph, discretizes the current distribution, reduces approximation errors, and improves computational efficiency.

[0132] In one embodiment, determining the first resistance according to each second resistance in step S320 includes:

[0133] The second resistors are connected in parallel to obtain a first resistor.

[0134] In this embodiment, the second resistor between two vertices located at different ports in each triangular area is determined by the finite element method, and then the second resistors are connected in parallel to obtain the first resistor. This parallel equivalent simplifies the synthesis process of the resistance of each target area, avoids complex matrix operations, and improves calculation efficiency.

[0135] It should be noted that the triangular areas may be completely equal triangles. In this way, there is no need to calculate the second resistance in each triangular area. Only the resistance of one triangular area needs to be calculated, and then the resistances of the triangular areas can be connected in parallel.

[0136] In one embodiment, the first graphic is a parallelogram and / or a trapezoid including a second number of ports. The second number can be any number, that is, the first graphic can include any number of ports.

[0137] like Figure 7 As shown in FIG, the first figure 10 is a parallelogram including two ports. Figure 8 As shown in FIG, the first graphic 10 is a trapezoid with two ports. The method for extracting resistance in an integrated circuit provided by the exemplary embodiments of the present disclosure supports extracting resistance from a first graphic with oblique sides (such as a trapezoid or parallelogram), can simulate the current flow in the first graphic, and is applicable to extracting resistance from integrated circuits with complex graphics.

[0138] In one embodiment, the area where the first graphic is located is divided in step S200 to obtain multiple target areas, including:

[0139] like Figure 3 As shown, when the first graphic 10 is a rectangle including a first number of ports, the area where the rectangle is located is divided into a plurality of rectangular areas.

[0140] like Figure 7 As shown, when the first figure 10 is a parallelogram including the second number of ports, the area where the parallelogram is located is divided into a plurality of congruent triangular areas.

[0141] like Figure 8 As shown, when the first figure 10 is a trapezoid including the second number of ports, the area where the trapezoid is located is divided into a plurality of parallelogram areas and triangular areas. Each parallelogram area is divided into a plurality of triangular areas.

[0142] like Figure 5 As shown, when the first graphic 10 is a trapezoid including a first number of ports, the polygonal area where the trapezoid is located is divided into a plurality of rectangular areas, and the polygonal areas are related to the ports of the first graphic.

[0143] In this embodiment, a partitioning strategy (rectangle / triangle / parallelogram and triangle mixed partitioning) is selected according to the graphic type or the number of ports of the first graphic, so that the versatility and efficiency of the extraction method can be achieved.

[0144] In order to more clearly explain the technical solution of the present disclosure, a specific embodiment of the method for extracting resistance in an integrated circuit provided by an exemplary embodiment of the present disclosure is given.

[0145] Example 1:

[0146] Combine Figure 3-Figure 4 As shown:

[0147] The pattern of the resistor to be extracted in the integrated circuit is cut into pieces to obtain a first pattern 10 , which is a multi-port rectangle.

[0148] Based on the location of the port 30 in the first figure 10, the first figure 10 is divided into four rectangular areas. In the rectangular area with the port 30, a target point 50 is inserted at the midpoint of the port 30, at the through hole 60, at the center point of the rectangular area, and at the corresponding point on the midline of the through hole in the rectangular area. In the rectangular area without the port 30, a target point 50 is inserted only at the through hole 60. Based on the location of the target point 50, the resistor network of the first figure 10 is formed. According to the rectangular resistance formula R = Rs(L / W), the first resistance of each rectangular area is calculated from left to right and from bottom to top, where L is the distance between the two target points and W is the length or width of the rectangular area. In addition, except for the leftmost rectangular area, the cross-area resistance of each rectangular area is calculated. The horizontal and vertical resistances between the last point of the previous rectangular area and the first point of the current rectangular area are calculated to ensure connectivity between the rectangular areas. The resistance of the first figure 10 is determined based on each first resistance and the cross-area resistance between each rectangular area. In this way, the resistance between any two points in the first figure 10 can be determined.

[0149] Example 2:

[0150] Combine Figure 7-Figure 8 As shown:

[0151] The graph of the resistor to be extracted in the integrated circuit is cut into pieces to obtain a first graph 10 , where the first graph 10 is a dual-port trapezoid.

[0152] by Figure 8 The midpoints of the short parallel sides of the trapezoid draw two parallel lines parallel to the two hypotenuses, dividing the trapezoid into two parallelograms and a triangle. Figure 7The division method in is used to divide it into multiple identical triangles. Each triangle can be represented by the conductivity matrix to represent the resistance between the two vertices. Since one side of the triangle is on the port and the port is close to equipotential, only two resistors R1 and R2 are required. Multiple R1 and R2 are connected in parallel to calculate the first resistance of the parallelogram. After the trapezoid is divided, the middle triangle is also solved in the same way. Finally, the first resistors of the two parallelograms and the middle triangle are connected in parallel to calculate the resistance of the two-port trapezoid (first figure 10). According to the resistance of the first figure and the connection between the first figures (for example, parallel connection or series connection), the resistance of the resistor to be extracted can be determined.

[0153] Example 3:

[0154] Combine Figure 5-Figure 6 As shown:

[0155] The pattern of the resistor to be extracted in the integrated circuit is cut into pieces to obtain a first pattern 10 , where the first pattern 10 is a multi-port trapezoid.

[0156] The first figure 10 is divided into eight rectangular areas according to the positions of the ports in the first figure 10. In the rectangular area with ports, the target points are inserted at the midpoint of the port, the through hole, the center point of the rectangular area, and the corresponding point of the through hole in the midline of the rectangular area. In the rectangular area without ports, the target points are only inserted at the through hole. According to the positions of the target points, the resistor network of the first figure 10 is formed, and the first resistor of each rectangular area is calculated from left to right and from bottom to top according to the rectangular resistance formula R=Rs(L / W). Among them, L is the distance between the two target points, and W is selected as follows Figure 6 The midline length of the trapezoidal area where the two target points are located is shown in . Furthermore, except for the leftmost rectangular area, cross-area resistances are calculated for all other rectangular areas. The horizontal and vertical resistances between the last point of the previous rectangular area and the first point of the current rectangular area are calculated to ensure connectivity between the rectangular areas. Based on each first resistance and the cross-area resistance between each rectangular area, the resistance of first graph 10 is determined. This allows the resistance between any two points in first graph 10 to be determined.

[0157] In an exemplary embodiment, a device for extracting resistance in an integrated circuit is provided. Figure 9As shown, the extraction device includes a slicing module 101, a dividing module 102, and an extraction module 103. The slicing module 101 is configured to slice a pattern of resistors to be extracted in an integrated circuit to obtain a first pattern. The first pattern is different from the second pattern, and the current in the second pattern flows from one port of the second pattern to another port in a preset direction. The dividing module 102 is configured to divide the area where the first pattern is located to obtain multiple target areas. The extraction module 103 is configured to extract the first resistors from at least part of the target areas.

[0158] The device for extracting resistance in an integrated circuit provided in this embodiment can divide a first graph with unclear current flow direction, obtained by segmenting the graph of the resistance to be extracted, into multiple target regions, and then extract the first resistance of at least some of the target regions. This allows the extraction of resistance between any points in the resistance to be extracted. The device can simplify the calculation process, improve the efficiency of extracting resistance in the integrated circuit, and ensure a certain degree of extraction accuracy, effectively solving the calculation problem when processing conductors with unclear current flow direction in the integrated circuit.

[0159] In one exemplary embodiment, an electronic device is provided, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to implement the method for extracting resistance in an integrated circuit provided in the exemplary embodiments of the present disclosure. When applied to extracting resistance in an integrated circuit, the electronic device can divide a first graph, obtained by segmenting the graph of the resistance to be extracted, where the current flow direction is unclear, into multiple target regions, and then extract the first resistance of at least some of the target regions. This allows the extraction of resistance between any points in the resistance to be extracted, simplifies the calculation process, improves the efficiency of extracting resistance in the integrated circuit, and ensures a certain degree of extraction accuracy, effectively resolving the computational difficulties associated with processing conductors in the integrated circuit where the current flow direction is unclear.

[0160] The contents described above can be implemented individually or in combination in various ways, and these variations are all within the scope of protection of the present disclosure.

[0161] Finally, it should be noted that in this article, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements that are inherent to such process, method, article or apparatus.

[0162] The above embodiments are intended only to illustrate the technical solutions of the present disclosure, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they may modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and such modifications or replacements do not deviate from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A method for extracting resistance in an integrated circuit, characterized in that: The extraction method comprises: Slicing a pattern of a resistor to be extracted in an integrated circuit to obtain a first pattern, wherein the first pattern is different from a second pattern, and current in the second pattern flows from one port of the second pattern to another port in a preset direction; Dividing the area where the first graphic is located to obtain multiple target areas; The first resistance of at least a portion of the target area is respectively extracted.

2. The method for extracting resistance in an integrated circuit according to claim 1, wherein: The multiple target areas are all rectangular areas; The extracting the first resistance of at least a portion of the target area separately includes: inserting target points in at least a portion of the rectangular area to form a resistor network of the first pattern; The resistance between at least some of the adjacent target points on the resistance network is determined as the first resistance.

3. The method for extracting resistance in an integrated circuit according to claim 2, wherein: Inserting a target point in at least a portion of the rectangular area includes: In the case where the rectangular area includes a port, inserting the target point between the midpoint of the port of the rectangular area and the center point of the rectangular area; In the case where the rectangular area includes a through hole, the through hole in the rectangular area and a corresponding point of the through hole in the center line of the rectangular area are inserted into the target point.

4. The method for extracting resistance in an integrated circuit according to claim 2, wherein: The first shape is a rectangle and / or a trapezoid including a first number of ports.

5. The method for extracting resistance in an integrated circuit according to claim 1, wherein: The plurality of target areas are triangular areas, and the vertices of the plurality of triangular areas are all located at ports of the first graph; and extracting the first resistance of at least part of the target areas respectively includes: determining a second resistance between two vertices located at different ports in each of the triangular regions; The first resistor is determined according to each of the second resistors.

6. The method for extracting resistance in an integrated circuit according to claim 5, wherein: The determining of the second resistance between two vertices located at different ports in each of the triangular regions includes: Determine each of the second resistors by a finite element method; and / or, The determining the first resistance according to each of the second resistances includes: The second resistors are connected in parallel to obtain the first resistor.

7. The method for extracting resistance in an integrated circuit according to claim 6, wherein: The first shape is a parallelogram and / or a trapezoid including a second number of ports.

8. The method for extracting resistance in an integrated circuit according to any one of claims 1 to 7, characterized in that: The area where the first graphic is located is divided to obtain multiple target areas, including: In a case where the first graphic is a rectangle including a first number of ports, dividing the area where the rectangle is located into a plurality of rectangular areas; In a case where the first figure is a parallelogram including a second number of ports, dividing the area where the parallelogram is located into a plurality of congruent triangular areas; In the case where the first graphic is a trapezoid including the second number of ports, dividing the area where the trapezoid is located into a plurality of parallelogram areas and triangular areas; and dividing each of the parallelogram areas into a plurality of triangular areas; In a case where the first graphic is a trapezoid including the first number of ports, a polygonal area where the trapezoid is located is divided into a plurality of rectangular areas, where the polygonal areas are associated with the ports of the first graphic.

9. A device for extracting resistance in an integrated circuit, characterized in that: The extraction device comprises: a slicing module configured to slice a pattern of resistance to be extracted in the integrated circuit to obtain a first pattern, wherein the first pattern is different from a second pattern, and current in the second pattern flows from one port of the second pattern to another port in a preset direction; a dividing module, wherein the dividing module is configured to divide the area where the first graphic is located into a plurality of target areas; The extraction module is configured to extract the first resistance of at least part of the target area respectively.

10. An electronic device, characterized in that: The electronic device comprises: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the method for extracting resistance in an integrated circuit according to any one of claims 1 to 8.

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