Driving circuit, driving method and display device

Abstract

The invention discloses a driving circuit, a driving method and a display device, the driving circuit is used for driving a display panel, the display panel comprises a plurality of data lines arranged in the horizontal direction and a plurality of gate lines arranged in the vertical direction, and the driving circuit comprises a gate driving module, a source driving module and a chip on film. The grid electrode driving module outputs a grid electrode driving signal to the grid electrode line, and the source electrode driving module outputs a data driving signal to the chip-on-film and then outputs the data driving signal to the data line through the chip-on-film and the fan-out line; the number of the chip-on-films is multiple, and the lengths of the fan-out wires corresponding to the fan-out areas of the chip-on-films are gradually increased in the transmission direction of the gate drive signals. According to the invention, the influence of the impedance of the gate lines, the data lines and the fan-out wires on signal transmission, especially the obvious boundary line appearing at the junction of the chip on film caused by the fan-out wires, is considered, and the fan-out wires are rearranged, so that the brightness difference appearing at the boundary line is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit, a driving method and a display device. Background Art

[0002] As the size of LCD panels increases, the fan-out area of ​​the LCD panel has become short in the middle and long on both sides due to routing space limitations. This results in a smaller RC loading on the source line near the middle of the chip-on-film (COF) and a larger RC loading on the source line on both sides.

[0003] Due to the RC differences of the data lines in the fanout area and the proximity of the pixels to the gate lines, the charging time of pixels at different positions on the left and right is different. The overall charging time of the channels on the sides is shorter than that in the middle. The data line in the center of each COF has a longer charging time, while the data lines on the sides have a shorter charging time. This will cause color shift on both sides of the display panel. In special images, there will be brightness differences between the pixels corresponding to the source line in the center of the COF and the pixels corresponding to the source lines on the sides (because it is related to the fanout impedance, it is called fanout mura). Summary of the Invention

[0004] The purpose of the present application is to provide a driving circuit, a driving method and a display device capable of improving the brightness difference at the junction of the data lines connected to the chip-on-film.

[0005] The present application discloses a driving circuit, which is used to drive a display panel. The display panel includes multiple data lines arranged in a horizontal direction and multiple gate lines arranged in a vertical direction. The driving circuit includes a gate driving module, a source driving module and a flip chip film. The gate driving module outputs a gate driving signal to the gate line; the source driving module outputs a data driving signal to the flip chip film, and the data driving signal is then output to the data line through the flip chip film and the fan-out wiring of the fan-out area; wherein the flip chip film is provided with multiple fan-out wirings, and along the transmission direction of the gate driving signal, the length of the fan-out wiring corresponding to the fan-out area of ​​each flip chip film gradually increases.

[0006] Optionally, the gate driving module includes a first gate driving circuit and a second gate driving circuit provided on both sides of the display panel, one end of the gate line is connected to the first gate driving circuit, and the other end is connected to the second gate driving circuit;

[0007] The source driver module includes a first source driver module and a second source driver module, the chip-on-chip film includes a plurality of first chip-on-chip films and a plurality of second chip-on-chip films, the output end of the first source driver module is connected to the plurality of first chip-on-chip films, and the output end of the second source driver module is connected to the plurality of second chip-on-chip films;

[0008] The display panel includes a fan-out area, the fan-out area including a first fan-out area and a second fan-out area, the first fan-out area corresponding to each first chip-on-film is provided with a first fan-out sub-area, the length of the fan-out traces in each first fan-out sub-area gradually increases along the first direction, the second fan-out area corresponding to each chip-on-film is provided with a second fan-out sub-area, the length of the fan-out traces in each second fan-out sub-area gradually increases along the second direction;

[0009] The first direction and the second direction are opposite to each other. The first direction is the direction from the first gate driving circuit to the second gate driving circuit, and the second direction is the direction from the second gate driving circuit to the first gate driving circuit.

[0010] Optionally, the driving circuit includes a timing control module, and the timing control module is connected to the first source driving module and the second source driving module respectively;

[0011] The change slope of the delay time of the data driving signal output by the first source driving module to the data line is the same as the change slope of the delay time of the scanning signal output by the first gate driving module to the gate line. The change slope of the delay time of the data driving signal output by the second source driving module to the data line is the same as the change slope of the delay time of the scanning signal output by the second gate driving module to the gate line. The timing control module adjusts the charging time of each data line connected to the flip film to be consistent through a data delay algorithm.

[0012] Optionally, the driving circuit further includes a first delay adjustment circuit and a second delay adjustment circuit;

[0013] The first delay adjustment circuit is provided on the first source driver module, and includes a plurality of sub-adjustment circuits. Each sub-adjustment circuit is provided with a resistor and a capacitor corresponding to all fan-out traces connected to each flip chip film, and the resistance value of the resistor and the capacitance value of the capacitor gradually increase along the first direction;

[0014] The second delay adjustment circuit is arranged on the second source driver module. The second delay adjustment circuit includes multiple sub-adjustment circuits. Each sub-adjustment circuit is equipped with a resistor and a capacitor corresponding to all fan-out lines connected to each flip chip film, and the resistance value of the resistor and the capacitance value of the capacitor gradually increase along the second direction.

[0015] Optionally, the display panel is divided into at least two areas along a first direction, the two areas being a first area and a second area, the data lines of the first area being connected to the fan-out lines of the first fan-out area in a one-to-one correspondence, and the data lines of the second area being connected to the fan-out lines of the second fan-out area in a one-to-one correspondence;

[0016] A plurality of pixels are provided in each of the first area and the second area, and the compensation number of the pixels in the first area and the compensation coefficient of the pixels in the second area are K1 and K2 respectively;

[0017] The compensation coefficients of the pixels on each data line are linearly interpolated according to the compensation coefficients of adjacent areas to obtain the compensation coefficients of the pixels to be compensated, and the charging time of each column of pixels is adjusted to be consistent.

[0018] Optionally, the gate driving module includes a first gate driving circuit, and the first gate driving circuit is connected to the gate line;

[0019] The source driver module includes a first source driver module and a second source driver module, the chip-on-chip film includes a plurality of first chip-on-chip films and a plurality of second chip-on-chip films, the output end of the first source driver module is connected to the plurality of first chip-on-chip films, and the output end of the second source driver module is connected to the plurality of second chip-on-chip films;

[0020] The display panel includes a fan-out area, the fan-out area including a first fan-out area and a second fan-out area, the first fan-out area corresponding to each first chip-on-film is provided with a first fan-out sub-area, the length of the fan-out traces in each first fan-out sub-area gradually increases along the first direction, the second fan-out area corresponding to each chip-on-film is provided with a second fan-out sub-area, the length of the fan-out traces in each second fan-out sub-area gradually increases along the first direction;

[0021] The first direction is the direction in which the first gate driving circuit outputs the gate driving signal to the gate line.

[0022] The present application also discloses a driving method, which is used for any of the above driving circuits to drive a display panel. The driving method includes:

[0023] Generate gate drive signals and output them to the gate lines; generate data drive signals and output them to the data lines through the flip chip film and the fan-out lines of the fan-out area;

[0024] Controlling the change slope of the delay time of the data driving signal on the data line to be the same as the change slope of the delay time of the scanning signal on the gate line;

[0025] The charging time of the data lines connected to each flip-chip film is controlled to be the same.

[0026] Optionally, all fan-out traces connected to each flip-chip film are provided with a resistor and a capacitor, and the step of controlling the change slope of the delay time of the data driving signal on the data line to be the same as the change slope of the delay time of the scanning signal on the gate line includes:

[0027] Acquire, along a first direction, the delay time of a data line connected to the first fan-out trace and the delay time of a data line connected to the last fan-out trace corresponding to each chip-on-film (COF), and calculate using a first preset formula to obtain a first change slope of the data line connected to the corresponding COF;

[0028] Acquire, along the second direction, the delay time of the gate line connected to the first fan-out trace and the delay time of the gate line connected to the last fan-out trace corresponding to each chip-on-film, and calculate using a second preset formula to obtain a second change slope of the data line connected to the corresponding chip-on-film;

[0029] Whether to connect the resistor and the capacitor is controlled according to the first change slope and the second change slope, so as to perform delay compensation on the data driving signal.

[0030] Optionally, the display panel is divided into at least two areas along a first direction, the two areas being a first area and a second area, the data lines of the first area being connected to the fan-out traces of the first fan-out area in a one-to-one correspondence, and the data lines of the second area being connected to the fan-out traces of the second fan-out area in a one-to-one correspondence; a plurality of pixels are provided in each of the first area and the second area, and the compensation number of the pixels in the first area and the compensation coefficient of the pixels in the second area are K1 and K2, respectively;

[0031] The driving method further comprises the following steps:

[0032] Locate the area where the compensation pixels are located and determine the compensation coefficient;

[0033] According to the compensation coefficients of the adjacent areas and the pixel columns of the intermediate pixels between the compensation pixel and the adjacent areas, a linear difference is performed using the compensation coefficient formula to obtain the compensation coefficient of the pixel to be compensated, and a compensation table is generated;

[0034] Where m is the pixel column from the compensation pixel to the middle pixel in the first region, and n is the pixel column from the compensation pixel to the middle pixel in the second region. The compensation coefficient formula is as follows:

[0035] K=(K1*n+K2*m) / (m+n).

[0036] The present application also discloses a display device, which includes a display panel and any of the driving circuits described above, wherein the driving circuit drives the display panel using any of the driving methods described above.

[0037] Compared with the scheme of transmitting data to the source driver module with different reverse delay times to supplement the signal delay at the near and far ends of the gate line, the present application provides a driving circuit to adjust the part of the data line located in the fan-out area, namely the fan-out line. Along the transmission direction of the gate drive signal, the length of the fan-out line corresponding to the fan-out area of ​​each flip chip film gradually increases. The longer the delay on the gate line, the longer the pixel charging time, and the longer the data signal delay, the shorter the charging time. The arrangement of the fan-out line is changed, and the overall impedance of the gate line and the fanout line is adjusted. The slope of the change of the data delay on the data line (source line) offsets the slope of the gate signal delay, so that the charging time of the pixels at the COF junction is close, thereby reducing the brightness difference at the junction and improving the display effect and user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without inventive work. In the drawings:

[0039] Figure 1 is a schematic structural diagram of a driving circuit according to a first embodiment of the present application;

[0040] Figure 2 is a schematic structural diagram of a driving circuit according to a second embodiment of the present application;

[0041] Figure 3 is a data driving signal delay waveform diagram of the second embodiment of the present application;

[0042] Figure 4 2 is a gate drive signal delay waveform diagram of the second embodiment of the present application;

[0043] Figure 5 This is a charging time adjustment diagram of the second embodiment of the present application;

[0044] Figure 6is a schematic structural diagram of a driving circuit according to a third embodiment of the present application;

[0045] Figure 7 is an enlarged schematic diagram of the first delay adjustment circuit of the third embodiment of the present application;

[0046] Figure 8 is an enlarged schematic diagram of the second delay adjustment circuit of the third embodiment of the present application;

[0047] Figure 9 is a schematic structural diagram of a driving circuit according to a fourth embodiment of the present application;

[0048] Figure 10 is a schematic structural diagram of a driving circuit according to a fifth embodiment of the present application;

[0049] Figure 11 is a flowchart of a driving method according to a sixth embodiment of the present application;

[0050] Figure 12 is a flowchart of a driving method according to a seventh embodiment of the present application;

[0051] Figure 13 is a schematic flow chart of a driving method according to an eighth embodiment of the present application;

[0052] Figure 14 It is a schematic structural diagram of a display device according to the ninth embodiment of the present application.

[0053] Among them, 100, drive circuit; 110, gate drive module; 111, first gate drive circuit; 112, second gate drive circuit; 120, source drive module; 121, first source drive module; 122, second source drive module; 130, chip-on-film; 131, first chip-on-film; 132, second chip-on-film; 140, fan-out area; 141, first fan-out area; 1411, first fan-out sub-area; 142, second Fan-out area; 1421, second fan-out sub-area; 150, timing control module; 160, first delay adjustment circuit; 170, second delay adjustment circuit; 180, sub-regulation circuit; 200, display panel; 201, gate line; 202, data line; 203, pixel; 204, fan-out trace; 210, first area; 220, second area; 300, display device; resistors - R0 ~ 960R; capacitors - C0 ~ 960C0. DETAILED DESCRIPTION

[0054] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative. However, the present application can be implemented in many alternative forms and should not be construed as being limited to the embodiments described herein.

[0055] The present application is described in detail below with reference to the accompanying drawings and optional embodiments.

[0056] refer to Figure 1 As shown, as a first embodiment of the present application, a driving circuit 100 is disclosed, which is used to drive a display panel 200. The display panel 200 includes crisscrossing data lines 202 and gate lines 201. That is, when the display panel 200 is placed normally, multiple data lines 202 are arranged in the horizontal direction, and multiple gate lines 201 are arranged in the vertical direction. The driving circuit 100 includes a gate driving module 110, a source driving module and a flip chip film 130. The gate driving module 110 outputs a gate driving signal to the gate line 201, and the source driving module 120 outputs a data driving signal to the flip chip film 130. The data driving signal is output to the fan-out trace 204 of the fan-out area 140 through the flip chip film 130, and then output to the data line 202. The flip chip film 130 is provided with multiple fan-out traces 204, and the length of the fan-out trace 204 corresponding to the fan-out area 140 of each flip chip film 130 gradually increases along the transmission direction of the gate driving signal.

[0057] In this embodiment, adjustments are made to a portion of the data lines 202 located in the fan-out area 140, namely, the fan-out traces 204, to change the arrangement of the fan-out traces 204. The original arrangement in which the multiple fan-out traces 204 corresponding to each chip-on-film 130 gradually increase from the middle to both sides is changed to a arrangement in which the length of the traces in the fan-out area 140 corresponding to each chip-on-film 130 gradually increases along the transmission direction of the gate drive signal, thereby adjusting the overall impedance of the gate lines 201 and the fan-out traces 204. The slope of the change in the signal delay on the data line 202 offsets the slope of the gate drive signal delay, thereby making the charging time of the pixels 203 at the COF junction close, thereby reducing the brightness difference at the junction and improving the display effect and user experience.

[0058] refer to Figure 2 As shown, as the second embodiment of the present application, it is a further refinement and improvement of the above-mentioned first embodiment, referring to Figures 1 to 4As shown, the gate driver module 110 includes a first gate driver circuit 111 and a second gate driver circuit 112 arranged on both sides of the display panel 200, one end of the gate line 201 is connected to the first gate driver circuit 111, and the other end is connected to the second gate driver circuit 112; that is, the display panel 200 is a bilaterally driven display panel 200; the source driver module 120 includes a first source driver module 121 and a second source driver module 122, and the chip-on-film 130 includes a plurality of first chip-on-films 131 and a plurality of second chip-on-films 132, the output end of the first source driver module 121 is connected to the plurality of first chip-on-films 131, and the output end of the second source driver module 122 is connected to the plurality of second chip-on-films 132; one end of each chip-on-film 130 is connected to the output end of the source driver module, that is, the data output channels CH1-CH960, and the other end is connected to the routing of the fan-out area 140, that is, part of the data line segments distributed in the fan-out area 140.

[0059] The display panel 200 includes a fan-out area 140, and the fan-out area 140 includes a first fan-out area 141 and a second fan-out area 142. The first fan-out area 141 is provided with a first fan-out sub-area 1411 corresponding to each first flip chip film 131, and the length of the fan-out trace 204 in each first fan-out sub-area 1411 gradually increases along the first direction. The second fan-out area 142 is provided with a second fan-out sub-area 1421 corresponding to each flip chip film 130, and the length of the fan-out trace 204 in each second fan-out sub-area 1421 gradually increases along the second direction; wherein, the first direction and the second direction are opposite, the first direction is the direction of the first gate drive circuit 111 toward the second gate drive circuit 112, and the second direction is the direction of the second gate drive circuit 112 toward the first gate drive circuit 111, the first direction is also the direction in which the first gate drive circuit 111 outputs the gate drive signal, and the second direction is also the direction in which the second gate drive circuit 112 outputs the gate drive signal.

[0060] As a double-sided driven display panel 200, the COF binding position is changed from the original center to the left side of the COF binding position of the left half screen and the right side of the COF binding position of the right half screen; in this way, the routing of the source line of a COF on the left half screen becomes longer and longer from left to right, and the load (RCloading) also becomes larger and larger from left to right; the routing of the source line of a COF on the right half screen becomes longer and longer from right to left, and the load (RCloading) also becomes larger and larger from right to left, that is, the length of the fan-out line 204 in each of the first fan-out sub-areas 1411 along the first direction gradually increases, and the length of the fan-out line 204 in each of the second fan-out sub-areas 1421 along the second direction gradually increases; as shown in FIG. Figure 3As shown, each COF corresponds to the data signal delay time on all source lines. Figure 4 For each source line, the delay time of the Gate signal on the pixel is calculated based on Figure 3 and Figure 4 It can be seen that the longer the gate delay is, the longer the pixel charging time is. The longer the data signal delay is, the shorter the charging time is. So we adjust the overall impedance of the gate line and fanout line to make the slope of the data delay on the source line just equal to the slope of the gate signal delay. After the two are offset, the charging time is as follows: Figure 5 As shown, the charging time of all source lines in each COF is equal. The charging time of the COF increases as it moves toward the center. This ensures that the charging time of the source lines connected to each COF is consistent, improving color shift and fanout mura on both sides of the COF while preventing the COF boundary problem.

[0061] Furthermore, the driving circuit 100 includes a timing control module 150, which is connected to the first source driving module 121 and the second source driving module 122 respectively; the change slope of the delay time of the data driving signal output by the first source driving module 121 to the data line 202 is the same as the change slope of the delay time of the scanning signal output by the first gate driving module 110 to the gate line 201, and the change slope of the delay time of the data driving signal output by the second source driving module 122 to the data line 202 is the same as the change slope of the delay time of the scanning signal output by the second gate driving module 110 to the gate line 201. The slopes are the same, and the timing control module 150 adjusts the charging time of the data lines 202 connected to each flip chip film 130 to be consistent through a data delay algorithm; wherein, in order to make the change slope of the delay time of the scanning signal on the gate line 201 and the change slope of the delay time of the data driving signal on the data line 202 the same, the gate line will also be changed. When other conditions remain unchanged, the resistance of different gate line segments in the gate line is adjusted by changing the line width of the gate line. For example, the line width of the gate line decreases from the middle to both sides in sequence, so that the impedance of the middle area of ​​the gate line is smaller. Of course, corresponding capacitors and resistors can also be set for the corresponding gate lines to adjust the delay time of the driving signal on the gate line.

[0062] refer to Figure 6 As shown, as the third embodiment of this application, it is a further refinement and improvement of the above second embodiment, referring to Figures 6 to 8As shown, the driving circuit 100 also includes a first delay adjustment circuit 160 and a second delay adjustment circuit 170; the first delay adjustment circuit 160 is arranged on the first source driving module 121, and the first delay adjustment circuit 160 includes a plurality of sub-adjustment circuits 180, each sub-adjustment circuit 180 is provided with a resistor and a capacitor corresponding to all fan-out traces 204 connected to each flip chip film 130, and the resistance value of the resistor and the capacitance value of the capacitor gradually increase along the first direction; the second delay adjustment circuit 170 is arranged on the second source driving module 122, and the second delay adjustment circuit 170 includes a plurality of sub-adjustment circuits 180, each sub-adjustment circuit 180 is provided with a resistor R and a capacitor C corresponding to all fan-out traces 204 connected to each flip chip film 130, and the resistance value of the resistor and the capacitance value of the capacitor gradually increase along the second direction.

[0063] Taking into account that in the second embodiment, when the RC delay of the gate line 201 (Gate line) of the display panel 200 and the impedance difference of each COF source line cannot be completely offset due to process fluctuations, the charging time may appear with the process fluctuations. For some display panels 200, the charging time of the left COF source line becomes longer and longer from left to right, and the charging time of the right COF source line becomes longer and longer from right to left; for some display panels 200, the charging time of the left COF source line becomes longer and longer from right to left, and the charging time of the right COF source line becomes longer and longer from left to right. The display panel 200 will have a slight boundary line at the COF boundary. This embodiment adds a right-increasing RC delay circuit and a left-increasing RC delay circuit on the basis of the source driver, namely, a first delay adjustment circuit 160 and a second delay adjustment circuit 170. Among the two delay adjustment circuits, the right-increasing RX delay circuit, namely, the first delay adjustment circuit 160, connects an RC delay element in series to the output of the source driver, and the values ​​of R and C increase from left to right, and the reference value of RC can be selected in multiple groups according to the factory process; the left-increasing RX The delay circuit, or second delay adjustment circuit 170, inserts an RC delay element in series with the source driver output. The R and C values ​​increase from right to left, and the RC baseline value can be selected in multiple sets based on the factory process. This allows for compensation based on the actual charging differences of the source lines on each COF on the panel, ensuring consistent charging time for the source lines connected to each COF.

[0064] refer to Figure 9As shown, as the fourth embodiment of the present application, which is also a further refinement and improvement of the above-mentioned second embodiment, the display panel 200 is divided into at least two areas along the first direction, the two areas being a first area 210 and a second area 220, the data lines 202 of the first area 210 are connected one-to-one with the fan-out traces 204 of the first fan-out area 141, and the data lines 202 of the second area 220 are connected one-to-one with the fan-out traces 204 of the second fan-out area 142; a plurality of pixels 203 are provided in both the first area 210 and the second area 220, the compensation number of the pixels 203 in the first area 210 and the compensation coefficient of the pixels 203 in the second area 220 are K1 and K2, respectively; wherein the compensation coefficient of the pixels 203 on each data line 202 is linearly differentiated according to the compensation coefficients of adjacent areas to obtain the compensation coefficient of the pixel 203 to be compensated, and the charging time of each column of pixels 203 is adjusted to be consistent.

[0065] This embodiment further improves upon the second embodiment. Unlike the third embodiment, this embodiment considers that, while adding an RC delay circuit to the source driver in the third embodiment requires adding an RC delay to each source line (or adding a set of RC delays to several source lines), while this improves the mura problem at the COF boundary, it also increases the source driver wafer size, thereby increasing the cost of the source driver module 120. Therefore, this application presents another improvement, proposing a novel linear OD compensation method to address the charging differences between each COF source line. The OD algorithm generally uses a common compensation table. This table specifies that when grayscale A in the previous frame switches to grayscale B in the next frame, the second grayscale compensates grayscale B to grayscale C. This compensation table applies to all pixels 203 in the entire panel. Furthermore, the panel is divided into several regions, each with multiple pixels 203. Each region has a separate compensation coefficient Kn. The compensation coefficient for the first region 210 is K1, and the compensation coefficient for the second region 220 is K2. During compensation, the second grayscale is compensated based on the compensation coefficient Kn for the panel region. The compensated value is A+Kn*(BA).

[0066] In this solution, based on the partition supplement, the compensation coefficient of each source line corresponding to the pixel 203 is linearly interpolated according to the compensation coefficient of the adjacent area. If the compensation coefficients of the two adjacent OD partitions are K1 and K2 respectively, the two columns of pixels 203 at the center point Q1 of the left partition in the horizontal direction of the pixel 203 point P are taken as an example to illustrate. There are 9 columns of pixels 203 away from the center point Q2 of the right partition. In this way, the OD compensation coefficient of the pixel 203 point P is K = (K1*9+K2*2) / 11. If the OD compensation table is adjusted, the charging time of the center point of each OD partition is compensated to a consistent level. Then, according to this linear OD algorithm, the charging time of each column of pixels 203 can be adjusted to be consistent.

[0067] refer to Figure 10 As shown, as the fifth embodiment of the present application, it is a further improvement of the above-mentioned first embodiment. Unlike the above-mentioned second embodiment, the display panel 200 in this embodiment is a single-sided drive display panel 200, the gate driving module 110 includes a first gate driving circuit 111, and the first gate driving circuit 111 is connected to the gate line 201; the source driving module 120 includes a first source driving module 121 and a second source driving module 122, the chip-on-film 130 includes a plurality of first chip-on-films 131 and a plurality of second chip-on-films 132, the output end of the first source driving module 121 is connected to the plurality of first chip-on-films 131, and the output end of the second source driving module 122 is connected to the plurality of second chip-on-films 132; the display panel 200 includes a fan-out area 140, and the fan-out area 140 includes a first fan-out area 141 and a second fan-out area 142. The first fan-out area 141 is provided with a first fan-out sub-area corresponding to each first chip-on-film 131, and the length of the fan-out trace 204 in each first fan-out sub-area gradually increases along the first direction. The second fan-out area 142 is provided with a second fan-out sub-area corresponding to each chip-on-film 130, and the length of the fan-out trace 204 in each second fan-out sub-area gradually increases along the first direction; wherein, the first direction is the direction in which the first gate drive circuit 111 outputs the gate drive signal to the gate line 201, and is divided into two source drive modules, which may correspond to different areas, such as the upper and lower parts, each part using a different COF and fan-out area 140, so that each source drive module only needs to process half of the data lines 202, which may reduce the signal load and improve the driving capability; at the same time, separate processing may make it easier to adjust their respective delays, because the wiring conditions in different areas are different and require different compensation.

[0068] Furthermore, the driving circuit 100 includes a timing control module 150, which is respectively connected to the first source driver module 121 and the second source driver module 122; the slope of change of the delay time of the data driving signal output by the first source driver module 121 to the data line 202 is the same as the slope of change of the delay time of the scanning signal output by the first gate driver module 110 to the gate line 201; the slope of change of the delay time of the data driving signal output by the second source driver module 122 to the data line 202 is the same as the slope of change of the delay time of the scanning signal output by the first gate driver module 110 to the gate line 201; the timing control module 150 adjusts the charging time of the data line 202 connected to each flip film 130 to be consistent through a data delay algorithm, and dynamically adjusts the delay through structured wiring compensation and timing control algorithm, thereby solving the core problems of signal delay mismatch and inconsistent charging time in the unilateral drive display panel 200, while optimizing wiring space and production yield.

[0069] As shown in FIG11 , as a sixth embodiment of the present application, a driving method is disclosed, which is used for the driving circuit described in any of the above embodiments to drive a display panel. The driving method includes:

[0070] S1: Generate gate drive signals and output them to the gate lines, generate data drive signals and output them to the data lines through the flip chip film and the fan-out lines of the fan-out area;

[0071] S2: controlling the change slope of the delay time of the data driving signal on the data line to be the same as the change slope of the delay time of the scanning signal on the gate line;

[0072] S3: Control the charging time of the data lines connected to each flip-chip film to be the same.

[0073] The driving method in this embodiment is mainly used in the driving circuit in which the wiring arrangement of the fan-out area is changed. The gate driving signal and the data driving signal are normally generated and output separately. The change in the wiring arrangement of the fan-out area can reduce the delay problem caused by the load. In order to ensure the display effect, the change slope of the delay time of the data driving signal is made the same as the change slope of the delay time of the scanning signal on the gate line. Even if there is a delay, it is a synchronous delay to ensure uniform brightness and darkness.

[0074] As shown in FIG12, as the seventh embodiment of the present application, a driving method is disclosed, which is a further refinement and improvement of the fifth embodiment described above, and is mainly used for the driving circuit 100 in the fourth embodiment. Figure 9 and Figure 12As shown, the gate driving module 110 includes a first gate driving circuit 111 and a second gate driving circuit 112 arranged on both sides of the display panel 200, one end of the gate line 201 is connected to the first gate driving circuit 111, and the other end is connected to the second gate driving circuit 112; the source driving module 120 includes a first source driving module 121 and a second source driving module 122, the chip-on-film 130 includes a plurality of first chip-on-films 131 and a plurality of second chip-on-films 132, the output end of the first source driving module 121 is connected to the plurality of first chip-on-films 131 ... The output end of the second source driver module 122 is connected to multiple second flip-chip films 132; the display panel 200 includes a fan-out area 140, and the fan-out area 140 includes a first fan-out area 141 and a second fan-out area 142. The first fan-out area 141 is corresponding to each first flip-chip film 131 and is provided with a first fan-out sub-area. The length of the fan-out trace 204 in each first fan-out sub-area gradually increases along the first direction. The second fan-out area 142 is corresponding to each flip-chip film 130 and is provided with a second fan-out sub-area. The length of the fan-out trace 204 in each second fan-out sub-area gradually increases along the second direction.

[0075] The first direction and the second direction are opposite, the first direction is the direction from the first gate driving circuit 111 to the second gate driving circuit 112, and the second direction is the direction from the second gate driving circuit 112 to the first gate driving circuit 111; the display panel 200 is divided into at least two areas along the first direction, namely a first area 210 and a second area 220, the data lines 202 of the first area 210 are connected to the fan-out traces 204 of the first fan-out area 141 in a one-to-one correspondence, and the data lines 202 of the second area 220 are connected to the fan-out traces 204 of the second fan-out area 142 in a one-to-one correspondence; a plurality of pixels 203 are provided in both the first area 210 and the second area 220, and the compensation number of the pixels 203 in the first area 210 and the compensation coefficient of the pixels 203 in the second area 220 are K1 and K2, respectively;

[0076] The driving method further comprises the following steps:

[0077] S4: Locate the area where the compensation pixel is located and determine the compensation coefficient;

[0078] S5: performing linear interpolation based on the compensation coefficients of the adjacent areas and the pixel columns of the intermediate pixels between the compensation pixel and the adjacent areas using the compensation coefficient formula to obtain the compensation coefficient of the pixel to be compensated, and generating a compensation table;

[0079] Where m is the pixel column from the compensation pixel to the middle pixel in the first region, and n is the pixel column from the compensation pixel to the middle pixel in the second region. The compensation coefficient formula is as follows:

[0080] K=(K1*n+K2*m) / (m+n).

[0081] In this solution, the compensation coefficient for pixel 203 corresponding to each source line is linearly interpolated based on the compensation coefficients of adjacent areas. For example, the compensation coefficients of two adjacent OD partitions are K1 and K2, and the horizontal direction of pixel 203 point P is two columns of pixels 203 from the center point Q1 of the left partition and nine columns of pixels 203 from the center point Q2 of the right partition. The OD compensation coefficient of pixel 203 point P is K = (K1*9+K2*2) / 11. If the OD compensation table is adjusted and the charging time of the center point of each OD partition is compensated to a consistent level, then according to this linear OD algorithm, the charging time of each column of pixels 203 can be adjusted to be consistent.

[0082] As shown in FIG13, as the eighth embodiment of the present application, a driving method is disclosed, which is a further refinement and improvement of the sixth embodiment. The difference from the sixth embodiment is that the driving method of FIG13 is Figure 2 and Figure 13As shown, the gate driving module 110 includes a first gate driving circuit 111 and a second gate driving circuit 112 arranged on both sides of the display panel 200, one end of the gate line 201 is connected to the first gate driving circuit 111, and the other end is connected to the second gate driving circuit 112; the source driving module 120 includes a first source driving module 121 and a second source driving module 122, the chip-on-film 130 includes a plurality of first chip-on-films 131 and a plurality of second chip-on-films 132, the output end of the first source driving module 121 is connected to the plurality of first chip-on-films 131 ... The output ends of the two source driver modules 122 are connected to a plurality of second COFs 132. The display panel 200 includes a fan-out region 140, which includes a first fan-out region 141 and a second fan-out region 142. The first fan-out region 141 is provided with a first fan-out sub-region corresponding to each first COF 131, and the fan-out traces 204 in each first fan-out sub-region gradually increase in length along the first direction. The second fan-out region 142 is provided with a second fan-out sub-region corresponding to each COF 130, and the fan-out traces 204 in each second fan-out sub-region gradually increase in length along the second direction. The first direction and the second direction are opposite, the first direction being the direction from the first gate driver circuit 111 toward the second gate driver circuit 112, and the second direction being the direction from the second gate driver circuit 112 toward the first gate driver circuit 111. The driver circuit 100 includes a timing control module 150, which is connected to the first source driver module 121 and the second source driver module 122, respectively.

[0083] For further reference, Figures 6 to 8 As shown, the driving circuit 100 further includes a first delay adjustment circuit 160 and a second delay adjustment circuit 170; the first delay adjustment circuit 160 is provided on the first source driving module 121, and the first delay adjustment circuit 160 includes a plurality of sub-adjustment circuits 180, each sub-adjustment circuit 180 corresponding to all fan-out traces 204 connected to each flip chip film 130 is provided with a resistor and a capacitor, and along the first direction, the resistance value of the resistor and the capacitance value of the capacitor gradually increase; the second delay adjustment circuit 170 is provided on the second source driving module 122, and the second delay adjustment circuit 170 includes a plurality of sub-adjustment circuits 180, each sub-adjustment circuit 180 corresponding to all fan-out traces 204 connected to each flip chip film 130 is provided with a resistor R and a capacitor C, and along the second direction, the resistance value of the resistor and the capacitance value gradually increase; the step of controlling the change slope of the delay time of the data driving signal on the data line to be the same as the change slope of the delay time of the scanning signal on the gate line includes:

[0084] S21: Acquire, along a first direction, a delay time of a data line connected to a first fan-out trace and a delay time of a data line connected to a last fan-out trace corresponding to each chip-on-film (COF), and calculate using a first preset formula to obtain a first change slope of the data line connected to the corresponding COF;

[0085] S22: Acquire, along the second direction, the delay time of the gate line connected to the first fan-out trace and the delay time of the gate line connected to the last fan-out trace corresponding to each chip-on-film, and calculate using a second preset formula to obtain a second change slope of the data line connected to the corresponding chip-on-film;

[0086] S23: Controlling whether to connect a resistor and a capacitor according to the first change slope and the second change slope to perform delay compensation on the data driving signal.

[0087] Considering that the change slope of the delay time of the data drive signal on the data line is the same as the change slope of the delay time of the scanning signal on the gate line, it may not be possible to completely cancel each other out. Therefore, the delay change slope of the chip-on-film (COF) fan-out line is calculated by direction (first direction / second direction), and resistors and capacitors are dynamically connected based on the slope for delay compensation. Through direction-specific slope analysis and dynamic RC compensation, the timing problem caused by the delay gradient of the fan-out line is solved. By inserting an RC delay element in series at the source driver output, the values ​​of R and C are selected according to actual conditions, and directional compensation is performed based on the actual charging differences of the source line on each COF, so that the source line charging of each COF is actually consistent.

[0088] The step S3 further comprises the following steps:

[0089] S31: The timing control module adjusts the charging time of the data lines connected to each flip chip to be consistent through a data delay algorithm.

[0090] In this embodiment, step S31 is performed after step S2. Step S1 generates a gate drive signal to gate line 201, and a data drive signal to chip-on-film 130, fan-out area 140 routing, and data line 202. The gate drive signal is used to control the gate line 201's selection, illuminating pixel 203 row by row, while the data drive signal transmits image data to pixel 203. Chip-on-film (COF) 130 refers to a chip mounted directly on a flexible film. The fan-out area 140 routing may be used to connect the COF to a denser wiring area, such as to reduce signal delay or improve accuracy. Step S2 controls the delay time slope of the data drive signal to be the same as the delay time slope of the scan signal, synchronizing the data and scan signal timings and avoiding data errors caused by gate line 201 not being selected when data arrives. If the delay change slopes of the two are consistent, signal synchronization may be improved at different grayscales or different positions, reducing image anomalies such as image sticking or color shift. In step S31, considering that different data lines 202 have different charging times due to differences in physical length or load, an algorithm is used to compensate for the different charging times of all data lines 202, thereby ensuring the consistency of the pixel 203 voltage and improving the display uniformity. Therefore, the timing control module 150 uses a data delay algorithm to adjust the charging time of the data lines 202 connected to each flip film 130 to be consistent.

[0091] As shown in Reference 14 , as the ninth embodiment of the present application, a display device 300 is disclosed, which includes a display panel 200 and a driving circuit 100 as described above. The driving circuit 100 drives the display panel 200 using the driving method described in any of the above embodiments.

[0092] It should be noted that the limitations of the various steps involved in this solution, without affecting the implementation of the specific solution, are not considered to limit the order of the steps, that is, the steps written in the front can be executed first, or can be executed later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application. The inventive concept of this application can form a large number of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the various embodiments or technical features described above can be arbitrarily combined to form new embodiments. After the various embodiments or technical features are combined, the original technical effects will be enhanced.

[0093] The above content is a further detailed description of the present application in conjunction with specific optional implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be considered to fall within the scope of protection of the present application.

Claims

1. A driving circuit for driving a display panel, wherein the display panel comprises a plurality of data lines arranged in a horizontal direction and a plurality of gate lines arranged in a vertical direction, wherein: The driving circuit includes a gate driving module, a source driving module and a flip chip film. The gate driving module outputs a gate driving signal to the gate line; the source driving module outputs a data driving signal to the flip chip film, and the data driving signal is then output to the data line through the flip chip film and the fan-out wiring of the fan-out area; wherein the flip chip film is provided with multiple fan-out wirings, and along the transmission direction of the gate driving signal, the length of the fan-out wiring corresponding to the fan-out area of ​​each flip chip film gradually increases.

2. The driving circuit according to claim 1, wherein: The gate driving module includes a first gate driving circuit and a second gate driving circuit arranged on both sides of the display panel, one end of the gate line is connected to the first gate driving circuit, and the other end is connected to the second gate driving circuit; The source driver module includes a first source driver module and a second source driver module, the chip-on-chip film includes a plurality of first chip-on-chip films and a plurality of second chip-on-chip films, the output end of the first source driver module is connected to the plurality of first chip-on-chip films, and the output end of the second source driver module is connected to the plurality of second chip-on-chip films; The display panel includes a fan-out area, the fan-out area including a first fan-out area and a second fan-out area, the first fan-out area corresponding to each first chip-on-film is provided with a first fan-out sub-area, the length of the fan-out traces in each first fan-out sub-area gradually increases along the first direction, the second fan-out area corresponding to each chip-on-film is provided with a second fan-out sub-area, the length of the fan-out traces in each second fan-out sub-area gradually increases along the second direction; The first direction and the second direction are opposite to each other. The first direction is the direction from the first gate driving circuit to the second gate driving circuit, and the second direction is the direction from the second gate driving circuit to the first gate driving circuit.

3. The driving circuit according to claim 2, wherein: The driving circuit includes a timing control module, and the timing control module is connected to the first source driving module and the second source driving module respectively; The change slope of the delay time of the data driving signal output by the first source driving module to the data line is the same as the change slope of the delay time of the scanning signal output by the first gate driving module to the gate line. The change slope of the delay time of the data driving signal output by the second source driving module to the data line is the same as the change slope of the delay time of the scanning signal output by the second gate driving module to the gate line. The timing control module adjusts the charging time of each data line connected to the flip film to be consistent through a data delay algorithm.

4. The driving circuit according to claim 2, wherein: The driving circuit further includes a first delay adjustment circuit and a second delay adjustment circuit; The first delay adjustment circuit is provided on the first source driver module, and includes a plurality of sub-adjustment circuits. Each sub-adjustment circuit is provided with a resistor and a capacitor corresponding to all fan-out traces connected to each flip chip film, and the resistance value of the resistor and the capacitance value of the capacitor gradually increase along the first direction; The second delay adjustment circuit is arranged on the second source driver module. The second delay adjustment circuit includes multiple sub-adjustment circuits. Each sub-adjustment circuit is equipped with a resistor and a capacitor corresponding to all fan-out lines connected to each flip chip film, and the resistance value of the resistor and the capacitance value of the capacitor gradually increase along the second direction.

5. The driving circuit according to claim 2, wherein: The display panel is divided into at least two areas along a first direction, the two areas being a first area and a second area, the data lines of the first area being connected to the fan-out lines of the first fan-out area in a one-to-one correspondence, and the data lines of the second area being connected to the fan-out lines of the second fan-out area in a one-to-one correspondence; A plurality of pixels are provided in each of the first area and the second area, and the compensation number of the pixels in the first area and the compensation coefficient of the pixels in the second area are K1 and K2 respectively; The compensation coefficients of the pixels on each data line are linearly interpolated according to the compensation coefficients of adjacent areas to obtain the compensation coefficients of the pixels to be compensated, and the charging time of each column of pixels is adjusted to be consistent.

6. The driving circuit according to claim 1, wherein: The gate driving module includes a first gate driving circuit, and the first gate driving circuit is connected to the gate line; The source driver module includes a first source driver module and a second source driver module, the chip-on-chip film includes a plurality of first chip-on-chip films and a plurality of second chip-on-chip films, the output end of the first source driver module is connected to the plurality of first chip-on-chip films, and the output end of the second source driver module is connected to the plurality of second chip-on-chip films; The display panel includes a fan-out area, the fan-out area including a first fan-out area and a second fan-out area, the first fan-out area corresponding to each first chip-on-film is provided with a first fan-out sub-area, the length of the fan-out traces in each first fan-out sub-area gradually increases along the first direction, the second fan-out area corresponding to each chip-on-film is provided with a second fan-out sub-area, the length of the fan-out traces in each second fan-out sub-area gradually increases along the first direction; The first direction is the direction in which the first gate driving circuit outputs the gate driving signal to the gate line.

7. A driving method, used for driving a display panel using the driving circuit according to any one of claims 1 to 6, characterized in that: The driving method includes: Generate gate drive signals and output them to the gate lines; generate data drive signals and output them to the data lines through the flip chip film and the fan-out lines of the fan-out area; Controlling the change slope of the delay time of the data driving signal on the data line to be the same as the change slope of the delay time of the scanning signal on the gate line; The charging time of the data lines connected to each flip-chip film is controlled to be the same.

8. The driving method according to claim 7, wherein: All fan-out traces connected to each flip-chip film are provided with a resistor and a capacitor, and the step of controlling the change slope of the delay time of the data driving signal on the data line to be the same as the change slope of the delay time of the scanning signal on the gate line includes: Acquire, along a first direction, the delay time of a data line connected to the first fan-out trace and the delay time of a data line connected to the last fan-out trace corresponding to each chip-on-film (COF), and calculate using a first preset formula to obtain a first change slope of the data line connected to the corresponding COF; Acquire, along the second direction, the delay time of the gate line connected to the first fan-out trace and the delay time of the gate line connected to the last fan-out trace corresponding to each chip-on-film, and calculate using a second preset formula to obtain a second change slope of the data line connected to the corresponding chip-on-film; Whether to connect the resistor and the capacitor is controlled according to the first change slope and the second change slope, so as to perform delay compensation on the data driving signal.

9. The driving method according to claim 7, wherein: The display panel is divided into at least two areas along a first direction, the two areas being a first area and a second area, the data lines of the first area being connected to the fan-out lines of the first fan-out area in a one-to-one correspondence, and the data lines of the second area being connected to the fan-out lines of the second fan-out area in a one-to-one correspondence; a plurality of pixels are provided in each of the first area and the second area, and the compensation number of the pixels in the first area and the compensation coefficient of the pixels in the second area are K1 and K2, respectively; The driving method further comprises the following steps: Locate the area where the compensation pixels are located and determine the compensation coefficient; According to the compensation coefficients of the adjacent areas and the pixel columns of the intermediate pixels between the compensation pixel and the adjacent areas, a linear difference is performed using the compensation coefficient formula to obtain the compensation coefficient of the pixel to be compensated, and a compensation table is generated; Where m is the pixel column from the compensation pixel to the middle pixel in the first region, and n is the pixel column from the compensation pixel to the middle pixel in the second region. The compensation coefficient formula is as follows: K=(K1*n+K2*m) / (m+n).

10. A display device, characterized in that: The display device includes a display panel and a driving circuit according to any one of claims 1 to 6, wherein the driving circuit drives the display panel using the driving method according to any one of claims 7 to 9.

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