Bonding structure and method for controlling the same

Abstract

This invention relates to a bonding structure and its control method. In the bonding structure, a third and a fourth bonding pad on the logic layer are each bonded to one of the first and second bonding pads on the first storage layer. The logic reversal control circuit on the first storage layer maintains the setting control logic for the multi-row storage cells received from the logic layer unchanged when the signals of the first and second bonding pads are 0 and 1, respectively. When the signals of the first and second bonding pads are 1 and 0, respectively, the setting control logic is reversed to a reversal control logic corresponding to the arrangement of the multi-row storage cells after axis flipping along the row direction. This ensures that the correspondence between each row of storage cells and the corresponding control signal is not affected by the bonding method, avoiding errors caused by control misalignment due to different bonding methods, and achieving adaptive logic reversal control, which can greatly reduce workload and cost.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional integration technology, and in particular to a bonding structure and a method for controlling the bonding structure. Background Technology

[0002] Three-dimensional integration technology can realize high-performance integrated interconnect circuits. Taking a three-dimensional integrated memory chip as an example, memory wafers (such as DRAM or SRAM) and logic wafers are first manufactured using wafer fabrication processes. The memory wafer includes multiple memory chips, and each memory chip includes multiple memory cells. The logic wafer includes logic circuits corresponding to the multiple memory cells. Then, as needed, the memory wafers or stacked structures of memory wafers are vertically stacked and bonded to the logic wafers, so that the memory cells in the memory wafers and the logic circuits in the logic wafers are vertically stacked and electrically connected. Subsequently, the stacked chips are formed by dicing.

[0003] Figure 1 and Figure 2 The surfaces to be bonded between storage wafer W1 and logic wafer W2 are shown, along with the orientation of the flipping during bonding. Figure 1 and Figure 2 As shown, the component distribution areas on memory wafer W1 and logic wafer W2 can be divided into positions "up" and "down," with the positive Y-axis in the wafer Cartesian coordinate system pointing from position "down" to position "up." When bonding the surfaces of memory wafer W1 and logic wafer W2 to be bonded together, refer to... Figure 1 One bonding method involves aligning the X-axis and Y-axis of the memory wafer W1 and the logic wafer W2, then flipping either the memory wafer W1 or the logic wafer W2 around the Y-axis so that their "top" and "bottom" positions are opposite each other. Bonding is then performed, as described above. Figure 2 Another bonding method involves aligning the X-axis and Y-axis of either the storage wafer W1 or the logic wafer W2. Then, the storage wafer W1 or the logic wafer W2 is flipped around the X-axis, so that the "up" position of the storage wafer W1 is opposite the "down" position of the logic wafer W2, and vice versa. Bonding is then performed. It can be seen that, depending on the bonding method, after bonding, the "up" position of the logic wafer W2 may correspond to either the "up" or "down" position of the storage wafer W1, and similarly, the "down" position of the logic wafer W2 may correspond to either the "down" or "up" position of the storage wafer W1. This means that when selecting the corresponding memory cell on the storage wafer W1 based on the address of the logic circuit on the logic wafer W2, the memory cell corresponding to the address of the same logic circuit may change due to the different bonding methods.

[0004] In practice Figure 1 and Figure 2 The bonding method shown or other types of bonding methods may be used. After bonding one or more memory wafers W1 to logic wafers W2, the memory wafers form a memory layer with a corresponding bonding structure, and the logic wafers form a logic layer with a corresponding bonding structure. When testing the bonding structure (e.g., Built-in Self-Test (BIST)), the testing manufacturer needs to confirm the bonding method with the bonding manufacturer when selecting the memory cell in the memory layer based on the address of the logic circuit on the logic layer. Otherwise, if the bonding method is uncertain or communication is inadequate, control misalignment and subsequent control errors may easily occur. To avoid errors, in some cases, it is required to provide bonding structures with different bonding methods, or to provide different synthesis solutions for the bonding structures for different bonding methods, so as to generate different control signals based on the code during the synthesis stage. However, this will increase the workload and cost. Summary of the Invention

[0005] To avoid control misalignment and errors caused by the bonding method during testing of bonded structures, and to reduce workload and cost, this invention provides a bonded structure and a control method for the bonded structure.

[0006] On one hand, the present invention provides a bonding structure, the bonding structure comprising:

[0007] A first storage layer is formed with multiple rows of storage cells for testing, a logic reversal control circuit, a first bonding pad, and a second bonding pad. The connection direction of the first and second bonding pads is perpendicular to the row direction of the multiple rows of storage cells. The logic reversal control circuit receives signals from the first and second bonding pads.

[0008] A logic layer is vertically bonded to the first storage layer. The logic layer has a third bonding pad and a fourth bonding pad for accessing signals 0 and 1, respectively. The third bonding pad and the fourth bonding pad are each bonded to one of the first bonding pad and the second bonding pad.

[0009] Specifically, when the signals of the first bonding pad and the second bonding pad are 0 and 1 respectively, the logic reversal control circuit maintains the setting control logic for the multi-row memory cells received from the logic layer unchanged, and when the signals of the first bonding pad and the second bonding pad are 1 and 0 respectively, it reverses the setting control logic for the multi-row memory cells received from the logic layer into a reversal control logic corresponding to the arrangement of the multi-row memory cells after the axis is flipped along the row direction.

[0010] Optionally, the logic layer has a first terminal connected to the third bonding pad and a second terminal connected to the fourth bonding pad on the side opposite to the first storage layer, wherein the first terminal and the second terminal are used for grounding and power supply, respectively.

[0011] Optionally, the logic reversal control circuit includes:

[0012] The reversal control module is configured to receive at least two row processing signals according to the set control logic for the multi-row storage unit, and to receive signals from the first bonding pad and the second bonding pad. When the signals of the first bonding pad and the second bonding pad are 0 and 1 respectively, the module outputs the at least two row processing signals according to the set control logic. When the signals of the first bonding pad and the second bonding pad are 1 and 0 respectively, the module outputs the at least two row processing signals according to the reversal control logic.

[0013] Optionally, the first storage layer further includes a BIST circuit for testing the multiple rows of storage units according to the set control logic, wherein the multiple rows of storage units include a first type of storage unit and a second type of storage unit that function differently during testing, and the at least two row processing signals according to the set control logic include a first row processing signal for controlling the first type of storage unit and a second row processing signal for controlling the second type of storage unit.

[0014] Optionally, the first row processing signal is configured to perform a storage performance test on the first type of storage cell, and the second row processing signal is configured to cause the second type of storage cell to store the test results of the first type of storage cell in adjacent rows.

[0015] Optionally, the first row processing signal and the second row processing signal are configured with different bias voltage parameters for the first type of memory cell and the second type of memory cell, respectively.

[0016] Optionally, the first type of storage unit and the second type of storage unit are respectively the storage units of odd-numbered rows and even-numbered rows in the direction from the first bonding pad to the second bonding pad, and the reversal control module includes:

[0017] A first 2-to-1 selector is used to generate a first control signal corresponding to the memory cells in the odd-numbered rows in the direction from the third bonding pad to the fourth bonding pad. The first input of the first 2-to-1 selector is connected to the second row processing signal, the second input is connected to the first row processing signal, and the address input is sequentially connected to the signals of the first bonding pad and the second bonding pad.

[0018] A second 2-to-1 selector is used to generate a second control signal corresponding to the storage cell of the even-numbered row in the direction from the third bonding pad to the fourth bonding pad. The first input terminal of the second 2-to-1 selector is connected to the first row processing signal, the second input terminal is connected to the second row processing signal, and the address input terminal is connected to the signals of the first bonding pad and the second bonding pad in sequence.

[0019] Specifically, when the signals of the first bonding pad and the second bonding pad are 0 and 1 respectively, the first 2-to-1 selector outputs the first row processing signal and the second 2-to-1 selector outputs the second row processing signal; when the signals of the first bonding pad and the second bonding pad are 1 and 0 respectively, the first 2-to-1 selector outputs the second row processing signal and the second 2-to-1 selector outputs the first row processing signal.

[0020] Optionally, the first type of storage unit and the second type of storage unit are respectively the storage units of odd-numbered rows and even-numbered rows in the direction from the first bonding pad to the second bonding pad, and the reversal control module includes:

[0021] A first 2-to-1 selector is used to generate a first control signal corresponding to the memory cells in the odd-numbered rows in the direction from the third bonding pad to the fourth bonding pad. The first input of the first 2-to-1 selector is connected to the second row processing signal, the second input is connected to the first row processing signal, and the address input is sequentially connected to the signals of the first bonding pad and the second bonding pad.

[0022] A second 2-to-1 selector is used to generate a second control signal corresponding to the storage cell in the even-numbered row in the direction from the third bonding pad to the fourth bonding pad. The first input terminal of the second 2-to-1 selector is connected to the second row processing signal, the second input terminal is connected to the first row processing signal, and the address input terminal is connected to the signals of the second bonding pad and the first bonding pad in sequence.

[0023] Specifically, when the signals of the first bonding pad and the second bonding pad are 0 and 1 respectively, the first 2-to-1 selector outputs the first row processing signal and the second 2-to-1 selector outputs the second row processing signal; when the signals of the first bonding pad and the second bonding pad are 1 and 0 respectively, the first 2-to-1 selector outputs the second row processing signal and the second 2-to-1 selector outputs the first row processing signal.

[0024] Optionally, the logic reversal control circuit further includes:

[0025] Two inverters are connected sequentially to each signal output terminal of the reversal control module.

[0026] Optionally, the bonding structure further includes at least one second storage layer stacked on the side of the first storage layer away from the logic layer, each of the at least one second storage layer also forming a corresponding multi-row storage cell.

[0027] Optionally, a first TSV signal path connecting the first bonding pad and a second TSV signal path connecting the second bonding pad are formed in the first storage layer and the at least one second storage layer, such that the signals of the first bonding pad and the second bonding pad are also connected to the at least one second storage layer.

[0028] Optionally, the second storage layer is formed with the logic reversal control circuit, and when the signals of the first bonding pad and the second bonding pad are 0 and 1 respectively, the logic reversal control circuit maintains the setting control logic for the multi-row storage cells on the corresponding second storage layer received from the logic layer unchanged, and when the signals of the first bonding pad and the second bonding pad are 1 and 0 respectively, it reverses the setting control logic for the multi-row storage cells on the corresponding second storage layer received from the logic layer to a reversal control logic corresponding to the arrangement of the multi-row storage cells on the second storage layer after the axis is flipped along the row direction.

[0029] On the other hand, the present invention provides a control method for the above-mentioned bonding structure, the control method comprising:

[0030] According to the set control logic, the multiple rows of storage cells on the storage layer are controlled from the logic layer side of the bonding structure, and the third bonding pad and the fourth bonding pad are connected to 0 and 1 respectively.

[0031] In the bonding structure provided by this invention, the third and fourth bonding pads on the logic layer are each bonded to one of the first and second bonding pads on the first memory layer. Depending on the bonding method, the third and fourth bonding pads may be connected to the first and second bonding pads respectively, or they may be connected to the second and first bonding pads respectively. The logic inversion control circuit formed in the first memory layer maintains the setting control logic for the multi-row memory cells received from the logic layer unchanged when the signals of the first and second bonding pads are 0 and 1 respectively. When the signals of the second bonding pad are 1 and 0 respectively, the setting control logic for the multi-row memory cells received from the logic layer is reversed into a reverse control logic corresponding to the arrangement of the multi-row memory cells after being flipped along the axis of the row direction. This ensures that the correspondence between each row memory cell on the first storage layer and the control signal based on the setting control logic is not affected by the bonding method, avoiding control misalignment caused by different bonding methods and thus preventing errors. Furthermore, the reversal of the setting control logic is executed in the first storage layer through the logic reversal control circuit, which can realize adaptive logic reversal control, greatly reducing workload and cost.

[0032] In the control method of the bonding structure provided by the present invention, while controlling multiple rows of memory cells on the storage layer from the logic layer side of the bonding structure according to the set control logic, the third bonding pad and the fourth bonding pad are respectively connected to 0 and 1. This ensures that the correspondence between each row of memory cells on the storage layer and the control signal based on the set control logic is not affected by the bonding method, avoids control misalignment caused by different bonding methods and thus avoids errors. It can realize adaptive logic reversal control, and connecting the third bonding pad and the fourth bonding pad to 0 and 1 respectively does not significantly increase the control complexity. It is easy to operate and has low cost. Attached Figure Description

[0033] Figure 1 and Figure 2 These are bonding diagrams of memory wafers and logic wafers, respectively.

[0034] Figure 3 This is a cross-sectional schematic diagram of a bonding structure according to an embodiment of the present invention.

[0035] Figure 4 and Figure 5 These are schematic diagrams of the bonding of a storage wafer and a logic wafer in a bonding structure according to an embodiment of the present invention.

[0036] Figures 6 to 8 These are schematic diagrams of the logic reversal control circuit in the embodiments of the present invention. Detailed Implementation

[0037] The bonding structure and control method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0038] Reference Figure 3 , Figure 4 and Figure 5 This invention relates to a bonding structure 100, which includes a first memory layer W11 and a logic layer W20 vertically bonded to the first memory layer W11. Optionally, the bonding structure 100 further includes at least one second memory layer W12 stacked on the side of the first memory layer W11 opposite to the logic layer W20. The first memory layer W11, the second memory layer W12, and the logic layer W20 are formed, for example, using wafer-level processes and vertically stacked and interconnected using a bonding process. Stacking and interconnecting the first memory layer W11 with at least one second memory layer W12 can achieve a larger memory density and memory capacity. In some embodiments, the bonding structure 100 may further include a packaging substrate (not shown) disposed on the side of the logic layer W20 opposite to the first memory layer W11.

[0039] A multi-row memory cell 10 for testing is formed in the first memory layer W11. The memory device in the memory cell 10 can be DRAM, SRAM, or other types of memory devices. In the following embodiments, the memory cell 10 is, for example, a DRAM memory cell with DRAM as the memory device. Each memory cell is, for example, a "BANK", and each "BANK" includes an array of memory devices with multiple word lines and multiple bit lines. As an example, a memory cell 10 includes an array of memory devices with 16K word lines and 16K bit lines, thereby storing 128M bits (i.e., 32M bytes) of data; it is worth noting that the number of word lines and bit lines in the memory cell 10 is not necessarily equal. For example, a memory cell 10 may also include an array of memory devices with 2K word lines and 16K bit lines, thereby storing 32M bits (i.e., 4M bytes) of data. The multi-row memory cell 10 can be located in the chip area of ​​the first memory layer W11 or in a dedicated test area. Here, the row direction of the multi-row memory cell 10 is the row direction targeted by the control logic when a control signal is applied to the memory cell 10. Each row of storage cells 10 includes, for example, multiple storage cells 10, and from the perspective of the column direction perpendicular to the row direction, the multiple rows of storage cells 10 are also arranged in multiple columns.

[0040] A logic circuit for connecting to the memory cell 10 on the first memory layer W11 is formed on the logic layer W20. If necessary, TSVs may be formed in the logic layer W20 and the first memory layer W11 to facilitate the connection of circuits formed on the front and back sides of the substrate. Redistribution layers (RDLs) for redistribution and signal transmission may also be formed on the front and back sides of the logic layer W20 and the first memory layer W11. The signal transmission path through the TSV is referred to as the TSV signal path. When testing the bonding structure 100, control signals applied from the logic layer W20 can be transmitted to the first memory layer W11 or the second memory layer W12 through the TSV signal path.

[0041] The distribution of multiple rows of storage cells 10 on the first storage layer W11 in a two-dimensional plane can be set using a Cartesian coordinate system, where the origin of the Cartesian coordinate system is the center point of the first storage layer W11. (Refer to...) Figure 4 and Figure 5 As an example, the first storage layer W11 includes, for instance, the following: Figure 4 and Figure 5 The multiple storage cells 10 shown are arranged in a Cartesian coordinate system. The positive X-axis of the Cartesian coordinate system represents the row direction of the multiple rows of storage cells 10. The Y-axis is perpendicular to the X-axis. The storage cells 10 are ordered from the opposite direction of the positive Y-axis (i.e., the negative Y-axis direction). Rows 1 to 4 (C1 to C4) of storage cells 10 are located on one side of the positive Y-axis (e.g., corresponding to the position "up"), and rows 5 to 8 (C5 to C8) of storage cells 10 are located on one side of the negative Y-axis (e.g., corresponding to the position "down"). The distribution of logic circuits corresponding to each storage cell 10 on the logic layer W20 can also be understood using a Cartesian coordinate system, as shown below. Figure 4 and Figure 5 As shown in the bonding facets, logic layer W20 also includes a portion located on the positive half-axis of the Y-axis (e.g., corresponding to position "up") and a portion located on the negative half-axis of the Y-axis (e.g., corresponding to position "down").

[0042] The correspondence between the logic circuits on the logic layer W20 and the memory cells on the first memory layer W11 differs depending on the bonding method used. For example, if the bonding method is used... Figure 4 In the bonding method shown, the logic circuit on the positive half-axis side of logic layer W20 is connected to the memory cell 10 on the positive half-axis side of first storage layer W11. When a control signal is input to the first row of memory cell 10 (i.e., C1) in the negative Y-axis direction according to the address of the logic circuit on logic layer W20, the first row of memory cell 10 on first storage layer W11 receives the control signal. However, if a bonding method is used... Figure 2The bonding method shown, with logic layer W20 as the reference, differs from the previous case in that the axis (e.g., X-axis) along the row direction of the multiple rows of storage cells 10 on the first storage layer W11 is flipped. This causes the logic circuit on the positive half-axis of the Y-axis of logic layer W20 to be connected to the storage cells 10 on the negative half-axis of the Y-axis of the first storage layer W11. If a control signal is input to the first row of storage cells 10 (i.e., C1) according to the address of the logic circuit on the positive half-axis of the Y-axis of logic layer W20, it is actually connected to the row symmetrical to the first row of storage cells 10 with respect to the X-axis (e.g., the row of storage cells 10). Figure 5 The 8th row of memory cells (i.e., C8) shown is input with a control signal, which causes a control misalignment. When the control signals for C1 and C8 are different, a control error will occur. It should be noted that the bonding method between the logic layer W20 and the first memory layer W11 is not limited to... Figure 1 and Figure 2 The bonding method shown can be selected according to the actual situation. For example, in some embodiments, when bonding, the positive Y-axis direction of the logic layer W20 is opposite to the positive Y-axis direction of the first storage layer W11.

[0043] To avoid the aforementioned control misalignment and consequent control errors, and to avoid increased workload and cost due to measures such as providing bonding structures with different bonding methods or offering different synthesis schemes for bonding structures based on different bonding methods, refer to... Figure 3 , Figure 4 and Figure 5 In the bonding structure of this embodiment, a first bonding pad 10a and a second bonding pad 10b are formed on the first storage layer W11. The line connecting the first bonding pad 10a and the second bonding pad 10b is perpendicular to the row direction of the multiple rows of storage cells 10 on the first storage layer W11. In this embodiment, the first bonding pad 10a and the second bonding pad 10b are symmetrical about the center point of the first storage layer W11, and the center point is the origin of the aforementioned rectangular coordinate system.

[0044] like Figure 3 As shown, in the bonding structure 100 of this embodiment, the logic layer W20 is vertically bonded to the first storage layer W11. The logic layer W20 has a third bonding pad 20a and a fourth bonding pad 20b respectively for receiving signals 0 and 1. On the side of the logic layer W20 opposite to the first storage layer W11, a first terminal 21 connected to the third bonding pad 20a and a second terminal 22 connected to the fourth bonding pad 20b are also formed to facilitate inputting signals to the third bonding pad 20a and the fourth bonding pad 20b. The first terminal 21 is used, for example, for grounding, so that the third bonding pad 20a is connected to 0; the second terminal 22 is used, for example, for connecting to power, so that the fourth bonding pad 20b is connected to 1. The signals 0 and 1 mentioned herein are binary signals.

[0045] The third bonding pad 20a and the fourth bonding pad 20b are each bonded to one of the first bonding pad 10a and the second bonding pad 10b. In the aforementioned rectangular coordinate system, the first bonding pad 10a and the second bonding pad 10b are, for example, symmetrical about the X-axis, and the third bonding pad 20a and the fourth bonding pad 20b are, for example, symmetrical about the X-axis. When respectively using Figure 1 and Figure 2 In the bonding configuration shown, the first bonding pad 10a and the second bonding pad 10b are bonded to the third bonding pad 20a and the fourth bonding pad 20b, but the connection method differs. Depending on the bonding method, the third bonding pad 20a and the fourth bonding pad 20b may be connected to the first bonding pad 10a and the second bonding pad 10b respectively (e.g., Figure 3 (As shown), it may also be connected to the second bonding pad 10b and the first bonding pad 10a respectively.

[0046] In the bonding structure of this embodiment, the first storage layer W11 also forms a logic reversal control circuit 110 (see reference). Figures 6 to 8 The logic reversal control circuit 110 is connected to the first bonding pad 10a and the second bonding pad 10b. When the signals of the first bonding pad 10a and the second bonding pad 10b are 0 and 1 respectively, the logic reversal control circuit 110 maintains the setting control logic for the multi-row memory cell 10 received from the logic layer W20 unchanged. When the signals of the first bonding pad 10a and the second bonding pad 10b are 1 and 0 respectively, the logic reversal control logic for the multi-row memory cell 10 received from the logic layer W20 is reversed to a reversal control logic corresponding to the arrangement of the multi-row memory cell 10 after the axis is flipped along the row direction.

[0047] The setting control logic, for example, has at least two different row processing signals for the multi-row storage unit 10. (Refer to...) Figure 6 The logic inversion control circuit 110 may include an inversion control module 111. The inversion control module 111 is configured to receive at least two row processing signals (such as TRIM_D<127:124> and TRIM_D<123:120>) according to the set control logic for the multi-row storage unit 10, and to receive signals from the first bonding pad 10a and the second bonding pad 10b. When the signals of the first bonding pad 10a and the second bonding pad 10b are 0 and 1 respectively, the at least two row processing signals according to the set control logic are output. When the signals of the first bonding pad 10a and the second bonding pad 10b are 1 and 0 respectively, the at least two row processing signals according to the inversion control logic are output. Optionally, the logic inversion control circuit 110 may further include two inverters (such as...) sequentially connected to each signal output terminal of the inversion control module 111. Figure 6 (As shown in INV1, INV2, INV3, and INV4).

[0048] The reversal control module 111 can select various circuit structures capable of achieving the above functions. In some embodiments, the reversal control module 111 includes at least two selectors. One input of each selector is connected to a row processing signal of at least one row of memory cells 10 received from the logic layer W20 according to the set control logic, and the other input is connected to the row processing signal of the at least one row of memory cells 10 according to the reversal control logic. The address input of each selector is connected to the signals of the first bonding pad 10a and the second bonding pad 10b to form an address signal. When the signals of the first bonding pad 10a and the second bonding pad 10b are 0 and 1 respectively, the selector selects the row processing signal output of the set control logic. When the signals of the first bonding pad 10a and the second bonding pad 10b are 1 and 0 respectively, the selector selects the row processing signal output of the reversal control logic.

[0049] As an example, in one embodiment, according to the set control logic, such as Figure 4 The multi-row storage unit 10 shown includes four groups: C1 and C2, C3 and C4, C5 and C6, and C7 and C8. Each group is given a different row processing signal according to a set control logic. The logic inversion control circuit 110 may include four selectors. One input of each selector is connected to the row processing signal for the C1 and C2 group, the C3 and C4 group, the C5 and C6 group, and the C7 and C8 group, respectively, according to the set control logic. The four groups of storage units 10, after being flipped along the row direction axis, are arranged as C8 and C7, C6 and C5, C4 and C3, and C2 and C1. The other input of each of the four selectors is connected to... The row processing signals according to the reverse control logic are respectively the row processing signals for groups C7 and C8, C5 and C6, C3 and C4, and C1 and C2 according to the set control logic. Based on the signals from the first bonding pad 10a and the second bonding pad 10b connected to the address input terminal, each selector either selects the row processing signal output of the set control logic or the row processing signal output of the reverse control logic. This ensures that when the signals of the first bonding pad 10a and the second bonding pad 10b are 01 and 10, the row processing signals actually applied to groups C1 and C2, C3 and C4, C5 and C6, and C7 and C8 are the same. It should be noted that the selector settings can be configured according to actual needs. For example, in another embodiment, such as... Figure 4The multi-row storage unit 10 shown is divided into a group consisting of odd-numbered rows and a group consisting of even-numbered rows in the direction from the first bonding pad 10a to the second bonding pad 10b. These two groups are given different row processing signals according to the set control logic. Two selectors corresponding to these two groups of storage units can be used, so that one input of each selector is connected to the row processing signal of the storage unit 10 of the corresponding group according to the set control logic, and the other input is connected to the row processing signal of the storage unit 10 of the corresponding group according to the reverse control logic. The address input is connected to the signals of the first bonding pad 10a and the second bonding pad 10b.

[0050] The first storage layer W11 may also form a BIST circuit for testing using the aforementioned multi-row storage cells 10 according to the set control logic. The aforementioned multi-row storage cells 10 may include first-type and second-type storage cells that function differently during testing. For example, in the first storage layer W11, following the direction from the first bonding pad 10a to the second bonding pad 10b, the first-type storage cells are located in odd-numbered rows (e.g.,...). Figure 4 and Figure 5 Storage units 10 (C1, C3, C5, and C7 as shown), the second type of storage unit is located in even-numbered rows (e.g., ...). Figure 4 and Figure 5 The storage cells 10 are shown as C2, C4, C6, and C8. The setting control logic includes a first row processing signal for controlling the first type of storage cells and a second row processing signal for controlling the second type of storage cells. The number of first and second type storage cells is, for example, the same, and the first and second row processing signals are inverse signals of each other. The first row processing signal is configured, for example, to perform a storage performance test on the first type of storage cells, and the second row processing signal is configured, for example, to cause the second type of storage cells to store the test results of adjacent rows of the first type of storage cells. Optionally, the first row processing signal and the second row processing signal configure different bias voltage parameters for the first type of storage cells and the second type of storage cells, respectively.

[0051] If the aforementioned first storage layer W11 is... Figure 1 and Figure 4 The bonding method shown is bonded to the logic wafer W20. From the angle of the logic layer W20 in the bonding structure 100, in the direction from the third bonding pad 20a to the fourth bonding pad 20b, the first type of memory cell (e.g., ...) located in the odd-numbered rows is the first type of memory cell on the first memory layer W11. Figure 4 As shown in C1, C3, C5, and C7 (these rows are filled with shading for clarity), the even-numbered rows are the second type of storage units (such as...). Figure 4 and Figure 5 (C2, C4, C6, and C8 are shown).

[0052] If the aforementioned first storage layer W11 is... Figure 2 and Figure 5 The bonding method shown is bonded to the logic wafer W20. Taking the logic layer W20 as a reference, the multi-row memory cell 10 is flipped along the axis of the row direction, so that the first bonding pad 10a and the second bonding pad 10b are also flipped along the axis of the row direction. At this time, from the angle of the logic layer W20 in the bonding structure 100, the direction from the third bonding pad 20a to the fourth bonding pad 20b corresponds to the direction from the second bonding pad 10b to the first bonding pad 10a on the first memory layer W11. Therefore, when addressing the row of memory cells from the logic layer W20 side according to the direction from the third bonding pad 20a to the fourth bonding pad 20b, the odd-numbered rows are actually the second type of memory cells on the first memory layer W11 (such as...). Figure 5 As shown in the diagram (C8, C6, C4, and C2 are shaded for clarity), the even-numbered rows actually represent the first type of memory cells on the first storage layer W11. It can be seen that, under different bonding methods, the memory cell 10 selected for addressing from the logic layer W20 side may be either the first type of memory cell or the second type of memory cell. If the addressing is directly performed from the logic layer W20 and the first or second row processing signal is applied, it may lead to control errors.

[0053] Reference Figures 6 to 8 The setting control logic is, for example, TRIM_D<127:120>, to control the first type of memory cell using a first control signal (such as TRIM_DD<123:120>) and to control the second type of memory cell using a second control signal (such as TRIM_DD<127:124>).

[0054] In one embodiment, the reversal control module 111 includes, for example, a cyclic right shift circuit that connects TRIM_D<127:124> and TRIM_D<123:120>. When the first bonding pad 10a and the second bonding pad 10b are connected to 0 and 1 respectively, the cyclic right shift circuit does not shift right. The high 4 bits of the output signal, TRIM_D<127:124>, after passing through inverters INV1 and INV2, form the first control signal TRIM_DD<123:120> corresponding to the storage cell 10 of the odd-numbered row in the direction from the third bonding pad 20a to the fourth bonding pad 20b after bonding. The low 4 bits of the output signal, TRIM_D<123:120>, after passing through inverters INV3 and INV4, form the even-numbered row in the direction from the third bonding pad 20a to the fourth bonding pad 20b after bonding. The second control signal TRIM_DD<127:124> corresponds to the storage unit 10 of the several rows; when the first bonding pad 10a and the second bonding pad 10b are connected to 1 and 0 respectively, the cyclic right shift circuit performs a cyclic right shift operation of the input TRIM_D<127:120> by 4 bits, realizing the reversal of the input high 4 bits TRIM_D<127:124> and low 4 bits TRIM_D<123:120>. At this time, the first control signal formed by the signal output by the cyclic right shift circuit through the inverters INV1 and INV2 satisfies TRIM_DD<123:120>=TRIM_D<127:124>, and the second control signal formed by the inverters INV3 and INV4 satisfies TRIM_DD<127:124>=TRIM_D<123:120>.

[0055] Reference Figure 7In another embodiment, the reversal control module 111 includes a first 2-to-1 selector MX1 ​​and a second 2-to-1 selector MX2. The first 2-to-1 selector MX1 ​​is used to generate a first control signal corresponding to the storage unit 10 of the odd-numbered rows in the direction from the third bonding pad 20a to the fourth bonding pad 20b. The first input terminal of the first 2-to-1 selector MX1 ​​is connected to the second row processing signal (as the row processing signal corresponding to the reversal control logic), the second input terminal is connected to the first row processing signal (as the row processing signal corresponding to the setting control logic), and the address input terminal is sequentially connected to the signals of the first bonding pad 10a and the second bonding pad 10b. The second 2-to-1 selector MX2 is used to generate a second control signal corresponding to the storage unit 10 of the even-numbered rows in the direction from the third bonding pad 20a to the fourth bonding pad 20b. The first input terminal of the second 2-to-1 selector MX2 is connected to the first row processing signal (as the row processing signal corresponding to the reversal control logic), the second input terminal is connected to the second row processing signal (as the row processing signal corresponding to the setting control logic), and the address input terminal is sequentially connected to the signals of the first bonding pad 10a and the second bonding pad 10b. Optionally, the logic inversion control circuit 110 further includes two inverters (such as inverters INV1 and INV2) connected sequentially to the output of the first 2-to-1 selector MX1, and / or, the logic inversion control circuit 110 may also include two inverters (such as inverters INV3 and INV4) connected sequentially to the output of the second 2-to-1 selector MX2. The output signal of the logic inversion control circuit 110 is the signal obtained by inverting the outputs of the first 2-to-1 selector MX1 ​​and the second 2-to-1 selector MX2 twice.

[0056] Based on the difference in signals from the first bonding pad 10a and the second bonding pad 10b, the control logic (TRIM_D<127:120>) is set... Figure 7 The output of the logic reversal control circuit 110 shown can be divided into the following two cases:

[0057] When the signals of the first bonding pad 10a and the second bonding pad 10b are 0 and 1 respectively, the address signals received by the first 2-to-1 selector MX1 ​​and the second 2-to-1 selector MX2 are 0 and 1, the same as the default value. The first 2-to-1 selector MX1 ​​selects the first row processing signal from the second row processing signal (TRIM_D<127:124>) and the first row processing signal (TRIM_D<123:120>), and outputs it. After being inverted twice by inverters INV1 and INV2, the first control signal is formed. At this time, the first control signal satisfies TRIM_DD<123:120>=TRIM_D<123:120>. The second selector MX2 selects the second row processing signal from the first row processing signal and the second row processing signal, and outputs it. After being inverted twice by inverters INV3 and INV4, the second control signal is formed. Figure 7 As shown, at this time, the second control signal satisfies TRIM_DD<127:124>=TRIM_D<127:124>, and the output of the logic inversion control circuit 110 does not change the input setting control logic, that is, TRIM_DD<127:120>= TRIM_D<127:120>. In other words, at this time, after passing through the logic inversion control circuit 110, from the angle of the logic layer W20 in the bonding structure, the odd-numbered rows of memory cells 10 in the direction from the third bonding pad 20a to the fourth bonding pad 20b (e.g., Figure 4 The first type of storage cells C1, C3, C5, and C7 in the image are given a first control signal equal to the first row processing signal, and the even-numbered row storage cells 10 (such as...) are given a first control signal equal to the first row processing signal. Figure 4 The second type of storage cells (C2, C4, C6, and C8) are given a second control signal equal to the second row processing signal, and the control logic is not reversed;

[0058] When the signals of the first bonding pad 10a and the second bonding pad 10b are 1 and 0 respectively, the address signal received by the first 2-to-1 selector MX1 ​​and the second 2-to-1 selector MX2 is 10, indicating that the bonding method between the first storage layer W11 and the logic layer W20 is different from that when the signals of the first bonding pad 10a and the second bonding pad 10b are 0 and 1 respectively. The row order of the above-mentioned multi-row storage cells 10 has been reversed along the axis of the row direction. At this time, the logic reversal control circuit 110 performs logic reversal control. Specifically, the first 2-to-1 selector MX1 ​​selects the second row processing signal from the first and second row processing signals and outputs it. After being inverted twice by inverters INV1 and INV2, it forms the first control signal, which satisfies TRIM_DD<123:120>=TRIM_D<127:124>. The second 2-to-1 selector MX2 selects the first row processing signal from the second and second row processing signals and outputs it. After being inverted twice by inverters INV3 and INV4, it forms the second control signal, which also satisfies TRIM_DD<127:124>=TRIM_D<123:120>. The outputs of the first 2-to-1 selector MX1 ​​and the second 2-to-1 selector MX2 reverse the input setting control logic, i.e., TRIM_DD<127:120>= TRIM_D<123:120,127:124>, at this time, after passing through the logic reversal control circuit 110, from the angle of the logic layer W20 in the bonding structure, the storage cell 10 of the odd-numbered row in the direction from the third bonding pad 20a to the fourth bonding pad 20b (e.g., Figure 5 The second type of memory cells C8, C6, C4, and C2 are given a second row processing signal, and the even-numbered row memory cells 10 (such as...) are given a second row processing signal. Figure 5The first type of memory cells C7, C5, C3 and C1 are given a first row of processing signals. Compared with the case where the signals of the first bonding pad 10a and the second bonding pad 10b are 1 and 0 respectively, the control logic is reversed. However, in reality, the first type of memory cells on the first memory layer W11 are given a first row of processing signals and the second type of memory cells are given a second row of processing signals. The control is not misaligned, which helps to ensure the accuracy of the control results.

[0059] Reference Figure 8 In another embodiment, the reversal control module 111 includes a first 2-to-1 selector MX1 ​​and a second 2-to-1 selector MX2, and... Figure 7 Similar to the illustrated embodiment, the first 2-to-1 selector MX1 ​​and the second 2-to-1 selector MX2 are also used to generate the first control signal and the second control signal corresponding to the storage cells 10 of the odd-numbered and even-numbered rows in the direction from the third bonding pad 20a to the fourth bonding pad 20b, respectively. Figure 7 The difference between the illustrated embodiment and this embodiment is that, in this embodiment, the first input terminals of both the first 2-to-1 selector MX1 ​​and the second 2-to-1 selector MX2 are connected to the second row processing signal, and the second input terminals are both connected to the first row processing signal. However, the address input terminal of the first 2-to-1 selector MX1 ​​is sequentially connected to the signals of the first bonding pad 10a and the second bonding pad 10b, and the address input terminal of the second 2-to-1 selector MX1 ​​is sequentially connected to the signals of the second bonding pad 10b and the first bonding pad 10a. In this embodiment, the inputs of the first 2-to-1 selector MX1 ​​and the second 2-to-1 selector MX2 are the same, but the order of the address signals input to the address input terminals is reversed, thus resulting in different outputs. This can achieve the same... Figure 7 The illustrated embodiment has the same set control logic output and reverse control logic output.

[0060] In the bonding structure 100 of this embodiment, a first bonding pad 10a, a second bonding pad 10b, and a logic reversal control circuit 110 are disposed on the first storage layer W11, and a third bonding pad 20a and a fourth bonding pad 20b are disposed on the logic layer W20. Regardless of whether the third bonding pad 20a and the fourth bonding pad 20b are connected to the first bonding pad 10a and the second bonding pad 10b respectively, or to the second bonding pad 10b and the first bonding pad 10a respectively, when the multi-row storage unit 10 is controlled from the logic layer W20 side according to the set control logic, it can ensure that the correspondence between each row of storage units on the first storage layer W11 and the corresponding control signal is not affected by the bonding method, avoid control misalignment caused by different bonding methods and thus avoid errors, realize adaptive logic reversal control, and greatly reduce workload and cost.

[0061] like Figure 3As shown, the bonding structure 100 may further include at least one second storage layer W12. Similar to the first storage layer W11, each second storage layer W12 may also form corresponding multi-row storage cells 10 for testing. As needed, the multi-row storage cells 10 on each second storage layer W12 can be controlled from the logic layer W20 side. To avoid errors caused by control misalignment when controlling the multi-row storage cells 10 on the second storage layer W12, such as... Figure 3 As shown, a TSV signal path 101 connecting the first bonding pad 10a and a TSV signal path 102 connecting the second bonding pad 10b are formed in the first storage layer W11 and at least one second storage layer W12, so that the signals of the first bonding pad 10a and the second bonding pad 10b are also connected to the second storage layer W12. Furthermore, each second storage layer W12 is also formed with a logic reversal control circuit 110 as described in the above embodiment. When the signals of the first bonding pad 10a and the second bonding pad 10b are 0 and 1 respectively, the logic reversal control circuit 110 maintains the setting control logic for the multi-row memory cells 10 on the corresponding second storage layer W12 received from the logic layer W20 unchanged. When the signals of the first bonding pad 10a and the second bonding pad 10b are 1 and 0 respectively, the setting control logic for the multi-row memory cells 10 on the corresponding second storage layer W12 received from the logic layer 20 is reversed to a reversal control logic corresponding to the arrangement of the multi-row memory cells on the second storage layer W12 after the axis is flipped along the row direction.

[0062] In the bonding structure 100 of this embodiment, the logic reversal control circuit 110 can perform adaptive logic reversal control within the first storage layer W11 and the second storage layer W12. Under different bonding methods, the set control logic can be adaptively adjusted so that the correspondence between each row of storage cells on the first storage layer W11 and the second storage layer W12 and the corresponding control signal is not affected by the bonding method. This avoids errors caused by control misalignment due to different bonding methods, and can greatly reduce workload and cost.

[0063] This invention also relates to a control method for a bonding structure, used to control the bonding structure 100 described in the above embodiments. The control method includes: controlling multiple rows of memory cells 10 on a memory layer (such as a first memory layer W11 or a second memory layer W12) from the logic layer W20 side of the bonding structure 100 according to a set control logic, while simultaneously connecting a third bonding pad 20a and a fourth bonding pad 20b to 0 and 1 respectively. As an example, the logic layer W10 has a first terminal 21 connected to the third bonding pad 20a and a second terminal 22 connected to the fourth bonding pad 20b on the side opposite to the memory layer. The third bonding pad 20a and the fourth bonding pad 20b can be connected to 0 and 1 respectively through the first terminal 21 and the second terminal 22. The first terminal 21 and the second terminal 22 are used, for example, for grounding and power supply.

[0064] The memory cells 10 on the first memory layer W11 or the second memory layer W12 in the bonding structure 100 can be selected and controlled according to the set control logic as needed. For example... Figure 4 and Figure 5 As shown, in one embodiment, from the direction of the first bonding pad 10a to the second bonding pad 10b, the multi-row storage cells 10 on the first storage layer W11 include first-type storage cells located in odd-numbered rows and second-type storage cells located in even-numbered rows. The setting control logic includes, for example, a first-row processing signal for controlling the first-type storage cells and a second-row processing signal for controlling the second-type storage cells. The first-row processing signal, for example, performs a storage performance test on the first-type storage cells, and the second-row processing signal, for example, causes the second-type storage cells to store the test results of the first-type storage cells in adjacent rows.

[0065] Using the aforementioned control method, when testing the memory cell 10 on the memory layer of the bonding structure 100 according to the set control logic, the third bonding pad 20a and the fourth bonding pad 20b are connected to 0 and 1 respectively. The signals received by the logic inversion control circuit 110 from the first bonding pad 10a and the second bonding pad 10b may be 0 and 1, or they may be 1 and 0. The logic inversion control circuit 110 can maintain the set control logic for the corresponding multi-row memory cell 10 received from the logic layer W20 unchanged when the signals of the first bonding pad 10a and the second bonding pad 10b are 0 and 1 respectively. When the signals of 10b are 1 and 0 respectively, the setting control logic for the corresponding multi-row storage unit 10 received from the logic layer W20 is reversed into a reverse control logic corresponding to the arrangement of the multi-row storage unit after the axis is flipped along the row direction. This ensures that the correspondence between each row storage unit 10 on the storage layer and the corresponding control signal is not affected by the bonding method, avoids errors caused by control misalignment due to different bonding methods, realizes adaptive logic reverse control, and does not significantly increase the control complexity by connecting 0 and 1 through the first terminal 21, the second terminal 22, the third bonding pad 20a, and the fourth bonding pad 20b respectively. It is easy to operate and has low cost.

[0066] It should be noted that the embodiments in this specification are described in a progressive manner, with each part focusing on the differences from the preceding parts, and the relevant parts can be understood by referring to them.

[0067] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A bonding structure, characterized in that, include: A first storage layer is formed with multiple rows of storage cells for testing, a logic reversal control circuit, a first bonding pad, and a second bonding pad. The connection direction of the first and second bonding pads is perpendicular to the row direction of the multiple rows of storage cells. The logic reversal control circuit receives signals from the first and second bonding pads. A logic layer is vertically bonded to the first storage layer. The logic layer has a third bonding pad and a fourth bonding pad for accessing signals 0 and 1, respectively. The third bonding pad and the fourth bonding pad are each bonded to one of the first bonding pad and the second bonding pad. Specifically, when the signals of the first bonding pad and the second bonding pad are 0 and 1 respectively, the logic reversal control circuit maintains the setting control logic for the multi-row memory cells received from the logic layer unchanged, and when the signals of the first bonding pad and the second bonding pad are 1 and 0 respectively, it reverses the setting control logic for the multi-row memory cells received from the logic layer into a reversal control logic corresponding to the arrangement of the multi-row memory cells after the axis is flipped along the row direction.

2. The bonding structure as described in claim 1, characterized in that, The logic layer has a first terminal connected to the third bonding pad and a second terminal connected to the fourth bonding pad on the side opposite to the first storage layer. The first terminal and the second terminal are used for grounding and power supply, respectively.

3. The bonding structure as described in claim 1, characterized in that, The logic reversal control circuit includes: The reversal control module is configured to receive at least two row processing signals according to the set control logic for the multi-row storage unit, and to receive signals from the first bonding pad and the second bonding pad. When the signals of the first bonding pad and the second bonding pad are 0 and 1 respectively, the module outputs the at least two row processing signals according to the set control logic. When the signals of the first bonding pad and the second bonding pad are 1 and 0 respectively, the module outputs the at least two row processing signals according to the reversal control logic.

4. The bonding structure as described in claim 3, characterized in that, The first storage layer also forms a BIST circuit for testing the multiple rows of storage units according to the set control logic, wherein the multiple rows of storage units include a first type of storage unit and a second type of storage unit that function differently during testing, and the at least two row processing signals according to the set control logic include a first row processing signal for controlling the first type of storage unit and a second row processing signal for controlling the second type of storage unit.

5. The bonding structure as described in claim 4, characterized in that, The first row processing signal is configured to perform a storage performance test on the first type of storage cell, and the second row processing signal is configured to cause the second type of storage cell to store the test results of the first type of storage cell in the adjacent row.

6. The bonding structure as described in claim 4, characterized in that, The first row processing signal and the second row processing signal respectively configure different bias voltage parameters for the first type of memory cell and the second type of memory cell.

7. The bonding structure as described in claim 4, characterized in that, The first type of storage unit and the second type of storage unit are respectively the storage units in the odd-numbered rows and the even-numbered rows in the direction from the first bonding pad to the second bonding pad. The reversal control module includes: A first 2-to-1 selector is used to generate a first control signal corresponding to the memory cells in the odd-numbered rows in the direction from the third bonding pad to the fourth bonding pad. The first input of the first 2-to-1 selector is connected to the second row processing signal, the second input is connected to the first row processing signal, and the address input is sequentially connected to the signals of the first bonding pad and the second bonding pad. A second 2-to-1 selector is used to generate a second control signal corresponding to the storage cell in an even-numbered row in the direction from the third bonding pad to the fourth bonding pad. The first input terminal of the second 2-to-1 selector is connected to the first row processing signal, the second input terminal is connected to the second row processing signal, and the address input terminal is connected to the signals of the first bonding pad and the second bonding pad in sequence. Specifically, when the signals of the first bonding pad and the second bonding pad are 0 and 1 respectively, the first 2-to-1 selector outputs the first row processing signal and the second 2-to-1 selector outputs the second row processing signal; when the signals of the first bonding pad and the second bonding pad are 1 and 0 respectively, the first 2-to-1 selector outputs the second row processing signal and the second 2-to-1 selector outputs the first row processing signal.

8. The bonding structure as described in claim 4, characterized in that, The first type of storage unit and the second type of storage unit are respectively the storage units in the odd-numbered rows and the even-numbered rows in the direction from the first bonding pad to the second bonding pad. The reversal control module includes: A first 2-to-1 selector is used to generate a first control signal corresponding to the memory cells in the odd-numbered rows in the direction from the third bonding pad to the fourth bonding pad. The first input of the first 2-to-1 selector is connected to the second row processing signal, the second input is connected to the first row processing signal, and the address input is sequentially connected to the signals of the first bonding pad and the second bonding pad. A second 2-to-1 selector is used to generate a second control signal corresponding to the storage cell in the even-numbered row in the direction from the third bonding pad to the fourth bonding pad. The first input terminal of the second 2-to-1 selector is connected to the second row processing signal, the second input terminal is connected to the first row processing signal, and the address input terminal is connected to the signals of the second bonding pad and the first bonding pad in sequence. Specifically, when the signals of the first bonding pad and the second bonding pad are 0 and 1 respectively, the first 2-to-1 selector outputs the first row processing signal and the second 2-to-1 selector outputs the second row processing signal; when the signals of the first bonding pad and the second bonding pad are 1 and 0 respectively, the first 2-to-1 selector outputs the second row processing signal and the second 2-to-1 selector outputs the first row processing signal.

9. The bonding structure as described in claim 3, characterized in that, The logic reversal control circuit also includes: Two inverters are connected sequentially to each signal output terminal of the reversal control module.

10. The bonding structure as described in claim 1, characterized in that, The bonding structure further includes at least one second storage layer stacked on the side of the first storage layer away from the logic layer, each of the at least one second storage layer also forming a corresponding multi-row storage cell.

11. The bonding structure as described in claim 10, characterized in that, The first storage layer and the at least one second storage layer form a first TSV signal path connecting the first bonding pad and a second TSV signal path connecting the second bonding pad, such that the signals of the first bonding pad and the second bonding pad are also connected to the at least one second storage layer.

12. The bonding structure as described in claim 11, characterized in that, The second storage layer is provided with the logic reversal control circuit. When the signals of the first bonding pad and the second bonding pad are 0 and 1 respectively, the logic reversal control circuit maintains the setting control logic for the multi-row storage cells on the corresponding second storage layer received from the logic layer unchanged. When the signals of the first bonding pad and the second bonding pad are 1 and 0 respectively, the logic reversal control circuit reverses the setting control logic for the multi-row storage cells on the corresponding second storage layer received from the logic layer to a reversal control logic corresponding to the arrangement of the multi-row storage cells on the second storage layer after the axis is flipped along the row direction.

13. A method for controlling the bonding structure as described in any one of claims 1 to 12, characterized in that, include: According to the set control logic, the multiple rows of storage cells on the storage layer are controlled from the logic layer side of the bonding structure, and the third bonding pad and the fourth bonding pad are connected to 0 and 1 respectively.

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