Wafer bonding method

Abstract

The invention provides a wafer bonding method, which comprises the following steps of: providing a first wafer and a second wafer, and performing chemical mechanical grinding treatment on the first wafer and the second wafer; bonding the second wafer with the first wafer; and forming a first filling layer which covers the bonded first wafer and second wafer and fills a gap between the second wafer and the first wafer. According to the invention, gaps at the edge can be eliminated through the arrangement of the filling layer, and the problems of repeated edge removal and wide edge removal band can be avoided at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a wafer bonding method. Background Art

[0002] In existing silicon-silicon and silicon-oxygen bonding processes, due to profile issues at the wafer edge, a bonding void is formed, requiring a 1mm to 2mm edge trimming process. If the process involves multiple bonding, the situation becomes even more serious, requiring more and wider (3mm to 6mm) edge trimming to prevent chipping during the thinning process and possible cracking problems in subsequent processes. However, multiple edge trimming processes can cause more step problems at the edge. A larger edge trimming width can affect the number of chips on the wafer. Furthermore, the larger edge trimming width and the more edge steps caused by multiple edge trimming processes can affect wafer leveling in subsequent exposure machines and focus plane confirmation during incomplete exposures. Summary of the Invention

[0003] The object of the present invention is to provide a wafer bonding method to eliminate edge gaps while avoiding the problems caused by multiple edge removals and wide edge removals.

[0004] In order to achieve the above-mentioned object and other related objects, the present invention provides a wafer bonding method, comprising the following steps:

[0005] Providing a first wafer and a second wafer, wherein the first wafer and the second wafer are both subjected to chemical mechanical polishing;

[0006] bonding the second wafer to the first wafer;

[0007] A first filling layer is formed, wherein the first filling layer covers the bonded first wafer and second wafer and fills a gap between the second wafer and the first wafer.

[0008] Optionally, in the wafer bonding method, the first filling layer includes a first gap filling layer and a second gap filling layer, the first gap filling layer fills the edge point gap between the second wafer and the first wafer; the second gap filling layer fills the remaining gap between the second wafer and the first wafer.

[0009] Optionally, in the wafer bonding method, the material of the first gap-filling layer includes silicon oxide or SiN.

[0010] Optionally, in the wafer bonding method, when the material of the first gap filling layer is silicon oxide, the method for forming the first gap filling layer includes: using a furnace tube process to oxidize the exposed surfaces of the first wafer and the second wafer into the first gap filling layer; or, using an LPCVD process to deposit the first gap filling layer on the exposed surfaces of the first wafer and the second wafer.

[0011] Optionally, in the wafer bonding method, the material of the second gap-filling layer includes polysilicon.

[0012] Optionally, in the wafer bonding method, the process for forming the second gap filling layer includes an LPCVD process.

[0013] Optionally, in the wafer bonding method, the bonding method of the first wafer and the second wafer includes melt bonding; and the first wafer and the second wafer both include silicon wafers.

[0014] Optionally, in the wafer bonding method, a first oxide layer is formed on the surface of the first wafer, and the first wafer is bonded to the second wafer through the first oxide layer.

[0015] Optionally, in the wafer bonding method, after the step of forming the first filling layer, the wafer bonding method further includes:

[0016] Providing a third wafer, and bonding the third wafer to the first filling layer on the surface of the second wafer;

[0017] A second filling layer is formed, where the second filling layer fills the gap between the third wafer and the first filling layer.

[0018] Optionally, in the wafer bonding method, after the step of forming the first filling layer, the wafer bonding method further includes:

[0019] Optionally, in the wafer bonding method, three wafers are bonded to the second oxide layer;

[0020] A third filling layer is formed, where the third filling layer fills the gap between the third wafer and the second oxide layer.

[0021] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0022] The present invention can fill the gaps at the edges after the first wafer and the second wafer are bonded by setting the first filling layer, thereby eliminating the gaps at the edges and avoiding the problems caused by multiple and wide edge removal.

[0023] Secondly, the first filling layer provided by the present invention includes a first gap-filling layer of silicon oxide or silicon nitride and a second gap-filling layer of polysilicon. Since silicon oxide or silicon nitride generally grows as a film layer, they can fill small gaps (edge ​​point-like gaps); while polysilicon generally grows as an island film layer, it can seal larger gaps. That is, the present invention can eliminate gaps at the edge through the provision of the first filling layer, reduce the edge trimming process, and even eliminate the edge trimming process, thereby avoiding the problems caused by multiple edge trimming and wide edge trimming. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the product structure after executing step S01 in the existing wafer bonding method;

[0025] Figure 2 This is a schematic diagram of the product structure after executing step S02 in the existing wafer bonding method;

[0026] Figure 3 is a graph of wafer edge thinning;

[0027] Figure 4 This is a schematic diagram of the product structure after executing step S03 in the existing wafer bonding method;

[0028] Figure 5 is an ultrasonic scanning image of the product after step S03 is performed in the existing wafer bonding method;

[0029] Figure 6 It is a schematic diagram of the product structure after the third wafer and the second wafer are melt-bonded in the existing wafer bonding method;

[0030] Figure 7 It is a schematic diagram of the product structure after two wafers obtained after performing step S03 in the existing wafer bonding method are bonded to each other;

[0031] Figure 8 1 is a schematic diagram of a product structure after executing step S2 in a wafer bonding method according to an embodiment of the present invention;

[0032] Figure 9 yes Figure 8 An enlarged view of the structure within the dotted box;

[0033] Figure 10 is an ultrasonic scanning image of a product after step S2 is performed in the wafer bonding method according to an embodiment of the present invention;

[0034] Figure 11 1 is a schematic diagram of a product structure after executing step S31 in a wafer bonding method according to an embodiment of the present invention;

[0035] Figure 12 yes Figure 11 An enlarged view of the structure within the dotted box;

[0036] Figure 13 is an ultrasonic scanning image of a product after step S31 is performed in the wafer bonding method according to an embodiment of the present invention;

[0037] Figure 14 1 is a schematic diagram of a product structure after executing step S32 in a wafer bonding method according to an embodiment of the present invention;

[0038] Figure 15 yes Figure 14 An enlarged view of the structure within the dotted box;

[0039] Figure 16 is an ultrasonic scanning image of a product after step S32 is performed in the wafer bonding method according to an embodiment of the present invention;

[0040] Figures 1 to 7 middle,

[0041] 011-first wafer, 012-second wafer, 013-third wafer, 02-oxide layer, 03-gap;

[0042] Figures 8 to 16 middle

[0043] 11 - first wafer, 12 - second wafer, 13 - third wafer, 20 - first oxide layer, 30 - first filling layer, 31 - first gap filling layer, 32 - second gap filling layer, 40 - gap. DETAILED DESCRIPTION

[0044] The wafer bonding method proposed in the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0045] See Figures 1 to 4 , shows the existing wafer bonding method, which specifically includes:

[0046] Step S01: providing a first wafer 011, wherein an oxide layer 02 is formed on the surface of the first wafer 011;

[0047] Step S02: providing a second wafer 012, and bonding the second wafer 012 to the oxide layer 02 on the surface of the first wafer 011;

[0048] Step S03: performing an edge trimming process on the bonded second wafer 012 .

[0049] In step S01, after the oxide layer 02 is formed on the surface of the first wafer 011, a chemical mechanical polishing (CMP) process is performed, and a patterning process is performed according to process requirements. The patterning process and the chemical mechanical polishing process will cause the edge of the first wafer to become thinner. Figure 3 Due to the edge thinning problem, after the second wafer 012 is bonded to the oxide layer 02 in step S02 , a gap 03 will appear at the edge where the second wafer 012 and the oxide layer 02 are bonded. The second wafer 012 and the oxide layer 02 are generally bonded by fusion bonding. Figure 5 If the oxide layer in the process contains a surface pattern (i.e., a patterning process is performed), a gap 03 will appear at the edge after the second wafer 012 is bonded to the oxide layer. If the oxide layer does not contain a surface pattern (i.e., a patterning process is not performed), a gap 03 will still appear at the edge after the second wafer 012 is bonded to the oxide layer. Therefore, the edge removal process in step S03 is required to solve the problem of edge gaps. If the process is bonded multiple times, for example Figure 6 After the third wafer 013 is bonded to the second wafer 012, a gap appears at the edge between the third wafer 013 and the second wafer 012, so another edge removal process is required to eliminate the edge gap; for example Figure 7 The situation is even more serious when two wafers (e.g., SOI wafers) obtained after step S03 are bonded together, requiring a wider edge trimming process. However, multiple edge trimming processes can result in multiple step-up issues. A wider edge trimming width can affect the number of chips on a wafer. Furthermore, a larger edge trimming width and multiple edge trimming processes can affect wafer leveling in subsequent exposure machines and focus plane confirmation during incomplete exposures.

[0050] In order to solve the above technical problems, the present invention provides a wafer bonding method, which may include the following steps: Figures 8 to 16 :

[0051] Step S1: providing a first wafer 11 and a second wafer 12, wherein the first wafer 11 and the second wafer 12 are both subjected to chemical mechanical polishing treatment;

[0052] Step S2: bonding the second wafer 11 to the first wafer 12;

[0053] Step S3 : forming a first filling layer 30 , wherein the first filling layer 30 covers the bonded first wafer 11 and second wafer 12 and fills a gap between the second wafer 12 and the first wafer 11 .

[0054] See Figures 8-10, perform step S1 to provide a first wafer 11 and a second wafer 12. In this embodiment, the first wafer 11 and the second wafer 12 are preferably silicon wafers, but are not limited thereto. For example, they can also be SOI wafers. The wafers are covered with cores, and chips are obtained after the cores are cut later. In this embodiment, the side of the wafer covered with cores is defined as the front side of the wafer, and the opposite side is defined as the back side.

[0055] In this embodiment, the surface 11 of the first wafer may be formed with a first oxide layer 20, and the surface of the second wafer 12 may not be formed with an oxide layer. The bonding between the first wafer 11 and the second wafer 12 is actually the bonding between the first oxide layer 20 and the second wafer, that is, silicon-oxygen bonding. The first oxide layer 20 is preferably formed on the front side of the first wafer 11, but is not limited to this. The material of the first oxide layer 20 is preferably silicon oxide (SiO2), but is not limited to this. The thickness of the first oxide layer 20 is preferably 0.1μm to 3μm. In other embodiments, the first oxide layer 20 may not be formed on the surface of the first wafer 11, and the bonding between the first wafer 11 and the second wafer 12 is silicon-silicon bonding.

[0056] Before executing step S2, the first wafer 11 and the second wafer 12 need to be planarized, preferably by a CMP (chemical mechanical polishing) process. When the first oxide layer 20 is formed on the surface of the first wafer 11, the first oxide layer 20 needs to be patterned first, and then a chemical mechanical polishing process is performed, that is, the chemical mechanical polishing process for the first wafer 11 is actually a chemical mechanical polishing process for the first oxide layer 20. In other embodiments, when the first oxide layer 20 is formed on the surface of the first wafer 11, the chemical mechanical polishing process can be directly performed without patterning the first oxide layer 20. Whether the first oxide layer 20 needs to be patterned can be specifically set according to the process requirements. In this embodiment, both the chemical mechanical polishing process and the patterning process will cause the edge of the wafer to become thinner.

[0057] Continue reading Figures 8-10 , execute step S2 to bond the second wafer 12 to the first wafer 11. In this embodiment, the bonding between the first wafer 11 and the second wafer 12 is preferably fusion bonding, but is not limited thereto. Since the edges of the first wafer 11 and the second wafer 12 will become thinner after the chemical mechanical polishing process, a gap 40 will appear between the first wafer 11 and the second wafer 12 after the bonding process, specifically at the edge after bonding. Figure 9 and Figure 10The gaps 40 include large gaps and small gaps in the form of dots on the edges. The large gaps are mainly caused by the thinning of the edge position after the chemical mechanical polishing process. The small gaps in the form of dots on the edges (i.e., edge dot gaps) are mainly caused by surface defects or residues on the wafer that lead to poor bonding. The surface defects and residues on the wafer can be formed by chemical mechanical polishing processes and patterning processes.

[0058] When the first oxide layer 20 is formed on the surface of the first wafer 11, the first oxide layer 20 of the first wafer 11 and the second wafer are bonded using a silicon-oxygen bond. When the first oxide layer 20 is not formed on the surface of the first wafer 11, the first wafer 11 and the second wafer are bonded using a silicon-silicon bond. Whether using a silicon-silicon bond or a silicon-oxygen bond, a gap 40 will appear at the edge of the bond.

[0059] See Figures 11 to 16 , perform step S3 to form a first filling layer 30. In this embodiment, the first filling layer 30 preferably includes a first gap filling layer 31 and a second gap filling layer 32, that is, the formation process of the first filling layer 30 may include:

[0060] Step S31 : forming a first gap-filling layer 31 on the surfaces of the first wafer 11 and the second wafer 12 ;

[0061] Step S32 : forming a second gap-filling layer 32 on the first gap-filling layer 31 .

[0062] See Figures 11 to 13 , execute step S31 to form a first gap filling layer 31 on the surface of the first wafer 11 and the second wafer 12. The first gap filling layer 31 can also fill the gap 40 between the second wafer 12 and the first wafer 11, which is mainly edge point gaps (i.e., small gaps).

[0063] The material of the first gap-filling layer 31 can be silicon oxide. Since the formation process of silicon oxide is mostly layered film growth, it will fill small gaps and voids. Therefore, the first gap-filling layer 31 is mainly used to fill the edge point gaps between the second wafer 12 and the first wafer 11. The first gap-filling layer 31 of this embodiment can fill some large gaps while filling the edge point gaps. In other embodiments, the material of the first gap-filling layer 31 can also be other materials that can meet the requirements of deposition processes with good conformal properties, that is, any material whose formation process is layered film growth, such as SiN.

[0064] The thickness of the first gap-filling layer 31 can be set based on the actual width of the gap 40. In this embodiment, ultrasonic scanning (C-SAM) can be performed on the bonded structure after each bonding to obtain the actual width of the gap 40. In this embodiment, the optimal value of the first gap-filling layer 31 can be obtained through multiple experiments. The specific process can be: continuously adjusting the thickness of the first gap-filling layer 31, and then comparing the filling conditions of the gap 40 corresponding to different first gap-filling layer 31 thicknesses through ultrasonic scanning results. When the filling condition of the gap 40 no longer changes, the optimal value of the first gap-filling layer 31 can be confirmed.

[0065] The formation process of the first gap filling layer 31 includes one of a furnace tube process and an LPCVD process, but is not limited thereto. For example, when the material of the first gap filling layer 31 is silicon oxide, the formation method of the first gap filling layer 31 may include: using a furnace tube process to oxidize the exposed surfaces of the first wafer 11 and the second wafer 12 into the first gap filling layer 31; or, using an LPCVD process to deposit the first gap filling layer 31 on the exposed surfaces of the first wafer 11 and the second wafer 12. When the material of the first gap filling layer 31 is other materials besides silicon oxide, the LPCVD process can be used to deposit the first gap filling layer 31 on the exposed surfaces of the first wafer 11 and the second wafer 12. In this embodiment, the first gap filling layer 31 preferably wraps up the entire bonded structure (i.e., the bonded first wafer 11 and the second wafer 12).

[0066] See Figures 14 to 16 , performing step S32, after forming the first gap filling layer 31, forming a second gap filling layer 32 on the first gap filling layer 31. The second gap filling layer 32 is mainly used to fill the remaining gap between the second wafer 12 and the first wafer 11.

[0067] The second gap-filling layer 32 can be made of polycrystalline silicon. Because polycrystalline silicon is often formed through island-shaped film growth, it can seal larger gaps. Therefore, the second gap-filling layer 32 is primarily used to fill the remaining gap 40 between the second wafer 12 and the first wafer 11, i.e., the larger gap. In other embodiments, the second gap-filling layer 32 can also be made of other materials, for example, other materials formed through island-shaped film growth.

[0068] In this embodiment, the thickness of the second gap-filling layer 32 can be set based on the actual width of the gap. The optimal thickness of the second gap-filling layer 32 can be determined through multiple experiments. Specifically, the thickness of the second gap-filling layer 32 can be adjusted continuously, and then ultrasonic scanning results can be used to compare the gap 40 filling conditions corresponding to different second gap-filling layer 32 thicknesses. The optimal thickness of the second gap-filling layer 32 can be determined when the gap 40 is completely filled. The second gap-filling layer 32 is preferably formed using an LPCVD process, but is not limited thereto.

[0069] When the first filling layer 30 is only the first gap-filling layer 31, that is, the gap 40 is filled only by the first gap-filling layer 31, and the first gap-filling layer 31 is mostly grown in a layered film, it will fill small gaps and voids, but will not be effective in filling large gaps. Therefore, using only the first gap-filling layer 31 will result in unsatisfactory filling of the gap 40. When the first filling layer 30 is only the second gap-filling layer 32, that is, the gap 40 is filled only by the second gap-filling layer 32, because the second gap-filling layer 32 is mostly grown in an island-shaped film, it is easy to seal the periphery before filling small gaps. Therefore, using only the second gap-filling layer 32 will also result in unsatisfactory filling of the gap 40. In this embodiment, however, the first gap-filling layer 31 is first used to fill the small gaps, and then the second gap-filling layer 32 is used to fill the remaining large gaps. This allows for good edge gap filling, thereby reducing the width of the edge trimming, or even eliminating it. This embodiment solves the problem of large edge gaps and avoids the problems associated with excessive edge trimming and wide widths. Furthermore, this embodiment preferably utilizes a furnace tube process to first grow the first gap-filling layer 31, followed by an LPCVD process to grow the second gap-filling layer 32. This not only achieves better gap-filling results but also saves process time.

[0070] In other embodiments, multiple bonding processes may be performed, that is, after the step of forming the first filling layer, multiple bonding processes may be performed, each bonding process may be a silicon-silicon bond or a silicon-oxygen bond. The multiple bonding processes may be achieved by repeatedly performing the bonding process and the filling layer formation process.

[0071] For example, after the step of forming the first filling layer 30 , the wafer bonding method may further include:

[0072] Step S41: providing a third wafer, and bonding the third wafer to the first filling layer 30;

[0073] Step S51 : forming a second filling layer, wherein the second filling layer fills the gap between the third wafer and the first filling layer.

[0074] In step S41, and before the third wafer is bonded to the first filling layer 30, the third wafer and the first filling layer 30 are both required to be planarized by a chemical mechanical polishing process. The bonding of the third wafer to the first filling layer 30 is actually the bonding of the third wafer to the second gap filling layer 32, i.e., silicon-silicon bonding. The bonding of the third wafer to the first filling layer 30 can be the bonding of the third wafer to the first filling layer 30 on the surface of the first wafer 11, or the bonding of the third wafer to the first filling layer 30 on the surface of the second wafer 12.

[0075] In step S51 , the second filling layer not only fills the gap between the third wafer and the first filling layer, but also covers the surface (unbonded surface) of the third wafer and the surface (unbonded surface) of the first filling layer 30 .

[0076] For another example, after the step of forming the first filling layer 30, the wafer bonding method may further include:

[0077] Step S42: forming a second oxide layer on the first filling layer;

[0078] Step S52: providing a third wafer, and bonding the third wafer to the second oxide layer;

[0079] Step S62: forming a third filling layer, wherein the third filling layer fills the gap between the third wafer and the second oxide layer.

[0080] In step S42 , a second oxide layer is formed on the first filling layer of the first wafer 11 or a second oxide layer is formed on the first filling layer of the second wafer 12 .

[0081] In step S52, before bonding the third wafer to the second oxide layer, the third wafer and the second oxide layer are both planarized by chemical mechanical polishing. The bonding between the third wafer and the second oxide layer is actually silicon-oxygen bonding.

[0082] In step S62 , the third filling layer not only fills the gap between the third wafer and the second oxide layer, but also covers the surface of the third wafer (unbonded surface) and the surface of the first filling layer (surface without the second oxide layer).

[0083] The multiple bonding process can solve the problem of large edge gaps and avoid the problems caused by excessive edge removal and wide width.

[0084] In summary, the present invention can fill the gaps that appear after wafers are bonded together by setting a filling layer, thereby eliminating edge gaps and avoiding problems caused by multiple deburring and wide deburring. This means that the problem of edge finding in a special machine caused by multiple steps in the deburring process can be avoided; the problem of reducing the number of chips on the wafer due to a large deburring width can be avoided; the problem of wafer leveling in the subsequent exposure machine due to a large deburring width can be avoided, as well as the problem of confirming the focus plane in incomplete exposure; the method of using glue to fill holes can be avoided, thereby avoiding the problem of incompatibility of subsequent processes. Moreover, the wafer bonding method of the present invention is simple and highly operable.

[0085] In addition, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

[0086] It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which may vary. It should also be understood that the terminology described herein is used only to describe specific embodiments and is not intended to limit the scope of the present invention. It should be noted that the singular forms "a," "an," and "the" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in their broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or," not a logical "exclusive or," unless the context clearly indicates otherwise. Structures described herein are to be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximating should be so interpreted unless the context clearly indicates otherwise.

Claims

1. A wafer bonding method, characterized in that: The following steps are involved: Providing a first wafer and a second wafer, wherein the first wafer and the second wafer are both subjected to chemical mechanical polishing; bonding the second wafer to the first wafer; A first filling layer is formed, wherein the first filling layer covers the bonded first wafer and second wafer and fills a gap between the second wafer and the first wafer.

2. The wafer bonding method according to claim 1, wherein: The first filling layer includes a first gap filling layer and a second gap filling layer. The first gap filling layer fills the edge point gaps between the second wafer and the first wafer; the second gap filling layer fills the remaining gaps between the second wafer and the first wafer.

3. The wafer bonding method according to claim 2, wherein: The material of the first gap-filling layer includes silicon oxide or SiN.

4. The wafer bonding method according to claim 3, wherein: When the material of the first gap-filling layer is silicon oxide, the method for forming the first gap-filling layer includes: using a furnace tube process to oxidize the exposed surfaces of the first wafer and the second wafer to form the first gap-filling layer; or, using an LPCVD process to deposit the first gap-filling layer on the exposed surfaces of the first wafer and the second wafer.

5. The wafer bonding method according to claim 2, wherein: The material of the second gap-filling layer includes polysilicon.

6. The wafer bonding method according to claim 2, wherein: The second gap-filling layer is formed by an LPCVD process.

7. The wafer bonding method according to claim 1, wherein: The bonding method of the first wafer and the second wafer includes fusion bonding; the first wafer and the second wafer both include silicon wafers.

8. The wafer bonding method according to claim 1, wherein: A first oxide layer is formed on the surface of the first wafer, and the first wafer is bonded to the second wafer through the first oxide layer.

9. The wafer bonding method according to claim 1, wherein: After the step of forming the first filling layer, the wafer bonding method further includes: Providing a third wafer, and bonding the third wafer to the first filling layer; A second filling layer is formed, where the second filling layer fills the gap between the third wafer and the first filling layer.

10. The wafer bonding method according to claim 1, wherein: After the step of forming the first filling layer, the wafer bonding method further includes: forming a second oxide layer on the first filling layer; Providing a third wafer, and bonding the third wafer to the second oxide layer; A third filling layer is formed, where the third filling layer fills the gap between the third wafer and the second oxide layer.

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