QFN chip structure and preparation method thereof

Abstract

The invention provides a QFN chip structure and a preparation method thereof, and the method comprises the steps: electroplating a metal material on the front surface of a metal sheet to form a first base island and a wire bonding finger, mounting a first chip on the surface of the first base island, and enabling the first chip to be electrically connected with the wire bonding finger through a lead; performing plastic packaging on the front surface of the metal sheet to form a first plastic packaging part; half-etching the back surface of the metal sheet to form at least one circle of metal columns and a second base island, disconnecting the metal columns and reserving steps at the bottoms of the metal columns, electroplating the surfaces of the steps to form bonding wire fingers, electroplating a metal layer on the surface of the second base island, further mounting a second chip, and electrically connecting the second chip with the bonding wire fingers; the back surface of the metal sheet is plastically packaged to form a second plastic packaging part, but the top surface of the metal column is exposed, and the exposed surface of the metal column is used for being connected with an external circuit. The QFN chip structure disclosed by the invention not only can realize double-sided chip integration, but also can avoid the problem that the bottom output pin is sunken, so that the packaging reliability and the welding performance are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly to a QFN chip structure and a preparation method thereof. Background Art

[0002] As electronic products develop towards being thinner, lighter, and smaller, semiconductor packaging technology is also constantly improving. However, the traditional four-sided leadless surface mount packaging structure has some shortcomings.

[0003] First, the traditional four-sided leadless surface mount packaging structure uses through-etching to make the lead frame, which is prone to causing problems such as overflow and contamination during the encapsulation process. At the same time, the chemical film is easily vaporized and contaminated by the high-temperature process, affecting the stability and reliability of the bonding wire.

[0004] Secondly, the bottom output pins of the traditional packaging structure are recessed, which easily leads to poor contact during the surface mounting process.

[0005] In addition, the number of I / Os in traditional packaging structures is limited, and the lead frame manufacturing process is complex, resulting in high manufacturing costs.

[0006] To overcome these shortcomings, a new packaging structure and manufacturing method are needed. This new packaging structure should have a smaller size and footprint while ensuring good reliability, conductivity, and heat dissipation. The manufacturing process should be simple and efficient, avoiding contamination and material waste. In particular, it is necessary to address the poor contact caused by the recessed bottom output pins and improve the soldering reliability of the packaging structure. Summary of the Invention

[0007] To address these issues, the present invention provides a QFN chip structure and its fabrication method. This structure and method utilize a half-etching and electroplating process to form bonding fingers and chip islands on both the front and back sides of a metal sheet. Chips are then mounted and wire-bonded separately. Finally, a double-sided QFN package with dual rows of terminals is formed through plastic encapsulation. This structure not only enables double-sided chip integration but also avoids the problem of recessed bottom output pins, thereby improving package reliability and solderability.

[0008] In a first aspect, the present invention discloses a method for preparing the above-mentioned QFN chip structure, which comprises the following steps: S1. Prepare a metal sheet, electroplate a metal material on the front of the metal sheet to form a first base island and bonding fingers, mount a first chip on the surface of the first base island, and electrically connect the first chip to the bonding fingers through wires; S2. Plastic-sealing the front side of the metal sheet to form a first plastic-sealed portion, where the first plastic-sealed portion covers all the first chips and leads; S3. Half-etching the back of the metal sheet to form at least one circle of metal pillars and a second base island, disconnecting the metal pillars and leaving steps at the bottom of the metal pillars. Electroplating the steps to form wire fingers. Electroplating a metal layer on the surface of the second base island, and then mounting a second chip. The second chip and the wire fingers are electrically connected. S4. Plastic-sealing the back of the metal sheet to form a second plastic-sealed portion, which covers all the second chips and wire fingers, but leaves the top surface of the metal column exposed. The exposed metal column surface is used for connecting to external circuits.

[0009] Preferably, the stringing fingers are provided with at least one circle.

[0010] Preferably, the cross-sectional shape of the metal column is rectangular, square or circular, and the height of the metal column is 0.2 mm to 0.5 mm. The metal column is activated on its surface and then plastic-sealed to increase the bonding between the metal column and the plastic sealing material.

[0011] In a second aspect, the present invention discloses a QFN chip structure, which includes a metal sheet, A first base island and bonding fingers are provided on the front surface of the metal sheet, a first chip is mounted on the surface of the first base island, the first chip is electrically connected to the bonding fingers via leads, and the front surface of the metal sheet is plastic-sealed to form a first plastic-sealed portion, the first plastic-sealed portion covering all the first chip and leads; At least one circle of metal pillars and a second base island are formed by half-etching on the back side of the metal sheet, with each metal pillar being disconnected and a step being retained at the bottom of the metal pillar. Wire fingers are formed by electroplating on the surface of the step. A metal layer is electroplated on the surface of the second base island for mounting a second chip. The second chip and the wire fingers are electrically connected. The back side of the metal sheet is plastic-sealed to form a second plastic-sealed portion. The second plastic-sealed portion covers all the second chip and the wire fingers, but the top surface of the metal pillar is exposed. The exposed metal pillar surface is used to connect to an external circuit. The front side of the metal sheet and the back side of the metal sheet are not penetrated.

[0012] In the present invention, the back of the metal sheet is processed using half-etching technology, so that the front and back of the metal sheet are not penetrated, and no overflow, contamination or other problems will occur in the subsequent encapsulation process, thereby ensuring the stability and reliability of the welding wire and the quality of the packaging structure.

[0013] Preferably, the height of the step at the bottom of the metal column is consistent with the height of the second base island, and the height of the bonding wire finger is consistent with the height of the metal layer.

[0014] Preferably, at least one first base island and / or second base island is provided, the number of first chips is equal to the number of first base islands, and the number of second chips is equal to the number of second base islands.

[0015] Preferably, when a plurality of first chips are provided, at least one first groove is etched on the front surface of the metal sheet to increase the contact area between the first plastic sealing portion and the front surface of the metal sheet.

[0016] Preferably, when a plurality of second chips are provided, at least one second groove is etched on the back surface of the metal sheet to increase the area of ​​the second plastic sealing portion and the back surface of the metal sheet.

[0017] Preferably, the metal sheet is a copper sheet, and the thickness of the metal sheet is 0.2 mm to 0.6 mm.

[0018] Compared with the prior art, the present invention has the following beneficial effects: 1. The double-sided QFN package structure with double-row terminals provided by the present invention realizes double-sided chip integration, with a smaller package volume and footprint, meeting the development trend of thin and light electronic products; 2. The present invention increases the number of I / Os, meeting the demand for high-density, multi-I / O packaging in the fields of mobile communications and mobile computers. It uses stepped metal pillars as output ports, avoiding problems such as poor contact and short circuits caused by recessed output pins at the bottom. 3. The preparation method of the QFN package structure provided by the present invention simplifies the manufacturing process and reduces manufacturing costs. The half-etching process is used in the packaging process, which improves manufacturing efficiency and avoids problems such as overflow and contamination. It also avoids the chemical film from vaporizing and contaminating the chip surface during the high-temperature process, thereby improving the stability and reliability of the bonding wire. 4. The present invention completely covers the chip and bonding wires through the plastic packaging process, thereby improving the airtightness and reliability of the packaging structure and avoiding the problem of chemical film vaporization and contamination of the chip surface during high-temperature processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic structural diagram of the front side of the metal sheet in Example 1 of the present invention; Figure 2 Schematic diagram of the structure of the QFN chip in Example 1 of the present invention; Figure 3 This is a structural diagram of mounting multiple first chips on the front side of a metal sheet in Example 2 of the present invention; Figure 4 This is a schematic diagram of the structure of mounting multiple second chips on the back of a metal sheet in embodiment 2 of the present invention; Figure 5 This is a schematic diagram of a structure in which multiple chips are mounted on both the front and back sides of a metal sheet in Example 2 of the present invention; Figure 6 Schematic diagram of a chip structure with a first groove in Example 3 of the present invention; Figure 7 Schematic diagram of the structure of the chip with the second groove in Example 3 of the present invention; Figure 8 This is a schematic structural diagram of Example 4 of the present invention; Figure 9 This is a schematic structural diagram of the front side of the metal sheet in Example 5 of the present invention; Figure 10 for Figure 9 Schematic diagram of the structure of the side of the middle metal sheet; Figure 11 for Figure 10 Schematic diagram of the structure after etching on the back of the metal sheet.

[0020] Explanation of the reference numerals: metal sheet 1, first base island 2, bonding finger 3, first chip 4, lead 5, first plastic package part 6, metal pillar 7, second base island 8, step 9, bonding finger 10, second chip 11, second plastic package part 12, first groove 13, second groove 14. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0022] The QFN chip structure disclosed in the present invention utilizes a metal sheet 1 in place of the lead frame used in the prior art. In this embodiment, the metal sheet 1 is a copper sheet, with a thickness ranging from 0.2 mm to 0.6 mm, with an optimal thickness of 0.4 mm. This thickness allows for subsequent work on the back of the sheet (the structure of the second base island 8 and metal pillars 7) to be performed using a half-etching technique. This prevents penetration of the front and back of the sheet, preventing problems such as overflow and contamination during the subsequent encapsulation process. This ensures the stability and reliability of the wirebonds and the quality of the package structure.

[0023] A base island and a mounting chip are respectively arranged on the front and back of the metal sheet 1 to form a double-sided QFN chip structure, thereby increasing the number of I / Os to meet the demand for high-density, multi-I / O packaging in the fields of mobile communications and mobile computers.

[0024] The number of base islands and chips can be set as needed, which will be described in detail below through specific embodiments.

[0025] Example 1 In the QFN chip structure disclosed in this embodiment, a first base island 2 is provided on the front surface of a metal sheet 1 , and a first chip 4 is mounted on the surface of the first base island 2 .

[0026] Specific structure such as Figure 1As shown, a first base island 2 and bonding fingers 3 are first arranged on the front surface of a metal sheet 1. The bonding fingers 3 can be arranged in a single or multiple circles, surrounding the first base island 2. A first chip 4 is mounted on the surface of the first base island 2. The first chip 4 is electrically connected to the bonding fingers 3 via leads 5. The front surface of the metal sheet 1 is then plastic-encapsulated to form a first plastic-encapsulated portion 6, which covers all of the first chip 4 and leads 5.

[0027] Then, at least one circle of metal pillars 7 and second base islands 8 are formed by half etching on the back of the metal sheet 1. The metal pillars 7 are disconnected and steps 9 are retained at the bottom of the metal pillars 7 to prevent short circuits. Wire fingers 10 are formed by electroplating on the surface of the steps 9, and a metal layer is electroplated on the surface of the second base island 8 for mounting the second chip 11. The second chip 11 and the wire fingers 10 are electrically connected, and the back of the metal sheet 1 is plastic-sealed to form a second plastic-sealed portion 12. The second plastic-sealed portion 12 covers all the second chips 11 and wire fingers 10, but the top surface of the metal pillars 7 is exposed. The exposed surface of the metal pillars 7 is used to connect to external circuits, forming a structure as shown in FIG. Figure 2 The QFN chip structure shown in the figure. The QFN chip structure disclosed in this embodiment increases the number of I / Os to meet the demand for high-density, multi-I / O packaging in the fields of mobile communications and mobile computers.

[0028] The height of the step 9 at the bottom of the metal column 7 is consistent with the height of the second base island 8 , and the height of the wire fingers 10 is consistent with the metal layer, which facilitates the connection of the lead 5 later.

[0029] The positions of the first base island 2 and the second base island 8 can be set at the corresponding positions on the front or back of the metal sheet 1, and the wire bonding positions and the positions of the wire bonding fingers 10 are also set accordingly. This layout is the most reasonable, and while realizing double-sided chip integration, it ensures that the volume and footprint of the overall packaging structure are smaller, meeting the development trend of light, thin and short electronic products.

[0030] Example 2 In this embodiment, in the QFN chip structure disclosed in Embodiment 1, multiple chips are mounted on the front and / or back side of the metal sheet 1 to increase the integration of the packaging structure.

[0031] Figure 3 The QFN chip structure is disclosed, in which two first base islands 2 and two first chips 4 are arranged on the front of the metal sheet 1. Two first base islands 2 are etched on the front of the metal sheet 1, and the first chips 4 are mounted on the surface of each of the first base islands 2. Subsequently, as needed, first grooves 13 are etched between adjacent first base islands 2 to increase the contact area between the first plastic sealing part 6 and the front of the metal sheet 1. Figure 6 shown.

[0032] Figure 4The QFN chip structure is disclosed, in which two second base islands 8 and two second chips 11 are provided on the back of the metal sheet 1. Two second base islands 8 are etched on the back of the metal sheet 1, and the second chips 11 are mounted on the surface of each of the second base islands 8. Subsequently, as needed, second grooves 14 are etched between adjacent second base islands 8 to increase the contact area between the second plastic sealing portion 12 and the back of the metal sheet 1. Figure 7 shown.

[0033] Figure 5 This is a schematic diagram of a structure in which multiple chips are mounted on the front and back of a metal sheet 1. While increasing the integration of the packaging structure, the volume and footprint of the overall packaging structure are smaller, meeting the development trend of thin and light electronic products.

[0034] Example 3 In this embodiment, in the QFN chip structure disclosed in Example 2, a groove is first half-etched on the front and / or back of the metal sheet 1, and then plastic-sealed, so as to increase the contact area between the plastic-sealed part and the front and / or back of the metal sheet 1, improve the bonding strength between the plastic-sealed part and the metal sheet 1, and increase the stability of the chip structure.

[0035] Specific examples Figure 6 As shown, before the front side of the metal sheet 1 is plastic-sealed, at least one first groove 13 is etched to increase the contact area between the first plastic-sealed portion 6 and the front side of the metal sheet 1. The first groove 13 can be located at the first base island 2.

[0036] You can also Figure 7 As shown, before the back of the metal sheet 1 is plastic-sealed, at least one second groove 14 is etched to increase the area of ​​the second plastic-sealed portion 12 and the back of the metal sheet 1. The second groove 14 can be located on the second base island 8.

[0037] Example 4 In this embodiment, in the QFN chip structure disclosed in Example 2, in which multiple chips are mounted on the front and back of the metal sheet 1, the metal sheet 1 is half-etched in advance between the first base island 2 on the front of the metal sheet 1 and between the first base island 2 and the bottom of the step 9 on the back of the metal sheet 1. During the secondary etching, the metal between the second base island 8 on the back of the metal sheet 1 and between the second base island 8 on the back and the wire bond finger 10 is removed, thereby increasing the bonding area between the first plastic package / the second plastic package and the metal sheet 1, and also increasing the bonding strength between the front and back of the metal sheet 1. Figure 8 The etching structure at point A in the QFN chip structure shown.

[0038] Example 5 The present invention discloses a method for preparing a QFN chip structure, which comprises the following steps: S1. Prepare a metal sheet 1, electroplate metal material on the front of the metal sheet 1 to form a first base island 2 and bonding fingers 3, mount a first chip 4 on the surface of the first base island 2, and electrically connect the first chip 4 to the bonding fingers 3 through leads 5.

[0039] In step S1, a first base island 2 and bonding fingers 3 are arranged on the front of the metal sheet 1. Specifically, electroplating is performed at the corresponding positions to form a metal layer to complete the preparation of the first base island 2 and bonding fingers 3. The metal layer material can be selected from gold, silver, or nickel-palladium metal, preferably a silver metal layer, and the plating thickness is 1μm~10μm, preferably 3μm. The bonding fingers 3 are provided with at least one circle. In actual operation, they can include a single circle or multiple circles inside and outside, which can increase the number of I / Os to meet the needs of high-density, multi-I / O packaging in the fields of mobile communications and mobile computers. Generally, the bonding fingers 3 are arranged in a manner that surrounds the first base island 2, and the structural arrangement is very reasonable.

[0040] The first chip 4 is mounted on the surface of the first base island 2 using silver glue. Non-conductive epoxy resin glue can be used as the glue material. After mounting, it is cured. The curing conditions are determined according to the properties of the selected glue material. The common curing temperature is 120°C~180°C, preferably 150°C, and the curing time is 30min~120min, preferably 60min.

[0041] The pressure area of ​​the first chip 4 is electrically connected to the bonding finger 3 through the lead 5. The lead 5 can be made of gold wire, silver wire, copper wire or aluminum wire, preferably copper wire, with a wire diameter of 15μm~30μm, preferably 20μm; Figure 9 The structure of the front side of the metal sheet 1 is shown. Figure 10 A schematic structural diagram of the side surface of the metal sheet 1 is shown.

[0042] S2, plastic-sealing the front side of the metal sheet 1 to form a first plastic-sealing portion 6, the first plastic-sealing portion 6 covers all the first chips 4 and leads 5; forming Figure 1 The structure shown.

[0043] Environmentally friendly epoxy resins with low water absorption and expansion coefficients can be used as the molding compound. Anti-warping processes and multi-stage injection molding anti-warping software control technology are used to address issues such as punching, warping, and delamination. Post-curing is performed in an oven with flexible temperature control and minimal temperature deviation. The post-curing temperature is 160°C to 200°C, preferably 180°C, and the post-curing time is 2 to 6 hours, preferably 4 hours.

[0044] S3, half-etching the back of the metal sheet 1 to form at least one circle of metal pillars 7 and a second base island 8, disconnecting the metal pillars 7 and leaving a step 9 at the bottom of the metal pillar 7, electroplating the surface of the step 9 to form a wire bond finger 10, electroplating a metal layer on the surface of the second base island 8, and then mounting the second chip 11, the second chip 11 and the wire bond finger 10 are electrically connected. Figure 11 The structure shown.

[0045] The cross-sectional shape of the metal column 7 is rectangular, square or circular, and the height of the metal column 7 is 0.2mm-0.5mm, preferably 0.35mm. The metal column 7 is surface activated and then plastic-sealed. The activation liquid can be palladium chloride solution to increase the bonding between the metal column 7 and the plastic sealing material.

[0046] S4, the back of the metal sheet 1 is plastic-sealed to form a second plastic-sealed portion 12, which covers all the second chips 11 and the wire fingers 10. The plastic-sealing material and the plastic-sealing process are the same as those in step S2. It should be noted that the surface of the metal column 7 needs to be exposed and cannot be plastic-sealed. The exposed surface of the metal column 7 is used to connect to the external circuit to form a Figure 2 The QFN chip structure shown.

[0047] The method for preparing the QFN package structure provided in this embodiment simplifies the manufacturing process and reduces manufacturing costs. An etching process is used in the packaging process, which improves manufacturing efficiency and avoids problems such as overflow and contamination. The chemical film is prevented from vaporizing and contaminating the chip surface during the high-temperature process, thereby improving the stability and reliability of the bonding wire. The chip and bonding wires are completely covered by the plastic encapsulation process, which improves the airtightness and reliability of the packaging structure and avoids the problem of chemical film vaporization and contamination of the chip surface during high-temperature processes.

[0048] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other variations and improvements can be made without departing from the creative concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A method for preparing a QFN chip structure, characterized in that: The following steps are involved: S1. Prepare a metal sheet, electroplate a metal material on the front of the metal sheet to form a first base island and bonding fingers, mount a first chip on the surface of the first base island, and electrically connect the first chip to the bonding fingers through wires; S2. Plastic-sealing the front side of the metal sheet to form a first plastic-sealed portion, where the first plastic-sealed portion covers all the first chips and leads; S3. Half-etching the back of the metal sheet to form at least one circle of metal pillars and a second base island, disconnecting the metal pillars and leaving steps at the bottom of the metal pillars. Electroplating the steps to form wire fingers. Electroplating a metal layer on the surface of the second base island, and then mounting a second chip. The second chip and the wire fingers are electrically connected. S4. Plastic-sealing the back of the metal sheet to form a second plastic-sealed portion, which covers all the second chips and wire fingers, but leaves the top surface of the metal column exposed. The exposed metal column surface is used for connecting to external circuits.

2. The preparation method according to claim 1, characterized in that The stringing fingers are provided with at least one circle.

3. The preparation method according to claim 2, characterized in that The cross-sectional shape of the metal column is rectangular, square or circular, and the height of the metal column is 0.2mm-0.5mm. The metal column is activated on the surface and then plastic-sealed to increase the bonding between the metal column and the plastic sealing material.

4. A QFN chip structure, prepared by the preparation method according to any one of claims 1 to 3, characterized in that: Including metal sheets, A first base island and bonding fingers are provided on the front surface of the metal sheet, a first chip is mounted on the surface of the first base island, the first chip is electrically connected to the bonding fingers via leads, and the front surface of the metal sheet is plastic-sealed to form a first plastic-sealed portion, the first plastic-sealed portion covering all the first chip and leads; At least one circle of metal pillars and a second base island are formed by half-etching on the back of the metal sheet, with each metal pillar being disconnected and a step being retained at the bottom of the metal pillar. Wire fingers are formed by electroplating on the surface of the step. A metal layer is electroplated on the surface of the second base island for mounting a second chip. The second chip and the wire fingers are electrically connected. The back of the metal sheet is plastic-sealed to form a second plastic-sealed portion. The second plastic-sealed portion covers all the second chip and the wire fingers. The top surface of the metal pillar is exposed, and the exposed metal pillar surface is used to connect to an external circuit. The front side of the metal sheet and the back side of the metal sheet are not penetrated.

5. The QFN chip structure according to claim 4, characterized in that: The height of the step at the bottom of the metal column is consistent with the height of the second base island, and the height of the bonding wire finger is consistent with the height of the metal layer.

6. The QFN chip structure according to claim 5, characterized in that: At least one first base island and / or second base island is provided, the number of the first chips is equal to the number of the first base islands, and the number of the second chips is equal to the number of the second base islands.

7. The QFN chip structure according to claim 6, characterized in that: When a plurality of the first chips are provided, at least one first groove is etched on the front surface of the metal sheet to increase the contact area between the first plastic sealing portion and the front surface of the metal sheet.

8. The QFN chip structure according to claim 6 or 7, characterized in that: When a plurality of the second chips are provided, at least one second groove is etched on the back surface of the metal sheet to increase the area of ​​the second plastic sealing portion and the back surface of the metal sheet.

9. The QFN chip structure according to claim 8, characterized in that: The metal sheet is a copper sheet, and the thickness of the metal sheet is 0.2mm-0.6mm.

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