Failure positioning method for semiconductor device

Abstract

The invention provides a semiconductor device failure positioning method, which comprises the following steps: S1, providing a failure sample, and carrying out hot spot grabbing on the failure sample at a first multiplying power to obtain a first position of a hot spot; s2, making a plurality of marks around the first position; s3, performing hot spot grabbing on the invalid sample at a second multiplying power, wherein the second multiplying power is greater than the first multiplying power; s4, recording a relative position relationship between the hot spot and the nearest mark; s5, putting the invalid sample into the FIB machine table, and finding out a second position of the hot spot according to the nearest mark and the relative position relation between the nearest mark and the hot spot; s6, a pit is dug in the preset position through the FIB machine table; and S7, recording the relative position relationship between the second position and the pit. The method is particularly suitable for a failure sample with a large-area repeated structure, micron-sized accurate positioning of the hot spot is achieved, data deviation caused by long-distance measurement of the hot spot position is avoided, and the efficiency and the success rate of failure analysis are improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a method for locating failure of a semiconductor device. Background Art

[0002] With the rapid development of semiconductor device and integrated circuit manufacturing technology, device feature sizes continue to shrink to the nanometer level, and the degree of integration continues to increase. Although this technological evolution has significantly improved chip performance, it has also made the defect location and failure mechanism analysis of failed devices face unprecedented challenges. In ultra-large-scale integrated circuits, the physical size of microscopic defects (such as micro short circuits, open circuits, leakage points, etc.) may be only a few nanometers to tens of nanometers, and are often deeply buried in multi-layer stacked structures. Traditional electrical testing and physical sectioning methods are difficult to achieve accurate positioning. Therefore, high-resolution and high-sensitivity defect location technology has become a key support in the field of failure analysis.

[0003] Currently, new high-resolution microscopic defect localization techniques such as Emission Microscopy (EMMI) and Optical Beam Induced Resistance Change (OBIRCH) are widely used in device failure analysis, enabling rapid and accurate localization of defective devices over a wide range. OBIRCH, a complementary technique to EMMI, uses laser scanning to induce localized resistance changes, resulting in higher sensitivity. When combined with lock-in amplifier technology, it significantly improves the signal-to-noise ratio.

[0004] When using EMMI and OBIRCH technology to capture hot spots, it is necessary to use the characteristic pattern on the sample (the characteristic pattern can be understood as a specific geometric shape or pattern formed on the metal layer of a semiconductor device through processes such as lithography and etching) to assist in positioning. The specific location of the hot spot on the sample is confirmed by gradually enlarging the hot spot position, and the hot spot is located and measured using the nearby characteristic pattern to facilitate subsequent failure analysis. Figure 1 As shown, taking image a as an example, Fail-2.5X in the upper left corner of image a is the magnification, 1.5μA in the upper right corner is the current, and 700mV is the voltage. Figure 2 、 Figure 3 、 Figure 10 、 Figure 11 、 Figure 12 Similarly (magnification in the upper left corner, current and voltage in the upper right corner). Figure 1The magnification of images a to e increases in sequence. In image e, the distances between the hotspot and the nearby characteristic pattern in the x- and y-directions are measured to be 2.82μm and 9.92μm, respectively. However, this method is not suitable for samples without characteristic patterns, such as the 55nm ultra-thin stack CMOS image sensor (UTS-CIS). When capturing hotspots on its pixel wafer, the hotspots are surrounded by repetitive structures that cannot assist in positioning, such as Figure 2 As shown in the figure, the magnification of image g is larger than that of image f. The blue dot in image g is a hotspot. At this time, it is meaningless to magnify the hotspot position to the maximum magnification. It can be seen that there are repeated structures near the hotspot of image g, which cannot be located. The distance between the hotspot and the distant feature pattern or the edge of the sample can only be measured at a small magnification, as shown in the figure. Figure 3 As shown, Figure 3 The hotspot is located in the lower right corner of the red rectangle. The measured x-distance in image h is 881.36μm, and the y-distance is 296.06μm. In image i, the measured x-distance is 903.14μm, and the y-distance is 290.72μm. However, the distance values ​​measured at low magnification deviate significantly from the actual values. The location subsequently determined based on the measured values ​​will also be far from the actual failure point, requiring a wide range of observation. This can be a case of "a small error can lead to a huge difference," complicating subsequent failure analysis, significantly reducing efficiency and success rates, and severely hindering the development and mass production yield of high-end chips. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for locating failures of semiconductor devices, which is particularly suitable for failed samples with large-area repetitive structures. It achieves micron-level precise positioning of hot spots, avoids data deviations caused by long-distance measurement of hot spot positions, and greatly improves the efficiency and success rate of failure analysis.

[0006] In order to achieve the above object, the present invention provides a method for locating semiconductor device failure, which comprises:

[0007] Step S1: providing a failed sample, capturing a hot spot of the failed sample at a first magnification to obtain a first position of the hot spot;

[0008] Step S2: making a plurality of marks around the first position, wherein each mark has a different shape;

[0009] Step S3: capturing the hot spot of the failed sample at a second magnification, wherein the second magnification is greater than the first magnification;

[0010] Step S4: recording the relative position relationship between the hotspot and the nearest marker;

[0011] Step S5: placing the failed sample into the FIB machine, and finding the second position of the hotspot based on the nearest mark and its relative position relationship with the hotspot;

[0012] Step S6: using the FIB machine to dig a pit at a preset position, wherein the distance between the preset position and the second position is within a preset range;

[0013] Step S7: Record the relative positional relationship between the second position and the pit.

[0014] Optionally, the method of recording the relative position relationship between the hotspot and the nearest marker includes: recording the distance from the hotspot to the nearest marker in the x direction, and recording the distance from the hotspot to the nearest marker in the y direction, wherein the x direction is perpendicular to the y direction.

[0015] Optionally, the method for recording the relative position relationship between the second position and the pit includes: recording the distance from the second position to the center of the pit in the x direction, and recording the distance from the second position to the center of the pit in the y direction, where the x direction is perpendicular to the y direction.

[0016] Optionally, if the shortest distance between the position of the hotspot captured in step S3 and the nearest marker is greater than or equal to a preset value, repeat steps S2 and S3 until the shortest distance between the hotspot captured in step S3 and the nearest marker is less than the preset value, and then proceed to step S4.

[0017] Optionally, the method of digging a pit at the preset position using the FIB machine includes: tilting the stage carrying the failed sample to a preset angle to make the electron beam and ion beam of the FIB machine co-focus, and then performing the pit digging operation.

[0018] Optionally, after hotspot capture of the failed sample in step S3, a hotspot image at the second magnification is obtained; after the pit is dug in step S6, the stage is tilted back to a horizontal state, and the second position is found again by combining the hotspot image, the nearest mark, and the relative position relationship between the nearest mark and the hotspot, and then step S7 is performed.

[0019] Optionally, the preset range is 80 μm to 120 μm.

[0020] Optionally, the mark is a plane mark.

[0021] Optionally, combined with the relative positional relationship between the second position and the pit recorded in step S7, a layer-by-layer failure analysis is performed on the failed sample to find the failure position.

[0022] Optionally, the hot spot capture operations in step S1 and step S3 are completed using a wafer-level failure analysis system, and step S2 is completed with the assistance of an optical microscope.

[0023] As configured above, the hotspot of the failed sample is captured at a first magnification to obtain the first position of the hotspot, and multiple marks of different shapes are made around the first position. The marks can be drawn with a pen, and then the hotspot of the failed sample is captured at a second magnification that is larger than the first magnification, and the hotspot is located using the nearest mark, thereby solving the problem in the prior art that the hotspot is surrounded by repeated structures and cannot be assisted in positioning; further, a pit is dug at a preset position using the FIB machine, so that the hotspot position can be located using the pit during subsequent layer-by-layer failure analysis. In summary, the present invention is particularly suitable for failed samples with large-area repeated structures, and achieves micron-level precise positioning of the hotspot, avoiding the data deviation caused by long-distance measurement of the hotspot position, greatly improving the efficiency and success rate of failure analysis, and improving the mass production yield, which is of great significance to the failure analysis of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0025] Figure 1 This is a schematic diagram of the existing technology using feature patterns to assist in locating hotspots;

[0026] Figure 2 Hot spot images of samples with large-area repetitive structures in the prior art;

[0027] Figure 3 These are hotspot images at two different magnifications in the prior art;

[0028] Figure 4 A schematic diagram of hotspot positions at a first magnification of a semiconductor device failure location method according to an embodiment of the present invention;

[0029] Figure 5 A schematic diagram of a hotspot and surrounding marks in a method for locating a semiconductor device failure according to an embodiment of the present invention;

[0030] Figure 6 Schematic diagram of hotspot positions at a second magnification in step S3 of a method for locating a semiconductor device failure according to an embodiment of the present invention;

[0031] Figure 7 A schematic diagram of step S4 of a semiconductor device failure locating method according to an embodiment of the present invention;

[0032] Figure 8 A schematic diagram of the positions of pits in a method for locating a semiconductor device failure according to an embodiment of the present invention;

[0033] Figure 9 A schematic diagram of step S7 of a method for locating a semiconductor device failure according to an embodiment of the present invention;

[0034] Figure 10 A hot spot image at a first magnification of a semiconductor device failure location method according to an embodiment of the present invention;

[0035] Figure 11 A schematic diagram of a method for locating a semiconductor device failure according to an embodiment of the present invention, wherein the method uses a paint pen to make a first mark;

[0036] Figure 12 A schematic diagram of a method for locating a semiconductor device failure according to an embodiment of the present invention, wherein the method uses a paint pen to make a second mark;

[0037] Figure 13 A hot spot image of a failed sample entering a FIB machine under low voltage in a method for locating a semiconductor device failure according to an embodiment of the present invention;

[0038] Figure 14 An image showing the locations of hot spots and pits in a method for locating semiconductor device failures according to an embodiment of the present invention;

[0039] Figure 15 An image showing a VC abnormality location found during failure analysis of a semiconductor device failure location method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In this document, unless otherwise specified, the terms "upper", "lower", "left", "right", "inside", "outside", "front", "back", "top", "bottom", etc. are used to indicate directions or positional relationships based on the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction and operation. Therefore, they cannot be understood as limiting the present invention.

[0041] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0042] An embodiment of the present invention provides a semiconductor device failure locating method, including step S1, step S2, step S3, step S4, step S5, step S6 and step S7. Step S1, step S2, step S3, step S4, step S5, step S6 and step S7 are described in detail below.

[0043] Step S1: Provide a failed sample, capture the hot spot of the failed sample at a first magnification, and obtain the first position of the hot spot, such as Figure 4 As shown, Figure 4 The red dot in the middle is a hotspot. For example, hotspot detection can be performed using a wafer-level failure analysis system (Meridian WS), which performs OBIRCH (laser-induced resistance change) detection on failed samples. It should be understood that the first position is the approximate location of the hotspot.

[0044] Step S2: Using an OM (Optical Microscope), make a plurality of marks around the first position, and each mark has a different shape. Further, the mark is a plane mark. For example, a plurality of oil-based pen marks can be made around the first position with a oil-based pen, so that the mark boundaries are clear and the marks are different in size and shape, such as Figure 5 The present invention can be marked with a pen and has the advantages of simple operation and low cost.

[0045] Step S3: Capture the hotspot of the failed sample at a second magnification and obtain a hotspot image at the second magnification, where the second magnification is greater than the first magnification. It is understood that the hotspot capture in step S3 can be performed using the same equipment as in step S1, namely, using a wafer-level failure analysis system (Meridian WS) to perform OBIRCH capture on the failed sample at the second magnification.

[0046] Preferably, you can refer to Figure 6If the shortest distance between the position of the hotspot captured in step S3 and the nearest marker is greater than or equal to the preset value, steps S2 and S3 are repeated until the shortest distance between the hotspot captured in step S3 and the nearest marker is less than the preset value, and then step S4 is performed. The preset value can be 8 to 12 μm. For example, the preset value can be 10 μm. If the shortest distance between the position of the hotspot captured in step S3 and the nearest marker is less than 10 μm, it indicates that the hotspot is close enough to the nearest marker. Locating the hotspot with the nearest marker can reduce the data deviation caused by the measurement. If the shortest distance between the position of the hotspot captured in step S3 and the nearest marker is greater than or equal to 10 μm, it indicates that the hotspot is far away from the nearest marker. In order to reduce the data deviation caused by the measurement, steps S2 and S3 are repeated until the shortest distance between the hotspot captured in step S3 and the nearest marker is less than 10 μm.

[0047] Step S4: Record the relative position relationship between the hotspot and the nearest marker. The hotspot position located based on this relative position relationship is the second position.

[0048] For example, the method of recording the relative position relationship between the hotspot and the nearest marker includes: recording the distance from the hotspot to the nearest marker in the x direction, and recording the distance from the hotspot to the nearest marker in the y direction, where the x direction is perpendicular to the y direction, such as Figure 7 At this time, the hotspot is at the second position.

[0049] Step S5: Place the failed sample into a FIB machine (focused ion beam machine) and find the second position of the hotspot based on the nearest mark and its relative position relationship with the hotspot.

[0050] Specifically, the hotspot location is found under low voltage using an E-beam (electron beam) based on the nearest marker and the relative positional relationship between the nearest marker and the hotspot (the x- and y-distances from the hotspot to the nearest marker). This hotspot location is referred to as the second location. The second location can be found by comparing the hotspot image obtained in step S3 with the direction of the repetitive structure correction near the hotspot.

[0051] Step S6: using the FIB machine to dig a pit at the preset position, where the distance between the preset position and the second position is within a preset range.

[0052] Specifically, the method of using a FIB machine to dig a pit at a preset position includes: placing the failed sample at Eucentric Height (concentric height), tilting the stage carrying the failed sample to a preset angle, the preset angle is 52°, making the electron beam (E-beam) and the ion beam (I-beam) confocal, and then performing the pit digging operation. The preset range is 80μm to 120μm. For example, under I-beam, with the second position as the center of the circle, select the Regular Cross Section mode of the FIB machine (regular cross section mode) at a radius of about 100μm (±20μm) to dig a pit with a length, width and height of about 10μm*10μm*10μm. This pit is a FIB mark or FIB pit, such as Figure 8 As shown, Figure 8 The red dot in the center is the hotspot.

[0053] After the pit is dug, the stage is tilted back to the horizontal state (0°). Under low voltage of the E-beam, the second position is found again by combining the hotspot image, the nearest mark, and the relative position relationship between the nearest mark and the hotspot (the search method is the same as in step S5), and then step S7 is performed.

[0054] Step S7: Record the relative position relationship between the second position and the pit to complete the micron-level precise positioning of the hotspot, such as Figure 9 Exemplarily, the method for recording the relative positional relationship between the second position and the pit includes: recording the distance from the second position to the center of the pit in the x direction, and recording the distance from the second position to the center of the pit in the y direction, where the x direction is perpendicular to the y direction.

[0055] Furthermore, combined with the relative position relationship between the second position and the pit recorded in step S7, the failure sample is subjected to layer-by-layer failure analysis to find the failure location. For example, the mark of the oil pen is erased, and the failure sample is ground layer by layer combined with the precise measurement values ​​of the x and y directions in step S7. With the aid of a scanning electron microscope (SEM), VC anomalies are finally found in the Via1 (first through hole) layer, such as Figure 15 As shown. It is understood that Voltage Contrast (VC) is a commonly used failure analysis technique in SEM. VC anomalies refer to abnormal light and dark differences in the voltage contrast image, typically indicating electrical defects (such as contact failure or leakage) in that area. Practice has demonstrated that the measurement error of the method in this embodiment can be precisely controlled within a range of 1 μm by 1 μm.

[0056] As configured above, the hotspot of the failed sample is captured at a first magnification to obtain the first position of the hotspot, and multiple marks of different shapes are made around the first position. The marks can be drawn with a pen, and then the hotspot of the failed sample is captured at a second magnification that is larger than the first magnification, and the hotspot is located using the nearest mark, thereby solving the problem in the prior art that the hotspot is surrounded by repeated structures and cannot be assisted in positioning; further, a pit is dug at a preset position using the FIB machine, so that the hotspot position can be located using the pit during subsequent layer-by-layer failure analysis. In summary, the present invention is particularly suitable for failed samples with large-area repeated structures, and achieves micron-level precise positioning of the hotspot, avoiding the data deviation caused by long-distance measurement of the hotspot position, greatly improving the efficiency and success rate of failure analysis, and improving the mass production yield, which is of great significance to the failure analysis of semiconductor devices.

[0057] The following describes in detail the failure point location of the PixelWafer (pixel layer wafer) in the 55CIS UTS (55nm ultra-thin stacked CMOS image sensor) structure as a specific example.

[0058] Capture the hot spot of the failed sample at a small magnification (first magnification) to obtain the approximate position of the hot spot on the failed sample (i.e., the first position), such as Figure 10 As shown in the figure, the bright spot is the hot spot. After making several marks near the hot spot with a marker (first mark), the OBIRCH point is re-taken from the failed sample (i.e., the second position) and the distance between the hot spot and the nearest mark is measured, as shown in the figure. Figure 11 As shown in Figure 1, the distance in the x-direction measured in image k is 370.86 μm and the distance in the y-direction is 102.96 μm. Therefore, the distance between the hotspot and the nearest mark is greater than the preset value of 10 μm. The distance is still too far, so the failed sample is marked a second time, as shown in Figure 1. Figure 12 As shown, after the second marking meets the requirements, the Figure 12 The repetitive structure of image n is oriented to straighten the failed sample and the hotspot is measured and located based on the nearest marked feature boundary near the hotspot.

[0059] The failed sample enters the FIB machine and the hot spot is found according to the nearest mark under low voltage, such as Figure 13 As shown, Figure 13 This is an image viewed using a SEM (integrated in the FIB machine). The red box in the image indicates the location of the hotspot. A FIB pit was dug about 110 μm away from the hotspot. The distance between the hotspot and the center of the FIB pit was accurately measured to achieve micron-level precision positioning of the failure point. Figure 14 As shown, the upper right corner is an enlarged view of the FIB pit, and the lower right corner of the dotted box is the hot spot. Figure 14The distance in the x-direction measured was 13.23 μm, and the distance in the y-direction was 113.9 μm.

[0060] Then erase the oil pen mark, according to Figure 14 The failure point was ground layer by layer based on the precise measurement values ​​in the , and finally VC anomaly was found in the Via1 layer, such as Figure 15 Practice has shown that the measurement error of this experimental method can be precisely controlled within the range of 1um*1um.

[0061] It should be noted that references in the specification to "one embodiment," "an embodiment," "a specific embodiment," "some embodiments," etc., merely indicate that the described embodiment may include a particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of persons skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, regardless of whether such feature, structure, or characteristic is explicitly described.

[0062] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.

[0063] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0064] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0065] It should also be understood that the terms described herein are intended to describe particular embodiments only and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for locating semiconductor device failure, characterized in that: include: Step S1: providing a failed sample, capturing a hot spot of the failed sample at a first magnification, and obtaining a first position of the hot spot; Step S2: making a plurality of marks around the first position, wherein each mark has a different shape; Step S3: capturing the hot spot of the failed sample at a second magnification, wherein the second magnification is greater than the first magnification; Step S4: recording the relative position relationship between the hotspot and the nearest marker; Step S5: placing the failed sample into the FIB machine, and finding the second position of the hotspot based on the nearest mark and its relative position relationship with the hotspot; Step S6: using the FIB machine to dig a pit at a preset position, wherein the distance between the preset position and the second position is within a preset range; Step S7: Record the relative positional relationship between the second position and the pit.

2. The semiconductor device failure locating method according to claim 1, wherein: The method for recording the relative position relationship between the hotspot and the nearest marker includes: recording the distance from the hotspot to the nearest marker in the x direction, and recording the distance from the hotspot to the nearest marker in the y direction, wherein the x direction is perpendicular to the y direction.

3. The semiconductor device failure locating method according to claim 1, wherein: The method for recording the relative position relationship between the second position and the pit includes: recording the distance from the second position to the center of the pit in the x direction, and recording the distance from the second position to the center of the pit in the y direction, where the x direction is perpendicular to the y direction.

4. The semiconductor device failure locating method according to claim 1, wherein: If the shortest distance between the hotspot captured in step S3 and the nearest marker is greater than or equal to the preset value, repeat steps S2 and S3 until the shortest distance between the hotspot captured in step S3 and the nearest marker is less than the preset value, and then proceed to step S4.

5. The semiconductor device failure locating method according to claim 1, wherein: The method of using the FIB machine to dig a pit at the preset position includes: tilting the stage carrying the failed sample at a preset angle to make the electron beam and ion beam of the FIB machine co-focus, and then performing the pit digging operation.

6. The semiconductor device failure locating method according to claim 5, wherein: In the step S3, the hot spot of the failed sample is captured to obtain a hot spot image at the second magnification; after the pit is dug in the step S6, the stage is tilted back to a horizontal state, and the second position is found again by combining the hot spot image, the nearest mark, and the relative position relationship between the nearest mark and the hot spot, and then step S7 is performed.

7. The semiconductor device failure locating method according to claim 1, wherein: The preset range is 80 μm to 120 μm.

8. The semiconductor device failure locating method according to claim 1, wherein: The mark is a flat mark.

9. The semiconductor device failure locating method according to claim 1, wherein: Combined with the relative positional relationship between the second position and the pit recorded in step S7, a layer-by-layer failure analysis is performed on the failed sample to find the failure position.

10. The semiconductor device failure locating method according to claim 1, wherein: The hot spot capture operations in step S1 and step S3 are completed using a wafer-level failure analysis system, and step S2 is completed with the assistance of an optical microscope.

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