Square wave generation circuit and system

Abstract

The application discloses a square wave generating circuit and system, and relates to the technical field of integrated circuits.The square wave generating circuit comprises a power supply injection end, a signal storage module, an electric energy release module, an output control module, a signal output module, and a signal output end; the signal storage module is used for storing the power supply signal injected by the power supply injection end and providing the output control module with an output control signal; the output control module is used for providing the electric energy release module and the signal output module with square wave generating signals respectively according to the power supply signal injected by the power supply injection end and the output control signal; the electric energy release module is used for controlling the release of the power supply signal stored in the signal storage module according to the square wave generating signal; and the signal output module is used for controlling the square wave signal output by the signal output end according to the power supply signal injected by the power supply injection end and the square wave generating signal.The application can generate the square wave signal without using a complex external timing source, and effectively reduces the manufacturing and maintenance costs of the square wave generating circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of integrated circuits, and in particular to a square wave generating circuit and system. Background Art

[0002] Square wave generators, as signal sources widely used in electronic circuits, play a key role in clock signal generation, digital circuit synchronization, communication systems, and embedded device control. Their performance directly affects the stability and operating efficiency of the system.

[0003] Existing technologies typically use chips to generate square wave signals, such as square wave generator circuits based on the NE555 timer. The NE555 timer generates a periodic square wave signal by configuring external resistors and capacitors, where the values ​​of the resistors and capacitors determine the output frequency and duty cycle of the square wave signal. However, the complex internal integrated structure and multi-stage circuit design of chip-based square wave generator circuits make the design and implementation of square wave generator circuits relatively complex, increasing manufacturing costs and making circuit debugging more difficult. Summary of the Invention

[0004] The present invention provides a square wave generating circuit and system, which can generate a square wave signal without using a complex external timing source, thereby effectively reducing the manufacturing and maintenance costs of the square wave generating circuit.

[0005] A first aspect of the present invention provides a square wave generating circuit, the square wave generating circuit comprising: a power injection terminal, a signal storage module, an electric energy release module, an output control module, a signal output module and a signal output terminal;

[0006] The signal storage module is electrically connected to the power injection terminal and the control terminal of the output control module respectively, and is used to store the power signal injected by the power injection terminal and provide an output control signal to the output control module;

[0007] The output control module is electrically connected to the power injection terminal, the control terminal of the power release module, and the control terminal of the signal output module, respectively, and is used to provide a square wave generating signal to the power release module and the signal output module according to the power signal injected by the power injection terminal and the output control signal;

[0008] The power release module is also electrically connected to the signal storage module, and is used to control the power signal stored in the signal storage module to release according to the square wave generating signal;

[0009] The signal output module is also electrically connected to the power injection end and the signal output end respectively, and is used to control the square wave signal output by the signal output end according to the power signal injected by the power injection end and the square wave generating signal.

[0010] Optionally, the signal storage module includes a first resistor and a first capacitor;

[0011] The power injection terminal is electrically connected to the first terminal of the first resistor, the second terminal of the first resistor is electrically connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is grounded.

[0012] Optionally, the electric energy release module includes a second resistor and a first MOS tube;

[0013] The first end of the second resistor is electrically connected to the first end of the first capacitor, the second end of the second resistor is electrically connected to the drain of the first MOS transistor, the gate of the first MOS transistor is the control end of the electric energy release module, and the source of the first MOS transistor is grounded.

[0014] Optionally, the output control module includes a switch control unit, a first switch unit and a second switch unit;

[0015] The input end of the switch control unit is electrically connected to the signal storage module, the output end of the switch control unit is electrically connected to the control end of the first switch unit, and the switch control unit is used to provide a first switch control signal to the first switch unit according to the output control signal;

[0016] The input end of the first switch unit is electrically connected to the power injection end, the output end of the first switch unit is electrically connected to the control end of the second switch unit, and the first switch unit is configured to provide a second switch control signal to the second switch unit according to the power signal injected by the power injection end and the first switch control signal;

[0017] The input end of the second switch unit is electrically connected to the power injection end, and the output end of the second switch unit is electrically connected to the control end of the electric energy release module and the control end of the signal output module respectively. The second switch unit is used to provide a square wave generating signal to the electric energy release module and the signal output module respectively according to the power signal injected by the power injection end and the second switch control signal.

[0018] Optionally, the switch control unit includes a third resistor and a fourth resistor;

[0019] The first end of the third resistor is the input end of the switch control unit, the second end of the third resistor is electrically connected to the first end of the fourth resistor, the second end of the fourth resistor is grounded, and the intermediate node where the third resistor and the fourth resistor are connected is the output end of the switch control unit.

[0020] Optionally, the first switch unit includes a fifth resistor and a second MOS transistor;

[0021] A first end of the fifth resistor is an input end of the first switch unit, a second end of the fifth resistor is electrically connected to a drain of the second MOS transistor, the drain of the second MOS transistor is an output end of the first switch unit, a gate of the second MOS transistor is a control end of the first switch unit, and a source of the second MOS transistor is grounded.

[0022] Optionally, the second switch unit includes a sixth resistor and a third MOS tube;

[0023] The first end of the sixth resistor is the input end of the second switch unit, the second end of the sixth resistor is electrically connected to the drain of the third MOS transistor, the drain of the third MOS transistor is the output end of the second switch unit, the gate of the third MOS transistor is the control end of the second switch unit, and the source of the third MOS transistor is grounded.

[0024] Optionally, the signal output module includes a seventh resistor and a fourth MOS transistor;

[0025] A first end of the seventh resistor is electrically connected to the power injection terminal, a second end of the seventh resistor is electrically connected to the drain of the fourth MOS transistor, a gate of the fourth MOS transistor is a control terminal of the signal output module, and a source of the fourth MOS transistor is grounded;

[0026] The signal output end is electrically connected to the second end of the seventh resistor and the drain of the fourth MOS transistor respectively.

[0027] A second aspect of the present invention provides a square wave generating system, the square wave generating system comprising: a power supply device, a square wave signal output device, and the square wave generating circuit as described above;

[0028] The power supply device is electrically connected to the power injection terminal, and the power supply device is used to supply power to the square wave generating circuit;

[0029] The square wave signal output device is electrically connected to the signal output end, and is used to obtain and transmit the square wave signal output by the signal output end.

[0030] The technical solution of the present invention is to provide a power injection terminal, a signal storage module, an electric energy release module, an output control module, a signal output module and a signal output terminal in a square wave generating circuit, and to provide the signal storage module to be electrically connected to the power injection terminal and the control terminal of the output control module respectively, so that the signal storage module can store the power signal injected by the power injection terminal and provide the output control signal to the output control module, thereby driving the circuit state switching of the output control module. The output control module is electrically connected to the power injection terminal, the control terminal of the electric energy release module and the control terminal of the signal output module respectively, so that the output control module can provide the square wave generating signal to the electric energy release module and the signal output module according to the power signal injected by the power injection terminal and the output control signal, thereby realizing the synchronous regulation of the electric energy release of the signal storage module and the square wave signal outputted by the signal output terminal of the signal output module. The electric energy release module is electrically connected to the signal storage module so that the electric energy release module can control the power signal stored in the signal storage module to release according to the square wave generating signal, thereby adjusting the output control signal provided by the signal storage module to the output control module. And by setting up a signal output module electrically connected to the power injection end and the signal output end respectively, the signal output module can control the square wave signal output by the signal output end according to the power signal injected by the power injection end and the square wave generating signal, thereby realizing the control of the circuit states of the output control module, the power release module and the signal output module in sequence according to the power signal injected by the power injection end stored in the signal storage module, and finally being able to output the square wave signal through the signal output end, without relying on a complex external timing source, thereby reducing the manufacturing and maintenance costs of the square wave generating circuit.

[0031] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 1 is a schematic structural diagram of a square wave generating circuit provided by an embodiment of the present invention;

[0034] Figure 2 1 is a schematic structural diagram of another square wave generating circuit provided by an embodiment of the present invention;

[0035] Figure 3 1 is a schematic structural diagram of a square wave signal output by a square wave generating circuit provided in an embodiment of the present invention;

[0036] Figure 4 1 is a schematic structural diagram of a square wave signal output by another square wave generating circuit provided in an embodiment of the present invention;

[0037] Figure 5 1 is a schematic structural diagram of a square wave signal output by another square wave generating circuit provided in an embodiment of the present invention;

[0038] Figure 6 It is a structural diagram of a square wave generating system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] Figure 1 FIG. 1 is a schematic diagram of a square wave generating circuit provided by an embodiment of the present invention. Figure 1As shown, the square wave generating circuit includes: a power injection terminal 01, a signal storage module 1, an electric energy release module 2, an output control module 3, a signal output module 4 and a signal output terminal 02; the signal storage module 1 is electrically connected to the power injection terminal 01 and the control terminal of the output control module 3 respectively, and the signal storage module 1 is used to store the power signal injected by the power injection terminal 01 and provide an output control signal to the output control module 3; the output control module 3 is electrically connected to the power injection terminal 01, the control terminal of the electric energy release module 2 and the control terminal of the signal output module 4 respectively, and the output control module 3 is used to provide a square wave generating signal to the electric energy release module 2 and the signal output module 4 respectively according to the power signal injected by the power injection terminal 01 and the output control signal; the electric energy release module 2 is also electrically connected to the signal storage module 1, and the electric energy release module 2 is used to control the release of the power signal stored in the signal storage module 1 according to the square wave generating signal; the signal output module 4 is also electrically connected to the power injection terminal 01 and the signal output terminal 02 respectively, and the signal output module 4 is used to control the square wave signal output by the signal output terminal 02 according to the power signal injected by the power injection terminal 01 and the square wave generating signal.

[0042] Specifically, power injection terminal 01 can be understood as the voltage input terminal of the square wave generating circuit. Power injection terminal 01 can be connected to an external power source, such as a 5V voltage source, to provide power support for signal storage module 1, power release module 2, output control module 3, and signal output module 4. Signal storage module 1 is electrically connected to power injection terminal 01, enabling signal storage module 1 to store the power signal injected by power injection terminal 01. Simultaneously, signal storage module 1 is electrically connected to the control terminal of output control module 3, enabling signal storage module 1 to provide an output control signal to output control module 3 based on the stored power signal injected by power injection terminal 01. This can drive the circuit state switching of output control module 3, laying the foundation for output control module 3 to continue to control the state switching of subsequent circuits and ultimately output a square wave signal through signal output terminal 02.

[0043] The output control module 3 is electrically connected to the power injection terminal 01, the control terminal of the power release module 2, and the control terminal of the signal output module 4, respectively, so that the output control module 3 can provide square wave generation signals to the power release module 2 and the signal output module 4, respectively, based on the power signal injected by the power injection terminal 01 and the output control signal provided by the signal storage module 1. This enables the output control module 3 to dynamically adjust the circuit states of the power release module 2 and the signal output module 4 based on the power signal injected by the power injection terminal 01 and the output control signal provided by the signal storage module 1, thereby achieving synchronous regulation of the power release of the signal storage module 1 and the square wave signal output by the signal output module 4 at the signal output terminal 02, thereby improving the stability and accuracy of the square wave signal output by the signal output terminal 02.

[0044] The power release module 2 is also electrically connected to the signal storage module 1, enabling the power release module 2 to control the release of the power signal stored in the signal storage module 1 according to the square wave generation signal. It is understood that the power release module 2 can control the amount of the stored power signal released by the signal storage module 1 according to the square wave generation signal provided by the output control module 3. In other words, the power release module 2 can adjust the amount of the power signal stored in the signal storage module 1, thereby adjusting the output control signal provided by the signal storage module 1 to the output control module 3, and further adjusting the circuit state of the output control module 3, thereby laying the foundation for outputting the square wave signal.

[0045] The signal output module 4 is also electrically connected to the power injection terminal 01 and the signal output terminal 02, respectively, so that the signal output module 4 can control the square wave signal output by the signal output terminal 02 according to the power signal injected by the power injection terminal 01 and the square wave generation signal. This achieves the goal of sequentially controlling the circuit states of the output control module 3, the power release module 2, and the signal output module 4 according to the power signal injected by the power injection terminal 01 stored in the signal storage module 1, and ultimately outputting a square wave signal through the signal output terminal 02. The signal output terminal 02 serves as the output interface of the square wave generation circuit and can transmit the generated square wave signal to an external load or test equipment. By storing the power signal and generating the output control signal through the signal storage module 1 to achieve the output of the square wave signal, the dependence on complex external timing sources is reduced, thereby reducing the design complexity of the square wave generation circuit.

[0046] Specifically, when power injection terminal 01 receives external power charging, signal storage module 1 has not yet stored the power signal injected by power injection terminal 01, and signal storage module 1 is unable to provide an output control signal to output control module 3. At this time, output control module 3 can control electric energy release module 2 based on the power signal injected by power injection terminal 01 to not trigger the power signal stored in signal storage module 1 for release, and control signal output module 4 based on the power signal injected by power injection terminal 01 to control signal output terminal 02 to output a high level. Because electric energy release module 2 does not trigger the power signal stored in signal storage module 1 for release, the signal amount of the power signal injected by power injection terminal 01 stored in signal storage module 1 gradually increases, and the output control signal can be provided to output control module 3. At this time, output control module 3 can control electric energy release module 2 based on the power signal injected by power injection terminal 01 and the output control signal to control the power signal stored in signal storage module 1 for release, and drive signal output module 4 based on the power signal injected by power injection terminal 01 and the output control signal to control signal output terminal 02 to output a low level. Because the power release module 2 controls the release of the power signal stored in the signal storage module 1, the signal amount of the power signal injected by the power injection terminal 01 stored in the signal storage module 1 gradually decreases until the signal storage module 1 can no longer provide the output control signal to the output control module 3. At this time, the output control module 3 can again control the power release module 2 based on the power signal injected by the power injection terminal 01 to not trigger the release of the power signal stored in the signal storage module 1, and control the signal output module 4 to control the signal output terminal 02 to output a high level based on the power signal injected by the power injection terminal 01. The signal storage module 1 periodically changes the storage state and release state of the power signal injected by the power injection terminal 01 to drive the circuit states of the power release module 2, the output control module 3, and the signal output module 4 to periodically switch, so that the signal output terminal 02 can output a square wave signal.

[0047] The square wave generator circuit utilizes the periodic changes in the storage and release states of the power signal injected from power injection port 01 by signal storage module 1, along with the modular design of power release module 2, output control module 3, and signal output module 4, to generate a square wave signal. This eliminates the need for complex chips, reducing the manufacturing and maintenance costs of the square wave generator circuit. Furthermore, the modular structure of the square wave generator circuit eliminates the need for an external oscillator and relies solely on an internal charge-discharge mechanism to achieve square wave signal output, simplifying the circuit layout and facilitating integration and expansion.

[0048] In this embodiment, a power injection terminal, a signal storage module, an electric energy release module, an output control module, a signal output module, and a signal output terminal are provided in a square wave generating circuit, and the signal storage module is provided to be electrically connected to the power injection terminal and the control terminal of the output control module, so that the signal storage module can store the power signal injected by the power injection terminal and provide the output control signal to the output control module, thereby driving the circuit state switching of the output control module. The output control module is provided to be electrically connected to the power injection terminal, the control terminal of the electric energy release module, and the control terminal of the signal output module, so that the output control module can provide the square wave generating signal to the electric energy release module and the signal output module respectively according to the power signal injected by the power injection terminal and the output control signal, thereby achieving the synchronous regulation of the electric energy release of the signal storage module and the square wave signal outputted by the signal output terminal controlled by the signal output module. The electric energy release module is provided to be electrically connected to the signal storage module, so that the electric energy release module can control the power signal stored in the signal storage module to release according to the square wave generating signal, thereby adjusting the output control signal provided by the signal storage module to the output control module. And by setting up a signal output module electrically connected to the power injection end and the signal output end respectively, the signal output module can control the square wave signal output by the signal output end according to the power signal injected by the power injection end and the square wave generating signal, thereby realizing the control of the circuit states of the output control module, the power release module and the signal output module in sequence according to the power signal injected by the power injection end stored in the signal storage module, and finally being able to output the square wave signal through the signal output end, without relying on a complex external timing source, thereby reducing the manufacturing and maintenance costs of the square wave generating circuit.

[0049] Optional, Figure 2 FIG. 1 is a schematic diagram of a square wave generating circuit provided by an embodiment of the present invention. Figure 2 As shown, the signal storage module 1 includes a first resistor R1 and a first capacitor C1; the power injection terminal O1 is electrically connected to the first end of the first resistor R1, the second end of the first resistor R1 is electrically connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is grounded.

[0050] Specifically, the first resistor R1 is electrically connected to the loop between the first end of the first capacitor C1 and the power injection terminal O1, so that the power signal injected from the power injection terminal O1 into the first capacitor C1 can be limited by the first resistor R1, ensuring a smooth and controllable charging process of the first capacitor C1 and avoiding overshoot or unstable charging process of the first capacitor C1. The power signal injected from the power injection terminal O1 is stored by the first capacitor C1, so that the voltage of the first capacitor C1 gradually increases, laying the foundation for subsequently providing an output control signal to the output control module 3 through the first capacitor C1 to drive the circuit state switching of the output control module 3.

[0051] Optional, continue to refer to Figure 2 The electric energy release module 2 includes a second resistor R2 and a first MOS transistor M1; a first end of the second resistor R2 is electrically connected to a first end of the first capacitor C1, a second end of the second resistor R2 is electrically connected to a drain of the first MOS transistor M1, a gate of the first MOS transistor is a control end of the electric energy release module 2, and a source of the first MOS transistor M1 is grounded.

[0052] Specifically, the first end of the second resistor R2 is electrically connected to the first end of the first capacitor C1, and the second end of the second resistor R2 is electrically connected to the drain of the first MOS transistor M1. The gate of the first MOS transistor M1 serves as the control end of the electric energy release module 2, and the source of the first MOS transistor M1 is grounded, that is, the gate of the first MOS transistor M1 is electrically connected to the output control module 3, so that the gate of the first MOS transistor M1 can receive the square wave generation signal provided by the output control module 3 to control the release of the power signal stored in the signal storage module 1. It is understandable that when the first MOS transistor M1 is disconnected under the control of the square wave generation signal, the first capacitor C1 cannot be discharged through the second resistor R2, and the first capacitor C1 will remain in a charged state; when the first MOS transistor M1 is turned on under the control of the square wave generation signal, the first capacitor C1 will be discharged through the second resistor R2, and the voltage of the first capacitor C1 will decrease. By dynamically adjusting the conduction state of the first MOS transistor M1 through the square wave generating signal, dynamic adjustment of the charge and discharge state of the first capacitor C1 is achieved, so that the voltage of the first capacitor C1 can be adjusted, thereby sequentially controlling the circuit states of the output control module 3, the power release module 2, and the signal output module 4, laying the foundation for outputting a square wave signal.

[0053] Optional, continue to refer to Figure 2 The output control module 3 includes a switch control unit 31, a first switch unit 32, and a second switch unit 33; the input end of the switch control unit 31 is electrically connected to the signal storage module 1, and the output end of the switch control unit 31 is electrically connected to the control end of the first switch unit 32. The switch control unit 31 is used to provide a first switch control signal to the first switch unit 32 according to the output control signal; the input end of the first switch unit 32 is electrically connected to the power injection end 01, and the output end of the first switch unit 32 is electrically connected to the control end of the second switch unit 33. The first switch unit 32 is used to provide a second switch control signal to the second switch unit 33 according to the power signal injected by the power injection end 01 and the first switch control signal; the input end of the second switch unit 33 is electrically connected to the power injection end 01, and the output end of the second switch unit 33 is electrically connected to the control end of the electric energy release module 2 and the control end of the signal output module 4 respectively. The second switch unit 33 is used to provide a square wave generation signal to the electric energy release module 2 and the signal output module 4 respectively according to the power signal injected by the power injection end 01 and the second switch control signal.

[0054] Specifically, the input end of the switch control unit 31 is electrically connected to the signal storage module 1, and the output end of the switch control unit 31 is electrically connected to the control end of the first switch unit 32, so that the switch control unit 31 can provide the first switch control signal to the first switch unit 32 according to the output control signal. Figure 2 The switch control unit 31 includes a third resistor R3 and a fourth resistor R4; the first end of the third resistor R3 serves as the input end of the switch control unit 31, the second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is grounded, and the intermediate node where the third and fourth resistors R3 and R4 are connected serves as the output end of the switch control unit 31. It is understood that the first end of the third resistor R3 is electrically connected to the first end of the first capacitor C1, the second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded, i.e., the third resistor R3 and the fourth resistor R4 are connected in series, and the third and fourth resistors R3 and R4 are connected in parallel with the first capacitor C1, so that the input voltage obtained by the input end of the switch control unit 31 changes in real time as the first capacitor C1 charges. At the same time, the intermediate node where the third resistor R3 and the fourth resistor R4 are connected is the output end of the switch control unit 31, that is, the control end of the first switch unit 32 is electrically connected to the second end of the third resistor R3 and the first end of the fourth resistor R4, respectively. The first switch control signal obtained by the first switch unit 32 through the control end is the voltage of the first capacitor C1 after being divided by the third resistor R3 and the fourth resistor R4, and the first switch control signal increases with the increase of the charging voltage of the first capacitor C1, thereby laying the foundation for the switch control unit 31 to provide the first switch control signal to the first switch unit 32.

[0055] The input end of the first switch unit 32 is electrically connected to the power injection terminal 01, and the output end of the first switch unit 32 is electrically connected to the control end of the second switch unit 33, so that the first switch unit 32 can provide the second switch control signal to the second switch unit 33 based on the power signal injected from the power injection terminal 01 and the first switch control signal. Optionally, the first switch unit 32 includes a fifth resistor R5 and a second MOS transistor M2; the first end of the fifth resistor R5 is the input end of the first switch unit 32, the second end of the fifth resistor R5 is electrically connected to the drain of the second MOS transistor M2, the drain of the second MOS transistor M2 is the output end of the first switch unit 32, the gate of the second MOS transistor M2 is the control end of the first switch unit 32, and the source of the second MOS transistor M2 is grounded. It can be understood that the first end of the fifth resistor R5 is electrically connected to the power injection terminal O1, the second end of the fifth resistor R5 is electrically connected to the drain of the second MOS transistor M2, the drain of the second MOS transistor M2 is electrically connected to the control terminal of the second switch unit 33, the gate of the second MOS transistor M2 is electrically connected to the second end of the third resistor R3 and the first end of the fourth resistor R4, respectively, and the source of the second MOS transistor M2 is grounded. Therefore, the voltage of the first capacitor C1 after the voltage is divided by the third resistor R3 and the fourth resistor R4 is the gate voltage of the second MOS transistor M2. When the voltage of the first capacitor C1 after the voltage is divided by the third resistor R3 and the fourth resistor R4 does not reach the threshold voltage of the second MOS transistor M2, the second MOS transistor M2 will be turned off; when the voltage of the first capacitor C1 after the voltage is divided by the third resistor R3 and the fourth resistor R4 reaches or exceeds the threshold voltage of the second MOS transistor M2, the second MOS transistor M2 will be turned on. The charging process of the first capacitor C1 and the voltage division control of the switch control unit 31 can accurately adjust the on / off state of the second MOS transistor M2, thereby laying a foundation for the first switch unit 32 to provide the second switch control signal to the second switch unit 33.

[0056] The input end of the second switch unit 33 is electrically connected to the power injection end 01, and the output end of the second switch unit 33 is electrically connected to the control end of the power release module 2 and the control end of the signal output module 4, so that the second switch unit 33 can provide a square wave generating signal to the power release module 2 and the signal output module 4 according to the power signal injected by the power injection end 01 and the second switch control signal. Figure 2The second switch unit 33 includes a sixth resistor R6 and a third MOS transistor M3. The first end of the sixth resistor R6 serves as the input end of the second switch unit 33, the second end of the sixth resistor R6 is electrically connected to the drain of the third MOS transistor M3, the drain of the third MOS transistor M3 serves as the output end of the second switch unit 33, the gate of the third MOS transistor M3 serves as the control end of the second switch unit 33, and the source of the third MOS transistor M3 is grounded. It is understood that the first end of the sixth resistor R6 is electrically connected to the power injection terminal O1, the second end of the sixth resistor R6 is electrically connected to the drain of the third MOS transistor M3, the gate of the third MOS transistor M3 is electrically connected to the drain of the second MOS transistor M2, the drain of the third MOS transistor M3 is electrically connected to the control end of the electric energy release module 2 and the control end of the signal output module 4, respectively, and the source of the third MOS transistor M3 is grounded. Therefore, when the second MOS transistor M2 is turned on by the charging process of the first capacitor C1 and the voltage division control of the switch control unit 31, the gate voltage of the third MOS transistor M3 is pulled down to below its threshold voltage, and the third MOS transistor M3 is turned off. When the second MOS transistor M2 is turned off by the charging process of the first capacitor C1 and the voltage division control of the switch control unit 31, the gate of the third MOS transistor M3 receives a voltage through the power injection terminal O1, causing the gate voltage of the third MOS transistor M3 to exceed its threshold voltage, and the third MOS transistor M3 is turned on. The conduction state of the third MOS transistor M3 is dynamically adjusted by the second switch control signal provided by the first switch unit 32, thereby dynamically adjusting the conduction state of the third MOS transistor M3 according to the charging process of the first capacitor C1. This lays the foundation for the third MOS transistor M3 to provide a square wave generation signal to the power release module 2 and the signal output module 4, respectively, so that the square wave signal can be output through the signal output terminal O2.

[0057] Optional, continue to refer to Figure 2 The signal output module 4 includes a seventh resistor R7 and a fourth MOS transistor M4; a first end of the seventh resistor R7 is electrically connected to the power injection terminal O1, a second end of the seventh resistor R7 is electrically connected to the drain of the fourth MOS transistor M4, a gate of the fourth MOS transistor M4 is the control terminal of the signal output module 4, and a source of the fourth MOS transistor M4 is grounded; the signal output terminal O2 is electrically connected to the second end of the seventh resistor R7 and the drain of the fourth MOS transistor M4, respectively.

[0058] Specifically, a first end of the seventh resistor R7 is electrically connected to the power injection terminal O1, a second end of the seventh resistor R7 is electrically connected to the drain of the fourth MOS transistor M4, a gate of the fourth MOS transistor M4 is electrically connected to the drain of the third MOS transistor M3, a source of the fourth MOS transistor M4 is grounded, and a signal output terminal O2 is electrically connected to the second end of the seventh resistor R7 and the drain of the fourth MOS transistor M4, respectively. Therefore, when the third MOS transistor M3 is turned on under the control of the first switch unit 32, the gate voltage of the fourth MOS transistor M4 is pulled down to below its threshold voltage, and the fourth MOS transistor M4 is turned off. When the third MOS transistor M3 is turned off under the control of the first switch unit 32, the gate of the fourth MOS transistor M4 receives a voltage through the power injection terminal O1, causing the gate voltage of the fourth MOS transistor M4 to be higher than its threshold voltage, and the fourth MOS transistor M4 is turned on. The second switch unit 33 dynamically adjusts the conduction state of the fourth MOS transistor M4, thereby dynamically adjusting the conduction state of the fourth MOS transistor M4 through the charging process of the first capacitor C1, thereby laying the foundation for the signal output module 4 to control the signal output terminal O2 to output a square wave signal.

[0059] The signal output terminal O2 is electrically connected to the second end of the seventh resistor R7 and the drain of the fourth MOS transistor M4, respectively, so that the signal output module 4 can control the signal output terminal O2 to output a square wave signal. It is understood that when the fourth MOS transistor M4 is turned on under the control of the second switch unit 33, the voltage at the signal output terminal O2 is pulled down to a low level, and the signal output terminal O2 will output a low-level signal. When the fourth MOS transistor M4 is turned off under the control of the second switch unit 33, the signal output terminal O2 receives voltage from the power injection terminal O1, and the signal output terminal O2 will output a high-level signal. This enables the signal output terminal O2 to output a square wave signal by controlling the charge and discharge state of the first capacitor C1 and the on / off state of the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4. This means that the square wave generating circuit can generate a square wave signal without relying on a complex external timing source.

[0060] In addition, the gate of the first MOS transistor M1 is electrically connected to the drain of the third MOS transistor M3. Therefore, when the third MOS transistor M3 is turned on under the control of the first switch unit 32, the gate voltage of the first MOS transistor M1 is pulled down to below its threshold voltage, and the first MOS transistor M1 is turned off. At this time, the first capacitor C1 cannot be discharged through the second resistor R2, and the first capacitor C1 remains in a charged state. When the third MOS transistor M3 is turned off under the control of the first switch unit 32, the gate of the first MOS transistor M1 obtains a voltage through the power injection terminal O1, so that the gate voltage of the first MOS transistor M1 is higher than its threshold voltage, and the first MOS transistor M1 is turned on. At this time, the first capacitor C1 is discharged through the second resistor R2, and the voltage of the first capacitor C1 is reduced, so that the voltage value of the output control signal obtained by the input terminal of the switch control unit 31 and the voltage value of the first switch control signal obtained by the input terminal of the first switch unit 32 are both reduced. When the input voltage obtained by the first switch unit 32 is lower than the threshold voltage of the second MOS transistor M2, the second MOS transistor M2 is turned off. The output control module 3 dynamically adjusts the conduction state of the first MOS transistor M1, thereby realizing dynamic adjustment of the charge and discharge state of the first capacitor C1. This enables the on and off states of the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, and the first MOS transistor M1 to be sequentially controlled by the charge and discharge state of the first capacitor C1, thereby ultimately outputting a square wave signal through the signal output terminal O2.

[0061] It is understood that the process of outputting a square wave signal through the signal output terminal 02 may specifically include: when the power injection terminal 01 receives external power charging, the initial voltage of the first capacitor C1 is 0V, and the voltage obtained by the first switch unit 32 after voltage division by the switch control unit 31 does not reach the threshold voltage of the second MOS transistor M2. The second MOS transistor M2 will be turned off, causing the third MOS transistor M3 to be turned on, and the first MOS transistor M1 and the fourth MOS transistor M4 to be turned off. At this time, the signal output terminal 02 will output a high-level signal. Because the first MOS transistor M1 is turned off, the first capacitor C1 will remain in a charged state, and the voltage of the first capacitor C1 will increase as the charging process progresses. The voltage obtained by the first switch unit 32 after voltage division by the switch control unit 31 will also increase. When the voltage obtained by the first switch unit 32 after voltage division by the switch control unit 31 reaches the threshold voltage of the second MOS transistor M2, the second MOS transistor M2 will be turned on, causing the third MOS transistor M3 to be turned off, and the first MOS transistor M1 and the fourth MOS transistor M4 to be turned on. At this time, the signal output terminal 02 will output a low-level signal. Since the first MOS transistor M1 is turned on, the first capacitor C1 will discharge through the second resistor R2, the voltage of the first capacitor C1 will decrease, and the voltage obtained by the first switch unit 32 after the voltage division by the switch control unit 31 will also decrease. When the voltage obtained by the first switch unit 32 after the voltage division by the switch control unit 31 falls below the threshold voltage of the second MOS transistor M2, the second MOS transistor M2 will be turned off again, causing the third MOS transistor M3 to be turned on again, and the first MOS transistor M1 and the fourth MOS transistor M4 to be turned off again. At this time, the signal output terminal O2 will once again output a high-level signal. The periodic changes in the charging and discharging states of the first capacitor C1 drive the periodic switching of the on and off states of the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, and the first MOS transistor M1, so that the signal output terminal O2 can output a square wave signal.

[0062] The square wave generating circuit uses capacitors, resistors, and MOS tubes to generate square wave signals, without relying on complex external timing sources, thus reducing the manufacturing and maintenance costs of the square wave generating circuit. At the same time, the output of the square wave signal is achieved through the charge and discharge state of the first capacitor C1, eliminating the delay of the complex external timing source, thereby increasing the frequency of the output square wave signal. In addition, by adjusting the capacitance value of the first capacitor C1, the frequency of the output square wave signal can be flexibly adjusted. For example, increasing the first capacitor C1 will increase the charge and discharge time constant of the first capacitor C1, slowing down the charging and discharging processes of the first capacitor C1, that is, extending the charge and discharge time, resulting in a decrease in the frequency of the output square wave signal, thereby improving the flexibility of the square wave generating circuit and making the square wave generating circuit suitable for a variety of usage scenarios.

[0063] It can also be understood that the first capacitor C1 is charged from the power injection terminal O1 through the first resistor R1. The charging voltage varies with time. Increasing the first resistor R1 increases the charging time constant of the first capacitor C1, slowing the charging speed of the first capacitor C1. This increases the time required for the first capacitor C1 to charge to a specific voltage, for example, a specific voltage at which the voltage obtained by the first switch unit 32 after voltage division by the switch control unit 31 equals the threshold voltage of the second MOS transistor M2. The frequency of the square wave signal output by the signal output terminal O2 is determined by the sum of the charging time and the discharging time of the first capacitor C1. If the charging time of the first capacitor C1 increases, the total period T will be extended, and the frequency f = 1 / T of the output square wave signal will decrease. At the same time, the duty cycle of the square wave signal output by the signal output terminal O2 is determined by the ratio of the high-level duration of the square wave signal to the sum of the high-level duration and the low-level duration. Prolonging the charging time of the first capacitor C1 will delay the conduction of the second MOS transistor M2. When the second MOS transistor M2 is turned off, the third MOS transistor M3 is turned on, and the first MOS transistor M1 and the fourth MOS transistor M4 are turned off. This increases the duration of the high-level signal output by the signal output terminal O2, thereby increasing the duty cycle of the output square wave signal. Furthermore, the first capacitor C1 discharges through the second resistor R2. Increasing the second resistor R2 increases the discharge time constant of the first capacitor C1, slowing the discharge of the first capacitor C1. This increases the time required for the first capacitor C1 to discharge to a specific voltage, for example, a specific voltage at which the voltage obtained by the first switch unit 32 after voltage division by the switch control unit 31 is less than the threshold voltage of the second MOS transistor M2. This increased discharge time of the first capacitor C1 prolongs the total period T, which reduces the frequency f = 1 / T of the output square wave signal. At the same time, the extended discharge time of the first capacitor C1 delays the disconnection of the second MOS transistor M2. When the second MOS transistor M2 is turned on, the third MOS transistor M3 is turned off, and the first MOS transistor M1 and the fourth MOS transistor M4 are turned on. This increases the duration of the low-level signal output by the signal output terminal O2, that is, reduces the duty cycle of the output square wave signal. By adjusting the values ​​of the first resistor R1 and the second resistor R2, the charge and discharge time of the first capacitor C1 can be flexibly adjusted, thereby controlling the frequency and duty cycle of the square wave signal output by the signal output terminal O2. This enhances the flexibility of the square wave generating circuit, making it suitable for a variety of usage scenarios and able to meet diverse frequency and duty cycle requirements.

[0064] It can also be understood that the gate voltage obtained by the gate of the second MOS transistor M2 is the voltage V C1 The voltage value after voltage division by the third resistor R3 and the fourth resistor R4 is specifically V C1 × This voltage acts on the gate of the second MOS transistor M2, determining whether the second MOS transistor M2 is on or off. By adjusting the ratio of the third resistor R3 and the fourth resistor R4, the on-time of the second MOS transistor M2 can be accurately controlled, thereby dynamically adjusting the duty cycle of the square wave signal output by the signal output terminal O2. For example, increasing the fourth resistor R4 makes the voltage division coefficient Increase, so that the gate voltage obtained by the gate of the second MOS tube M2 is at the same V C1 The lower one is higher, that is, the V required to turn on the second MOS tube M2 is C1 The conduction time of the second MOS tube M2 is shortened. When the second MOS tube M2 is turned on, the third MOS tube M3 is turned off, and the first MOS tube M1 and the fourth MOS tube M4 are turned on. That is, the duration of the low-level signal output by the signal output terminal O2 is increased, resulting in a decrease in the duty cycle of the output square wave signal. Reducing the fourth resistor R4 makes the voltage division coefficient Reduced, so that the gate voltage obtained by the gate of the second MOS tube M2 is at the same V C1 The lower the V required to turn on the second MOS tube M2, the lower the V required to turn on the second MOS tube M2. C1 The turn-on time of the second MOS transistor M2 is increased, and the turn-on time of the second MOS transistor M2 is delayed. When the second MOS transistor M2 is turned off, the third MOS transistor M3 is turned on, and the first MOS transistor M1 and the fourth MOS transistor M4 are turned off. That is, the duration of the signal output terminal O2 outputting a high-level signal is increased, resulting in an increase in the duty cycle of the output square wave signal. By adjusting the ratio of the third resistor R3 and the fourth resistor R4, the duty cycle of the square wave signal output by the signal output terminal O2 can be dynamically adjusted, making the square wave generating circuit suitable for a variety of usage scenarios and able to meet diverse duty cycle requirements. At the same time, by optimizing the resistance values ​​of the third resistor R3 and the fourth resistor R4, the output control module 3 can more accurately respond to the charging state of the first capacitor C1, thereby improving the stability of the square wave signal output by the signal output terminal O2 to meet high-precision requirements.

[0065] In an exemplary embodiment, the resistance value of the first resistor R1 is set to 2950Ω, the resistance value of the second resistor R2 is set to 3100Ω, the resistance value of the third resistor R3 is set to 10000Ω, the resistance value of the fourth resistor R4 is set to 10000Ω, the resistance value of the fifth resistor is set to 50Ω, the resistance value of the sixth resistor is set to 50Ω, the resistance value of the seventh resistor is set to 50Ω, the capacitance value of the first capacitor C1 is set to 0.1nF, the threshold voltage of the first MOS transistor M1 is set to 1.1V, the threshold voltage of the second MOS transistor M2 is set to 1.1V, the threshold voltage of the third MOS transistor M3 is set to 1.1V, and the threshold voltage of the fourth MOS transistor M4 is set to 1.1V, so that the signal output terminal O2 can output the following signal: Figure 3The square wave signal with a frequency of 1 MHz is shown; in another exemplary embodiment, the resistance value of the first resistor R1 is set to 169 Ω, the resistance value of the second resistor R2 is set to 145 Ω, the resistance value of the third resistor R3 is set to 500 Ω, the resistance value of the fourth resistor R4 is set to 500 Ω, the resistance value of the fifth resistor is set to 50 Ω, the resistance value of the sixth resistor is set to 50 Ω, the resistance value of the seventh resistor is set to 50 Ω, the capacitance value of the first capacitor C1 is set to 0.1 nF, the threshold voltage of the first MOS transistor M1 is set to 1.1 V, the threshold voltage of the second MOS transistor M2 is set to 1.1 V, the threshold voltage of the third MOS transistor M3 is set to 1.1 V, and the threshold voltage of the fourth MOS transistor M4 is set to 1.1 V, so that the signal output terminal O2 can output the following signal: Figure 4 The square wave signal with a frequency of 10 MHz is shown; in another exemplary embodiment, the resistance value of the first resistor R1 is set to 69 Ω, the resistance value of the second resistor R2 is set to 90 Ω, the resistance value of the third resistor R3 is set to 80 Ω, the resistance value of the fourth resistor R4 is set to 80 Ω, the resistance value of the fifth resistor is set to 50 Ω, the resistance value of the sixth resistor is set to 50 Ω, the resistance value of the seventh resistor is set to 50 Ω, the capacitance value of the first capacitor C1 is set to 0.1 nF, the threshold voltage of the first MOS transistor M1 is set to 1.1 V, the threshold voltage of the second MOS transistor M2 is set to 1.1 V, the threshold voltage of the third MOS transistor M3 is set to 1.1 V, and the threshold voltage of the fourth MOS transistor M4 is set to 1.1 V, so that the signal output terminal O2 can output the following signal: Figure 5 The frequency shown is a 20MHz square wave signal. This allows the square wave signal generated by the square wave generator circuit to break through the frequency limit of traditional chips, such as the NE555 timer, which has a maximum frequency of 500kHz. This improves the flexibility of the square wave generator circuit and the frequency of the output square wave signal.

[0066] Based on the same inventive concept, an embodiment of the present invention further provides a square wave generating system. Figure 6 FIG. 1 is a schematic diagram of the structure of a square wave generating system provided by an embodiment of the present invention. Figure 6 As shown, the square wave generating system includes: a power supply device 5, a square wave signal output device 6 and the square wave generating circuit of the above embodiment; the power supply device 5 is electrically connected to the power injection terminal 01, and the power supply device 5 is used to power the square wave generating circuit; the square wave signal output device 6 is electrically connected to the signal output terminal 02, and the square wave signal output device 6 is used to obtain and transmit the square wave signal output by the signal output terminal 02.

[0067] Specifically, the power supply device 5 is electrically connected to the power injection terminal 01 so that the power supply device 5 can provide the required electrical energy to the square wave generating circuit to ensure the normal operation of each module in the square wave generating circuit. Exemplarily, the power supply device 5 can include a battery pack or a power adapter, and the power supply device 5 can output a voltage of 5V. The square wave signal output device 6 is electrically connected to the signal output terminal 02 so that the square wave signal output device 6 can obtain the square wave signal output by the signal output terminal 02 and transmit the square wave signal to an external device, such as an external load or test equipment, to implement the application or monitoring of the square wave signal. Exemplarily, the square wave signal output device 6 can include a signal transmission line, an oscilloscope, or a clock input module.

[0068] Therefore, the square wave generating system provided in this embodiment has the structure and operation of the square wave generating circuit of the above embodiment, and can achieve the effect of the square wave generating circuit of the above embodiment. The similarities can be referred to the above description and will not be repeated here.

[0069] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present invention can be achieved. This is not limited herein.

[0070] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A square wave generating circuit, characterized in that: include: Power injection terminal, signal storage module, power release module, output control module, signal output module and signal output terminal; The signal storage module is electrically connected to the power injection terminal and the control terminal of the output control module respectively, and is used to store the power signal injected by the power injection terminal and provide an output control signal to the output control module; The output control module is electrically connected to the power injection terminal, the control terminal of the power release module, and the control terminal of the signal output module, respectively, and is used to provide a square wave generating signal to the power release module and the signal output module according to the power signal injected by the power injection terminal and the output control signal; The power release module is also electrically connected to the signal storage module, and is used to control the power signal stored in the signal storage module to release according to the square wave generating signal; The signal output module is also electrically connected to the power injection end and the signal output end respectively, and is used to control the square wave signal output by the signal output end according to the power signal injected by the power injection end and the square wave generating signal.

2. The square wave generating circuit according to claim 1, characterized in that: The signal storage module includes a first resistor and a first capacitor; The power injection terminal is electrically connected to the first terminal of the first resistor, the second terminal of the first resistor is electrically connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is grounded.

3. The square wave generating circuit according to claim 2, characterized in that: The electric energy release module includes a second resistor and a first MOS tube; The first end of the second resistor is electrically connected to the first end of the first capacitor, the second end of the second resistor is electrically connected to the drain of the first MOS transistor, the gate of the first MOS transistor is the control end of the electric energy release module, and the source of the first MOS transistor is grounded.

4. The square wave generating circuit according to claim 3, characterized in that: The output control module includes a switch control unit, a first switch unit and a second switch unit; The input end of the switch control unit is electrically connected to the signal storage module, the output end of the switch control unit is electrically connected to the control end of the first switch unit, and the switch control unit is used to provide a first switch control signal to the first switch unit according to the output control signal; The input end of the first switch unit is electrically connected to the power injection end, the output end of the first switch unit is electrically connected to the control end of the second switch unit, and the first switch unit is configured to provide a second switch control signal to the second switch unit according to the power signal injected by the power injection end and the first switch control signal; The input end of the second switch unit is electrically connected to the power injection end, and the output end of the second switch unit is electrically connected to the control end of the electric energy release module and the control end of the signal output module respectively. The second switch unit is used to provide a square wave generating signal to the electric energy release module and the signal output module respectively according to the power signal injected by the power injection end and the second switch control signal.

5. The square wave generating circuit according to claim 4, characterized in that: The switch control unit includes a third resistor and a fourth resistor; The first end of the third resistor is the input end of the switch control unit, the second end of the third resistor is electrically connected to the first end of the fourth resistor, the second end of the fourth resistor is grounded, and the intermediate node where the third resistor and the fourth resistor are connected is the output end of the switch control unit.

6. The square wave generating circuit according to claim 4, characterized in that: The first switch unit includes a fifth resistor and a second MOS tube; A first end of the fifth resistor is an input end of the first switch unit, a second end of the fifth resistor is electrically connected to a drain of the second MOS transistor, the drain of the second MOS transistor is an output end of the first switch unit, a gate of the second MOS transistor is a control end of the first switch unit, and a source of the second MOS transistor is grounded.

7. The square wave generating circuit according to claim 4, characterized in that: The second switch unit includes a sixth resistor and a third MOS tube; The first end of the sixth resistor is the input end of the second switch unit, the second end of the sixth resistor is electrically connected to the drain of the third MOS transistor, the drain of the third MOS transistor is the output end of the second switch unit, the gate of the third MOS transistor is the control end of the second switch unit, and the source of the third MOS transistor is grounded.

8. The square wave generating circuit according to claim 1, characterized in that: The signal output module includes a seventh resistor and a fourth MOS tube; A first end of the seventh resistor is electrically connected to the power injection terminal, a second end of the seventh resistor is electrically connected to the drain of the fourth MOS transistor, a gate of the fourth MOS transistor is a control terminal of the signal output module, and a source of the fourth MOS transistor is grounded; The signal output end is electrically connected to the second end of the seventh resistor and the drain of the fourth MOS transistor respectively.

9. A square wave generating system, characterized in that: include: A power supply device, a square wave signal output device, and a square wave generating circuit as claimed in any one of claims 1 to 8; The power supply device is electrically connected to the power injection terminal, and the power supply device is used to supply power to the square wave generating circuit; The square wave signal output device is electrically connected to the signal output end, and is used to obtain and transmit the square wave signal output by the signal output end.

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