A charge regulation method and system for an ultrahigh voltage planar mos

Abstract

The application discloses a charge regulation method and system of an ultrahigh-voltage planar MOS, relates to the field of semiconductor device performance regulation, and comprises the following steps: pre-constructing a reconfigurable depletion layer function in a device drift region; performing state sensing of the reconfigurable depletion layer function based on a preset time window; performing driving initialization according to a real-time working state, outputting initial gate driving behavior; performing state transition prediction on the real-time working state, outputting K predicted state characteristics, then performing driving behavior matching, and outputting K transition driving behaviors; performing state tracking on the reconfigurable depletion layer function, and according to the time-space correlation between the tracking result and the K predicted state characteristics, updating driving behavior from the K transition driving behaviors; and controlling a gate driving circuit to perform dynamic impedance switching of a multistage resistance path. The application solves the technical problem of poor regulation precision and adaptability of the existing ultrahigh-voltage planar MOS, and achieves the technical effect of improving the precision and adaptability of charge regulation.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device performance control, and in particular to a charge control method and system for ultra-high voltage planar MOS. Background Art

[0002] In ultra-high voltage planar MOS device applications, precise charge regulation is crucial for improving device performance, reliability, and energy efficiency. This is especially true when dealing with dynamic characteristic changes under complex operating conditions, as the accuracy of charge regulation directly affects the stable operation and lifespan of the device. Currently, the main approach to addressing this problem is to responsively regulate the device's operating state through a fixed-impedance gate drive circuit combined with an open-loop control strategy. However, current methods lack the ability to accurately perceive and dynamically predict the device's real-time operating state, making it impossible to adjust drive parameters in a timely manner when faced with rapidly changing operating conditions. This can easily lead to problems such as charge accumulation imbalance, increased switching losses, and even device failure.

[0003] In the current related technologies, the charge control of ultra-high voltage planar MOS has technical problems such as poor control accuracy and adaptability. Summary of the Invention

[0004] The present application provides a charge control method and system for ultra-high voltage planar MOS, which adopts a pre-constructed reconfigurable depletion layer function in the drift region of the device, and realizes dynamic control by configuring a gate drive circuit with a multi-level resistance path. The chip junction temperature, drain-source voltage and current change rate and other working conditions are monitored in real time with a preset time window as a period. The gate drive behavior is initialized based on these parameters, and K possible state transition paths are predicted and matched to generate corresponding drive strategies. By continuously tracking the depletion layer state and combining the spatiotemporal correlation between the prediction results and the actual state, the drive parameters are dynamically adjusted. The impedance switching of the multi-level resistance path is used to perform precise charge control and other technical means to solve the technical problems of poor control accuracy and adaptability of the existing charge control of ultra-high voltage planar MOS, and achieve the technical effect of improving the accuracy and adaptability of charge control.

[0005] The present application provides a charge control method for an ultra-high voltage planar MOS, comprising: pre-constructing a reconfigurable depletion layer function in a device drift region of an ultra-high voltage planar gate MOSFET, wherein an output end of a gate drive circuit of the ultra-high voltage planar gate MOSFET is configured with a parallel multi-stage resistance path; performing state perception of the reconfigurable depletion layer function based on a preset time window to obtain a real-time working state, wherein the real-time working state includes a real-time chip junction temperature, a drain-source voltage change rate, and a drain current change rate; performing drive initialization according to the real-time working state and outputting an initial gate drive behavior; performing state transition prediction on the real-time working state and outputting K predicted state features, then performing drive behavior matching on the K predicted state features and outputting K transfer drive behaviors; performing state tracking on the reconfigurable depletion layer function and, based on the spatiotemporal correlation between the tracking result and the K predicted state features, retrieving an updated drive behavior from the K transfer drive behaviors; and using the updated drive behavior to control the gate drive circuit to execute dynamic impedance switching of the multi-stage resistance path.

[0006] In a possible implementation, the drive is initialized according to the real-time working state, the initial gate drive behavior is output, and the following processing is performed: using the real-time working state, a first-order linear mapping is performed under a predefined multi-scale parameter adjustment mapping rule, and basic drive behavior parameters are output; after interactively obtaining multiple sample multi-dimensional working condition combinations and multiple sample drive modes, a matching relationship between the multiple sample multi-dimensional working condition combinations and the multiple sample drive modes is constructed to obtain a drive mode information library; the real-time working state is loaded into the drive mode information library, the working condition combination attribution matching is performed, and the enhanced drive mode is located; the enhanced drive mode and the basic drive behavior parameters are combined to output the initial gate drive behavior.

[0007] In a possible implementation, state transition prediction is performed on the real-time working state, and after K predicted state features are output, driving behavior matching is performed on the K predicted state features, and K transfer driving behaviors are output. The following processing is performed: historical working state logs are locally called; typical working condition aggregation is performed on the historical working state logs to obtain multi-scale state intervals; based on the multi-scale state intervals, time-series associated state transition data is extracted from the historical working state logs to construct a state transition prediction matrix; based on the coverage relationship of the multi-scale state intervals on the real-time working state, transition prediction is performed on the state transfer prediction matrix to output K predicted state features; the K predicted state features are used to perform first-order linear mapping of the multi-scale parameter adjustment mapping rule to output the K transfer driving behaviors.

[0008] In a possible implementation, the reconfigurable depletion layer function is state tracked, and based on the spatiotemporal correlation between the tracking result and the K predicted state features, an update driving behavior is retrieved from the K transfer driving behaviors, and the following processing is performed: the reconfigurable depletion layer function is state tracked to obtain a real-time tracking feature; based on a spatiotemporal correlation measurement rule, K spatiotemporal correlation matching degrees between the real-time tracking feature and the K predicted state features are calculated; after arranging the K transfer driving behaviors in descending order according to the K spatiotemporal correlation matching degrees, the transfer driving behavior with the highest ranking is retrieved as the update driving behavior.

[0009] In a possible implementation, the updated driving behavior is used to control the gate driving circuit to perform dynamic impedance switching of the multi-stage resistance path, and the following processing is performed: by parsing the updated driving behavior, a target impedance value, a switching mode and a switching time window are obtained; according to the target impedance value, an action instruction set of a target control switch is matched in a pre-built switch action mapping rule library; when the switching mode is ramp switching, a real-time impedance value is acquired through an impedance feedback loop, and a real-time impedance deviation between the real-time impedance value and the target impedance value is calculated; according to the real-time impedance deviation, an impedance switching strategy is matched in a multi-stage transition strategy library; after loading the action instruction set to execute the state switching of the target control switch, dynamic impedance switching of the multi-stage resistance path is performed according to the impedance switching strategy within the switching time window.

[0010] In a possible implementation, a reconfigurable depletion layer function is pre-constructed in the device drift region of the ultra-high voltage planar gate MOSFET, and the following processing is performed: with the charge multi-scenario balance as a constraint, structural balance optimization is performed in the device drift region to obtain a three-dimensional charge balance gate structure; based on the three-dimensional charge balance gate structure, alternatingly arranged P-type columns and N-type columns are constructed in the device drift region to dynamically reconstruct the structure to support the depletion layer, thereby forming the reconfigurable depletion layer function.

[0011] In a possible implementation, with charge multi-scenario balance as a constraint, structural balance optimization is performed in the drift region of the device to obtain a three-dimensional charge-balanced gate structure, and the following processing is performed: charge balance constraints are predefined, wherein the charge balance constraints include static turn-off scenario charge balance constraints, dynamic switching scenario charge balance constraints, and high-temperature turn-on scenario charge balance constraints; a structural parameter space is pre-established; the charge balance constraints are used as iterative convergence judgment conditions, multi-objective genetic iteration is performed in the structural parameter space, and a target structural parameter combination is output; the target structural parameter combination is used to define the geometric topology and doping distribution of the three-dimensional charge-balanced gate structure.

[0012] In a possible implementation, the following processing is performed: the structural parameter space includes a width ratio scale of the P-type pillar and the N-type pillar, a doping concentration gradient scale, and a pillar depth-to-diameter ratio scale.

[0013] In a possible implementation, the following processing is performed: the multi-scale parameter adjustment mapping rule includes a temperature multi-scale mapping rule, a voltage change multi-scale mapping rule, and a current change multi-scale mapping rule.

[0014] The present application also provides a charge control system for an ultra-high voltage planar MOS, comprising: a reconfigurable depletion layer function construction module, for pre-constructing a reconfigurable depletion layer function in the device drift region of the ultra-high voltage planar gate MOSFET, wherein the gate drive circuit output end of the ultra-high voltage planar gate MOSFET is configured with a parallel multi-stage resistance path; a state perception module, for performing state perception of the reconfigurable depletion layer function based on a preset time window to obtain a real-time working state, wherein the real-time working state includes the real-time chip junction temperature, the drain-source voltage change rate, and the drain current change rate; a drive initialization module, for performing a state perception based on the real-time working state. A drive initialization module outputs an initial gate drive behavior; a drive behavior matching module is used to predict the state transfer of the real-time working state, output K predicted state features, match the drive behavior of the K predicted state features, and output K transfer drive behaviors; an updated drive behavior retrieval module is used to track the state of the reconfigurable depletion layer function, and retrieve an updated drive behavior from the K transfer drive behaviors based on the spatiotemporal correlation between the tracking result and the K predicted state features; a dynamic impedance switching module is used to use the updated drive behavior to control the gate drive circuit to perform dynamic impedance switching of the multi-stage resistance path.

[0015] The present application proposes a charge control method and system for an ultra-high voltage planar MOSFET. First, a reconfigurable depletion layer function is pre-built in the device drift region of an ultra-high voltage planar gate MOSFET. A multi-stage parallel resistance path is configured at the output end of the gate drive circuit of the ultra-high voltage planar gate MOSFET. The reconfigurable depletion layer function is then state-sensed based on a preset time window to obtain a real-time operating state, including the real-time chip junction temperature, the rate of change of the drain-source voltage, and the rate of change of the drain current. Drive initialization is then performed based on the real-time operating state, outputting an initial gate drive behavior. State transition prediction is then performed on the real-time operating state, outputting K predicted state features. Drive behavior matching is then performed on the K predicted state features, outputting K transition drive behaviors. The reconfigurable depletion layer function is then state-tracked. Based on the spatiotemporal correlation between the tracking results and the K predicted state features, an updated drive behavior is retrieved from the K transition drive behaviors. Finally, the updated drive behavior is used to control the gate drive circuit to perform dynamic impedance switching of the multi-stage resistance path. This achieves the technical effect of improving the accuracy and adaptability of charge control. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments of the present invention are briefly introduced below. Flowcharts are used in this application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in precise order. Instead, various steps may be processed in reverse order or simultaneously as needed. Furthermore, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0017] Figure 1 A flow chart of a charge control method for an ultra-high voltage planar MOS provided in an embodiment of the present application.

[0018] Figure 2 A schematic structural diagram of a charge control system for an ultra-high voltage planar MOS is provided in an embodiment of the present application.

[0019] Explanation of the reference numerals: reconfigurable depletion layer function building module 10 , state sensing module 20 , driving initialization module 30 , driving behavior matching module 40 , updated driving behavior calling module 50 , dynamic impedance switching module 60 . DETAILED DESCRIPTION

[0020] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below.

[0021] In order to make the purpose, technical solutions and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limiting this application. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0022] In the following description, reference is made to “some embodiments” which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. The terms “including” and “having” and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used herein are for the purpose of describing the embodiments of this application only.

[0023] The present application embodiment provides a charge control method for an ultra-high voltage planar MOS, such as Figure 1 As shown, the method includes:

[0024] Step S100 , pre-building a reconfigurable depletion layer function in a device drift region of an ultra-high voltage planar gate MOSFET, wherein an output end of a gate drive circuit of the ultra-high voltage planar gate MOSFET is configured with a parallel multi-stage resistance path.

[0025] Specifically, the reconfigurable depletion layer function refers to the ability to adjust the charge distribution and depletion region range within the MOSFET's drift region under different operating conditions through specific device structure design and doping processes, thereby optimizing device performance such as withstand voltage, on-resistance, and switching speed. A multi-level resistance path refers to multiple resistor branches of varying resistance values ​​connected in parallel within the gate drive circuit. By controlling their on and off states, the total impedance of the drive circuit can be dynamically adjusted, thereby varying the magnitude and rate of change of the gate drive current or voltage to accommodate the drive requirements under different MOSFET operating conditions.

[0026] Specifically, multiple epitaxial growth processes are used in the drift region to form a layered doping structure, allowing the charge distribution within the drift region to be adjusted under different operating conditions. Furthermore, a multi-stage parallel resistance path is configured at the output of the gate drive circuit of the ultra-high voltage planar gate MOSFET. This can be achieved by adding multiple resistors of different values ​​to the circuit design and controlling their on and off via electronic switches, thereby achieving a parallel combination of different resistance paths and changing the total impedance of the drive circuit.

[0027] For example, suppose the drift region of an ultra-high voltage planar gate MOSFET requires a three-layer reconfigurable depletion layer structure. First, a high concentration of N-type doping is performed at the bottom of the drift region to form the first layer; then, a low concentration of P-type doping is performed in the middle layer; and finally, a medium concentration of N-type doping is performed at the top. In actual operation, by controlling the gate voltage and source-drain voltage, the middle P-type layer can form a depletion region under different conditions, thereby changing the overall charge distribution and electric field distribution in the drift region. For example, when the gate voltage is increased, the depletion region in the middle P-type layer expands to both sides, increasing the effective resistance of the drift region and thus limiting the growth of drain current.

[0028] In one possible implementation, a reconfigurable depletion layer function is pre-established in the device drift region of an ultra-high voltage planar gate MOSFET. Step S100 further includes step S110, where structural balance optimization is performed in the device drift region, constrained by multi-scenario charge balance, to obtain a three-dimensional charge-balanced gate structure. Specifically, a three-dimensional physical model of the ultra-high voltage planar gate MOSFET is constructed using computer-aided design (CAD) software and semiconductor device simulation tools. The charge distribution under different operating scenarios, such as normal operation, high voltage stress, and high current surge, is analyzed. An optimization algorithm (such as a genetic algorithm or simulated annealing algorithm) is then used to optimize the drift region's geometric structural parameters (such as the drift region's length, width, and doping concentration profile) to achieve a balanced charge distribution under various scenarios, thereby obtaining a three-dimensional charge-balanced gate structure.

[0029] Step S120, based on the three-dimensional charge balance gate structure, construct alternatingly arranged P-type columns and N-type columns in the drift region of the device, so as to support the depletion layer with a dynamic reconstruction structure, thereby forming the reconfigurable depletion layer function. Specifically, in the actual manufacturing process, through semiconductor processes such as photolithography, etching and ion implantation, first, photolithography is performed in the drift region according to the pre-designed three-dimensional charge balance gate structure to form an alternating columnar pattern. Then, ion implantation of P-type impurities is performed on the P-type column region, and ion implantation of N-type impurities is performed on the N-type column region. After subsequent annealing and other process steps, the impurities are activated and a stable alternating P-type column and N-type column structure is formed. When the device is working, these alternating columns can dynamically adjust the formation and expansion of the depletion layer to achieve a reconfigurable depletion layer function.

[0030] The alternating arrangement of P-type and N-type columns in this implementation provides structural support for the dynamic reconstruction of the depletion layer. Under different operating conditions, such as different drain-source voltages, gate voltages, and operating temperatures, these columnar structures can cause the range and shape of the depletion layer to change accordingly, thereby achieving flexible control of charge distribution.

[0031] In one possible implementation, a structural balance optimization is performed in the drift region of the device, using charge balance in multiple scenarios as a constraint, to obtain a three-dimensional charge-balanced gate structure. Step S110 further includes step S111, predefining charge balance constraints. These constraints include charge balance constraints for a static off-state scenario, charge balance constraints for a dynamic switching scenario, and charge balance constraints for a high-temperature on-state scenario. Specifically, the static off-state charge balance constraint requires that the charge distribution within the drift region ensure a uniform electric field when the MOSFET is in the off state, avoiding localized excessive electric fields that could lead to increased leakage current or breakdown. For example, in the off state, the charge density change rate at each point in the drift region along the electric field direction must be within a certain range to ensure a flat electric field distribution. The dynamic switching charge balance constraint constrains the charge distribution to suppress parasitic oscillations and electromagnetic interference caused by dv / dt (voltage rate of change) during the MOSFET switching process, when voltage and current change rapidly. For example, the charge accumulation and release rates within the drift region must match during voltage rise and fall, ensuring a smooth electric field change and reducing overshoot and oscillation. Charge balance constraints in high-temperature turn-on scenarios involve constraining charge distribution to prevent a significant increase in on-resistance and device performance degradation due to the decrease in carrier mobility and changes in charge distribution when the MOSFET operates in a high-temperature environment. For example, the charge concentration in the drift region must be maintained at a certain level at high temperatures to ensure conductivity.

[0032] Step S112, pre-establishing a structural parameter space. Specifically, the pre-establishing structural parameter space is to determine the possible value ranges of all geometric and doping-related parameters that affect the three-dimensional charge balance gate structure of the drift region. Among them, the geometric parameters include the width, height, and spacing of the P-type column and the N-type column; the doping parameters include the doping concentration and doping depth of the P-type column and the N-type column. For example, the width range of the P-type column is set to 0.1μm-1μm, and the doping concentration range is set to 1e16cm -3 -1e17cm -3 , the width of the N-type column ranges from 0.2μm to 1.5μm, and the doping concentration ranges from 5e16cm -3 -8e16cm -3 Etc., thereby constructing a multidimensional structural parameter space.

[0033] In step S113, using the charge balance constraint as an iterative convergence criterion, a multi-objective genetic iteration is performed in the structural parameter space, outputting a target structural parameter combination. Specifically, multiple structural parameter combinations are randomly generated, each containing geometric dimensions and doping distribution parameters of the P-type and N-type pillars, as individuals in the initial population. For each individual, semiconductor device simulation software is used to calculate its charge distribution and electric field distribution under different operating scenarios, checking whether it meets the predefined charge balance constraints. The degree of proximity to the target performance (such as withstand voltage and on-resistance) is calculated as the fitness value. Based on the fitness value, outstanding individuals are selected to enter the next generation population, and crossover and mutation operations are performed to generate new individuals with structural parameter combinations. For example, individuals are selected using a roulette wheel selection method, with a certain probability of crossovering the geometric parameters and doping parameters of two individuals. With a small probability, certain parameters of the individual are randomly mutated, such as randomly changing the width or doping concentration of the P-type pillar within a certain range. Repeat the fitness evaluation, selection, crossover and mutation operations until the charge balance constraint is met and the fitness values ​​of the individuals in the population converge stably, and output the target structural parameter combination at this time.

[0034] Step S114 uses the target structural parameter combination to define the geometric topology and doping distribution of the three-dimensional charge-balanced gate structure. Specifically, based on the output parameters such as the geometric size, shape, and doping concentration of the P-type and N-type pillars, the structure is manufactured and processed in the drift region of an actual ultra-high voltage planar gate MOSFET device to form a specific three-dimensional charge-balanced gate structure, enabling the device to have a reconfigurable depletion layer function.

[0035] This implementation method predefines charge balance constraints under multiple typical working scenarios and performs multi-objective genetic iterative optimization, so that the three-dimensional charge balance gate structure constructed in the drift region can achieve uniform charge distribution in various actual working conditions.

[0036] In one possible implementation, step S112 further includes: the structural parameter space includes the width ratio scale of the P-type column and the N-type column, the doping concentration gradient scale and the column depth-to-diameter ratio scale. Specifically, the width ratio scale refers to the proportional relationship between the width of the P-type column and the width of the N-type column. For example, if the width of the P-type column is set to 0.5μm and the width of the N-type column is 1μm, the width ratio scale is 0.5:1. This ratio will affect the uniformity of the charge distribution and the formation width of the depletion layer. During the optimization process, it is necessary to determine a suitable width ratio so that the charge can be balanced in different working scenarios. The doping concentration gradient scale refers to the degree of change in the doping concentration of the P-type column and the N-type column. For example, from the surface to the inside of the column, the doping concentration decreases or increases according to a certain gradient. For example, the surface doping concentration of the P-type column is 5e16cm -3 , the bottom is 2e16cm -3 , forming a certain concentration gradient. This gradient doping can affect the vertical distribution of charge and the extension depth of the depletion layer. Determining a reasonable doping concentration gradient scale during multi-target genetic iteration helps achieve dynamic charge balance. The column depth-to-diameter ratio refers to the ratio of the column depth to its diameter (or width). For example, if the column depth is 2μm and the diameter (or width) is 1μm, the column depth-to-diameter ratio is 2:1. The column depth-to-diameter ratio affects the vertical charge storage capacity and the lateral extension of the depletion layer. During the optimization process, it is necessary to find the optimal column depth-to-diameter ratio to meet the charge balance requirements in different scenarios.

[0037] During multi-objective genetic iterations, the algorithm searches within the multidimensional space defined by these three scaling parameters. Each individual represents a specific combination of width ratio, doping concentration gradient, and pillar depth-to-diameter ratio parameters. Simulations evaluate each individual to calculate its charge balance under static off-state, dynamic switching, and high-temperature on-state scenarios, as well as corresponding device performance metrics (such as withstand voltage, on-resistance, and switching speed). High-performing individuals are selected based on the fitness function, and new individuals are continuously generated through genetic operations (selection, crossover, and mutation), gradually approaching the optimal structural parameter combination that satisfies the charge balance constraints. The resulting target structural parameter combination precisely defines the geometry and doping distribution details of the P-type and N-type pillars in the three-dimensional charge-balanced gate structure. For example, these parameters, such as their specific widths, doping concentration gradients, and pillar depth-to-diameter ratios, are determined, thereby constructing a gate structure that achieves charge balance under various operating scenarios.

[0038] This implementation method concretizes the structural parameter space into width ratio scale, doping concentration gradient scale and column depth-to-diameter ratio scale, making it easier to control and adjust these parameters during the manufacturing process, ensuring that the manufactured device structure meets the design requirements.

[0039] Step S200 , performing state sensing of the reconfigurable depletion layer function based on a preset time window to obtain a real-time working state, wherein the real-time working state includes real-time chip junction temperature, drain-source voltage change rate, and drain current change rate.

[0040] Specifically, the real-time operating status can reflect the temperature, voltage, and current changes of the MOSFET during actual operation, providing a basis for adjusting the driving behavior. The status of the reconfigurable depletion layer function is sensed through various sensors installed inside or around the chip. The real-time chip junction temperature can be measured using an integrated temperature sensor, while the rate of change of the drain-source voltage and drain current can be monitored in real time using voltage and current sensors. These sensors convert the measured physical quantities into electrical signals, which are then sampled by an analog-to-digital converter (ADC) and transmitted to the chip's internal control unit for processing.

[0041] For example, within an ultra-high voltage planar gate MOSFET chip, a temperature sensor is integrated near the active area to measure real-time chip junction temperature. A voltage sensor and a current sensor are installed on the drain and source leads, respectively, to measure the drain-source voltage and drain current. These sensors sample data every 10μs, convert it into a digital signal via an ADC, and transmit it to the chip's internal control unit. For example, when the chip is operating normally, the temperature sensor measures a junction temperature of approximately 80°C, with a drain-source voltage change rate of 10V / μs and a drain current change rate of 5A / μs. When the chip is overloaded, the junction temperature rises rapidly to 120°C, and the rates of change of the drain-source voltage and drain current also increase significantly.

[0042] Step S300 , performing drive initialization according to the real-time working status, and outputting an initial gate drive behavior.

[0043] Specifically, the control unit inside the chip compares the received real-time chip junction temperature, drain-source voltage change rate, drain current change rate and other information with the pre-stored threshold or model, determines the initial gate drive signal according to the preset rules, such as the amplitude, rise time and fall time of the drive voltage, and outputs the corresponding initial gate drive behavior through the drive circuit.

[0044] In one possible implementation, the drive is initialized based on the real-time operating state and the initial gate drive behavior is output. Step S300 further includes step S310, which uses the real-time operating state to perform a first-order linear mapping based on a predefined multi-scale parameter adjustment mapping rule to output basic drive behavior parameters. Specifically, based on information such as the real-time chip junction temperature, the rate of change of the drain-source voltage, and the rate of change of the drain current, a linear conversion is performed according to a pre-set mapping rule to obtain preliminary basic drive behavior parameters, such as a basic drive voltage and a basic drive current. Through the linear mapping relationship, the real-time operating state is quickly converted into basic drive parameters, providing a basis for fine-tuning.

[0045] Step S320: After interactively obtaining multiple sample multi-dimensional operating condition combinations and multiple sample drive modes, a matching relationship between these multiple sample multi-dimensional operating condition combinations and the multiple sample drive modes is constructed to obtain a drive mode information library. Specifically, through a large amount of experimental or simulation data, different operating condition combinations (such as different combinations of chip junction temperature, drain-source voltage change rate, and drain current change rate) and corresponding optimal drive mode samples are collected. Then, using methods such as data mining and machine learning, a matching relationship between the operating condition combinations and drive modes is constructed to form a drive mode information library. The drive mode information library can quickly query the corresponding drive mode based on the input multi-dimensional operating condition combination.

[0046] Step S330 loads the real-time operating status into the drive mode information library, performs matching of operating condition combinations, and locates the enhanced drive mode. Specifically, the real-time monitored operating status is input into the drive mode information library as a query condition. A matching algorithm is then used to find the closest operating condition combination, thereby locating the corresponding enhanced drive mode. This enhanced drive mode is derived from a large amount of sample data and actual operating condition experience. Compared to basic driving behavior parameters, it is more adaptable to complex real-world situations and provides better driving performance.

[0047] Step S340 combines the enhanced drive mode and the basic drive behavior parameters to output the initial gate drive behavior. Specifically, the located enhanced drive mode is integrated with the previously obtained basic drive behavior parameters, combining the advantages of both to ultimately output the initial gate drive behavior, which not only meets the basic drive requirements but also has stronger adaptability and optimized performance.

[0048] This implementation method combines multi-dimensional information of real-time working status with rich sample data in the drive mode information library, enabling the initial gate drive behavior of the output to better adapt to the actual working conditions.

[0049] In a possible implementation, step S310 further includes step S311, and the multi-scale parameter adjustment mapping rules include temperature multi-scale mapping rules, voltage change multi-scale mapping rules, and current change multi-scale mapping rules. Specifically, since the chip has performance differences at different temperatures, a mapping from the real-time chip junction temperature to the basic driving behavior parameters is constructed. At low temperatures, the carrier mobility is high, and the driving parameters focus on fast switching; at high temperatures, the performance decreases, and the driving parameters focus on stable conduction and heat resistance balance. The mapping rules comprehensively consider the various effects of temperature on material properties, carrier concentration, and device electrical properties. After a large number of experiments and simulations, a multi-interval and multi-scale mapping model including normal temperature, high temperature, and low temperature is constructed.

[0050] A corresponding mapping relationship is established for the drain-source voltage change rate. When the drain-source voltage change rate is small, the drive parameters are adjusted to maintain stable device conduction and avoid unnecessary switching. When the drain-source voltage change rate is large, such as sudden changes, the drive parameters focus on fast response, suppressing overvoltage and ensuring reliable device shutdown. At the same time, to prevent electromagnetic interference and parasitic oscillation caused by excessive voltage change rates, a comprehensive analysis of the device's insulation withstand voltage performance and switching characteristics is conducted to develop a multi-scale mapping strategy.

[0051] The corresponding drive parameter mapping is set based on the drain current rate of change. When the drain current rate of change is low, the drive parameters focus on reducing on-resistance and improving the device's current-carrying efficiency. When the drain current rate of change is high, the drive parameters must balance the current rise speed with device safety, meeting the requirements of sudden load changes while avoiding device overheating or damage due to current overshoot. The impact of the current rate of change on device heating, electric field distribution, and reliability is fully analyzed to construct multi-scale mapping rules.

[0052] When performing first-order linear mapping, the three mapping rules described above are applied separately to convert the real-time chip junction temperature, drain-source voltage change rate, and drain current change rate into their respective corresponding basic drive behavior parameters. For example, if the real-time chip junction temperature is 80°C, the corresponding basic drive voltage is 4.5V according to the temperature multi-scale mapping rule; the drain-source voltage change rate is 12V / μs, and the corresponding basic drive current is 3A according to the voltage change multi-scale mapping rule; the drain current change rate is 6A / μs, and the corresponding basic drive pulse width is 1.5μs according to the current change multi-scale mapping rule. Finally, these basic drive behavior parameters are integrated to form a preliminary set of basic drive behavior parameters.

[0053] This implementation method accurately maps real-time operating conditions into basic drive behavior parameters by subdividing multi-scale parameter mapping rules. Compared to a single mapping rule, this subdivided mapping method can more accurately match actual operating conditions. For example, under the complex combination of low temperature, low voltage change rate, and high current change rate, the various mapping rules can work together to generate adaptive drive parameters, ensuring reliable MOSFET conduction and shutdown, improving system stability and operating efficiency.

[0054] Step S400 , performing state transition prediction on the real-time working state, outputting K predicted state features, performing driving behavior matching on the K predicted state features, and outputting K transfer driving behaviors.

[0055] Specifically, state transition prediction involves estimating the future operating state of a MOSFET based on historical operating state data and an established prediction model. The prediction model then outputs K possible predicted state characteristics, enabling pre-planning and matching of corresponding drive behaviors to improve system stability and reliability. Machine learning algorithms or physical models can be used to establish the prediction model. For example, machine learning involves collecting a large amount of historical operating state data, including chip junction temperature, drain-source voltage change rate, and drain current change rate, along with corresponding state transitions, to train a neural network or other model. When a new real-time operating state is input, the trained model outputs K predicted state characteristics. Based on each predicted state characteristic, the algorithm then matches the corresponding K transition drive behaviors by looking up a table or re-invoking a pre-set algorithm. These transition drive behaviors are gate drive behaviors corresponding to the predicted state characteristics, including drive voltage amplitude, rise time, fall time, and multi-stage resistance path combinations. When the predicted state occurs, the driver circuit characteristics are adjusted to ensure a smooth transition of the MOSFET's operating state to the target state, avoiding abnormal conditions such as overvoltage and overcurrent.

[0056] In one possible implementation, after state transition prediction is performed on the real-time operating state and K predicted state features are output, driving behavior matching is performed on the K predicted state features and K transition driving behaviors are output. Step S400 further includes step S410 of locally retrieving historical operating state logs. Specifically, relevant data is extracted from historical operating state records stored in a local device (such as a controller or computer). These historical operating state logs contain various information about the ultra-high voltage planar MOS during past operations, such as chip junction temperature, drain-source voltage change rate, drain current change rate, and corresponding driving behaviors.

[0057] Step S420: Aggregate the historical working status logs under typical working conditions to obtain multi-scale state intervals. Specifically, by analyzing a large amount of historical data, similar working conditions are aggregated together to form several typical working conditions. For example, the working conditions with a chip junction temperature of 50°C-70°C, a drain-source voltage change rate of 5V / μs-10V / μs, and a drain current change rate of 2A / μs-4A / μs are aggregated into a typical working condition interval. These multi-scale state intervals include the operating conditions of the device under different working conditions and are used to provide a basis for state transition prediction.

[0058] In step S430, based on the multi-scale state intervals, time-series-correlated state transition data is extracted from the historical operating state logs to construct a state transition prediction matrix. Specifically, based on typical operating condition intervals, transition relationships between adjacent states are identified in the historical data, and the frequency or probability of these transitions is recorded. For example, between typical operating condition intervals A and B, the number of transitions from A to B and the corresponding time intervals are counted. This data is then presented in matrix form to generate a state transition prediction matrix, where the elements in the matrix represent, for example, the transition probability or rate from one state interval to another.

[0059] In step S440, based on the multi-scale state interval's coverage of the real-time operating state, transition prediction is performed within the state transition prediction matrix, outputting K predicted state features. Specifically, the real-time operating state is compared with the multi-scale state interval to determine the interval range to which it belongs. Then, based on the transition relationship between this interval and other intervals in the state transition prediction matrix, K state features that may subsequently appear are predicted. For example, if the real-time operating state belongs to interval A, the state transition prediction matrix predicts K state features that may transition from interval A to intervals B, C, or D, and outputs the specific parameters of these predicted state features (such as chip junction temperature, drain-source voltage change rate, and drain current change rate).

[0060] Step S450: Using the K predicted state features, a first-order linear mapping is performed using a multi-scale parameter mapping rule to output the K transfer drive behaviors. Specifically, for each predicted state feature, a first-order linear mapping is performed using predefined multi-scale parameter mapping rules (including temperature multi-scale mapping rules, voltage change multi-scale mapping rules, and current change multi-scale mapping rules) to convert it into corresponding transfer drive behavior parameters. For example, for predicted state feature 1, the corresponding drive voltage, drive current, and drive pulse width parameters are obtained based on its chip junction temperature, drain-source voltage change rate, and drain current change rate using the temperature, voltage change, and current change multi-scale mapping rules, respectively. These parameters are combined into a transfer drive behavior. This process is repeated to obtain K transfer drive behaviors.

[0061] Step S500 : tracking the state of the reconfigurable depletion layer function, and retrieving an updated driving behavior from the K transfer driving behaviors according to the spatiotemporal correlation between the tracking result and the K predicted state features.

[0062] Specifically, multiple monitoring points are set up within the drift region, using devices such as capacitive sensors or varistors to sense the state changes of the reconfigurable depletion layer function in real time. Based on the spatiotemporal correlation between the tracking results and the K predicted state features, that is, comparing the temporal and spatial similarity between the tracked state and the predicted state, an algorithm (such as the least squares method or correlation analysis algorithm) is used to determine the best matching predicted state feature, thereby retrieving the corresponding update drive behavior from the K transfer drive behaviors.

[0063] In one possible implementation, the reconfigurable depletion layer function is state-tracked, and based on the spatiotemporal correlation between the tracking results and the K predicted state features, an updated driving behavior is retrieved from the K transfer driving behaviors. Step S500 further includes step S510, where the state of the reconfigurable depletion layer function is tracked to obtain real-time tracking features. Specifically, various high-precision sensors installed within or around the chip, such as temperature sensors, voltage sensors, and current sensors, monitor key parameters such as chip junction temperature, drain-source voltage change rate, and drain current change rate in real time. The sensors sample at a high frequency to ensure that any subtle changes are captured promptly. The measured physical quantities are converted into electrical signals, digitized by an analog-to-digital converter (ADC), and transmitted to a control unit for analysis and processing.

[0064] Step S520, based on the spatiotemporal correlation measurement rule, calculate the K spatiotemporal correlation matching degrees of the real-time tracking feature and the K predicted state features. Specifically, the spatiotemporal correlation measurement rule is an algorithm for evaluating the degree of similarity between the real-time tracking feature and the predicted state feature in the time and space dimensions. Specifically, the spatiotemporal correlation measurement rule will comprehensively consider the changing trends of the chip junction temperature, the drain-source voltage change rate and the drain current change rate in the time series and their correlation in spatial distribution. For example, if the real-time tracking feature shows that the chip junction temperature is gradually rising, and the drain-source voltage change rate and the drain current change rate are also increasing, this may match the trend corresponding to a certain state in the predicted state feature. By calculating this matching degree, the spatiotemporal correlation matching degree between each predicted state feature and the real-time tracking feature is obtained.

[0065] Step S530: After sorting the K transfer driving behaviors in descending order based on the K spatiotemporal correlation matching degrees, the highest-ranked transfer driving behavior is retrieved as the updated drive behavior. Specifically, after obtaining the K spatiotemporal correlation matching degrees, the corresponding K transfer driving behaviors are sorted according to their magnitudes to identify the transfer driving behavior corresponding to the predicted state characteristics that most closely matches the current actual state. The control unit selects the highest-ranked transfer driving behavior as the updated drive behavior, which is used to adjust the parameters of the gate drive circuit to adapt to the current actual state of the reconfigurable depletion layer function, ensuring stable operation and optimized performance of the device.

[0066] This implementation method can accurately find the transfer drive behavior that best matches the current actual state through real-time state tracking of the reconfigurable depletion layer function and calculation of the spatiotemporal correlation matching degree, thereby achieving more precise drive behavior adjustment and ensuring the optimal performance of the ultra-high voltage planar MOS under different operating conditions.

[0067] Step S600 : Using the update driving behavior, controlling the gate driving circuit to perform dynamic impedance switching of the multi-stage resistance path.

[0068] Specifically, electronic switches (such as MOSFETs or IGBTs) in the driver circuit switch the on / off states of resistor paths of different resistance values ​​based on control signals from the updated drive behavior, thereby changing the total impedance of the gate drive circuit and dynamically adjusting the gate drive current or voltage, thereby regulating the charge distribution and operating state of the MOSFET. In one possible implementation, the updated drive behavior is used to control the gate drive circuit to perform dynamic impedance switching of the multi-stage resistor path. Step S600 further includes step S610, where the updated drive behavior is analyzed to obtain a target impedance value, a switching mode, and a switching time window. Specifically, the updated drive behavior contains specific information required to achieve optimal device operation. The target impedance value refers to the impedance level that the gate drive circuit should reach after dynamic impedance switching; the switching mode includes various methods, such as ramp switching and immediate switching; and the switching time window specifies the time range within which the impedance switching operation is completed. For example, the analysis results indicate a target impedance value of 200Ω, a ramp switching mode, and a switching time window of 10μs after receiving the updated drive behavior.

[0069] Step S620 matches the target control switch action instruction set to a pre-built switch action mapping rule library based on the target impedance value. Specifically, the switch action mapping rule library pre-stores control switch action instruction sets corresponding to different impedance values. For example, if the target impedance value is 200Ω, the switch action mapping rule library reveals that to achieve this impedance value, a specific action instruction combination is required, such as placing switch S1 in the closed state and switch S2 in the open state. These action instruction sets are used to guide the control switch to perform the corresponding operation.

[0070] Step S630: When the switching mode is ramp switching, a real-time impedance value is acquired through an impedance feedback loop, and a real-time impedance deviation between the real-time impedance value and the target impedance value is calculated. Specifically, the impedance feedback loop can monitor the actual impedance value of the gate drive circuit in real time and transmit it to the control unit. The control unit calculates the impedance deviation based on the target impedance value and the real-time impedance value. For example, if the target impedance value is 200Ω and the real-time monitored impedance value is 180Ω, the impedance deviation is 20Ω.

[0071] In step S640, an impedance switching strategy is matched in a multi-stage transition strategy library based on the real-time impedance deviation. Specifically, the multi-stage transition strategy library stores impedance switching strategies corresponding to different impedance deviation ranges. For example, when the impedance deviation is between 10Ω and 30Ω, a two-stage switching strategy is adopted, which first quickly switches a portion of the resistance path, followed by fine-tuning, to gradually approach the target impedance value.

[0072] Step S650, after loading the action instruction set to execute the state switching of the target control switch, within the switching time window, the dynamic impedance switching of the multi-stage resistance path is executed according to the impedance switching strategy. Specifically, the control unit first loads the action instruction set obtained by the previous matching, performs the state switching operation on the target control switch, and starts the impedance switching process. Within the entire switching time window, according to the impedance switching strategy, the combination of resistance paths is gradually adjusted in multiple stages until the target impedance value is achieved. For example, within the switching time window of 10μs, first quickly switch part of the resistance path in the first 3μs to increase the impedance from the initial value of 100Ω to 160Ω, and then continue to adjust the resistance path according to the fine adjustment strategy in the next 7μs so that the impedance is finally stabilized at the target value of 200Ω.

[0073] This implementation parses and updates the driver behavior to obtain precise target impedance values ​​and other information, and matches the corresponding action instruction set based on the switch action mapping rule library, enabling impedance switching to accurately achieve the target value. In ramp switching mode, an impedance feedback loop is used to monitor impedance deviation in real time, and dynamic impedance switching is performed in conjunction with a multi-level transition strategy library. This achieves a smooth impedance transition, avoiding current surges and voltage overshoots that may be caused by sudden impedance changes. This effectively improves the operational stability of devices and systems, and reduces the risk of electromagnetic interference and device damage caused by sudden impedance changes.

[0074] The embodiment of the present application adopts a method of pre-building a reconfigurable depletion layer function in the drift region of the device, and realizing dynamic control by configuring a gate drive circuit of a multi-level resistance path. With a preset time window as a period, the working conditions such as the chip junction temperature, drain-source voltage and current change rate are monitored in real time. The gate drive behavior is initialized based on these parameters, and K possible state transition paths are predicted at the same time, and the corresponding drive strategies are generated by matching. By continuously tracking the depletion layer state and combining the spatiotemporal correlation between the prediction results and the actual state, the drive parameters are dynamically adjusted. The impedance switching of the multi-level resistance path is used to perform precise charge control and other technical means to solve the technical problems of poor control accuracy and adaptability of the charge control of the existing ultra-high voltage planar MOS, and achieve the technical effect of improving the accuracy and adaptability of the charge control.

[0075] In the above, refer to Figure 1 A charge control method for an ultra-high voltage planar MOS according to an embodiment of the present invention is described in detail. Figure 2 A charge control system for an ultra-high voltage planar MOS according to an embodiment of the present invention is described.

[0076] According to an embodiment of the present invention, a charge control system for an ultra-high voltage planar MOS is designed to address the technical issues of poor control accuracy and adaptability in existing ultra-high voltage planar MOS charge control, thereby achieving the technical effect of improving the accuracy and adaptability of charge control. The charge control system for an ultra-high voltage planar MOS includes: a reconfigurable depletion layer function construction module 10, a state sensing module 20, a drive initialization module 30, a drive behavior matching module 40, an updated drive behavior retrieval module 50, and a dynamic impedance switching module 60.

[0077] The reconfigurable depletion layer function construction module 10 is used to pre-construct a reconfigurable depletion layer function in the device drift region of the ultra-high voltage planar gate MOSFET, wherein the gate drive circuit output end of the ultra-high voltage planar gate MOSFET is configured with a parallel multi-stage resistance path; the state perception module 20 is used to perform state perception of the reconfigurable depletion layer function based on a preset time window to obtain a real-time working state, wherein the real-time working state includes the real-time chip junction temperature, the drain-source voltage change rate, and the drain current change rate; the drive initialization module 30 is used to perform drive initialization according to the real-time working state and output an initial gate drive behavior; a driving behavior matching module 40, used to perform state transfer prediction on the real-time working state, output K predicted state features, perform driving behavior matching on the K predicted state features, and output K transfer driving behaviors; an updated driving behavior calling module 50, used to perform state tracking on the reconfigurable depletion layer function, and call an updated driving behavior from the K transfer driving behaviors based on the spatiotemporal correlation between the tracking result and the K predicted state features; a dynamic impedance switching module 60, used to adopt the updated driving behavior to control the gate drive circuit to perform dynamic impedance switching of the multi-stage resistance path.

[0078] The specific configuration of the drive initialization module 30 is described in detail as follows: As described above, the drive initialization is performed according to the real-time working state, and the initial gate drive behavior is output. The drive initialization module 30 may further include: a first-order linear mapping unit for adopting the real-time working state, performing first-order linear mapping according to a predefined multi-scale parameter adjustment mapping rule, and outputting basic drive behavior parameters; a matching relationship construction unit for interactively obtaining multiple sample multi-dimensional working condition combinations and multiple sample driving modes, and then constructing a matching relationship between the multiple sample multi-dimensional working condition combinations and the multiple sample driving modes to obtain a driving mode information library; a working condition combination attribution matching unit for loading the real-time working state into the driving mode information library, performing working condition combination attribution matching, and locating the enhanced driving mode; an initial gate driving behavior output unit for combining the enhanced driving mode and the basic driving behavior parameters to output the initial gate driving behavior.

[0079] The specific configuration of the driving behavior matching module 40 is described in detail as follows: As described above, after state transition prediction is performed on the real-time working state and K predicted state features are output, driving behavior matching is performed on the K predicted state features to output K transfer driving behaviors. The driving behavior matching module 40 may further include: a historical working state log calling unit for locally calling the historical working state log; a typical working condition aggregation unit for performing typical working condition aggregation on the historical working state log to obtain a multi-scale state interval; a time-series associated state transition data extraction unit for extracting time-series associated state transition data from the historical working state log based on the multi-scale state interval to construct a state transition prediction matrix; a transfer prediction unit for performing transfer prediction in the state transfer prediction matrix based on the coverage relationship of the multi-scale state interval on the real-time working state, and outputting K predicted state features; a first-order linear mapping unit for using the K predicted state features to perform first-order linear mapping of the multi-scale parameter adjustment mapping rule to output the K transfer driving behaviors.

[0080] The specific configuration of the update driving behavior calling module 50 is described in detail as follows: As described above, the state of the reconfigurable depletion layer function is tracked, and based on the spatiotemporal correlation between the tracking result and the K predicted state features, the update driving behavior is called from the K transfer driving behaviors. The update driving behavior calling module 50 may further include: a state tracking unit for tracking the state of the reconfigurable depletion layer function to obtain real-time tracking features; a spatiotemporal correlation matching degree calculation unit for calculating K spatiotemporal correlation matching degrees of the real-time tracking features and the K predicted state features based on spatiotemporal correlation measurement rules; a descending order arrangement unit for arranging the K transfer driving behaviors in descending order according to the K spatiotemporal correlation matching degrees, and then calling the transfer driving behavior with the highest ranking as the update driving behavior.

[0081] The detailed description of the specific configuration of the dynamic impedance switching module 60 is explained as follows: As described above, the updated driving behavior is adopted to control the gate drive circuit to perform dynamic impedance switching of the multi-stage resistance path. The dynamic impedance switching module 60 may further include: an updated driving behavior parsing unit for obtaining a target impedance value, a switching mode and a switching time window by parsing the updated driving behavior; an action instruction set matching unit for matching an action instruction set of a target control switch in a pre-built switch action mapping rule library according to the target impedance value; a real-time impedance deviation calculation unit for obtaining a real-time impedance value through an impedance feedback loop when the switching mode is ramp switching, and calculating a real-time impedance deviation between the real-time impedance value and the target impedance value; an impedance switching strategy matching unit for matching an impedance switching strategy in a multi-stage transition strategy library according to the real-time impedance deviation; and a dynamic impedance switching unit for performing dynamic impedance switching of the multi-stage resistance path according to the impedance switching strategy within the switching time window after loading the action instruction set to execute the state switching of the target control switch.

[0082] The specific configuration of the reconfigurable depletion layer function construction module 10 is described in detail as follows: As described above, a reconfigurable depletion layer function is pre-constructed in the device drift region of the ultra-high voltage planar gate MOSFET. The reconfigurable depletion layer function construction module 10 may further include: a structural balance optimization unit for performing structural balance optimization in the device drift region with charge multi-scenario balance as a constraint to obtain a three-dimensional charge balance gate structure; a reconfigurable depletion layer function forming unit for constructing alternatingly arranged P-type columns and N-type columns in the device drift region based on the three-dimensional charge balance gate structure to dynamically reconstruct the structure to support the depletion layer and form the reconfigurable depletion layer function.

[0083] In which, with the charge multi-scenario balance as a constraint, structural balance optimization is performed in the drift region of the device to obtain a three-dimensional charge balance gate structure, and the structural balance optimization unit may further include: a charge balance constraint condition predefinition subunit for predefining charge balance constraints, wherein the charge balance constraints include static shutdown scenario charge balance constraints, dynamic switching scenario charge balance constraints and high-temperature conduction scenario charge balance constraints; a structural parameter space pre-establishment subunit for pre-establishing structural parameter space; a multi-objective genetic iteration subunit for using the charge balance constraints as iterative convergence judgment conditions, performing multi-objective genetic iteration in the structural parameter space, and outputting a target structural parameter combination; a three-dimensional charge balance gate structure definition subunit for using the target structural parameter combination to define the geometric topology and doping distribution of the three-dimensional charge balance gate structure.

[0084] The structural parameter space pre-establishment subunit may further include: the structural parameter space includes a width ratio scale of the P-type column and the N-type column, a doping concentration gradient scale, and a column depth-to-diameter ratio scale.

[0085] Among them, the first-order linear mapping unit may further include: the multi-scale parameter adjustment mapping rule includes a temperature multi-scale mapping rule, a voltage change multi-scale mapping rule and a current change multi-scale mapping rule.

[0086] An ultra-high voltage planar MOS charge control system provided by an embodiment of the present invention can execute an ultra-high voltage planar MOS charge control method provided by any embodiment of the present invention, and has functional modules and beneficial effects corresponding to the execution method.

[0087] Although the present application makes various references to certain modules in the system according to the embodiments of the present application, any number of different modules may be used and run on the user terminal and / or server, and the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present invention.

[0088] The above specific embodiments do not constitute a limitation to the scope of protection of this application. It should be understood by those skilled in the art that various modifications, combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of this application should be included in the scope of protection of this application. In some cases, the actions or steps recorded in this application can be performed in an order different from that in the embodiments and can still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A charge control method for ultra-high voltage planar MOS, characterized in that: The method comprises: Pre-building a reconfigurable depletion layer function in the device drift region of an ultra-high voltage planar gate MOSFET, wherein the output end of the gate drive circuit of the ultra-high voltage planar gate MOSFET is configured with a parallel multi-stage resistance path; Performing state sensing of the reconfigurable depletion layer function based on a preset time window to obtain a real-time operating state, wherein the real-time operating state includes a real-time chip junction temperature, a drain-source voltage change rate, and a drain current change rate; Performing drive initialization according to the real-time working state and outputting initial gate drive behavior; Performing state transition prediction on the real-time working state, outputting K predicted state features, performing driving behavior matching on the K predicted state features, and outputting K transfer driving behaviors; Tracking the state of the reconfigurable depletion layer function, and retrieving an updated driving behavior from the K transfer driving behaviors based on a spatiotemporal correlation between the tracking result and the K predicted state features; Using the update driving behavior, controlling the gate drive circuit to perform dynamic impedance switching of the multi-stage resistance path; Controlling the gate drive circuit to perform dynamic impedance switching of the multi-stage resistance path includes: By analyzing the update driving behavior, a target impedance value, a switching mode and a switching time window are obtained; Matching an action instruction set of a target control switch in a pre-built switch action mapping rule library according to the target impedance value; When the switching mode is ramp switching, a real-time impedance value is acquired through an impedance feedback loop, and a real-time impedance deviation between the real-time impedance value and a target impedance value is calculated; matching an impedance switching strategy in a multi-stage transition strategy library according to the real-time impedance deviation; After the action instruction set is loaded to execute the state switching of the target control switch, the dynamic impedance switching of the multi-stage resistance path is executed according to the impedance switching strategy within the switching time window.

2. The charge control method for ultra-high voltage planar MOS according to claim 1, characterized in that: Performing drive initialization according to the real-time working state and outputting initial gate drive behavior, the method includes: Using the real-time working state, a first-order linear mapping is performed in a predefined multi-scale parameter adjustment mapping rule to output basic driving behavior parameters; After interactively obtaining a plurality of sample multi-dimensional working condition combinations and a plurality of sample driving modes, a matching relationship between the plurality of sample multi-dimensional working condition combinations and the plurality of sample driving modes is constructed to obtain a driving mode information library; Loading the real-time working status into the driving mode information library, performing working condition combination matching, and locating the enhanced driving mode; The enhanced driving mode and basic driving behavior parameters are combined to output the initial gate driving behavior.

3. The charge control method for ultra-high voltage planar MOS according to claim 2, characterized in that: After performing state transition prediction on the real-time working state and outputting K predicted state features, performing driving behavior matching on the K predicted state features and outputting K transfer driving behaviors, the method includes: Local call history work status log; Aggregating typical working conditions on the historical working status log to obtain multi-scale state intervals; Extracting time-series associated state transition data from the historical working state log according to the multi-scale state intervals and constructing a state transition prediction matrix; According to the coverage relationship of the multi-scale state interval to the real-time working state, transfer prediction is performed in the state transfer prediction matrix to output K predicted state features; The K predicted state features are used to perform first-order linear mapping of a multi-scale parameter adjustment mapping rule, and the K transfer driving behaviors are output.

4. The charge control method for ultra-high voltage planar MOS according to claim 1, wherein: Tracking the state of the reconfigurable depletion layer function and, based on the spatiotemporal correlation between the tracking result and the K predicted state features, retrieving an updated driving behavior from the K transfer driving behaviors, the method comprising: Performing state tracking on the reconfigurable depletion layer function to obtain a real-time tracking feature; Based on the spatiotemporal correlation measurement rule, calculating K spatiotemporal correlation matching degrees of the real-time tracking feature and the K predicted state features; After arranging the K transfer driving behaviors in descending order according to the K spatiotemporal correlation matching degrees, the transfer driving behavior with the highest ranking is retrieved as the update driving behavior.

5. The charge control method for ultra-high voltage planar MOS according to claim 1, wherein: Pre-building a reconfigurable depletion layer function in a device drift region of an ultra-high voltage planar gate MOSFET, the method comprising: Taking charge multi-scenario balance as a constraint, structural balance optimization is performed in the drift region of the device to obtain a three-dimensional charge-balanced gate structure; According to the three-dimensional charge balance gate structure, alternating P-type columns and N-type columns are constructed in the drift region of the device to support the depletion layer with a dynamic reconfiguration structure, thereby forming the reconfigurable depletion layer function.

6. The charge control method for ultra-high voltage planar MOS according to claim 5, characterized in that: Taking charge multi-scenario balance as a constraint, structural balance optimization is performed in the drift region of the device to obtain a three-dimensional charge balance gate structure, the method comprising: Predefined charge balance constraints, wherein the charge balance constraints include static shutdown scenario charge balance constraints, dynamic switching scenario charge balance constraints, and high temperature conduction scenario charge balance constraints; Pre-established structural parameter space; Using the charge balance constraint as an iterative convergence judgment condition, performing multi-objective genetic iteration in the structural parameter space, and outputting a target structural parameter combination; The target structural parameter combination is used to define the geometric topology and doping distribution of the three-dimensional charge balance gate structure.

7. The charge control method for ultra-high voltage planar MOS according to claim 6, characterized in that: The structural parameter space includes the width ratio scale of the P-type column and the N-type column, the doping concentration gradient scale and the column depth-to-diameter ratio scale.

8. The charge control method for ultra-high voltage planar MOS according to claim 2, wherein: The multi-scale parameter adjustment mapping rule includes a temperature multi-scale mapping rule, a voltage change multi-scale mapping rule and a current change multi-scale mapping rule.

9. A charge control system for ultra-high voltage planar MOS, characterized in that: The system is used to implement the charge control method of an ultra-high voltage planar MOS according to any one of claims 1 to 8, and the system includes: A reconfigurable depletion layer function building module is used to pre-build a reconfigurable depletion layer function in the device drift region of an ultra-high voltage planar gate MOSFET, wherein the output end of the gate drive circuit of the ultra-high voltage planar gate MOSFET is configured with a parallel multi-stage resistance path; a state sensing module, configured to sense the state of the reconfigurable depletion layer function based on a preset time window to obtain a real-time operating state, wherein the real-time operating state includes a real-time chip junction temperature, a drain-source voltage change rate, and a drain current change rate; A drive initialization module, configured to perform drive initialization according to the real-time working state and output an initial gate drive behavior; A driving behavior matching module is used to perform state transition prediction on the real-time working state, output K predicted state features, perform driving behavior matching on the K predicted state features, and output K transfer driving behaviors; An update driving behavior retrieval module is configured to track the state of the reconfigurable depletion layer function and retrieve an update driving behavior from the K transfer driving behaviors based on a spatiotemporal correlation between the tracking result and the K predicted state features; A dynamic impedance switching module is configured to control the gate drive circuit to perform dynamic impedance switching of the multi-stage resistance path by adopting the update drive behavior.

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