Wideband background calibration module, method and time-interleaved analog-to-digital converter

Abstract

The application provides a broadband background calibration module, a method and a time-interleaved analog-to-digital converter, wherein the broadband background calibration module comprises a clock source, N error compensation units and N error estimation units, N is a natural number greater than or equal to 2; the clock source is used for providing N clock signals, each clock signal has a preset phase difference; the input end of each error estimation unit is connected to the output end of each error compensation unit one by one, and a corresponding phase compensation signal is generated based on the relative offset of the corresponding sampling clock and the reference clock; the input end of each error compensation unit is connected to the output end of the clock source and the corresponding error estimation unit, and the corresponding clock signal is phase compensated based on the phase compensation signal to obtain the sampling clock of each sub-ADC unit in the time-interleaved analog-to-digital converter. The broadband background calibration module, the method and the time-interleaved analog-to-digital converter of the application can realize broadband calibration without significant increase in area and power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a wideband background calibration module, method and time-interleaved analog-to-digital converter. BACKGROUND

[0002] With the development of electronic and communication technology, the bandwidth of various communication systems is increasing. As the bridge between digital systems and the analog world, the analog-to-digital converter (ADC) is responsible for rapidly increasing data throughput, and most mainstream high-speed ADCs use time-interleaved technology. Time-interleaved analog-to-digital converter (TIADC) is a technology that samples multiple sub-ADCs staggered in time, alternately samples the same signal in the time dimension, integrates digital codes at the output end, and ultimately achieves a fold increase in sampling rate.

[0003] However, due to the influence of layout design and chip manufacturing deviation, the consistency between each sub-channel is different, which seriously limits the overall performance. The inter-channel mismatch of TIADC system includes mismatch, gain mismatch and sampling time mismatch. Analyzing and calibrating the above several mismatches can greatly improve the overall performance of the ADC.

[0004] Sampling time mismatch refers to the existence of uneven phase difference in the sampling clock of adjacent sub-channels. The time interval is not ideal Ts, or the time delay of the input signal to each sub-channel is inconsistent, which will cause mismatch in sampling time. As shown in Figure 1 , in the ideal state, each sampling time t0, t1……t M-2 , t M-1 is uniformly distributed (the time difference between adjacent sampling times is Ts). As shown in Figure 2 , in actual use, each sampling time t0, t1……t M-2 , t M-1 may have mismatch, and the amount of mismatch (δ0, δ1……δ M-2 , δ M-1 ) is also not completely the same, resulting in inconsistent time difference between each sampling time. Therefore, for a time-interleaved analog-to-digital converter with M channels, as long as there is a deviation in the sampling clock of any two sub-ADCs, it can be considered that the system has a sampling clock mismatch. Sampling clock mismatch will cause distortion and noise in the frequency spectrum, as shown in Figure 3 , sampling clock mismatch calibration for time-interleaved analog-to-digital converter is the key to ensure high accuracy of the overall ADC.

[0005] To ensure the normal work of the chip, a TIADC inter-channel mismatch calibration technology is generally needed. The traditional calibration method based on a reference channel needs to introduce an additional channel, and in the calibration process, the remaining channels gradually approach the reference channel, thereby eliminating the inter-channel mismatch, but this method will cause additional area and power consumption. The derivative filter based on the first-order Taylor expansion approximation is widely used in digital domain calibration, but this method will cause the integer multiple frequency point calibration failure, which seriously limits the performance of the wideband ADC. The calibration method based on the statistical characteristics of the output signal usually has slow convergence speed and certain requirements for the input signal.

[0006] In the fields of radar and communication, the input signal usually far exceeds the Nyquist frequency band, therefore, a sampling mismatch calibration technology capable of realizing wideband signal calibration is very necessary in the time-interleaved ADC system.

[0007] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art only because they are described in the background section of the present application. SUMMARY

[0008] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a wideband background calibration module, method and time-interleaved analog-to-digital converter, which is used to solve the problems of high cost, limited wideband ADC performance, slow convergence speed, and requirements for input signals in the prior art TIADC inter-channel mismatch calibration technology.

[0009] To achieve the above-mentioned purpose and other related purposes, the present application provides a wideband background calibration module for calibrating the sampling time mismatch of a time-interleaved analog-to-digital converter, which comprises at least:

[0010] a clock source, N error compensation units and N error estimation units, N being a natural number greater than or equal to 2;

[0011] The clock source is used to provide N clock signals, each clock signal having a preset phase difference;

[0012] The input end of each error estimation unit is connected to the output end of each error compensation unit one by one, and a corresponding phase compensation signal is generated based on the relative offset of the sampling clock output by the corresponding error compensation unit and the reference clock;

[0013] The input end of each error compensation unit is connected to the output end of the corresponding error estimation unit and the clock source, receives a clock signal, and performs phase compensation on the corresponding clock signal based on the phase compensation signal provided by the error estimation unit to obtain a sampling clock of each sub-ADC unit in the time-interleaved analog-to-digital converter; wherein the phase difference between each adjacent sampling clock after compensation is consistent.

[0014] Optionally, the error estimation unit comprises a phase detection module, a majority vote counter and a delay adjustment counter.

[0015] The phase detection module is connected to the output end of the corresponding error compensation unit, detects whether the sampling clock leads or lags the reference clock, and outputs a detection result.

[0016] The majority vote counter counts the leading and lagging conditions of the sampling clock, respectively, and outputs a voting result according to the majority voting principle.

[0017] The delay adjustment counter is connected to the output end of the majority vote counter and adjusts the phase compensation signal based on the voting result.

[0018] More optionally, the phase detection module is implemented by a flip-flop; the input end of the flip-flop is connected to the corresponding sampling clock, the clock end is connected to the reference clock, and the output end outputs the detection result; the majority vote counter counts the leading and lagging conditions in the detection result when the corresponding sampling clock arrives.

[0019] Optionally, the error compensation unit comprises a decoder and a variable delay line.

[0020] The decoder receives the corresponding phase compensation signal, decodes the phase compensation signal to obtain a delay control signal of the variable delay line.

[0021] The input end of the variable delay line receives the corresponding clock signal, adjusts the delay time of the clock signal, and obtains the sampling clock.

[0022] More optionally, the variable delay line comprises a capacitor delay array and at least two cascaded inverters.

[0023] One end of an M-path delay unit in the capacitor delay array is connected between the two cascaded inverters, and the other end is grounded; the corresponding delay unit is selected to be turned on based on the delay control signal to realize the adjustment of the delay time; M is a natural number greater than or equal to 2.

[0024] To achieve the above object and other related objects, the present application further provides a wideband background calibration method for calibrating the sampling time mismatch of a time-interleaved analog-to-digital converter, which at least comprises:

[0025] 1) providing N clock signals with preset phase difference, each clock signal is provided to each sub-ADC unit in a time-interleaved analog-to-digital converter as a sampling clock; wherein N is a natural number greater than or equal to 2;

[0026] 2) detecting the relative phase relationship of each sampling clock and a reference clock respectively, and determining whether the corresponding sampling clock is leading or lagging, and giving a determination result;

[0027] 3) generating a corresponding phase compensation signal based on the leading or lagging of each sampling clock, and adjusting the delay time of the corresponding clock signal based on each phase compensation signal to realize the adjustment of the phase of the corresponding sampling clock;

[0028] 4) returning to step 2) until the phase difference between each adjacent sampling clock after compensation is consistent.

[0029] Optionally, the leading or lagging of the corresponding sampling clock is determined when the sampling clock arrives in step 2).

[0030] More optionally, in step 2), after obtaining the preliminary determination of leading or lagging, the final determination of leading or lagging is determined by majority voting principle within a preset period.

[0031] Optionally, in step 1), in the initial state, each clock signal is subjected to an initial delay time to obtain a corresponding sampling clock; in step 3), when it is detected that the corresponding sampling clock is leading, the delay time is increased by a preset time length; when it is detected that the corresponding sampling clock is lagging, the delay time is decreased by the preset time length.

[0032] More optionally, the initial delay time is configured as the middle value of the delay adjustment range.

[0033] Optionally, when the inconsistent adjacent determination results occur continuously for at least twice, it is determined that the current sampling clock is calibrated.

[0034] To achieve the above object and other related objects, the present application further provides a time-interleaved analog-to-digital converter, which comprises at least a sampling module, N sub-ADC units, a data selection module and the above-mentioned wideband background calibration module.

[0035] The input end of the sampling module receives an analog input signal, and samples the analog input signal based on the N sampling clocks provided by the wideband background calibration module;

[0036] The input end of each sub-ADC unit is connected to the output end of the sampling module, and the N sampling signals output by the sampling module are subjected to analog-to-digital conversion;

[0037] The data selection module is connected to the output end of each sub-ADC unit and sequentially outputs data converted by each sub-ADC unit.

[0038] As described above, the broadband background calibration module, method and time-interleaved analog-to-digital converter have the following beneficial effects:

[0039] 1. In the broadband background calibration module, method and time-interleaved analog-to-digital converter, the calibration of the sampling time mismatch is independent of the input signal, which is a broadband calibration method.

[0040] 2. The broadband background calibration module does not significantly increase the area and power consumption, and has low implementation cost.

[0041] 3. The broadband background calibration module, method and time-interleaved analog-to-digital converter use the majority voting technology, which has certain inhibitory effect on clock jitter and noise, and improves accuracy.

[0042] 4. The broadband background calibration method is background calibration, and the calibration value is continuously updated, which does not affect the normal conversion of the analog-to-digital converter, and the calibration is independent of the mismatch calibration and gain mismatch calibration of the time-interleaved analog-to-digital converter. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 A distribution diagram of sampling time points in an ideal state is shown.

[0044] Figure 2 A distribution diagram of sampling time points in actual application is shown.

[0045] Figure 3 An output spectrum diagram of the time-interleaved analog-to-digital converter with sampling time mismatch is shown.

[0046] Figure 4 A structure diagram of the broadband background calibration module of the application is shown.

[0047] Figure 5 A structure diagram of the first compensation channel of the application is shown.

[0048] Figure 6 An implementation diagram of the phase detection module of the application is shown.

[0049] Figure 7 An implementation diagram of the phase detection module of the application is shown. Figure 6

[0050] Figure 8 A structure diagram of the first error compensation unit of the application is shown.

[0051] Figure 9 ​A schematic diagram showing the principle of detecting each sampling clock by the reference clock of the present application.

[0052] Figure 10 A schematic diagram showing a flow of the broadband background calibration method of the present application.

[0053] Figure 11 A schematic diagram showing the structure of the time-interleaved analog-to-digital converter of the present application.

[0054] Element Number Description

[0055] 1 broadband background calibration module

[0056] 11 clock source

[0057] 121 first error compensation unit

[0058] 12a decoder

[0059] 12b variable delay line

[0060] 12N Nth error compensation unit

[0061] 131 first error estimation unit

[0062] 13a phase detection module

[0063] 13b majority vote counter

[0064] 13c delay adjustment counter

[0065] 13N Nth error estimation unit

[0066] 2 sampling module

[0067] 3 sub-ADC unit

[0068] 4 data selection module DETAILED DESCRIPTION

[0069] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is construed that persons skilled in the art can easily appreciate other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied in other different embodiments, and each detail in this specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0070] Please refer to Figures 1-11It is to be noted that the drawings provided in the embodiments only schematically illustrate the basic concepts of the present application, and thus only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The shape, number and ratio of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0071] In a multi-channel time-interleaved analog-to-digital converter, the root cause of sampling time mismatch comes from the non-uniform phase difference of the sampling clock. Therefore, the present application compensates the sampling clock of each ADC subunit through an additional calibration module to ensure that the sampling clock has a uniform (same) phase difference. In the calibration module and calibration method proposed in the present patent, the calibration of sampling mismatch error does not depend on the input signal and does not require an additional signal generator to be integrated in the chip. Therefore, the calibration has extremely low implementation cost and can complete the calibration of a wideband input signal. Moreover, since the calibration module and calibration method of the present application directly eliminate the non-uniform phase difference of the sampling clock from the root cause, the calibration is relatively independent of the calibration of the tuning mismatch and gain mismatch, and there is no problem of mutual restraint.

[0072] As shown in Figure 4 , the present application provides a wideband background calibration module 1 for calibrating the sampling time mismatch of a time-interleaved analog-to-digital converter, which comprises:

[0073] a clock source 11, N error compensation units and N error estimation units, N being a natural number greater than or equal to 2. The value of N can be set according to the number of sub-ADC units in the time-interleaved analog-to-digital converter, including but not limited to 6, 8, 10, 16, 24, 32, which will not be described one by one here.

[0074] As shown in Figure 4 , the clock source 11 is configured to provide N clock signals, denoted as CK[N-1:0], each clock signal CK[N-1:0] having a preset phase difference.

[0075] Specifically, each clock signal CK[N-1:0] introduces an error in the process of generation and transmission, which makes the phase difference between each adjacent clock signal CK[N-1:0] not equal, and further causes the sampling time mismatch of each sub-ADC unit.

[0076] As shown in Figure 4 , each error compensation unit corresponds to each error estimation unit, one error compensation unit and one error estimation unit form a compensation channel for compensating one clock signal; that is, there are N compensation channels corresponding to N clock signals for compensation.

[0077] Specifically, the input of each error estimation unit is connected to the output of the corresponding error compensation unit, and a corresponding phase compensation signal is generated based on the relative offset of the sampling clock and the reference clock output by the corresponding error compensation unit. In this embodiment, each error estimation unit is denoted as a first error estimation unit 131, a second error estimation unit 132, and an Nth error estimation unit 13N. Each error estimation unit detects whether the sampling clock leads or lags the reference clock, and generates a corresponding phase compensation signal according to the detection result. In this embodiment, each error estimation unit has the same structure, and in actual use, the structure of each error estimation unit can also be set as needed. As long as the phase relationship between the sampling clock and the reference clock can be detected, it is not limited to this embodiment.

[0078] Specifically, the input of each error compensation unit is connected to the output of the corresponding error estimation unit and the clock source 11, and receives a clock signal respectively. The phase of the corresponding clock signal is compensated based on the phase compensation signal provided by the error estimation unit, and the sampling clock of each sub-ADC unit in the time-interleaved analog-to-digital converter is obtained. In this embodiment, each error estimation unit is denoted as a first error compensation unit 121, a second error compensation unit 122, and an Nth error compensation unit 12N. Each error estimation unit receives a clock signal respectively, and adjusts the delay time of the clock signal to obtain the sampling clock of each sub-ADC unit. After compensation, the phase difference between each adjacent sampling clock is consistent. In this embodiment, each error compensation unit has the same structure, and in actual use, the structure of each error compensation unit can also be set as needed. As long as the phase difference between each adjacent sampling clock after compensation is consistent, it is not limited to this embodiment.

[0079] As shown in Figure 5 , in this embodiment, the first compensation channel is taken as an example, which includes the first error compensation unit 121 and the first error estimation unit 131. The adaptive adjustment of the corresponding signals of the other compensation channels is not described one by one here.

[0080] Specifically, as shown in Figure 5 , the first error estimation unit 131 includes a phase detection module 13a, a majority vote counter 13b, and a delay adjustment counter 13c.

[0081] More specifically, the phase detection module 13a is connected to the output of the corresponding error compensation unit, and detects whether the sampling clock leads or lags the reference clock CLKref. As an example, as shown in Figure 6 , the phase detection module 13a is implemented by using a flip-flop (D flip-flop). The input D of the flip-flop is connected to the corresponding sampling clock CLK0, the clock end Clk is connected to the reference clock CLKref, and the output detection result DFFout0 is output; as shown in Figure 7As shown, when the sampling clock CLK0 leads the reference clock CLKref (at this time, the sampling clock CLK0 is solid line), the rising edge of the reference clock CLKref detects the high level of the sampling clock CLK0, and outputs the high level of the detection result DFFout0, until the next rising edge of the reference clock CLKref, the detection result DFFout0 jumps to low level (at this time, the detection result DFFout0 is solid line); when the sampling clock CLK0 lags behind the reference clock CLKref (at this time, the sampling clock CLK0 is dotted line), the rising edge of the reference clock CLKref detects the low level of the sampling clock CLK0, and outputs the low level of the detection result DFFout0 (at this time, the detection result DFFout0 is dotted line). Therefore, taking the output result of the phase detection module 13a as the direction information of adjusting the sampling clock of each sub-ADC unit, the correct adjustment of the sampling clock can be achieved.

[0082] More specifically, the majority voting counter 13b counts the leading and lagging conditions respectively, and outputs the voting result according to the majority voting principle. In this embodiment, based on the implementation mode of the phase detection module 13a, the majority voting counter 13b counts the leading and lagging conditions in the detection result corresponding to the arrival of the sampling clock respectively, that is, for the majority voting counter 13b in the first compensation channel, only when the sampling clock CLK0 arrives, the majority voting counter 13b will count the leading and lagging conditions, and will not count the detection results output by other reference clocks CLKref in the period. At the same time, the majority voting counter 13b records the number of high and low levels in the preset period, and takes the level with more number as the voting result, and outputs the corresponding level, so as to ensure the accuracy of calibration. As an example, the preset period is set to 16, and there are 12 high levels and 4 low levels in 16 periods, then the voting result is high level, and the number of preset periods is set according to actual needs, and theoretically, the larger the number of preset periods, the higher the accuracy.

[0083] More specifically, the delay adjustment counter 13c is connected to the output end of the majority voting counter 13b, and adjusts the phase compensation signal CTL0 based on the voting result. As an example, the delay adjustment counter 13c has an initial count value, which corresponds to the initial delay time of the variable delay line 12b (in this example, the initial count value is set to the middle value of the count interval, for example, the count interval is set to 0-63, and the initial count value is set to 31; at this time, the initial delay time is set to the middle value of the delay adjustment range, which can be set according to actual needs in actual use). The delay adjustment counter 13c performs +1 or -1 operation on the last count value based on the voting result, and inputs the adjusted count value into the first error compensation unit 121.

[0084] Specifically, as shown in FIG. 4, the first error compensation unit 121 is connected to the output end of the delay adjustment counter 13c, and adjusts the sampling clock CLK0 based on the phase compensation signal CTL0. As an example, the first error compensation unit 121 has a variable delay line 12b, which is connected to the output end of the delay adjustment counter 13c, and adjusts the sampling clock CLK0 based on the phase compensation signal CTL0.Figure 8 As shown, in this example, the first error compensation unit 121 includes a decoder 12a and a variable delay line 12b.

[0085] More specifically, decoder 12a receives the corresponding phase compensation signal CTL0 and decodes the phase compensation signal CTL0 to obtain the delay control signal of variable delay line 12b; decoder 12a can be configured according to the structure of variable delay line 12b, which will not be described in detail here.

[0086] More specifically, the input of the variable delay line 12b receives the corresponding clock signal CK[0], and the delay time of the clock signal CK[0] is adjusted to obtain the corresponding sampling clock CLK0. Any structure of the variable delay line 12b is applicable to this invention. As an example, such as... Figure 8 As shown, the variable delay line 12b includes a capacitor delay array and at least two cascaded inverters. One end of one of the M delay units in the capacitor delay array is connected between the two cascaded inverters, and the other end is grounded, where M is a natural number greater than or equal to 2. Each delay unit includes a capacitor and a switch connected in series. When the switch closes under the control of the delay control signal, the corresponding capacitor is connected to the delay line, resulting in a delay related to the capacitance value. The delay capability t of the variable delay line 12b is... delay Mainly composed of load capacitance C delay The size of the total capacitance (of all capacitors connected to the delay line) determines the following: Among them, V DD I is the power supply voltage. ave This represents the average current of the inverter during one cycle of charging and discharging. The variable delay line 12b selects the corresponding delay unit to conduct based on the delay control signal, thereby adjusting the delay time. For example, at the start of calibration, the total number of capacitors is in the middle position. Ultimately, based on the majority vote, the code value at the input of the decoder 12a will fluctuate repeatedly within ±1, marking the completion of the calibration. Therefore, the calibration accuracy of the broadband background calibration module 1 of this invention depends on the accuracy of the variable delay line 12b and is not closely related to the detection circuit.

[0087] The calibration process of this invention is a background calibration. When the PVT of the environment changes, the clock skew changes. At this time, the variable delay line 12b will be adjusted again to follow the changes in the external environment in real time and ensure that each sampling clock has a uniform phase difference.

[0088] The present invention also provides a broadband back-end calibration method for calibrating sampling time mismatch in a time-interleaved analog-to-digital converter, the broadband back-end calibration method comprising:

[0089] 1) providing N clock signals with preset phase difference, and providing each clock signal to each sub-ADC unit in the time-interleaved analog-to-digital converter as a sampling clock; wherein N is a natural number greater than or equal to 2.

[0090] Specifically, in the embodiment, in the initial state, each clock signal is subjected to an initial delay time to obtain a corresponding sampling clock, and the initial delay time of each clock signal should be kept consistent as much as possible. As an example, the initial delay time is configured as the middle value of the delay adjustment range; in actual use, it can be set as needed.

[0091] 2) detecting the relative phase relationship between each sampling clock and the reference clock, and determining whether the corresponding sampling clock leads or lags, and giving a judgment result.

[0092] Specifically, as shown in Figure 9 In the embodiment, the reference clock is used to sample each sampling clock to obtain a detection result, wherein each sampling clock corresponds to a period of the reference clock in turn, and the detection result obtained when the sampling clock arrives can be used as a judgment result to reflect the information of whether the sampling clock leads or lags with respect to the reference clock.

[0093] Specifically, in order to improve the calibration accuracy, in the embodiment, after obtaining the preliminary judgment of leading or lagging, the majority voting principle is used to determine the final judgment of leading or lagging within a preset period.

[0094] 3) generating a corresponding phase compensation signal based on the leading or lagging of each sampling clock, and adjusting the delay time of the corresponding clock signal based on each phase compensation signal to realize the adjustment of the phase of the corresponding sampling clock.

[0095] Specifically, when it is detected that the corresponding sampling clock leads, the delay time is increased by a preset length to move the sampling clock backward, so that the phases of the sampling clock and the reference clock are close to each other; when it is detected that the corresponding sampling clock lags, the delay time is decreased by a preset length to move the sampling clock forward, so that the phases of the sampling clock and the reference clock are close to each other.

[0096] 4) returning to step 2) until the phase difference between each adjacent sampling clock after compensation is consistent.

[0097] Specifically, the delay time of the clock signal is adjusted according to the relative phase relationship between the sampling clock and the reference clock to make the corresponding period phases of each sampling clock and the reference clock consistent, and since each period of the reference clock is the same, the phase difference between adjacent sampling clocks is the same (i.e. one period of the reference clock).

[0098] It should be noted that in actual use, the corresponding period phases of the sampling clock and the reference clock can not be completely aligned. In the embodiment, when the judgment results of the adjacent advance or lag are inconsistent, it is determined that the current sampling clock is calibrated; the calibration accuracy is determined by the accuracy of the variable delay line; in order to improve the accuracy of the calibration end judgment, the judgment results of the continuous multiple (three times and above) advance or lag are monitored, and when the judgment results repeatedly jump between the advance and the lag, it is considered that the calibration is completed.

[0099] As shown in Figure 10 In the embodiment, the wideband background calibration method of the application is implemented based on the wideband background calibration module 1 of the application, and the calibration process is as follows: after the chip is powered on, the background calibration starts, and the sampling clock of each sub-ADC unit is sent to the corresponding error estimation unit. The rising edge of the reference clock is used to sample each sampling clock to obtain the phase signal of the sampling clock in each compensation channel. The detection results of the majority vote counter when the corresponding sampling clock arrives are counted, and the detection results in the continuous multiple periods are majority voted, and the delay adjustment counter adjusts the count value of the phase compensation signal according to the voting result (the result of the advance or the lag corresponds to +1 or-1 of the count value respectively). The delay control signal of the variable delay line is obtained by decoding the phase compensation signal, and the number of capacitors turned on in the capacitive delay array is adjusted based on the delay control signal. The process of detection and adjustment is repeated until the decision results of the majority vote counter before and after are different, and then the channel completes the calibration. When each channel completes the calibration, the phase difference between each adjacent sampling clock is consistent. When the environment changes, the steps of detection and adjustment are repeated.

[0100] As shown in Figure 11 The application also provides a time-interleaved analog-to-digital converter, which comprises the wideband background calibration module 1, the sampling module 2, the N sub-ADC units 3 and the data selection module 4 of the application.

[0101] The N sampling clocks provided by the wideband background calibration module 1 have consistent phase differences between each adjacent sampling clock. The input end of the sampling module 2 receives an analog input signal, and the analog input signal is sampled based on the N sampling clocks. The input end of each sub-ADC unit 3 is connected to the output end of the sampling module 2, and the N sampling signals output by the sampling module 2 are analog-to-digital converted. The data selection module 4 is connected to the output end of each sub-ADC unit 3, and the data converted by each sub-ADC unit 3 is sequentially output.

[0102] In summary, the present application provides a wideband background calibration module, method and time-interleaved analog-to-digital converter, wherein the wideband background calibration module comprises a clock source, N error compensation units and N error estimation units, N is a natural number greater than or equal to 2; the clock source is used to provide N clock signals, each clock signal has a preset phase difference; the input end of each error estimation unit is connected to the output end of each error compensation unit one by one, and a corresponding phase compensation signal is generated based on the relative offset of the sampling clock output by the corresponding error compensation unit and the reference clock; the input end of each error compensation unit is connected to the output end of the clock source and the corresponding error estimation unit, respectively receives one clock signal, and performs phase compensation on the corresponding clock signal based on the phase compensation signal provided by the error estimation unit to obtain the sampling clock of each sub-ADC unit in the time-interleaved analog-to-digital converter; the phase difference between each adjacent compensated sampling clock is consistent. The wideband background calibration module, method and time-interleaved analog-to-digital converter of the present application can realize wideband calibration without significantly increasing the area and power consumption. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0103] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A broadband background calibration module for calibrating a sampling time mismatch of a time-interleaved analog-to-digital converter, characterized in that, The wideband background calibration module at least comprises: a clock source, N error compensation units and N error estimation units, N being a natural number greater than or equal to 2; the clock source is configured to provide N clock signals, each clock signal having a preset phase difference; the input end of each error estimation unit is connected to the output end of each error compensation unit one by one, and a corresponding phase compensation signal is generated based on the relative offset of the sampling clock and the reference clock output by the corresponding error compensation unit; wherein the error estimation unit comprises a phase detection module, a majority vote counter and a delay adjustment counter; the phase detection module is connected to the output end of the corresponding error compensation unit, and detects whether the sampling clock leads or lags the reference clock; the majority vote counter counts the leading and lagging conditions of the sampling clock respectively, and outputs a voting result according to the majority vote principle; the delay adjustment counter is connected to the output end of the majority vote counter, and adjusts the phase compensation signal based on the voting result; the input end of each error compensation unit is connected to the clock source and the output end of the corresponding error estimation unit, and receives one clock signal respectively, and the phase of the corresponding clock signal is compensated based on the phase compensation signal provided by the error estimation unit, to obtain the sampling clock of each sub-ADC unit in the time-interleaved analog-to-digital converter; wherein the phase difference between each adjacent compensated sampling clock is consistent.

2. The wideband background calibration module of claim 1, wherein: The phase detection module is realized by a flip-flop; the input end of the flip-flop is connected to the corresponding sampling clock, the clock end is connected to the reference clock, and the output detects the result; the majority vote counter counts the leading and lagging conditions in the detection result when the corresponding sampling clock arrives.

3. The wideband background calibration module of claim 1, wherein: The error compensation unit comprises a decoder and a variable delay line; the decoder receives the corresponding phase compensation signal, decodes the phase compensation signal to obtain the delay control signal of the variable delay line; the input end of the variable delay line receives the corresponding clock signal, adjusts the delay time of the clock signal, and obtains the sampling clock.

4. The wideband background calibration module of claim 3, wherein: The variable delay line comprises a capacitor delay array and at least two stages of cascaded inverters; one end of M delay units in the capacitor delay array is connected between the two stages of cascaded inverters, and the other end is grounded; based on the delay control signal, the corresponding delay unit is selected to be turned on to realize the adjustment of the delay time; M is a natural number greater than or equal to 2.

5. A broadband background calibration method for calibrating sampling time mismatch of a time-interleaved analog-to-digital converter, implemented based on the broadband background calibration module according to any one of claims 1-4, characterized in that, The wideband background calibration method at least comprises: 1) providing N clock signals with a preset phase difference, and providing each clock signal to each sub-ADC unit in the time-interleaved analog-to-digital converter as a sampling clock; wherein N is a natural number greater than or equal to 2; 2) detecting the relative phase relationship of each sampling clock and a reference clock respectively, and determining whether the corresponding sampling clock leads or lags, and giving a judgment result; 3) generating a corresponding phase compensation signal based on the leading or lagging condition of each sampling clock, and adjusting the delay time of the corresponding clock signal based on each phase compensation signal to realize the adjustment of the phase of the corresponding sampling clock; 4) returning to step 2) until the phase difference between each adjacent compensated sampling clock is consistent.

6. The wideband background calibration method of claim 5, wherein: In step 2), the leading or lagging of the corresponding sampling clock is determined when the corresponding sampling clock arrives.

7. The wideband background calibration method of claim 5 or 6, wherein: In step 2), after the preliminary determination of the leading or lagging, a majority voting principle is used to determine the final determination of the leading or lagging within a preset period.

8. The wideband background calibration method of claim 5, wherein: In step 1), in the initial state, each clock signal is subjected to an initial delay time to obtain a corresponding sampling clock; in step 3), when it is detected that the corresponding sampling clock is leading, the delay time is increased by a preset time length; when it is detected that the corresponding sampling clock is lagging, the delay time is decreased by the preset time length.

9. The wideband background calibration method of claim 8, wherein: The initial delay time is configured as a middle value of a delay adjustment range.

10. The wideband background calibration method of claim 5, wherein: When the inconsistent adjacent determination results occur at least twice continuously, it is determined that the current sampling clock is calibrated.

11. A time-interleaved analog-to-digital converter, comprising: The time-interleaved analog-to-digital converter at least comprises a sampling module, N sub-ADC units, a data selection module and the wideband background calibration module according to any one of claims 1-4. An input end of the sampling module receives an analog input signal, and the analog input signal is sampled based on N sampling clocks provided by the wideband background calibration module. An input end of each sub-ADC unit is connected to an output end of the sampling module, and N sampling signals output by the sampling module are subjected to analog-to-digital conversion. The data selection module is connected to output ends of the sub-ADC units, and data converted by the sub-ADC units is sequentially output.

Images