Sampling circuit, servo driver control MCU and control system

Abstract

The embodiment of the invention provides a sampling circuit, a servo driver control MCU and a control system, and the circuit comprises an amplification unit which is connected to a sampling unit and is used for amplifying an electric signal obtained by sampling of the sampling unit according to a preset amplification factor; the bias unit is connected to the amplification unit, the bias unit is composed of at least N bias paths, each bias path comprises a bias circuit, the bias circuit is used for offsetting an electric signal amplified by the amplification unit, the offset amount is set according to a preset mapping relation, the bias circuit is further connected with a voltage clamping circuit, and the voltage clamping circuit is used for clamping the electric signal amplified by the amplification unit. The circuit is protected; and the analog-to-digital conversion unit is connected to the bias unit. According to the embodiment of the invention, the amplified voltage range is reasonably split, and the plurality of analog-to-digital converters are used for sampling after different offsets, so that the resolution of the sampling current is improved on the premise that the precision of the analog-to-digital converters is not changed.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a sampling circuit, a servo drive control MCU and a control system. Background Art

[0002] In existing technology, servo motor control circuits typically use a fixed reference voltage (such as 3.3V) to construct an analog-to-digital converter (ADC) sampling system. A level-shifting circuit maps bipolar input signals to the -1.65V to +1.65V range, and a 12-bit ADC achieves a quantized output range of 0-4096. This architecture offers a theoretical ADC resolution of 3.3V / 4096 (≈0.0008V / step). However, practical applications suffer from the following inherent drawbacks: First, the fixed reference voltage and fixed level offset compress the signal's dynamic range. When the input signal amplitude exceeds the preset offset range, nonlinear distortion is introduced, which cannot be eliminated through software calibration. Second, due to the hardware characteristics of the 12-bit ADC, quantization error is amplified by the system bandwidth in high-speed closed-loop control scenarios, directly affecting the steady-state accuracy of the current loop. Third, existing solutions generally use a single reference source and fixed offset circuit to reduce costs. While this reduces hardware complexity, it sacrifices signal conditioning flexibility. This makes it difficult to balance noise suppression with effective resolution, especially under low-power or wide-load conditions. Therefore, how to improve the effective resolution and dynamic adaptability of the sampling system by improving the reference voltage generation mechanism while maintaining the existing ADC bit number and hardware cost has become a technical problem that urgently needs to be broken through in the servo drive field.

[0003] It should be pointed out that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0004] In view of this, the present application provides a sampling circuit, a servo drive control MCU and a control system to solve the problem of insufficient resolution of the sampling circuit in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a sampling circuit, comprising:

[0006] an amplifying unit, connected to the sampling unit, and configured to amplify the electrical signal sampled by the sampling unit according to a preset amplification factor;

[0007] a bias unit connected to the amplifying unit, the bias unit comprising at least N bias paths, where N is a positive integer greater than or equal to 2, the bias paths comprising bias circuits configured to offset the electrical signal amplified by the amplifying unit, the offset being set according to a preset mapping relationship, and at least one of the bias circuits being connected to a voltage clamping circuit for protecting the circuit;

[0008] The analog-to-digital conversion unit is connected to the bias unit, and is used to perform analog-to-digital conversion on the electrical signal.

[0009] In an embodiment of the present application, the sampling voltage is amplified by a preset multiple through the amplification unit, so that the effective resolution of the weak current signal is significantly improved while maintaining the ADC bit width unchanged. At the same time, the segmented mapping mechanism of the multi-channel voltage bias path is utilized to adaptively match signals of different amplitudes to the corresponding bias intervals, thereby avoiding the signal saturation distortion caused by the traditional fixed offset and maximizing the ADC range utilization, thereby realizing linear sampling within the full operating range.

[0010] In one possible implementation,

[0011] The analog-to-digital conversion unit includes at least N A / D converters, where N is a positive integer greater than or equal to 2, and each of the A / D converters is connected to an output end of the bias path.

[0012] In the embodiment of the present application, the electrical signal output by the bias path is connected to a separate A / D converter, so that the sampling results of each path do not interfere with each other.

[0013] In one possible embodiment, the preset mapping relationship is to amplify the electrical signal sampled by the sampling unit according to a preset amplification factor, divide it into equal intervals, and perform a corresponding offset on each electrical signal sub-interval and map it to a different A / D converter, wherein each electrical signal sub-interval has only one A / D converter for sampling.

[0014] In the embodiment of the present application, a single A / D converter is only responsible for signal quantization of its corresponding electrical signal sub-interval, so at the same bit width, the actual equivalent resolution is improved.

[0015] In one possible embodiment, the bias circuit includes a second amplifier, a tenth resistor, and a second capacitor, wherein a common end of the tenth resistor and the second capacitor is connected to a first preset bias voltage corresponding to the preset mapping relationship, and the other common end of the tenth resistor and the second capacitor is connected to the positive input end of the second amplifier.

[0016] In this embodiment, a bias circuit is added to the amplifier circuit with an amplification factor of one to generate a bias effect of a first preset voltage value, that is, a forward bias effect, so that the collected voltage corresponding to the electrical signal interval can be accurately represented within the range of the A / D converter.

[0017] In one possible implementation, the bias path includes a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor; the positive input of the second amplifier is connected to the first end of the sixth resistor, the second end of the sixth resistor is connected to the output of the amplifying unit, the output of the second amplifier is connected to the first end of the seventh resistor, the second end of the seventh resistor is connected to the output of the bias path, two ends of the eighth resistor are respectively connected to the sampling unit and the negative input of the second amplifier, and two ends of the ninth resistor are respectively connected to the negative input of the second amplifier and the second end of the seventh resistor; and the resistance values ​​of the sixth, eighth, ninth, and tenth resistors are equal.

[0018] In a possible implementation manner, when the voltage offset is a negative value,

[0019] The bias circuit includes a second amplifier, a third amplifier, a tenth resistor, a second capacitor, a fourteenth resistor, and a third capacitor. A common terminal of the tenth resistor and the second capacitor is connected to the ground terminal, and another common terminal is connected to the positive input terminal of the second amplifier. A common terminal of the fourteenth resistor and the third capacitor is connected to a second preset bias voltage corresponding to the preset mapping relationship, and another common terminal is connected to the positive input terminal of the third amplifier.

[0020] In this embodiment, a bias circuit is added to the amplifier circuit with an amplification factor of one to generate a bias effect of a second preset voltage value, that is, to generate a negative voltage offset effect, so that the collected voltage of the corresponding voltage interval can be accurately represented within the voltage range of the A / D converter.

[0021] In one possible implementation, the bias circuit includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, an eleventh resistor, a twelfth resistor, and a thirteenth resistor; a positive input terminal of the second amplifier is connected to the first end of the sixth resistor, a second end of the sixth resistor is connected to the output end of the amplification unit, an output end of the second amplifier is connected to the first end of the seventh resistor, a second end of the seventh resistor is connected to the output end of the bias path, a negative input terminal of the second amplifier is connected to the first end of the eighth resistor, two ends of the ninth resistor are respectively connected to the negative input terminal of the second amplifier and the second end of the seventh resistor; and the resistance values ​​of the sixth, eighth, ninth, and tenth resistors are equal.

[0022] The positive input terminal of the third amplifier is connected to the first terminal of the eleventh resistor, the second terminal of the eleventh resistor is connected to the sampling unit, the output terminal of the third amplifier is connected to the second terminal of the eighth resistor, the two ends of the twelfth resistor are respectively connected to the ground terminal and the negative input terminal of the third amplifier, the two ends of the thirteenth resistor are respectively connected to the negative input terminal of the third amplifier and the second end of the twelfth resistor, and the resistance values ​​of the eleventh resistor, the twelfth resistor, the thirteenth resistor and the fourteenth resistor are equal.

[0023] In one possible implementation, the voltage clamping circuit includes a filter circuit, a protection circuit, and a sampling signal terminal; the filter circuit is connected to the sampling signal terminal, and a common terminal of the filter circuit and the protection circuit is connected to the output terminal of the bias path;

[0024] The protection circuit includes a clamping diode, the clamping diode includes a first diode and a second diode, the first diode and the second diode are connected in series, a common end of the first diode and the second diode is connected to the sampling signal end, the negative end of the first diode is connected to the power supply end, and the positive end of the second diode is connected to the ground end;

[0025] The filtering circuit includes a filtering resistor and a filtering capacitor, wherein two ends of the filtering resistor are respectively connected to the output end of the bias path and the clamping diode, and two ends of the filtering capacitor are respectively connected to the filtering resistor and the ground end, and a common end of the filtering resistor and the filtering capacitor is connected to the sampling signal end;

[0026] The amplification unit includes a first amplifier, a third resistor, a fourth resistor, and a fifth resistor. The positive input of the first amplifier is connected to the sampling unit, the output of the first amplifier is connected to the first end of the third resistor, the two ends of the fourth resistor are respectively connected to the sampling unit and the negative input of the first amplifier, and the two ends of the fifth resistor are respectively connected to the negative input of the first amplifier and the second end of the third resistor. The resistance value of the fifth resistor can be adjusted in the following ways: the fifth resistor can be a variable resistor and / or a node selected from a plurality of fixed resistors is short-circuited. In an embodiment of the present application, by limiting the input voltage of the gating unit to a safe voltage range, the gating unit is effectively prevented from being damaged by excessive input signal voltage, thereby significantly reducing the failure rate of the device; by adding a filtering circuit before the sampling signal is output, the circuit noise is effectively reduced, thereby improving the anti-interference ability of the system. The amplification factor of the amplifier circuit is the ratio of the fifth resistor to the fourth resistor. The ratio of the fifth resistor to the fourth resistor in each sampling amplification path is set to a different value, so that the amplification factor of the amplifier circuit of each sampling amplification path is different. The fifth resistor can select the required amplification factor according to the defined operating current upper limit, configure different resistance values, and then amplify the voltage.

[0027] In a second aspect, an embodiment of the present application provides a servo drive control MCU having a current sampling circuit as described in any one of the first aspects.

[0028] In a third aspect, an embodiment of the present application provides a control system comprising a servo driver control MCU and a servo motor as described in any one of the second aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 This is a schematic diagram of a sampling circuit structure in the prior art.

[0031] Figure 2 A block diagram of a sampling circuit provided in an embodiment of the present application.

[0032] Figure 3 A schematic diagram of the circuit structure of a sampling circuit provided in an embodiment of the present application.

[0033] Figure 4 A mapping relationship diagram of a bias unit of a sampling circuit provided in an embodiment of the present application.

[0034] Figure 5 This is a schematic diagram of the circuit structure of a fifth resistor R5 of an amplifying unit of a sampling circuit provided in an embodiment of the present application.

[0035] Figure 6 This is a structural block diagram of a servo drive control MCU provided in an embodiment of the present application.

[0036] Figure 7 This is a structural block diagram of a control system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0038] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0039] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0040] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0041] Servo drive designs typically use the minimum maximum operating current of a hardware module or component as the maximum design current for the entire servo drive. To achieve this, the hardware design includes an amplifier circuit that maps the maximum current to a voltage range of 0-3.3V after applying a bias.

[0042] like Figure 1 As shown, ISU is the input signal and ISV_U is the output signal.

[0043] The calculation formulas for ISU and ISV_U are as follows:

[0044]

[0045] ISU=I·R 采样 (2)

[0046] Where, I is the sampling current, R 采样 is the sampling resistor. Substituting formula (2) into formula (1), formula (1) can be further expressed as:

[0047]

[0048] Essentially, the design maps the current to the ADC's 0-3.3V input range through a certain amplification factor and bias. The 0-3.3V voltage signal then corresponds to the 0-4096 register value of the 12-bit ADC used by most chips.

[0049] Under this architecture, the theoretical ADC resolution is 3.3V / 4096≈0.0008V / step. However, practical applications suffer from the following inherent flaws: First, the fixed reference voltage and fixed level offset force compression of the signal's dynamic range. When the input signal amplitude exceeds the preset offset range, nonlinear distortion is introduced, which cannot be eliminated through software calibration. Second, due to the hardware characteristics of the 12-bit ADC, quantization error is amplified by the system bandwidth in high-speed closed-loop control scenarios, directly affecting the steady-state accuracy of the current loop. Third, existing solutions generally use a single reference source and fixed offset circuit to reduce costs. While this reduces hardware complexity, it sacrifices signal conditioning flexibility. This makes it difficult to balance noise suppression with effective resolution, especially under low-power or wide-load conditions. Therefore, improving the effective resolution and dynamic adaptability of the sampling system by improving the reference voltage generation mechanism while maintaining the existing ADC bit count and hardware cost has become a technical challenge that urgently needs to be overcome in the servo drive field.

[0050] In view of this, the present application provides a sampling circuit, a servo drive control MCU and a control system to solve the problem of insufficient resolution of the sampling circuit in the prior art.

[0051] The following is a description with reference to the accompanying drawings.

[0052] See also Figure 2 , is a block diagram of a sampling circuit provided in an embodiment of the present application. Figure 1As shown, the sampling circuit includes a sampling unit 100, an amplifying unit 200, a bias unit 300, and an analog-to-digital conversion unit 400. The input end of the amplifying unit 200 is electrically connected to the sampling unit 100 for collecting and amplifying the differential signals IU and U of the sampling unit, and representing the current magnitude based on the voltage difference. The input end of the bias unit 300 is electrically connected to the amplifying unit 200. The bias unit 300 is composed of at least N voltage bias paths, where N is a positive integer greater than or equal to 2. Each bias path has a different offset, which is set according to a preset mapping relationship. Taking bias path 1 as an example, bias path 1 includes a bias circuit 311 and a voltage clamp circuit 312. The voltage clamp circuit 312 is connected to the output end of the bias circuit 311 for protecting circuit components. The output ends of the multiple bias paths are all electrically connected to the analog-to-digital conversion unit 400, which is used to convert the input electrical signal into analog-to-digital form.

[0053] See also Figure 3 , is a schematic diagram of the circuit structure of a sampling circuit provided in an embodiment of the present application. Figure 3 As shown, the sampling unit 100 may be a sampling resistor R1, and the amplifying unit 200 is electrically connected to the sampling unit 100 and is used to amplify the voltage difference between the two ends of the sampling resistor R1 according to a preset amplification factor. Figure 3 As shown, the voltage range of the sampling resistor R1 is -1.65V to +1.65V. When the amplification factor is 2, the voltage difference across the sampling resistor R1 is amplified to -3.3V to +3.3V. The bias unit 300 is electrically connected to the output end of the amplifier unit 200 and is used to divide the output voltage VOUT into different voltage intervals according to a preset mapping relationship, and offset them to the sampling intervals of the A / D converter through multiple voltage bias paths. The analog-to-digital conversion unit 400 is electrically connected to the bias path 300 and includes N A / D converters, which are used to simultaneously receive the output results of the multiple voltage offset paths, so that different voltage intervals are sampled by different A / D converters. Among them, the bias circuit is used to positively offset the voltage in the voltage range of -1.65V to +1.65V by 1.65V, and output the data to A / D converter 1 for sampling, and the data result is ADC1_Uin; the bias circuit 321 is used to positively offset the voltage in the voltage range of -3.3V to -1.65V by 4.95V, and output the data to A / D converter 2 for sampling, and the data result is ADC2_Uin; the bias circuit 331 is used to negatively offset the voltage in the voltage range of +1.65V to +3.3V by 1.65V, and output the data to A / D converter 3 for sampling, and the data result is ADC3_Uin.

[0054] The effectiveness of this solution can be described as follows: Conventionally, the hardware current extremes are (-Imax, +Imax), and the data is sampled by A / D converter 1. This design doubles the amplification factor. When the hardware current is (-Imax / 2, +Imax / 2), the VOUT1 voltage range is within 3.3V, allowing A / D converter 1 to sample. When the hardware current is (-Imax, -Imax / 2), the VOUT1 voltage range is below -3.3V, allowing A / D converter 2 to sample after an offset. When the hardware current is (+Imax / 2, +Imax), the VOUT1 voltage range is above +3.3V, allowing A / D converter 3 to sample after an offset. The three sampling paths do not interfere with each other, and each bias path is designed with a voltage clamp protection circuit to prevent damage to the A / D converter due to excessive voltage in any one path.

[0055] The mapping relationship diagram of the bias unit 300 is shown in FIG. Figure 4 As shown, the voltage range is divided into voltage sub-ranges, which are offset by bias circuits with different offsets. Each voltage sub-range is mapped to a different A / D converter for sampling. Take the voltage sub-range from -1.65 to +1.65 as an example: the original voltage sub-range is forward biased by 1.65V to a voltage range of 0 to +3.3V, which just corresponds to the operating range of the A / D converter 1. It can be understood that Figure 4 The voltage mapping shown is for illustrative purposes only and corresponds to Figure 3 In actual work, various voltage mapping designs and corresponding hardware circuit designs can be performed according to the amplification factor, the number of A / D converters, the operating voltage range of the A / D converter, etc., which are all within the protection scope of this application.

[0056] The voltage bias method of this solution can ensure that the current sampling results are converted to digital via an independent A / D converter channel group, ensuring the one-to-one validity of the mapping, and using pure hardware logic to implement multi-interval processing without affecting the actual sampling efficiency.

[0057] In one possible implementation, Figure 3As shown, the protection circuit includes a clamping diode, which includes a first diode D1 and a second diode D2. The first diode D1 and the second diode D2 are connected in series, and the common terminal of the first diode D1 and the second diode D2 is connected to the sampling signal terminal (ADC-Uin). The negative terminal of the first diode D1 is connected to the power supply terminal (3.3V), and the positive terminal of the second diode D2 is connected to the ground terminal (GND). During the operation of the sampling circuit, the protection circuit 432 is used to limit the voltage of the sampling signal terminal (ADC-Uin) to 3.3V to prevent the input signal voltage from being too high and causing damage to the A / D converter components in the analog-to-digital conversion unit 400.

[0058] In one possible implementation, Figure 3 As shown in the figure, the filter circuit includes a filter resistor R2 and a filter capacitor C1. The two ends of the filter resistor R2 are connected to the output terminal of the amplifier circuit and the clamping diode, respectively. The two ends of the filter capacitor C1 are connected to the filter resistor and the ground terminal (GND), respectively. The common end of the filter resistor R2 and the filter capacitor C1 is connected to the sampling signal terminal (ADC-Uin). By adding an RC filter circuit before the sampling signal output, the circuit noise can be effectively reduced and the circuit's anti-interference ability can be enhanced. This design ensures that the output sampling signal is more realistic and accurate, thereby improving the overall performance and reliability of the system.

[0059] In one possible implementation, Figure 3 As shown, the amplifier unit 200 includes a first amplifier U1, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The two input terminals of the first amplifier U1 are respectively connected to the two ends of the sampling resistor R1. The output terminal of the first amplifier U1 is connected to one end of the third resistor R3. The second end of the third resistor R3 is connected to the output terminal of the amplifier unit 200. The two ends of the fourth resistor R4 are respectively connected to the other end of the sampling resistor R1 and the negative input terminal of the first amplifier U1. The two ends of the fifth resistor R5 are respectively connected to the negative input terminal of the first amplifier U1 and the second end of the third resistor R3. The amplification factor of the amplifier unit 200 is the ratio of the fifth resistor R5 to the fourth resistor R4.

[0060] In a possible implementation, the resistance of the fifth resistor is adjusted in a manner that: the fifth resistor may be a variable resistor, and the amplification factor may be changed by changing the value of the resistor, or a node may be selected from a plurality of fixed-value resistors for short-circuiting.

[0061] See also Figure 5 , is a circuit structure diagram of a fifth resistor R5 of an amplifying unit of a sampling circuit provided in an embodiment of the present application. Figure 5As shown, multiple resistors (R51, R52, R53, R54) are designed to be connected in series, and multiple ports (A, B, C, D) are output. By short-circuiting different ports, the resistance value between ports a and b is changed, thereby changing the amplification factor of the amplification unit.

[0062] In this embodiment, different resistor values ​​can be configured according to a preset amplification factor to further adjust the gain.

[0063] In one possible implementation, when the voltage offset of the bias circuit is positive, such as Figure 3 As shown in the bias circuit 311, the bias circuit 311 includes a second amplifier U2, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The positive input terminal of the second amplifier U2 is connected to the first end of the sixth resistor R6, the second end of the sixth resistor R6 is connected to the output terminal of the amplification unit 200, the output terminal of the second amplifier U2 is connected to the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected to the output terminal of the bias path, two ends of the eighth resistor R8 are respectively connected to the sampling unit 100 and the negative input terminal of the second amplifier U2, and two ends of the ninth resistor R9 are respectively connected to the negative input terminal of the second amplifier U2 and the second end of the seventh resistor R7;

[0064] Based on a preset mapping relationship, bias circuit 311 further includes a tenth resistor R10 and a second capacitor C2 connected in parallel. A common terminal of the tenth resistor R10 and the second capacitor C2 is connected to a bias voltage of 1.65V. The other common terminal of the tenth resistor R10 and the second capacitor C2 is connected to the positive input terminal of the second amplifier U2. The sixth resistor R6, the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10 have equal resistance values. Bias circuit 321 has the same structure as bias circuit 311, except that a common terminal of the tenth resistor R10' and the second capacitor C2' is connected to a bias voltage of 4.95V.

[0065] In a possible implementation manner, when the voltage offset is a negative value, such as Figure 3 As shown in the bias circuit 331, the bias circuit 331 includes a second amplifier U2", a sixth resistor R6", a seventh resistor R7", an eighth resistor R8", and a ninth resistor R9". The positive input terminal of the second amplifier U2" is connected to the first end of the sixth resistor R6", the second end of the sixth resistor R6" is connected to the output terminal of the amplification unit 200, the output terminal of the second amplifier U2" is connected to the first end of the seventh resistor R7", the second end of the seventh resistor R7" is connected to the output terminal of the bias path, the two ends of the eighth resistor R8" are respectively connected to the sampling unit 100 and the negative input terminal of the second amplifier U2", and the two ends of the ninth resistor R9" are respectively connected to the negative input terminal of the second amplifier U2" and the second end of the seventh resistor R7".

[0066] According to the preset mapping relationship, the bias circuit 331 also includes a tenth resistor R10″ and a second capacitor C2″ connected in parallel. One common end of the tenth resistor R10″ and the second capacitor C2″ is connected to the ground end, and the other common end of the tenth resistor R10″ and the second capacitor C2″ is connected to the positive input end of the second amplifier U2″. The resistance values ​​of the sixth resistor R6″, the eighth resistor R8″, the ninth resistor R9″ and the tenth resistor R10″ are equal.

[0067] The bias circuit 331 includes a third amplifier U3, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13. The positive input terminal of the third amplifier U3 is connected to the first terminal of the eleventh resistor R11, the second terminal of the eleventh resistor R11 is connected to the sampling unit 100, the output terminal of the third amplifier U3 is connected to the second terminal of the eighth resistor R8, the two ends of the twelfth resistor R12 are respectively connected to the ground terminal and the negative input terminal of the third amplifier U3, and the two ends of the thirteenth resistor R13 are respectively connected to the negative input terminal of the third amplifier U3 and the second end of the twelfth resistor R12.

[0068] The bias circuit 331 also includes a fourteenth resistor R14 and a third capacitor C3 connected in parallel. One common end of the fourteenth resistor R14 and the third capacitor C3 is connected to a bias voltage of 1.65V, and the other common end of the fourteenth resistor R14 and the third capacitor C3 is connected to the positive input end of the third amplifier U3. The resistance values ​​of the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13 and the fourteenth resistor R14 are equal.

[0069] like Figure 3 The current sampling circuit shown is demonstrated with a magnification of 2. Figure 4 The voltage mapping relationship shown in the figure shows that this design divides the sampled values ​​into intervals for processing. Using only hardware logic, namely multiple voltage bias paths and multiple A / D converters, this multi-interval voltage processing is achieved, improving sampling accuracy without affecting actual sampling efficiency. It can be understood that to achieve a larger amplification factor, adding voltage bias paths and A / D converters allows a wider voltage range to be represented within the same current interval. As a result, an A / D converter with the same number of bits can represent smaller currents and finer resolution.

[0070] Corresponding to the above embodiment, an embodiment of the present application provides a servo drive control MCU.

[0071] See also Figure 6 , is a structural block diagram of a servo drive control MCU provided in an embodiment of the present application. Figure 6As shown, the servo driver control MCU 500 includes a current sampling circuit 510. The specific content of the current sampling circuit 510 can be found in the description of the above embodiment, and will not be repeated here for the sake of simplicity.

[0072] Corresponding to the above embodiment, an embodiment of the present application provides a servo drive control system.

[0073] See also Figure 7 , is a structural block diagram of a control system provided in an embodiment of the present application. Figure 7 As shown, the servo drive control system 600 includes a servo motor 700 and a servo drive control MCU 500. The specific content of the servo drive control MCU 500 can be found in the description of the above embodiment, and will not be repeated here for the sake of brevity.

[0074] Corresponding to the above embodiment, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, wherein, when the program is executed, the device containing the computer-readable storage medium may be controlled to perform some or all of the steps in the above method embodiment. In a specific implementation, the computer-readable storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0075] Corresponding to the above embodiment, an embodiment of the present application further provides a computer program product, which includes executable instructions. When the executable instructions are executed on a computer, the computer executes some or all of the steps in the above method embodiment.

[0076] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0077] Those skilled in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented using a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0078] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0079] In the several embodiments provided in this application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of this application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0080] The above description is merely a specific embodiment of the present application. Any person skilled in the art may easily conceive of variations or substitutions within the technical scope disclosed in this application, and such variations or substitutions shall be within the scope of protection of this application. The scope of protection of this application shall be subject to the scope of protection of the claims.

Claims

1. A sampling circuit, characterized in that: include: an amplifying unit, connected to the sampling unit, and configured to amplify the electrical signal sampled by the sampling unit according to a preset amplification factor; a bias unit connected to the amplifying unit, the bias unit comprising at least N bias paths, where N is a positive integer greater than or equal to 2, the bias paths comprising bias circuits configured to offset the electrical signal amplified by the amplifying unit, the offset being set according to a preset mapping relationship, and at least one of the bias circuits being connected to a voltage clamping circuit for circuit protection; The analog-to-digital conversion unit is connected to the bias unit, and is used to perform analog-to-digital conversion on the electrical signal.

2. The circuit sampling circuit according to claim 1, characterized in that: The analog-to-digital conversion unit includes at least N A / D converters, where N is a positive integer greater than or equal to 2, and each of the A / D converters is connected to an output end of the bias path.

3. The sampling circuit according to claim 2, wherein: The preset mapping relationship is to amplify the electrical signal sampled by the sampling unit according to a preset amplification factor, divide it into equal intervals, and perform a corresponding offset on each electrical signal sub-interval and map it to a different A / D converter, wherein each electrical signal sub-interval has only one A / D converter for sampling.

4. The sampling circuit according to claim 1, wherein: When the voltage offset of the bias circuit is positive, the bias circuit includes a second amplifier, a tenth resistor, and a second capacitor, wherein a common terminal of the tenth resistor and the second capacitor is connected to a first preset bias voltage corresponding to the preset mapping relationship, and another common terminal of the tenth resistor and the second capacitor is connected to a positive input terminal of the second amplifier.

5. The sampling circuit according to claim 4, characterized in that: The bias path includes a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. The positive input terminal of the second amplifier is connected to the first end of the sixth resistor, the second end of the sixth resistor is connected to the output terminal of the amplifying unit, the output terminal of the second amplifier is connected to the first end of the seventh resistor, the second end of the seventh resistor is connected to the output terminal of the bias path, two ends of the eighth resistor are respectively connected to the sampling unit and the negative input terminal of the second amplifier, and two ends of the ninth resistor are respectively connected to the negative input terminal of the second amplifier and the second end of the seventh resistor. The resistance values ​​of the sixth resistor, the eighth resistor, the ninth resistor, and the tenth resistor are equal.

6. The sampling circuit according to claim 1, wherein: When the voltage offset is a negative value, the bias circuit includes a second amplifier, a third amplifier, a tenth resistor, a second capacitor, a fourteenth resistor, and a third capacitor. One common end of the tenth resistor and the second capacitor is connected to the ground terminal, and the other common end is connected to the positive input terminal of the second amplifier. One common end of the fourteenth resistor and the third capacitor is connected to a second preset bias voltage corresponding to the preset mapping relationship, and the other common end is connected to the positive input terminal of the third amplifier.

7. The sampling circuit according to claim 6, characterized in that: The bias circuit includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, an eleventh resistor, a twelfth resistor, and a thirteenth resistor; a positive input terminal of the second amplifier is connected to the first end of the sixth resistor; a second end of the sixth resistor is connected to the output terminal of the amplifying unit; an output terminal of the second amplifier is connected to the first end of the seventh resistor; a second end of the seventh resistor is connected to the output terminal of the bias path; a negative input terminal of the second amplifier is connected to the first end of the eighth resistor; two ends of the ninth resistor are respectively connected to the negative input terminal of the second amplifier and the second end of the seventh resistor; and resistance values ​​of the sixth, eighth, ninth, and tenth resistors are equal; The positive input terminal of the third amplifier is connected to the first terminal of the eleventh resistor, the second terminal of the eleventh resistor is connected to the sampling unit, the output terminal of the third amplifier is connected to the second terminal of the eighth resistor, the two ends of the twelfth resistor are respectively connected to the ground terminal and the negative input terminal of the third amplifier, the two ends of the thirteenth resistor are respectively connected to the negative input terminal of the third amplifier and the second end of the twelfth resistor, and the resistance values ​​of the eleventh resistor, the twelfth resistor, the thirteenth resistor and the fourteenth resistor are equal.

8. The sampling circuit according to claim 1, wherein: The voltage clamping circuit includes a filter circuit, a protection circuit and a sampling signal terminal; the filter circuit is connected to the sampling signal terminal, and a common terminal of the filter circuit and the protection circuit is connected to the output terminal of the bias path; The protection circuit includes a clamping diode, the clamping diode includes a first diode and a second diode, the first diode and the second diode are connected in series, a common end of the first diode and the second diode is connected to the sampling signal end, the negative end of the first diode is connected to the power supply end, and the positive end of the second diode is connected to the ground end; The filtering circuit includes a filtering resistor and a filtering capacitor, wherein two ends of the filtering resistor are respectively connected to the output end of the bias path and the clamping diode, and two ends of the filtering capacitor are respectively connected to the filtering resistor and the ground end, and a common end of the filtering resistor and the filtering capacitor is connected to the sampling signal end; The amplification unit includes a first amplifier, a third resistor, a fourth resistor, and a fifth resistor. The positive input terminal of the first amplifier is connected to the sampling unit, the output terminal of the first amplifier is connected to the first terminal of the third resistor, two ends of the fourth resistor are respectively connected to the sampling unit and the negative input terminal of the first amplifier, and two ends of the fifth resistor are respectively connected to the negative input terminal of the first amplifier and the second terminal of the third resistor. The resistance value of the fifth resistor can be adjusted in the following ways: the fifth resistor can be a variable resistor and / or a node selected from multiple fixed resistors can be short-circuited.

9. A servo drive control MCU, characterized in that: A sampling circuit according to any one of claims 1 to 8 is provided.

10. A control system, characterized in that: The device comprises a servo drive control MCU and a servo motor as claimed in claim 9.

Images