Intelligent lamp and control method and storage medium thereof

Abstract

The application relates to an intelligent lamp, a control method thereof and a storage medium. The intelligent lamp comprises a main control chip and a plurality of light emitting units. Each light emitting unit comprises a unit control chip and a light emitting element. The unit control chips of the plurality of light emitting units are cascaded to the main control chip to form a control lamp link. The main control chip sends hierarchical control lamp data to the control lamp link. Each unit control chip receives the hierarchical control lamp data of the previous control chip through a data input port, intercepts the current control lamp data, and then forwards the remaining hierarchical control lamp data to the next control chip through a data output port. According to the current control lamp data intercepted, a pulse control lamp signal is generated. After the hierarchical control lamp data is received from the data input port and reaches a preset lag time difference, the pulse control lamp signal is sent through a pulse output port to drive the light emitting element. The application can effectively reduce the electromagnetic interference of the intelligent lamp and the peak current of the power supply system, and can improve the stability and reliability of the intelligent lamp.

Description

Technical Field

[0001] The present application relates to the field of intelligent lighting, and in particular to an intelligent lighting fixture, a control method thereof, and a storage medium. Background Art

[0002] RGB ICs (RGB lighting control chips) are widely used to control the brightness and color of LED lights. These chips receive hierarchical control data from a main control chip and generate PWM-based pulse control signals to drive the light-emitting elements. However, existing technologies have some issues, particularly with electromagnetic interference (EMI) and power system stability.

[0003] like Figure 1 As shown in the figure, in the existing RGBIC lighting control framework, when a chip (RGBIC) receives lighting control data via the data input pin (DIN), it first shapes the data, extracts the first data packet for its own use, and then sends the remaining data packets to the next chip via the data output pin (DOUT). This data transmission method is serial, ensuring that data is delivered to each chip one by one. However, the reset operation of all chips is synchronized. When the DIN signal pin remains low for 200 microseconds or longer, all chips enter the reset state almost simultaneously. After the reset, all chips begin processing data almost simultaneously and output pulsed lighting control signals to each LED lamp through the RGB Out port. This synchronization causes the pulsed lighting control signals from all chips to be output almost simultaneously, resulting in large current spikes and high-frequency ringing. These current spikes and ringing not only radiate energy, increasing electromagnetic interference (EMI) intensity, but also may cause power system instability, affecting the normal operation of the lighting fixture.

[0004] Furthermore, because all chips output pulse control signals almost simultaneously, the peak current of the entire lamp is highly concentrated, placing significant pressure on the power supply module. To address this issue, existing technologies typically optimize the power supply module at the expense of increased costs, such as by adopting more complex filtering circuits or higher-quality power modules. However, these approaches not only increase product cost and complexity, but also reduce product competitiveness.

[0005] As can be seen, the synchronization issues between the existing RGBIC chip's light control data processing and pulse control signal output lead to increased electromagnetic interference (EMI) and unstable power supply modules, while also limiting the room for cost and performance optimization of smart lamps. These issues need to be addressed urgently to improve the performance and market competitiveness of smart lamps. Summary of the Invention

[0006] The primary purpose of the present application is to solve at least one of the above problems and to provide a smart lamp, a control method thereof, and a storage medium.

[0007] In order to meet the various objectives of this application, this application adopts the following technical solutions:

[0008] An intelligent lamp provided to meet one of the purposes of the present application includes a main control chip and multiple light-emitting units, each light-emitting unit including a unit control chip and a light-emitting element driven by a pulse light-control signal generated by the unit control chip. The unit control chips of the multiple light-emitting units are cascaded and connected to the main control chip to form a light-control link. The main control chip is used to send hierarchical light-control data to the light-control link, wherein:

[0009] Each unit control chip is configured to receive the hierarchical light control data provided by the previous control chip through the data input port, intercept the current level light control data therefrom, and forward the remaining hierarchical light control data to the next level control chip through the data output port;

[0010] Each unit control chip is configured to generate a pulse light control signal based on the light control data of this level that it intercepts. After receiving the graded light control data from the data input port and reaching a preset lag time difference, the pulse light control signal is sent through the pulse output port to drive the light-emitting element of the light-emitting unit of this level.

[0011] Optionally, the unit control chip is configured to start a timer after receiving hierarchical lighting control data from the data input port, and output a pulse lighting control signal generated according to the current level lighting control data after the timer reaches a preset lag time difference.

[0012] Optionally, the hierarchical lighting control data output by the main control chip includes sequence delay values ​​corresponding to the unit control chips at each level in the lighting control link. The unit control chip is configured to determine the output time of the corresponding pulse lighting control signal based on the time when the main control chip sends the clock synchronization signal, and compare it with the sequence delay value in the lighting control data at this level to generate the lag time difference.

[0013] Optionally, the unit control chip is configured to disable a reset synchronization function, including:

[0014] Disable the monitoring function of the silent period of the data input port;

[0015] Disable the function of triggering the pulse light control signal based on the silence duration.

[0016] Optionally, the hysteresis time difference is configured so that the peak current of each light-emitting unit is evenly distributed on the time axis.

[0017] Optionally, the lag time difference takes values ​​within a preset time domain interval, the lower limit value of the time domain interval is greater than twice the internal processing delay caused by the unit control chip itself processing the hierarchical lighting control data, and the upper limit value is less than 50% of the product of the total number of cascaded unit control chips in the lighting control link and the internal processing delay.

[0018] Optionally, the internal processing delay caused by the unit control chip itself processing the graded lighting control data is 80±20ns, the hysteresis time difference is 1000±200ns, and the rising edge time deviation of the pulse lighting control signal is less than 1 / 10 of the hysteresis time difference.

[0019] To meet one of the purposes of this application, this application further proposes an intelligent lighting control method applied to the intelligent lighting of this application, which includes:

[0020] Receive the hierarchical lighting control data provided by the front-stage control chip through the data input port;

[0021] Intercepting the current level light control data from the received hierarchical light control data, and forwarding the remaining hierarchical light control data to the subsequent control chip through the data output port;

[0022] A pulse light control signal is generated according to the light control data of this level. After the hierarchical light control data is received from the data input port for a preset lag time difference, the pulse light control signal is sent through the pulse output port to drive the light-emitting element of the light-emitting unit of this level.

[0023] Optionally, generating a pulse light control signal according to the current-level light control data, and sending the pulse light control signal via a pulse output port to drive the light-emitting element of the current-level light-emitting unit after receiving the hierarchical light control data from the data input port for a preset hysteresis time difference, includes:

[0024] Obtaining a data processing duration determined by a timer, wherein the timer starts to calculate the data processing duration from the moment when the hierarchical lighting control data is received from the data input port;

[0025] Detect whether the data processing duration reaches a preset hysteresis time difference. When the hysteresis time difference is reached, determine the current moment as the output moment of the pulse light control signal, and output the pulse light control signal generated according to the graded light control data at this output moment.

[0026] Optionally, generating a pulse light control signal according to the current-level light control data, and sending the pulse light control signal via a pulse output port to drive the light-emitting element of the current-level light-emitting unit after receiving the hierarchical light control data from the data input port for a preset hysteresis time difference, includes:

[0027] Extracting a sequence delay value and a luminous parameter from the current-level light control data, wherein the sequence delay values ​​of the light control data at each level form an arithmetic progression, and the tolerance between the arithmetic progressions is greater than the internal processing delay caused by the unit control chip itself processing the hierarchical light control data, and the sequence delay value of the first-level light control data is the sum of the tolerance and a preset lag time difference;

[0028] Obtaining a duration counted by a timer starting from a link synchronization moment, detecting whether the duration reaches a duration corresponding to the sequence delay value, and determining the current moment as an output moment of the pulse light control signal when the duration reaches a duration corresponding to the sequence delay value, wherein the link synchronization moment is a moment when a clock synchronization signal sent by a main control chip is received;

[0029] At the output moment, the pulse light control signal generated according to the light-emitting parameters is transmitted to the corresponding light-emitting element via the pulse output port to control the operation of the light-emitting element.

[0030] Optionally, before receiving the hierarchical lighting control data provided by the front-stage control chip through the data input port, the following steps are included:

[0031] Disable the monitoring function of the silent period of the data input port;

[0032] Disable the function of triggering the pulse light control signal based on the silence duration.

[0033] On the other hand, a computer-readable storage medium is provided to meet another purpose of the present application, which stores a computer program implemented according to the intelligent lighting control method in the form of computer-readable instructions. When the computer program is called and executed by a computer, the steps included in the corresponding method are executed.

[0034] The present application effectively solves the electromagnetic interference and power supply stability problems existing in the prior art by introducing a fixed lag time difference into each unit control chip within the lighting control link of the smart lamp. Specifically, after receiving the hierarchical lighting control data provided by the preceding control chip, each unit control chip intercepts the lighting control data of this level and forwards the remaining data to the succeeding control chip. When using the lighting control data of this level to generate a pulse lighting control signal, the output moment of each unit control chip maintains a fixed lag time difference relative to the preceding and / or succeeding control chips. This design allows the output time of the pulse lighting control signals of each unit control chip to be spread out, avoiding the simultaneous output of pulse signals from all chips, thereby significantly reducing the peak current and high-frequency ringing phenomenon of the power supply system.

[0035] In this way, this application effectively reduces the intensity of electromagnetic interference without adding additional hardware costs. Because the output time of the pulse control signal is rationally distributed, the pressure on the power supply module is relieved, thereby improving the stability and reliability of the control link. Furthermore, this design optimizes the overall performance of the smart lamp, making it more stable during operation and reducing problems such as flickering, uneven brightness, or abnormal color caused by power supply fluctuations or electromagnetic interference.

[0036] As can be seen, this application, through improved control logic and time delay mechanisms, effectively manages the output timing of pulse control signals from each unit control chip in the lighting control chain, significantly reducing electromagnetic interference, improving the power supply stability of smart lamps, and optimizing the overall performance of smart lamps. These improvements not only enhance the user experience but also provide broader development space for the design and application of smart lamps. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0038] Figure 1 This is a schematic diagram of the light control framework of the light-emitting unit used in the smart lamp of this application;

[0039] Figure 2 This is a schematic diagram of the electrical structure of the smart lamp of this application;

[0040] Figure 3 This is a schematic diagram of a curtain light product, one of the product forms of the smart lamp of this application;

[0041] Figure 4 This is a schematic diagram of one of the product forms of the smart lamp of this application, namely a planar lamp product form;

[0042] Figure 5 This is a flow chart of a typical embodiment of the intelligent lighting control method of the present application;

[0043] Figure 6 This is a principle block diagram of the intelligent lighting control device of this application;

[0044] Figure 7 This is a schematic diagram of the structure of a computer device used in this application. DETAILED DESCRIPTION

[0045] See also Figure 2 , Figure 2The electrical structure schematic diagram of the smart lighting fixture of the present application is shown, which includes a light control chain 20. The number of light control chains 20 can be one or more. Each light control chain 20 includes a main control chip 10 and multiple light-emitting units 3. When there are multiple light control chains 20, the multiple light control chains 20 share and are connected to the same main control chip 10. In other words, multiple light control chains 20 can be constructed using a single main control chip 10, where the light-emitting units 3 in each light control chain 20 are cascaded and connected to the main control chip 10.

[0046] Please review Figure 1 The light control framework corresponding to the light-emitting units 3 shown in the figure. Each light-emitting unit 3 in this light control framework includes a control unit (RGBIC) encapsulated with a specific chip (IC) and a light-emitting element. The light-emitting element can be individual LED lights corresponding to the three RGB colors (LEDR, LEDG, LEDB) or individual LED lights corresponding to the four RGBA colors. Each LED light is connected in series via resistors (R1, R2, R3) to the unit control chip (RGBIC). The unit control chip has a data input port DIN, a data output port DOUT, and a pulse output port (RGB out). In the same light-control link 20, the cascade connection between the light-emitting units 3 is achieved through the cascade connection between their unit control chips. Specifically, in the light-control link 20, according to the cascade direction starting from the main control chip 10, the unit control chip of the light-emitting unit 3 at this level, which can also be referred to as the unit control chip at this level or the control chip at this level, is connected to the data output port of its previous-level unit control chip or the previous-level control chip through its data input port, and is connected to the data input port of its subsequent-level unit control chip or the subsequent-level control chip through its data output port, thereby achieving cascade connection between the unit control chips at each level, that is, between the light-emitting units 3 at each level. The pulse output port of each unit control chip can be connected to each light-emitting element of the light-emitting unit 3 at this level through its multiple pins, so that the pulse control signal can be output through the pulse output port to control the operation of each light-emitting element.

[0047] The main control chip 10 is responsible for generating corresponding hierarchical light-control data for each light-control link 20 according to a preset communication protocol. The hierarchical light-control data includes light-control data provided for each light-emitting unit 3 in the light-control link 20. The light-control data corresponding to each light-emitting unit 3 in the hierarchical light-control data of the same light-control link 20 are arranged in the order of the light-emitting units 3 in the cascade direction starting from the main control chip 10, so that the hierarchical light-control data is organized serially in the cascade direction.

[0048] The cascade relationship of the individual light-emitting units 3 in the light-control link 20 can be set as a linear relationship arranged in series along the same main line, or as a tree relationship with a bifurcated structure. Regardless of which relationship is used to organize the light-control link 20, for the first unit control chip in the light-control link 20 in the cascade direction starting from the main control chip 10, its previous-stage control chip is actually the main control chip 10. For the last unit control chip in the cascade direction, since its data output port is not connected to a subsequent-stage control chip, the transmission of the hierarchical light-control data ends here, without hindering the embodiment of the creative spirit of the present application.

[0049] For the lighting control link 20 organized according to a linear relationship, the main control chip 10 only needs to arrange the lighting control data of each unit control chip according to the cascade order of each light-emitting unit 3 in the lighting control link 20, encapsulate it into the same hierarchical lighting control data, and then forward it to the first unit control chip in the corresponding lighting control link 20, so as to start the downlink transmission of the hierarchical lighting control data. Each unit control chip only needs to intercept the first lighting control data from the hierarchical lighting control data received from its previous control chip. This lighting control data is the lighting control data required by the control chip at this level. Then, the remaining lighting control data can be re-encapsulated into hierarchical lighting control data and forwarded to the next control chip. By analogy, the lighting control data required by each light-emitting unit 3 can be accurately sent to the corresponding unit control chips, thereby driving the light-emitting elements of each light-emitting unit 3 to work.

[0050] For the light control link 20 organized in a tree-like relationship, its specifications for hierarchical light control data may be slightly different from the linear relationship. Specifically, the light control link 20 may have a unit control chip of a certain light-emitting unit 3 at this level, which forwards hierarchical light control data to the unit control chips in more than two branches through its two or more data output ports. These forwarded hierarchical light control data originate from the previous-level control chip of the unit control chip at this level. After the control chip at this level intercepts its own light control data at this level, it re-encapsulates the hierarchical light control data corresponding to the unit control chip of each branch corresponding to each branch, and then outputs it to the corresponding subsequent-level control chip in the corresponding branch through the data output port correspondingly connected to the branch by the control chip at this level. In order to facilitate the unit control chips at each level to determine the direction of the branch, the hierarchical light control data generated by the main control chip 10 may further include the chip identifier and branch identifier of each unit control chip, so that each unit control chip can efficiently parse, process, and encapsulate the hierarchical light control data according to the chip identifier and branch identifier.

[0051] The smart lamp of this application has a more flexible implementation method in terms of product form. For example, Figure 3It is a form of curtain light, which includes the main control chip 10 of the present application and multiple light strips 13. Each light strip 13 includes multiple cascaded light-emitting units 3 of the present application. When the light strip 13 is connected to the main control chip 10, or is connected in series with other light strips and then connected to the main control chip 10, it constitutes the light control link of the present application.

[0052] Figure 4 It is a planar lamp, which includes a plurality of lamp panels 40. These lamp panels 40 can be in the form of a polygonal shape that can be spliced ​​together, for example Figure 4 The regular hexagonal light panels 40 in the figure are arranged in a linear fashion. Each light panel contains multiple light-emitting units (not shown) distributed across the panel in various locations. These units connect to a main control chip within the panel or to a main control chip 10 external to the panel, forming a relatively independent light control chain. These light panels can be joined together in a physical space to create unique shapes, showcasing artistic quality.

[0053] Therefore, it can be seen that the product form of smart lamps is flexible and does not affect the embodiment of the creative spirit of this application. In particular, the lighting control link of this application can flexibly adjust its physical form to match the product form of the smart lamp, but the cascade relationship between each light-emitting unit in the lighting control link is determined in accordance with the relevant specifications described in this application.

[0054] The control chip of the present application includes a main control chip 10 and a unit control chip (RGBIC), which can be implemented using various embedded chips, such as Bluetooth SoC (System on Chip), WiFi SoC, MCU (MicroController Unit), DSP (Digital Signal Processing), and other types of chips. The control chip usually includes a central processing unit and a memory, and the memory and the central processing unit are respectively used to store and execute program instructions to achieve corresponding functions.

[0055] In some embodiments, in addition to the structural components disclosed above, the smart lamp may also include components configured on demand, such as a control panel, a communication component, and a display screen.

[0056] The control panel usually provides one or more buttons for implementing on-off control of the main control chip, selecting various preset lighting effects so that the main control chip can generate corresponding graded lighting control data, and so on.

[0057] The communication component is used to realize wireless communication connection with an external terminal so as to obtain the lighting effect description information or instructions required for playing the lighting effects from the external terminal, so that the main control chip can be controlled by the external terminal to play the corresponding lighting effects and generate hierarchical lighting control data according to the lighting effect description information or instructions of the external terminal.

[0058] The display screen can be used to display various control information, so as to cooperate with the buttons in the control panel to support the implementation of human-computer interaction functions. The control panel and the display screen can also be integrated into the same touch screen.

[0059] In some embodiments, some of the control functions of the main control chip of the smart lighting fixtures of this application can be implemented by independent computing devices. For example, these computing devices can input the lighting effect description information required to generate hierarchical lighting control data to the main control chip. When implemented in a computing device, various inherent resources of the computing device can be shared to reduce overall implementation costs. The computing device referred to herein can be any terminal device available to users, such as a smartphone, personal computer, laptop computer, tablet computer, etc.

[0060] In order to achieve efficient control of smart lamps and reduce electromagnetic interference, this application, based on the basic structure disclosed above, has made a special program configuration for the unit control chip. The core is to introduce a hysteresis time difference into the unit control chip. This hysteresis time difference corresponds to the period from the time when the unit control chip receives the graded light control data to the time when the pulse light control signal is output, ensuring that the output moments of the pulse light control signals of each unit control chip in the light control link are evenly distributed along the time axis, so that the signal current is relatively dispersed, avoiding excessive power supply pressure caused by concentrated peak current load. In this way, the simultaneous output of pulse signals from all unit control chips is avoided, effectively reducing peak current and high-frequency ringing phenomena, thereby reducing the possibility of electromagnetic interference. By evenly distributing the peak current, not only can electromagnetic interference be reduced, but also flickering, uneven brightness or color abnormalities caused by power supply fluctuations or electromagnetic interference can be reduced. It can also improve the efficiency and life of the power supply module, thereby enhancing the user experience of smart lamps.

[0061] Specifically, after receiving the hierarchical lighting control data from the preceding control chip, each unit control chip first intercepts its own lighting control data from the received hierarchical lighting control data as the lighting control data for this level. This data contains all the necessary information to generate the pulsed lighting control signal for this level's light-emitting unit. The unit control chip at this level then forwards the remaining hierarchical lighting control data to the succeeding control chip via its data output port. This process is triggered sequentially within the same lighting control link, ensuring that data can smoothly reach each light-emitting unit along the lighting control link and be transmitted to each unit control chip.

[0062] When generating pulse control signals, each unit control chip determines the output timing of the pulse control signal based on a preset rule. This rule can be based on a fixed delay set by an internal timer or on a clock synchronization signal and sequence delay value sent by the master control chip. Whether determining the output timing by internal timer timing or sequence delay value, the goal is to ensure that the output timing of the pulse control signal is evenly distributed along the time axis. For example, a unit control chip can start an internal timer after receiving hierarchical control data and output the pulse control signal after the timer reaches a preset lag time difference. Alternatively, the unit control chip can determine the output timing based on the clock synchronization signal sent by the master control chip and the sequence delay value in the control data. Both approaches can achieve uniform distribution of the pulse control signal, thereby reducing electromagnetic interference and peak current in the power supply system.

[0063] In one embodiment, to ensure that the output timing of pulse control signals from each unit control chip in the lighting control chain is evenly distributed along the time axis, each unit control chip is specifically configured to start an internal timer upon receiving hierarchical lighting control data from the preceding control chip. The timer then outputs a pulse control signal after a preset hysteresis. This configuration precisely controls the output timing of the pulse control signal, preventing simultaneous output of pulse signals from all unit control chips, thereby effectively reducing peak current and high-frequency ringing.

[0064] Specifically, when the unit control chip receives the hierarchical lighting control data sent by the previous control chip through its data input port, it first intercepts its own level of lighting control data from this data. This data contains all the necessary information to generate the pulse control signal for the current level of light-emitting units. After completing the data interception, the unit control chip starts an internal timer that starts counting from the moment the hierarchical lighting control data is received. This timer continues to run until the preset hysteresis is reached. The preset hysteresis is a fixed time interval used to ensure that the output of the pulse control signal is evenly distributed along the time axis.

[0065] For example, assuming a preset lag time of 1000 nanoseconds (ns), each unit control chip will wait 1000 nanoseconds after receiving data before outputting a pulse control signal. Because each unit control chip has an internal processing delay when processing hierarchical control data, this internal processing delay allows each unit control chip to naturally stagger its output of its own pulse control signal. This approach ensures that each unit control chip outputs its pulse control signal at a fixed interval relative to the output of the preceding control chip, creating an orderly time distribution across the entire control chain. This temporal staggering ensures that the current load on the smart lamp's power supply module is not overly concentrated at any given moment, thereby reducing the possibility of electromagnetic interference.

[0066] Through this internal timer-based hysteresis control mechanism, the unit control chip can independently determine the output timing of the pulse control signal, without relying on synchronization signals from other chips. This design not only improves the system's flexibility and scalability, but also enhances its stability and reliability. By evenly distributing the output timing of the pulse control signal, the smart lamps of this application can effectively reduce electromagnetic interference, improve the stability and reliability of the power supply system, and thus enhance the user experience.

[0067] In another embodiment, the hierarchical lighting control data output by the master control chip includes not only the luminous parameters used to control the light-emitting elements, but also the sequence delay values ​​corresponding to each unit control chip at each level in the lighting control chain. These sequence delay values ​​are set and arranged in an arithmetic progression. The sequence delay value of each unit control chip corresponds to its position in the chain, and the difference in sequence delay values ​​between adjacent levels, or the tolerance, is a constant that is greater than the internal processing delay generated by the unit control chip itself when processing the hierarchical lighting control data. The sequence delay value for each level includes the cumulative value of the corresponding level tolerance and a preset lag time difference to indicate the specific time when the unit control chip at the corresponding level outputs the pulse lighting control signal. This design allows the master control chip to centrally control each unit control chip, enabling it to precisely determine the output time of its pulse lighting control signal based on its position in the lighting control chain, thereby achieving uniform distribution of the pulse lighting control signal throughout the entire lighting control chain.

[0068] In practice, before sending the hierarchical lighting control data, the main control chip generates a clock synchronization signal and sends it to the start of the lighting control chain. This clock synchronization signal provides a common time reference point for the entire lighting control chain. When each unit control chip receives the hierarchical lighting control data, it first intercepts its own portion of the lighting control data—the data for that level, which includes the sequence delay value for that unit control chip. The unit control chip then starts an internal timer, starting from the moment it receives the clock synchronization signal.

[0069] The unit control chip continuously monitors the timing results of the internal timer until the timing results match the sequence delay value in the current level of lighting control data. Once the timer timing results reach the sequence delay value, the unit control chip determines the current moment as the output moment, generates and outputs the pulse lighting control signal at this output moment, and thus drives the light-emitting elements of this level. Because the sequence delay values ​​of each unit control chip are arranged according to an arithmetic progression, the pulse lighting control signal output time of each chip has a tolerance time relative to the previous control chip. This tolerance time ensures the orderly output of the pulse lighting control signal in the entire lighting control chain, avoiding the simultaneous output of pulse signals from all chips, thereby effectively reducing electromagnetic interference (EMI) and the peak current of the smart lamp.

[0070] The embodiment of control based on the sequence delay value provides a flexible and precise way to manage the output timing of the pulse light control signal. It allows the main control chip to dynamically adjust the sequence delay value according to the specific lighting needs and link configuration, thereby optimizing the performance of the entire system. In addition, since the sequence delay value is pre-set and included in the hierarchical light control data, each unit control chip does not need to perform complex calculations or communication coordination, but only needs to simply read and apply its corresponding sequence delay value. This not only improves the chip execution efficiency, but also enhances the reliability and scalability of the execution. In this way, the smart lamps of the present application can significantly reduce electromagnetic interference while ensuring the lighting effect, improve the stability and reliability of the power supply system, and thus enhance the user experience.

[0071] In one embodiment, the unit control chip can be a mature programmable chip that pre-implements a reset synchronization function to meet product versatility requirements. This reset synchronization function is typically used to ensure that each unit control chip in the lighting control chain 20 can output pulsed lighting control signals almost simultaneously. However, in this application, to ensure that the output times of pulsed lighting control signals from adjacent unit control chips are dispersed, this reset synchronization function needs to be restricted. Therefore, the unit control chips in this embodiment are specifically configured to disable the reset synchronization function.

[0072] Specifically, the unit control chip disables the function of monitoring the silence duration of the data input port. This means that the chip does not detect the silence state of the data input port, thus avoiding the reset synchronization operation triggered by the silence duration reaching a certain threshold. In addition, the unit control chip also disables the function of triggering the pulse control signal based on the silence duration. This way, even if the data input port is silent, the chip will not automatically trigger the output of the pulse control signal, ensuring that the output timing of the pulse control signal is completely determined by the preset hysteresis.

[0073] As can be seen, even when the unit control chip has its own reset synchronization function, disabling the reset synchronization function allows the output timing of the pulse control signal to be independently controlled without being affected by the synchronization signals of other chips. This configuration allows each unit control chip to accurately determine the output timing of the pulse control signal based on the sequence delay value in the received hierarchical light control data or an internally preset lag time difference. In this way, the output timing of the pulse control signal in the entire light control chain 20 is orderly distributed, under the constraints of a time difference at least equal to the inherent internal processing delay of the unit control chip, effectively reducing electromagnetic interference (EMI) and the peak current of the power supply system. Therefore, disabling the reset synchronization function not only improves the flexibility and scalability of the light control chain 20, but also enhances its stability and reliability.

[0074] In one embodiment of the present application, to ensure the stability and reliability of the smart lighting fixture while optimizing electromagnetic interference performance and power system stress, the time interval (i.e., lag time) between the unit control chip receiving hierarchical lighting control data and outputting a pulsed lighting control signal is set within a preset time domain interval. The lower limit of this time domain interval is greater than twice the internal processing delay caused by the unit control chip processing the hierarchical lighting control data, while the upper limit is less than 50% of the product of the total number of cascaded unit control chips in the lighting control chain and the internal processing delay caused by the unit control chip processing the hierarchical lighting control data. This setting is intended to balance the smart lighting fixture's response speed and electromagnetic compatibility, ensuring that the output of the pulsed lighting control signal is neither too concentrated nor too slow.

[0075] Specifically, assuming the internal processing delay of a unit control chip is 80 nanoseconds, this means that each chip takes 80 nanoseconds to process the received hierarchical lighting control data and prepare to output a pulsed lighting control signal. To ensure sufficient time interval to reduce electromagnetic interference, the lower limit of the hysteresis time difference is set to twice the internal processing delay, or 160 nanoseconds. This way, each unit control chip outputs a pulsed lighting control signal at least 160 nanoseconds later than the previous unit control chip, effectively spreading the peak current of the power system and reducing electromagnetic interference.

[0076] To ensure response speed, the upper limit of the latency is set to less than 50% of the product of the total number of cascaded unit control chips in the lighting control chain and the internal processing delay. For example, if there are 100 unit control chips in the lighting control chain, the product of the total number of cascaded units and the internal processing delay is 8000 nanoseconds (100 x 80 nanoseconds). Therefore, the upper limit of the latency should be less than 4000 nanoseconds (50% of 8000 nanoseconds). This setting ensures that the response time of the entire lighting control chain will not be excessively slowed by excessive latency, thereby reducing electromagnetic interference while maintaining the efficiency of the lighting control chain and the user experience.

[0077] By setting this precise time interval, the unit control chip can output pulse control signals in an orderly manner after receiving the hierarchical lighting control data, after a preset hysteresis. This not only optimizes the electromagnetic compatibility of the smart lamp, but also ensures the stability and reliability of the system, while also avoiding excessive pressure on the power supply system caused by excessive pulse signal concentration.

[0078] In a more specific embodiment, the internal processing delay of the unit control chip is rated at 80±20 nanoseconds. To ensure that each unit control chip has sufficient time to process the hierarchical lighting control data and to avoid excessive signal output congestion caused by processing delays, the lag time difference is precisely set to 1000±200 nanoseconds. Furthermore, to further improve the stability and consistency of the link, the rising edge timing deviation of the pulse control signal is strictly controlled to within 1 / 10 of the lag time difference. This means that although there is a certain lag in the output of the pulse control signal from each chip, the rising edge timing deviation of these signals is very small, ensuring highly consistent signal output across the entire lighting control link, reducing electromagnetic interference and improving the stability and reliability of the lighting control link. Through this precise timing control, the unit control chip can output the pulse control signal in an orderly manner after receiving the hierarchical lighting control data, after a preset lag time difference. This not only optimizes the electromagnetic compatibility of the smart lighting fixture, but also ensures stability and reliability, while also avoiding excessive stress on the power supply system caused by excessive pulse signal congestion.

[0079] This application further provides a smart lamp control method, which can be implemented as a computer program and stored in the storage medium of the unit control chip of the smart lamp of this application. The unit control chip calls from the storage medium and runs it, so as to coordinate with other unit control chips in the light control chain to control the output timing of the pulse light control signal of each light emitting element, orderly control the operation of the light emitting elements in the entire light control chain, and achieve the purpose of reducing the electromagnetic interference effect of the smart lamp and improving the power supply stability of the smart lamp. Figure 5The intelligent lamp control method of the present application is applied to the unit control chip of the intelligent lamp of the present application, including:

[0080] Step S5100: receiving the hierarchical lighting control data provided by the front-stage control chip through the data input port;

[0081] As previously mentioned, hierarchical lighting control data is generated by the master control chip and sent to the lighting control link. This data contains lighting control data for each light-emitting unit, serving as lighting control instructions for adjusting parameters such as brightness and color. Each unit control chip has a distinct position in the lighting control link. It receives hierarchical lighting control data from the preceding control chip (the master control chip for the first unit control chip) through its data input port. This data is transmitted serially within the lighting control link, ensuring that each control chip receives its portion of the lighting control data.

[0082] In practice, a data input port is typically a physical interface, such as a pin or a group of pins, that receives data signals from the preceding control chip. These signals are encoded using a specific communication protocol, such as a serial communication protocol, in which data is transmitted bit by bit as a stream. The unit control chip is responsible for interpreting these signals and converting them into a data format that can be processed internally.

[0083] Step S5200: intercepting the current level light control data from the received hierarchical light control data, and forwarding the remaining hierarchical light control data to the subsequent control chip through the data output port;

[0084] When the unit control chip receives the hierarchical lighting control data sent by the previous control chip through its data input port, it analyzes this data and intercepts the data belonging to it from the received hierarchical lighting control data according to preset rules to obtain the current level lighting control data. This data contains all the necessary information for generating pulse lighting control signals, such as the brightness and color of the light-emitting components.

[0085] The interception process can be implemented in a variety of ways, and can be implemented using the following different embodiments as needed:

[0086] One embodiment is to intercept the first light control data in the received hierarchical light control data according to the arrangement position as the light control data of this level. Specifically, when the unit control chip receives the hierarchical light control data sent by the previous control chip through its data input port, it will parse the data and, based on the arrangement order of the data, intercept the light control data at the front as the light control data of this level. This method is suitable for the situation where the hierarchical light control data are arranged in sequence according to the cascade order of the unit control chips in the light control link. For example, assuming that there are 100 unit control chips in the light control link, the hierarchical light control data generated by the main control chip will contain the light control data of each unit control chip in turn. After receiving the data, each unit control chip will intercept the light control data arranged at the front, and this part of the data is the light control data of this level. Then, the unit control chip forwards the remaining data to the next control chip through the data output port. This method of intercepting according to the arrangement position is simple and direct, and can ensure that each unit control chip accurately obtains its own light control data.

[0087] Another embodiment uses relevant identifiers to identify and extract the corresponding unit control chip's own level of lighting control data. In this approach, when generating hierarchical lighting control data, the master control chip embeds an identifier in each light control data packet. This identifier indicates which unit control chip the packet belongs to. Upon receiving the hierarchical lighting control data, the unit control chip parses the data and searches for its own identifier. Once a matching identifier is found, the unit control chip extracts the light control data associated with that identifier as the current level of lighting control data. This approach provides greater flexibility and accuracy, especially when the hierarchical lighting control data includes data from multiple unit control chips. For example, if there are 100 unit control chips in a lighting control link, each light control data packet generated by the master control chip contains a unique identifier to distinguish between different unit control chips. Upon receiving the data, each unit control chip searches for a data packet that matches its own identifier and extracts the light control data contained therein as the current level of lighting control data. The unit control chip then forwards the remaining data to the subsequent control chip via its data output port. This identification method ensures that each unit control chip accurately obtains its own lighting control data, and maintains data accuracy and integrity even in complex lighting control links.

[0088] After intercepting the current-level lighting control data, the unit control chip needs to forward the remaining hierarchical lighting control data to the subsequent control chip through its data output port, so that the hierarchical lighting control data can be smoothly transmitted to each unit control chip along the lighting control link. When forwarding data, the unit control chip can perform necessary data processing, such as adding check bits and adjusting the data format, to ensure data integrity and accuracy.

[0089] For example, if there are 100 unit control chips in a lighting control chain, the hierarchical lighting control data generated by the master control chip will be transmitted sequentially through the data input port of each chip. After receiving the data, each unit control chip will perform necessary processing, such as data verification and decoding, to ensure data integrity and accuracy. Then, the unit control chip at that level will intercept its portion of the data for subsequent pulse control signal generation, while forwarding the remaining data to the next unit control chip through the data output port. And so on, so that each unit control chip can obtain the lighting control data it needs for its own level.

[0090] Step S5300: Generate a pulse light control signal according to the light control data of this level; after receiving the graded light control data from the data input port for a preset lag time, send the pulse light control signal through the pulse output port to drive the light emitting element of the light emitting unit of this level.

[0091] When the unit control chip receives the hierarchical lighting control data sent by the previous control chip through its data input port and intercepts its own level of lighting control data from it, it can generate a pulse lighting control signal based on this data. This level of lighting control data contains all the necessary information to generate the pulse lighting control signal, such as the brightness and color of the light-emitting element. The unit control chip can analyze this data and generate the corresponding pulse lighting control signal according to preset rules.

[0092] When generating pulse control signals, the unit control chip determines the output timing based on pre-set rules. To reduce electromagnetic interference and peak current in the power supply system, the unit control chip's pulse control signal output timing is designed to be evenly distributed along the time axis. This uniform distribution ensures relatively dispersed signal current, preventing simultaneous output of pulse signals from all unit control chips, effectively reducing electromagnetic interference and peak current in the power supply system.

[0093] In order to achieve this function, the unit control chip can use a variety of methods to determine the output time of the pulse light control signal. One embodiment is based on the clock synchronization signal issued by the main control chip. Before sending the hierarchical light control data, the main control chip will generate a clock synchronization signal and send this signal to the starting end of the light control link. After receiving the hierarchical light control data, each unit control chip will start an internal timer and start timing from the moment the clock synchronization signal is received. The hierarchical light control data output by the main control chip contains the sequence delay values ​​corresponding to the unit control chips at each level in the light control link, and these sequence delay values ​​constitute an arithmetic progression. Each unit control chip will extract the sequence delay value from the light control data at this level according to its position in the light control link, and generate and output the pulse light control signal when the timer reaches the sequence delay value. Since this sequence delay value includes the tolerance time accumulated according to the level position of the unit control chip and the preset lag time difference, and the tolerance time is greater than the internal processing delay corresponding to the unit control chip's own processing of the hierarchical lighting control data, this method ensures that the pulse lighting control signal output moments in the entire lighting control link are orderly, avoiding the simultaneous output of pulse signals from all chips, thereby effectively reducing electromagnetic interference and the peak current of the power supply system.

[0094] Another embodiment is to preset a fixed delay in each unit control chip, and this fixed delay is equal to the desired lag time difference. When the unit control chip receives the hierarchical lighting control data and intercepts the current level lighting control data, it will wait for a preset fixed delay time before generating a pulse lighting control signal. This fixed delay time is pre-set, and the length of this delay time is the same for all unit control chips. For example, assuming the fixed delay time is 1000 nanoseconds, each unit control chip will wait for 1000 nanoseconds after receiving the data before generating and outputting a pulse lighting control signal. This method also ensures that the pulse lighting control signal output moment of each unit control chip has a fixed lag time difference relative to the previous control chip, thereby avoiding the simultaneous output of pulse signals of all chips, effectively reducing electromagnetic interference and the peak current of the power supply system.

[0095] According to the above embodiments, by implementing the various steps of the intelligent lighting control method of the present application, significant technical advantages are achieved, which are mainly reflected in the following aspects:

[0096] First, by introducing a fixed hysteresis time difference in each unit control chip, the electromagnetic interference and power supply system stability problems existing in the prior art are effectively solved. In the traditional solution, all unit control chips output pulse light control signals almost simultaneously, resulting in excessively high peak currents in the power supply system, large spike currents and high-frequency ringing, which increases electromagnetic interference. However, by setting a fixed hysteresis time difference, the output time of the pulse light control signals of each unit control chip is reasonably distributed, avoiding the simultaneous output of pulse signals, significantly reducing the peak current and electromagnetic interference of the power supply system, and improving the electromagnetic compatibility of the intelligent lamp control link.

[0097] Secondly, this application improves the overall performance and reliability of smart lamps. Because the output timing of the pulse-controlled light signal is precisely controlled, problems such as flickering, uneven brightness, or abnormal colors caused by power supply fluctuations or electromagnetic interference are reduced. This makes the smart lamp more stable during operation and enhances the user experience. Furthermore, the evenly distributed peak current reduces pressure on the power supply module, improving its efficiency and lifespan, further enhancing the stability and reliability of the smart lamp.

[0098] Furthermore, this application offers high flexibility and scalability. By controlling the output timing of pulsed lighting control signals through a preset clock synchronization signal or a fixed delay time, the unit control chip can accurately generate pulse signals without the need for complex communication coordination. This design is not only applicable to simple linear lighting control links but can also be expanded to more complex lighting control systems with tree or other topological structures, providing broader development opportunities in the field of intelligent lighting.

[0099] Finally, this application achieves effective management of pulse-controlled lighting signals through software programs without adding additional hardware costs. The unit control chip can be a mature programmable chip, and the control method is executed through a computer program stored in its storage medium. This approach not only reduces product costs, but also simplifies product complexity and improves product market competitiveness.

[0100] Based on any embodiment of the method of the present application, a pulse light control signal is generated according to the current-level light control data, and after receiving the hierarchical light control data from the data input port for a preset hysteresis time difference, the pulse light control signal is sent through the pulse output port to drive the light-emitting elements of the current-level light-emitting units, including:

[0101] Step S5211: Acquire a data processing duration determined by a timer, wherein the timer starts to calculate the data processing duration from the moment when the hierarchical lighting control data from the data input port is received;

[0102] When the unit control chip receives the hierarchical lighting control data sent by the previous control chip through its data input port, it starts an internal timer. This timer starts counting from the moment the hierarchical lighting control data is received at the data input port and records the duration of data processing.

[0103] Therefore, the data processing duration is the time from when the unit control chip receives the graded lighting control data to when it decides to output the pulse control signal. By accurately measuring the data processing duration, the unit control chip can ensure that the pulse control signal is accurately output to the light-emitting element when the preset fixed delay time expires.

[0104] In actual implementation, the data processing duration can be obtained in a variety of ways. One embodiment uses a hardware timer within the unit control chip. This timer typically features high precision and low latency, accurately recording time intervals. For example, assume the unit control chip uses an internal hardware timer. When the data input port receives the hierarchical lighting control data, the timer starts counting. During the data processing process, the timer continues to run until the data processing is completed. At this point, the time recorded by the timer is the data processing duration.

[0105] Another embodiment uses a software timing mechanism to obtain data processing duration. In this approach, upon receiving hierarchical lighting control data, the unit control chip starts a software timer. This timer uses a software algorithm to calculate the time interval. While software timers may be slightly less accurate than hardware timers, they offer greater flexibility and configurability. For example, the unit control chip can use a software timer to measure the time from data reception to data processing completion using loop counting or other algorithms.

[0106] Step S5212: Detect whether the data processing duration reaches a preset hysteresis time difference. When the hysteresis time difference is reached, determine the current moment as the output moment of the pulse light control signal, and output the pulse light control signal generated according to the graded light control data at this output moment.

[0107] The unit control chip continuously monitors the data processing duration generated by the timer to determine whether it has reached the delay time corresponding to the preset fixed delay. The fixed delay is used to ensure that each unit control chip has a fixed time interval before forwarding the remaining graded light control data. This fixed time interval is the lag time difference that the present application expects to generate, and it is the same for each unit control chip in the light control link. For example, assuming that the fixed delay time is 1000 nanoseconds, the unit control chip will wait for 1000 nanoseconds after receiving the data before outputting the pulse light control signal. Since the unit control chip itself also has an internal processing delay in processing the graded light control data, the output moment of the pulse light control signal of each unit control chip will also have an interval time difference relative to the output moment of the previous control chip. This interval time difference can avoid the pulse signals of all chips being output almost at the same time, but instead act in each light-emitting unit relatively dispersedly along the time axis, so that the peak current of each light-emitting unit is more uniform overall, effectively reducing electromagnetic interference.

[0108] When the preset fixed delay time arrives, the unit control chip determines that the current moment is the output moment of the pulse light control signal, and outputs the pulse light control signal at this moment to drive the light-emitting elements of the light-emitting units at this level to work. In actual implementation, the unit control chip can use a variety of methods to generate pulse light control signals. One method is to directly generate pulse signals through hardware circuits. The advantages of this method are fast speed and high precision, and it is suitable for application scenarios with high real-time requirements. Another method is to generate pulse signals through software algorithms. The advantage of this method is high flexibility, and the parameters of the pulse signal can be adjusted through software updates, which is suitable for application scenarios that require frequent adjustments. Regardless of which method is used, the unit control chip needs to ensure that the output moment of the pulse light control signal is consistent with the preset fixed delay time.

[0109] In the above embodiment, the unit control chip begins calculating a fixed delay the moment it receives hierarchical lighting control data from its data input port. This design offers significant technical advantages. First, it ensures that each unit control chip can independently and accurately control the output timing of the pulsed lighting control signal, without relying on an external clock signal. This not only improves the organizational flexibility and scalability of the entire control chain, but also reduces reliance on external clock synchronization signals, reducing system design complexity and cost. Second, by using an internal timer to start timing from the moment data is received, the unit control chip can precisely control the interval between pulse signal outputs, thereby ensuring a high degree of consistency and regularity in the pulse signal output timing across the entire lighting control chain. This precise timing control effectively prevents simultaneous pulse signal output from all chips, reduces electromagnetic interference and peak current in the power supply system, and improves the electromagnetic compatibility and stability of the lighting control chain. Furthermore, this processing approach enhances the lighting control chain's anti-interference capabilities, as each chip initiates timing based on its own received data signal, reducing clock synchronization errors caused by external interference.

[0110] Based on any embodiment of the method of the present application, a pulse light control signal is generated according to the current-level light control data, and after receiving the hierarchical light control data from the data input port for a preset hysteresis time difference, the pulse light control signal is sent through the pulse output port to drive the light-emitting elements of the current-level light-emitting units, including:

[0111] Step S5221: extracting the sequence delay value and luminous parameters from the current-level light control data, wherein the sequence delay values ​​of the light control data at each level form an arithmetic progression, and the tolerance between the arithmetic progressions is greater than the internal processing delay caused by the unit control chip itself processing the hierarchical light control data. The sequence delay value of the first-level light control data is the sum of the tolerance and the preset lag time difference;

[0112] When the unit control chip receives the hierarchical light control data sent by the previous control chip through its data input port, it intercepts the light control data of its own level from it. In this embodiment, the light control data not only includes the luminous parameters used to generate the pulse light control signal, such as the brightness and color of the light-emitting element, but also includes the sequence delay value. The sequence delay value is a preset time value used to indicate the delay time of the pulse light control signal of the unit control chip relative to the link synchronization moment. The sequence delay values ​​of each level of light control data constitute an arithmetic progression, which means that the sequence delay value of each unit control chip corresponds to its position in the light control link, and the difference in delay values ​​between adjacent levels, that is, the tolerance, is a constant. The time structure of the sequence delay value includes the tolerance accumulation value corresponding to the level and the lag time difference expected to be achieved by this application, and the value range of this tolerance can be slightly larger than the internal processing delay corresponding to the unit control chip processing the hierarchical light control data, and the sequence delay value of the first-level light control data is the sum of the tolerance and the preset lag time difference.

[0113] The sequence delay values ​​in each level of lighting control data are set by the master control chip. For example, if there are 100 unit control chips in a lighting control chain, each data packet in the hierarchical lighting control data generated by the master control chip will contain a sequence delay value. After receiving the data, each unit control chip extracts the sequence delay value corresponding to itself, as well as the lighting parameters used to control the light-emitting elements. In this way, each unit control chip can accurately determine the output timing of its pulse lighting control signal based on its position in the lighting control chain.

[0114] Step S5222: Obtain the duration of the timer starting from the link synchronization moment, detect whether the duration reaches the duration corresponding to the sequence delay value, and determine the current moment as the output moment of the pulse light control signal when the duration reaches the duration. The link synchronization moment is the moment when the clock synchronization signal sent by the main control chip is received.

[0115] Before the master control chip sends hierarchical control data to the control chain, it first sends a clock synchronization signal to each unit control chip in the control chain. This clock synchronization signal provides a common time reference point for the entire control chain, ensuring that all unit control chips can determine the output timing of their pulse control signals based on the same time base.

[0116] When the unit control chip receives the clock synchronization signal from the main control chip, it starts an internal timer, counting from the moment the clock synchronization signal is received. The time recorded by this timer is the duration of the link synchronization. The unit control chip continuously monitors this duration to determine whether it has reached the preset sequence delay value.

[0117] When the duration recorded by the timer reaches the sequence delay value of the unit control chip, the unit control chip determines the current moment as the output time of the pulse control light signal. This output time is determined based on the clock synchronization signal, ensuring the orderly output time of the pulse control light signal in the entire light control chain, avoiding the simultaneous output of pulse signals from all chips, thereby effectively reducing electromagnetic interference and peak current of the power supply system.

[0118] Step S5223: at the output moment, the pulse light control signal generated according to the light-emitting parameters is transmitted to the corresponding light-emitting element via the pulse output port to control the operation of the light-emitting element.

[0119] When the preset sequence delay time arrives, the unit control chip will determine that the current moment is the output moment of the pulse light control signal, and output the pulse light control signal through the pulse output port at this moment to drive the light-emitting element of the light-emitting unit at this level to work. In actual implementation, the unit control chip can use a variety of methods to generate pulse light control signals. One method is to directly generate pulse signals through hardware circuits. The advantages of this method are fast speed and high precision, and it is suitable for application scenarios with high real-time requirements. Another method is to generate pulse signals through software algorithms. The advantage of this method is high flexibility, and the parameters of the pulse signal can be adjusted through software updates, which is suitable for application scenarios that require frequent adjustments. Regardless of which method is used, the unit control chip needs to ensure that the output moment of the pulse light control signal is consistent with the preset sequence delay time.

[0120] In the above embodiments, the unit control chips use the clock synchronization signal provided by the master control chip to determine the hysteresis time difference, rather than having the unit control chips insert a fixed delay themselves. This design offers significant technical advantages. First, through the clock synchronization signal provided by the master control chip, all unit control chips can determine the output timing of their pulse control signals based on the same time reference, thereby ensuring a high degree of consistency and regularity in the output timing of pulse signals throughout the entire lighting control chain. This unified time reference reduces synchronization errors caused by individual differences or clock drift between unit control chips, improving the stability and reliability of the chain. Second, it allows the master control chip to dynamically adjust the sequence delay value based on specific lighting requirements and chain configuration, enhancing controllability and optimizing overall system performance. For example, the master control chip can flexibly set the sequence delay value based on the actual length of the lighting control chain and the number of light-emitting units, ensuring that each unit control chip accurately outputs the pulse control signal at its predetermined time. Furthermore, the hysteresis time difference control mechanism based on the clock synchronization signal simplifies the design and implementation of the unit control chips, as each chip only needs to determine the output timing based on the received clock synchronization signal and the sequence delay value, eliminating the need for complex internal timing and delay insertion logic. This not only reduces chip complexity and cost, but also improves the scalability and flexibility of the system.

[0121] Based on any embodiment of the method of the present application, before receiving the hierarchical lighting control data provided by the front-stage control chip through the data input port, the method includes:

[0122] Step S4100: disabling the monitoring function of the silence duration of the data input port;

[0123] Mature programmable unit control chips on the market typically monitor the silence duration of their data input ports. This duration refers to the duration of time when the data input port receives no data signal. In traditional designs, when the silence duration reaches a certain threshold, the control chip may trigger a reset or other synchronization operation. However, to achieve precise pulse control of the light-emitting diode signal output, this step disables this monitoring function in the unit control chip. This is achieved by calling a pre-defined function interface. This means that the chip does not detect the silence state of the data input port, thus avoiding the reset synchronization operation triggered by the silence duration reaching a certain threshold.

[0124] Step S4200: Turn off the function of triggering the pulse light control signal based on the silence duration.

[0125] After disabling the monitoring function of the unit control chip, the corresponding preset function interface is further called to disable the function of triggering the pulse control signal based on the silence duration. This means that the chip will not automatically trigger the output of the pulse control signal based on the silence state of the data input port, but will determine the output time according to the preset rules.

[0126] The technical advantage of disabling silence duration monitoring and the function that triggers pulse control signals based on silence duration is that they allow the unit control chip to determine the output timing of the pulse control signal based on preset rules, rather than relying on the silence state of the data input port. This not only improves system flexibility and scalability, but also reduces synchronization errors and unnecessary reset operations caused by silence duration monitoring. For example, in complex lighting control links, the silence duration may vary due to various factors (such as data transmission delays and signal interference). Disabling this function can prevent these factors from affecting the output timing of the pulse control signal.

[0127] By disabling the function that triggers pulse control signals based on silence duration, the unit control chip can more precisely control the output timing of the pulse control signals, ensuring that the pulse signal output timing of the entire lighting control chain is orderly, avoiding the simultaneous output of pulse signals from all chips, and effectively reducing electromagnetic interference and peak current of the power supply system. This not only improves the stability and reliability of smart lamps, but also enhances their anti-interference capabilities, allowing them to maintain excellent performance under various operating conditions.

[0128] It should be noted that the various related configurations in the various embodiments of the smart lamp of the present application can be implemented in the specific execution link of the smart lamp control method of the present application. Therefore, the various embodiments of the smart lamp of the present application are also applicable to the smart lamp control method of the present application.

[0129] See also Figure 6 , an intelligent lamp control device provided to meet one of the purposes of the present application is a functional embodiment of the intelligent lamp control method of the present application, the device includes a data receiving module 5100, a hierarchical forwarding module 5200, and a light control module 5300, wherein the data receiving module 5100 receives the hierarchical light control data provided by the previous control chip through the data input port; the hierarchical forwarding module 5200 is configured to intercept the current level light control data from the received hierarchical light control data, and forward the remaining hierarchical light control data to the subsequent control chip through the data output port; the light control module 5300 is configured to generate a pulse light control signal according to the current level light control data, and after receiving the hierarchical light control data from the data input port and reaching a preset lag time difference, send the pulse light control signal through the pulse output port to drive the light-emitting element of the current level light-emitting unit.

[0130] Based on any embodiment of the device of the present application, the light control module 5300 includes: a receiving timing module, which is configured to obtain the data processing duration determined by the timer, and the timer calculates the data processing duration from the moment when the graded light control data of the data input port is received; a delayed forwarding module, which is configured to detect whether the data processing duration reaches a preset lag time difference, and when the lag time difference is reached, determines the current moment as the output moment of the pulse light control signal, and outputs the pulse light control signal generated according to the graded light control data at this output moment.

[0131] Based on any embodiment of the device of the present application, the light control module 5300 includes: a data extraction module, configured to extract a sequence delay value and a light-emitting parameter from the light-control data of the current level, wherein the sequence delay values ​​of the light-control data of each level constitute an arithmetic progression, and the tolerance between the arithmetic progressions is greater than the internal processing delay caused by the unit control chip itself processing the hierarchical light-control data, and the sequence delay value of the first-level light-control data is the sum of the tolerance and a preset lag time difference; a synchronization timing module, configured to obtain the duration of the timer starting from the link synchronization moment, detect whether the duration reaches the duration corresponding to the sequence delay value, and determine the current moment as the output moment of the pulse light-control signal when it reaches the moment, wherein the link synchronization moment is the moment when the clock synchronization signal sent by the main control chip is received; a pulse output module, configured to transmit the pulse light-control signal generated according to the light-control parameters to the corresponding light-emitting element via the pulse output port at the output moment to control the operation of the light-emitting element.

[0132] Based on any embodiment of the device of the present application, the device of the present application also includes: a monitoring disabling module, which is configured to disable the monitoring function of the silence period of the data input port; and a trigger shutdown module, which is configured to shut down the function of triggering the pulse light control signal based on the silence period.

[0133] In order to solve the above technical problems, the embodiment of the present application also provides a computer device. Figure 7 As shown, a schematic diagram of the internal structure of a computer device. The computer device includes a processor, a computer-readable storage medium, a memory, and a network interface connected via a system bus. The computer-readable storage medium of the computer device stores an operating system, a database, and computer-readable instructions. The database may store a control information sequence. When the computer-readable instructions are executed by the processor, the processor may implement an intelligent lamp control method. The processor of the computer device is used to provide computing and control capabilities to support the operation of the entire computer device. The memory of the computer device may store computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor may execute the intelligent lamp control method of the present application. The network interface of the computer device is used to connect and communicate with a terminal. Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0134] In this embodiment, the processor is used to execute Figure 6The memory stores the program code and various data required to execute the specific functions of each module and its submodule. The network interface is used to transmit data between user terminals or servers. The memory in this embodiment stores the program code and data required to execute all modules / submodules in the intelligent lighting control device of this application. The server can call the server's program code and data to execute the functions of all submodules.

[0135] The present application also provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors execute the steps of the smart lighting control method of any embodiment of the present application.

[0136] Those skilled in the art will appreciate that all or part of the processes in the above-described embodiments of the present application can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes in the above-described embodiments of the method. The aforementioned storage medium can be a computer-readable storage medium such as a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0137] Those skilled in the art will understand that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be interchanged, changed, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, changed, rearranged, decomposed, combined, or deleted. Furthermore, the steps, measures, and schemes in the various operations, methods, and processes in the prior art that are open source and disclosed in this application may also be interchanged, changed, rearranged, decomposed, combined, or deleted.

[0138] The above description is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A smart lamp comprising a main control chip and multiple light-emitting units, each light-emitting unit comprising a unit control chip and a light-emitting element driven by a pulsed light-control signal generated by the unit control chip. The unit control chips of the multiple light-emitting units are cascaded and connected to the main control chip to form a light-control link. The main control chip is used to send hierarchical light-control data to the light-control link. The invention is characterized by: Each unit control chip is configured to receive the hierarchical light control data provided by the previous control chip through the data input port, intercept the current level light control data therefrom, and forward the remaining hierarchical light control data to the next level control chip through the data output port; Each unit control chip is configured to generate a pulse light control signal based on the intercepted light control data of this level, and after receiving the hierarchical light control data from the data input port for a preset hysteresis time difference, send the pulse light control signal through the pulse output port to drive the light emitting element of the light emitting unit of this level; Among them, it also includes: the unit control chip is configured to start a timer after receiving the hierarchical lighting control data from the data input port, and output a pulse lighting control signal generated according to the current level lighting control data after the timer reaches a preset lag time difference; or it also includes: the hierarchical lighting control data output by the main control chip contains a sequence delay value corresponding to the unit control chips at each level in the lighting control link, and the unit control chip is configured to determine the output time of the corresponding pulse lighting control signal based on the time when the main control chip sends a clock synchronization signal, and compare it with the sequence delay value in the current level lighting control data to generate the lag time difference.

2. The intelligent lamp according to claim 1, characterized in that: The unit control chip is configured to disable the reset synchronization function, including: Disable the monitoring function of the silent period of the data input port; Disable the function of triggering the pulse light control signal based on the silence duration.

3. The intelligent lamp according to claim 1 or 2, characterized in that: The hysteresis time difference is configured so that the peak current of each light emitting unit is evenly distributed on the time axis.

4. The intelligent lamp according to claim 1 or 2, characterized in that: The lag time difference takes values ​​within a preset time domain interval, the lower limit of which is greater than twice the internal processing delay caused by the unit control chip itself processing the hierarchical lighting control data, and the upper limit is less than 50% of the product of the total number of cascaded unit control chips in the lighting control link and the internal processing delay.

5. The intelligent lamp according to claim 1 or 2, characterized in that: The internal processing delay caused by the unit control chip itself processing the graded lighting control data is 80±20ns, the hysteresis time difference is 1000±200ns, and the rising edge time deviation of the pulse lighting control signal is less than 1 / 10 of the hysteresis time difference.

6. A smart lamp control method, applied to the unit control chip of the smart lamp according to claim 1, characterized in that: include: Receive the hierarchical lighting control data provided by the front-stage control chip through the data input port; Intercepting the current level light control data from the received hierarchical light control data, and forwarding the remaining hierarchical light control data to the subsequent control chip through the data output port; A pulse light control signal is generated according to the light control data of this level. After the hierarchical light control data is received from the data input port for a preset lag time difference, the pulse light control signal is sent through the pulse output port to drive the light-emitting element of the light-emitting unit of this level.

7. The intelligent lighting control method according to claim 6, characterized in that: Generate a pulse light control signal according to the current level light control data, and send the pulse light control signal through the pulse output port to drive the light emitting element of the current level light emitting unit after receiving the hierarchical light control data from the data input port and reaching a preset hysteresis time difference, including: Obtaining a data processing duration determined by a timer, wherein the timer starts to calculate the data processing duration from the moment when the hierarchical lighting control data is received from the data input port; Detect whether the data processing duration reaches a preset hysteresis time difference. When the hysteresis time difference is reached, determine the current moment as the output moment of the pulse light control signal, and output the pulse light control signal generated according to the graded light control data at this output moment.

8. The intelligent lighting control method according to claim 6, characterized in that: Generate a pulse light control signal according to the current level light control data, and send the pulse light control signal through the pulse output port to drive the light emitting element of the current level light emitting unit after receiving the hierarchical light control data from the data input port and reaching a preset hysteresis time difference, including: Extracting a sequence delay value and a luminous parameter from the current-level light control data, wherein the sequence delay values ​​of the light control data at each level form an arithmetic progression, and the tolerance between the arithmetic progressions is greater than the internal processing delay caused by the unit control chip itself processing the hierarchical light control data, and the sequence delay value of the first-level light control data is the sum of the tolerance and a preset lag time difference; Obtaining a duration counted by a timer starting from a link synchronization moment, detecting whether the duration reaches a duration corresponding to the sequence delay value, and determining the current moment as an output moment of the pulse light control signal when the duration reaches a duration corresponding to the sequence delay value, wherein the link synchronization moment is a moment when a clock synchronization signal sent by a main control chip is received; At the output moment, the pulse light control signal generated according to the light-emitting parameters is transmitted to the corresponding light-emitting element via the pulse output port to control the operation of the light-emitting element.

9. The intelligent lighting control method according to any one of claims 6 to 8, characterized in that: Before receiving the hierarchical lighting control data provided by the front-stage control chip through the data input port, it includes: Disable the monitoring function of the silent period of the data input port; Disable the function of triggering the pulse light control signal based on the silence duration.

10. A computer-readable storage medium, characterized in that It stores a computer program implemented according to the method described in any one of claims 6 to 9 in the form of computer-readable instructions, and when the computer program is called and executed by a computer, the steps included in the corresponding method are executed.

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