Storage array, memory and electronic equipment

Abstract

The invention provides a storage array, a memory and electronic equipment, and relates to the technical field of semiconductors. The stacking structure of the storage array comprises a plurality of electrode layers and a plurality of insulating layers which are sequentially and alternately arranged in a stacked mode in the third direction, the electrode layers comprise a plurality of first electrodes and a plurality of second electrodes, and the first electrodes and the second electrodes are sequentially and alternately arranged at intervals in the second direction. Each storage structure is arranged between the first electrode and the second electrode and penetrates through the stacking structure, the storage structure comprises a gate structure and a channel layer, the gate structure penetrates through the stacking structure, and the channel layer is arranged around the gate structure and makes contact with the first electrode and the second electrode. Wherein the channel layers in contact with the first electrodes and the second electrodes in different electrode layers are mutually disconnected in the third direction, so that the crosstalk problem caused by mutual connection of a plurality of channel layers can be avoided, and the stacking layer number and the integration density of the storage array can be further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a storage array, a memory, and an electronic device. Background Art

[0002] With the continuous evolution of process nodes, the size reduction of planar structured memory has reached its limit, making it difficult to further increase its storage density and capacity. The original bottleneck can be broken through through the three-dimensional integration method, that is, stacking multiple memory devices in the vertical direction. However, the channels of multiple memory devices between the layers of the three-dimensional integrated memory are interconnected, which makes it easy for crosstalk to occur between memory devices in different layers, thereby limiting the increase in the number of stacked layers of memory devices and further improving the storage density of the memory. Summary of the Invention

[0003] This application proposes a storage array, a memory, and an electronic device, aiming to avoid the crosstalk problem of the channel layer and further increase the number of stacking layers and storage density.

[0004] In a first aspect, a storage array is provided, comprising a stacked structure and a plurality of storage structures, wherein the stacked structure comprises a plurality of electrode layers and a plurality of insulating layers alternately and stacked in sequence along a third direction, the electrode layer comprises a plurality of first electrodes and a plurality of second electrodes, the plurality of first electrodes and the plurality of second electrodes alternately and spaced in sequence along a second direction, and the second direction is perpendicular to the third direction. Each storage structure penetrates the stacked structure, the plurality of storage structures are arranged in an array along the first direction and the second direction, and each storage structure is arranged between the first electrode and the second electrode; the storage structure comprises a gate structure and a channel layer, the gate structure penetrates the stacked structure, the channel layer is arranged around the gate structure and contacts the first electrode and the second electrode, respectively, the first direction is perpendicular to the third direction and intersects with the second direction. The channel layers contacted by the first electrode and the second electrode in different electrode layers are disconnected from each other in the third direction.

[0005] In the above-mentioned embodiments of the present application, the channel layers in different electrode layers that are in contact with the first electrode and the second electrode are disconnected from each other along the third direction. For example, multiple channel layers in different electrode layers in the third direction are spaced apart to separate the multiple channel layers in different electrode layers from each other. This can avoid crosstalk problems caused by the interconnection of multiple channel layers, thereby facilitating further improving the number of stacking layers and the integration density of the storage array.

[0006] In some embodiments, the storage array further includes:

[0007] The isolation layer is provided on a portion of the surface of the channel layer except for a portion in contact with the first electrode and the second electrode.

[0008] In some embodiments, the storage array further includes:

[0009] The insulating structure is arranged between the first electrode and the second electrode and between two adjacent storage structures; the insulating structure runs through the stacked structure.

[0010] In some embodiments, the stack structure is provided with an opening, and the storage structure is disposed in the opening; the electrode layer is provided with a groove, which is disposed on the inner wall of the opening and surrounds the storage structure;

[0011] The channel layer is filled in the groove, and the channel layers filled in the grooves of two adjacent electrode layers are spaced apart by an insulating layer.

[0012] In some embodiments, the memory array further includes an isolation layer and an insulating structure;

[0013] The groove includes a first sub-groove and a second sub-groove, the first sub-groove is opened in the first electrode and the second electrode, the side wall of the insulating structure close to the opening is spaced apart from the storage structure, and a portion of the insulating structure located in the electrode layer and the insulating layer form the second sub-groove;

[0014] The isolation layer is disposed on an inner wall of the second sub-groove and on an inner wall of the first sub-groove formed of the insulating layer.

[0015] In some embodiments, each electrode layer further includes a bit line and a source line, and the bit line and the source line are arranged along the first direction on both sides of the region where the plurality of first electrodes and the plurality of second electrodes are located;

[0016] The bit line is electrically connected to one end of the plurality of first electrodes and spaced apart from one end of the plurality of second electrodes; the source line is electrically connected to the other end of the plurality of second electrodes and spaced apart from the other end of the plurality of first electrodes.

[0017] In some embodiments, the gate structure includes a gate, a blocking layer, a charge storage layer, and a tunneling layer stacked in an annular manner, and the channel layer surrounds the surface of the tunneling layer;

[0018] The charge storage layer is a floating gate structure or a charge trap structure.

[0019] In a second aspect, an embodiment of the present application further provides a memory, which includes the memory array in the above embodiment and a peripheral circuit, wherein the peripheral circuit is electrically connected to the memory array.

[0020] The memory has a memory array that is stacked vertically and whose channel layers are disconnected from each other. This structural feature can improve the storage density and reliability of the memory.

[0021] In a third aspect, an embodiment of the present application further provides an electronic device, which includes the memory in the above embodiment and a bus, wherein the bus is electrically connected to the memory.

[0022] The above electronic device has the same structure and beneficial technical effects as the memory provided in some of the above embodiments, which will not be repeated here.

[0023] In a fourth aspect, an embodiment of the present application further provides a method for preparing a storage array, comprising:

[0024] forming an initial stacking structure; the initial stacking structure comprises a plurality of dielectric layers and a plurality of sacrificial layers alternately and stacked in sequence along a third direction;

[0025] A plurality of storage structures are formed that penetrate the initial stacked structure; the plurality of storage structures penetrate the initial stacked structure; the plurality of storage structures are arranged in an array along a first direction and a second direction; the storage structure includes a gate structure and a channel layer, the gate structure penetrates the initial stacked structure, and the channel layer is arranged around the gate structure; the first direction and the second direction intersect and are both perpendicular to the third direction;

[0026] The sacrificial layer is replaced with an electrode layer; each electrode layer includes a plurality of first electrodes and a plurality of second electrodes, and the plurality of first electrodes and the plurality of second electrodes are alternately and spaced apart along a second direction; each storage structure is disposed between the first electrode and the second electrode and is in contact with the first electrode and the second electrode respectively;

[0027] The channel layers contacted by the first electrode and the second electrode in different electrode layers are disconnected from each other in the third direction.

[0028] In some embodiments, forming a plurality of storage structures through the initial stacked structure includes:

[0029] forming a first slot; the first slot includes an opening and a groove, the opening passes through the initial stacking structure, and the groove is arranged on the inner wall of the opening and is located on the same layer as the sacrificial layer;

[0030] filling the first trench with a channel material;

[0031] The portion of the channel material located in the opening is removed to form the channel layer.

[0032] The above-mentioned memory array preparation method is simple to operate and easy to implement. In the memory array prepared by this method, multiple channel layers of different electrode layers are disconnected from each other in the third direction, which can avoid the crosstalk problem caused by the interconnection of multiple channel layers, and is conducive to further improving the number of stacking layers and integration density of the memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application. For those skilled in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and do not represent the actual dimensions of the products or the actual processes of the methods involved in the embodiments of this application.

[0034] Figure 1 A schematic diagram of the structure of a storage array provided in this application;

[0035] Figure 2 for Figure 1 A cross-sectional view of the memory array along section line DD';

[0036] Figure 3 for Figure 1 A cross-sectional view of the memory array along section line CC';

[0037] Figure 4 for Figure 1 A schematic diagram of the storage structure of the storage array in FIG.

[0038] Figure 5 for Figure 1 A circuit diagram of a storage array in FIG.

[0039] Figure 6 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0041] Figure 8 A flow chart of a method for preparing a memory array provided in an embodiment of the present application;

[0042] Figures 9 to 20 are Figure 8 The steps of the preparation method are shown. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0045] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0046] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0047] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0048] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0049] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the areas of regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0050] With the continuous evolution of semiconductor manufacturing process nodes, the size of existing memories continues to shrink in order to continuously improve the storage density of memories. In the pursuit of extreme miniaturization, the size reduction of memories has gradually approached the physical limit. Taking planar NOR Flash devices as an example, they face the bottleneck of further reducing the device size at the 28nm process node, making the process of planar Flash devices difficult to be compatible with the FinFET transistor process of more advanced process nodes, thereby limiting the further improvement of NOR Flash storage density and capacity.

[0051] To this end, attempts have been made to prepare memories using a three-dimensional integration method to significantly improve storage density, storage capacity, and application scenarios. However, existing three-dimensional integrated memories, such as three-dimensional integrated NOR Flash, do not separate the Flash device channels between each layer, which will cause crosstalk problems, thereby limiting the number of stacking layers of the memory array and further improving the storage density.

[0052] To solve the above problems, the present invention provides a storage array. Figure 1 A schematic diagram of the structure of a storage array provided in an embodiment of the present application is provided. Figure 2 for Figure 1 A cross-sectional view of the memory array along the section line DD' in FIG. Figure 3 for Figure 1 A cross-sectional view of the memory array along the section line CC', Figure 4 for Figure 1 A schematic diagram of the storage structure of the storage array in FIG. Figure 5 for Figure 1 Circuit diagram of the storage array in .

[0053] like Figures 1 to 3 As shown, the memory array 100 includes a stacking structure S1 and a storage structure S2.

[0054] The stacked structure S1 includes multiple insulating layers 1 and multiple electrode layers 2. These insulating layers 1 and electrode layers 2 can be alternately and stacked in sequence along a third direction. In this way, while improving the storage density of the memory, the breakdown risk can be reduced and charge leakage can be avoided, thereby enhancing data stability and improving the voltage resistance and reliability of the memory.

[0055] like Figures 1 to 3 As shown, the third direction here is the vertical direction, for example, Figure 1 The direction Z in .

[0056] For example, in Figure 1 In the embodiment, along the direction Z, an insulating layer 1 and an electrode layer 2 may be sequentially arranged to form a stacked structure S1.

[0057] Exemplarily, the material of the insulating layer 1 may include non-metallic multinary compounds and metallic multinary compounds. For example, the non-metallic multinary compounds in the insulating layer 1 may be silicon oxide (SiOx), silicon nitride (SiNx), phosphorus oxide (POx), and silicon oxynitride (SiNxOy), etc., and the metallic multinary compounds in the insulating layer 1 may be aluminum oxide (AlOx), titanium oxide (TiOx), yttrium oxide (YOx), and other metallic multinary compounds. The embodiments of the present application do not limit this. In actual use, personnel in this field can select corresponding materials according to actual needs.

[0058] Exemplarily, the material of the electrode layer 1 may include metals and their alloys, and metallic compounds. For example, the metal in the electrode layer 2 may be platinum (Pt), palladium (Pd), iridium (Ir), tantalum (Ta), hafnium (Hf), titanium (Ti), zirconium (Zr), tungsten (W), ruthenium (Ru) and aluminum (Al), etc. The metallic oxide in the electrode layer 2 may be titanium nitride (TiN), tantalum nitride (TaN) and polycrystalline silicon (Poly-Si), etc. The embodiments of the present application do not limit this. In actual use, personnel in this field can select corresponding materials according to actual needs.

[0059] For example, Figure 2 and Figure 5 As shown, the electrode layer 2 may include a plurality of first electrodes 21 and a plurality of second electrodes 22 .

[0060] The first electrode 21 here can be regarded as a drain of the storage structure S2 , and the second electrode 22 can be regarded as a source of the storage structure S2 .

[0061] For example, the constituent materials of the first electrode 21 and the second electrode 22 may be the same as the constituent materials of the electrode layer 2 , that is, they may be metals, alloys thereof, and metallic compounds.

[0062] For example, Figure 2 and Figure 5 As shown, along the second direction, multiple first electrodes 21 and multiple second electrodes 22 can be arranged alternately and at intervals, that is, in the second direction, a first electrode 21 can be set first, and then a second electrode 22 can be set, and there is a distance interval between adjacent first electrodes 21 and second electrodes 22. In this way, the setting of multiple first electrodes 21 and multiple second electrodes 22 is completed alternately in sequence, so that the setting of subsequent storage structures S2 can be better adapted, so that multiple storage structures S2 set at different positions can be electrically connected.

[0063] Among them, the distance intervals between adjacent first electrodes 21 and second electrodes 22 in the multiple first electrodes 21 and the multiple second electrodes 22 can be consistent, that is, fixed distance intervals, or the distance intervals are different, but can also adapt to the setting of the storage structure S2. This application does not impose any restrictions on this.

[0064] The second direction may be a planar direction and perpendicular to the third direction, for example, Figure 2 in the direction Y.

[0065] For example, in Figure 2In the figure, the electrode layer 2 includes two first electrodes 21 and two second electrodes 22. Along the direction Y, from top to bottom, a first electrode 21 is first set at a certain distance, and then a second electrode 22 is set. After a certain distance, another first electrode 21 is set, and another second electrode 22 is set after a certain distance.

[0066] like Figures 1 to 5 As shown, the memory array 100 in the above embodiment may include multiple memory structures S2, and these memory structures S2 may penetrate the stacking structure S1 along the third direction to achieve stacking of multiple memory structures S2 in the vertical direction, thereby improving the storage density of the memory. Figure 1 In the figure, along the direction Z, the four storage structures S2 are stacked through the stacking structure S1.

[0067] The storage structure S2 may be a transistor, such as a charge-trap transistor (CTT), which is used to store and retain data and supports data reading and writing operations, thereby realizing data storage and access.

[0068] For example, Figures 1 to 3 As shown, along the third direction, the storage structure S2 may be a vertical ring structure so that it penetrates the stacking structure S1 .

[0069] For example, Figures 1 to 5 As shown, the above-mentioned multiple storage structures S2 can be regularly arranged along the first direction and the second direction to form an ordered array, for example, an N*N array or an N*M array. In this way, not only can more storage structures S2 be set in a limited space to improve storage density, but also data management can be simplified and the efficiency of data access can be improved.

[0070] The first direction here may be a planar direction, and this direction intersects with the second direction and is perpendicular to the third direction, for example, Figure 2 The direction X in .

[0071] For example, Figure 5 As shown, in each layer, 3 rows of storage structures S2 are sequentially arranged along direction X, and m / 3 columns of storage structures S2 are sequentially arranged along direction Y, where m is a multiple of 3, forming a 3*(m / 3) array.

[0072] For example, Figure 1 、 Figure 3 and Figure 5 As shown, after a plurality of storage structures S2 are arrayed along the first direction and the second direction, a storage structure S2 array is formed, and the array can be stacked along the third direction. Figure 5In the example, after forming a 3*(m / 3) array along the X and Y directions, n 3*(m / 3) arrays are stacked along the Z direction to form n layers.

[0073] For example, Figures 1 to 5 As shown, along the second direction, each storage structure S2 may be disposed between the first electrode 21 and the second electrode 22 to ensure that each storage structure S2 can be electrically connected.

[0074] The number of the first electrodes 21 and the second electrodes 22 may be the same as the number of columns of the storage structure S2 array in the second direction, so that each column of storage structures S2 in the second direction may be disposed between the first electrodes 21 and the second electrodes 22 .

[0075] For example, in Figure 5 In each layer, along the direction Y, the storage structure S2 in the first column can be set between the first first electrode 21 and the first second electrode 22, and so on. The storage structures S2 in the remaining (m / 3-1) columns can be set in sequence between (m / 3-1) first electrodes 21 and (m / 3-1) second electrodes 22, where m is a multiple of 3.

[0076] like Figures 1 to 4 As shown, the storage structure S2 in the above embodiment includes a gate structure 3 and a channel layer 4 .

[0077] The gate structure 3 here may penetrate the stack structure S1 along the third direction to adapt to the storage structure S2 that penetrates the stack structure S1 along the third direction.

[0078] For example, Figure 2 and Figure 4 As shown, the gate structure 3 can be a ring-shaped stacked structure for storing and reading data. Figure 4 In the embodiment, the gate structure 3 can be formed by sequentially surrounding multiple layers.

[0079] like Figures 1 to 4 As shown, the channel layer can be a ring structure and be arranged around the gate structure 3, that is, the channel layer 4 can be arranged around the periphery of the gate structure 3 and pass through the stacking structure S1, so that the gate structure 3 can more evenly control the electric field distribution of the channel layer 4, realize the electrical connection between the storage structure S2 and the circuit, and improve the integration and stability of the storage structure S2.

[0080] For example, Figures 1 to 4 As shown, the channel layer 4 can be in contact with the first electrode 21 and the second electrode 22 along the second direction, respectively, to ensure the integrity of the storage structure S2, thereby achieving electrical connection between the storage structure S2 and the circuit, for example, Figure 2In the direction Y, the upper arc of the channel layer 4 contacts the first electrode 21 , and the lower arc of the channel layer 4 contacts the second electrode 22 .

[0081] For example, Figures 1 to 3 As shown, along the third direction, in different electrode layers 2, channel layers 4 in contact with the first electrode 21 and the second electrode 22 can be arranged at intervals, that is, in the third direction, multiple channel layers 4 of multiple storage structures S2 in different electrode layers 2 are disconnected from each other to avoid the multiple channel layers 4 being connected to each other and forming crosstalk.

[0082] For example, in Figure 1 In the figure, along the direction Z, from top to bottom, the channel layer 4 in the first electrode layer 2 is spaced a certain distance from the channel layer 4 in the second electrode layer 2, and the channel layer 4 in the second electrode layer 2 is spaced a certain distance from the channel layer 4 in the third electrode layer 2, and thus multiple channel layers 4 of different electrode layers 2 are arranged in sequence.

[0083] Exemplarily, the channel layer 4 may include semiconductor materials, oxide transistor materials, and two-dimensional materials. For example, the semiconductor material in the channel layer 4 may be silicon (Si), polycrystalline silicon (Poly-Si), silicon carbide (SiC), gallium nitride (GaN), and germanium (Ge), etc. The oxide transistor material may be indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium tungsten oxide (IWO), etc. The two-dimensional material may be graphene, molybdenum disulfide (MoS), and hexagonal boron nitride (h-BN), etc. The embodiment of the present application is not limited to this.

[0084] It can be understood that along the third direction, the channel layers in different electrode layers that are in contact with the first electrode and the second electrode are disconnected from each other. For example, multiple channel layers in different electrode layers in the third direction are spaced apart to separate the multiple channel layers in different electrode layers from each other. This can avoid crosstalk problems caused by the interconnection of multiple channel layers, thereby helping to further improve the number of stacking layers and the integration density of the storage array.

[0085] In some embodiments, as Figure 4 As shown, the gate structure 3 includes a gate 31 , a blocking layer 32 , a charge storage layer 33 and a tunneling layer 34 .

[0086] The gate 31 , the blocking layer 32 , the charge storage layer 33 and the tunneling layer 34 are stacked in an annular manner in sequence and extend along the third direction to form a cylindrical gate structure 3 .

[0087] The gate 31 may be a control gate for electrically connecting to a word line to control the on and off of the transistor.

[0088] Illustratively, the gate 31 may be composed of metal, its alloys, or metallic compounds, that is, it may be the same as or different from the material of the electrode layer 2 , and this application does not impose any limitation on this.

[0089] Exemplarily, the constituent materials of the barrier layer 32 and the tunneling layer 34 can be the same, and both can be composed of non-metallic multinary compounds and metallic multinary compounds, that is, the constituent materials of the barrier layer 32 and the tunneling layer 34 can be the same as or different from the materials of the insulating layer 1, and this application does not impose any restrictions on this.

[0090] The blocking layer 32 is used to isolate the charge storage layer 33 and the gate 31 to prevent leakage current, thereby improving the reliability of the device.

[0091] The tunneling layer 34 can facilitate the movement of electrons between the channel layer 4 and the charge storage layer 33 and isolate the charges in the charge storage layer 33 , thereby preventing charge leakage and ensuring the charge storage performance of the charge storage layer 34 .

[0092] For example, Figure 4 As shown, the channel layer 4 may surround the surface of the tunnel layer 34 so that electrons in the channel layer 4 may tunnel through the layer 34 .

[0093] The charge storage layer 33 in the above embodiment is used to store charges to achieve data storage.

[0094] Exemplarily, the charge storage layer 33 may be a floating gate structure, so that the charge storage layer 33 can store charges.

[0095] Alternatively, illustratively, the charge storage layer 33 is a charge trap structure, which can enhance the reliability of the gate structure 3 while ensuring that the charge storage layer 33 stores charges. This embodiment of the present application is not limited to this.

[0096] In some embodiments, as Figure 1 、 Figure 2 、 Figure 3 and Figure 5 As shown, the electrode layer 2 in the above embodiment further includes a bit line 23 and a source line 24 .

[0097] For example, Figure 1 、 Figure 3 and Figure 5 As shown, each electrode layer 2 may include a bit line 23 and a source line 24. For example, Figure 5 In the figure, along the direction Z, the first electrode layer 2 includes a bit line 23 (BL1) and a source line 24 (SL1), the second electrode layer 2 includes a bit line 23 (BL2) and a source line 24 (SL2), ..., the nth electrode layer 2 includes a bit line 23 (BLn) and a source line 24 (SLn).

[0098] The bit line 23 may be used to electrically connect to the drain of the storage structure S2 , and the source line 24 may be used to electrically connect to the source of the storage structure S2 .

[0099] Exemplarily, the materials of the bit line 23 and the source line 24 may be the same as the materials of the gate 31 , for example, both may be composed of metals, alloys thereof, and metallic compounds.

[0100] For example, Figure 2 As shown, the bit lines 23 and source lines 24 in each electrode layer 2 can be respectively arranged on both sides of the areas where the multiple second electrodes 22 and the multiple first electrodes 21 are located along the first direction, so that the bit lines 23 and source lines 24 can be electrically connected to the multiple storage structures S2 along the second direction.

[0101] Among them, such as Figure 2 and Figure 5 As shown, the plurality of first electrodes 21 and the plurality of second electrodes 22 may extend along the first direction to achieve contact with the plurality of storage structures S2 , thereby controlling the plurality of storage structures S2 .

[0102] For example, Figure 2 In the figure, the two first electrodes 21 and the two second electrodes 22 extend along the direction X, wherein, in the Y direction, from top to bottom, the first first electrode 21 and the first second electrode 22 are in contact with the three storage structures within the distance between them, the first second electrode 22 and the second first electrode 21 are in contact with the two storage structures S2 within the distance between them, and the second first electrode 21 and the second second electrode 22 are in contact with the three storage structures S2 within the distance between them.

[0103] In the above embodiment, the region where the plurality of second electrodes 22 and the plurality of first electrodes 21 are located may be the total region occupied by the plurality of first electrodes 21 and the plurality of second electrodes 22 after extending along the first direction. For example, Figure 2 In FIG, the two first electrodes 21 and the two second electrodes 22 are both extended along the direction X and occupy a rectangular area.

[0104] For example, Figure 2 and Figure 5 As shown, the bit lines 23 and source lines 24 in each electrode layer 2 can be extended along the second direction, so that the multiple first electrodes 21 and the multiple second electrodes 22 in each electrode layer 2 can be electrically connected to the same bit line 23 and source line 24, so that all storage structures S2 in each electrode layer 2 can be controlled by one bit line 23 and source line 24, thereby improving the integration of the product while reducing the difficulty of management.

[0105] For example, Figure 2In the embodiment, the bit line 23 and the source line 24 extend along the direction Y. The bit line 23 is electrically connected to the two first electrodes 21 , and the source line 24 is electrically connected to the two second electrodes 22 .

[0106] For example, Figure 2 As shown, along the first direction, in each electrode layer 2, the bit line 23 can be electrically connected to one end of multiple first electrodes 21 in the layer, and spaced apart from one end of multiple second electrodes 22 in the layer to ensure that the bit line 23 remains disconnected from the second electrode 22 while being electrically connected to the first electrode 21.

[0107] For example, Figure 2 In the embodiment, along the direction X, the bit line 23 can be electrically connected to the left ends of the two first electrodes 21 at the same time, while maintaining a certain distance from the left ends of the two second electrodes 22 .

[0108] For example, Figure 2 and Figure 5 As shown, along the first direction, in each electrode layer 2, the source line 24 can be electrically connected to the other end of the multiple second electrodes 22 in the layer, and spaced apart from the other end of the multiple first electrodes 21 in the layer to ensure that the source line 24 remains disconnected from the first electrode 21 while being electrically connected to the second electrode 22.

[0109] For example, Figure 2 In the figure, along the direction X, the source line 24 can be electrically connected to the right ends of the two second electrodes 22 at the same time, while maintaining a certain distance from the right ends of the two first electrodes 21.

[0110] For example, Figure 2 As shown, the spacing distance between the bit line 23 and one end of the multiple second electrodes 22 can be the same as or different from the spacing distance between the source line 24 and one end of the multiple first electrodes 21, but it can ensure that the bit line 23 and the multiple second electrodes 22 remain disconnected, and the source line 24 and the multiple first electrodes 21 remain disconnected. This application does not impose any restrictions on this.

[0111] For example, Figure 2 As shown, the bit line 23 in each electrode layer 2 can be integrally arranged with the multiple first electrodes 21 in the layer, and similarly, the source line 24 can be integrally arranged with the multiple second electrodes 22 in the layer, that is, the bit line 23 and the multiple first electrodes 21 in each electrode layer 2 respectively belong to different parts of the same conductive line, and the source line 24 and the multiple second electrodes 22 respectively belong to different parts of the same conductive line. In this way, not only can the connection points between components be reduced, the reliability of the memory array 100 can be improved, but also the preparation cost can be reduced.

[0112] For example, Figure 2In the figure, along the direction X, there are two finger-shaped conductors on the left and right, where the left side of the left finger-shaped conductor is the bit line 23, and the extension along the direction Y is a plurality of first electrodes 21. Correspondingly, the right side of the right finger-shaped conductor is the source line 24, and the extension along the direction Y is a plurality of second electrodes 22.

[0113] In some embodiments, as Figures 1 to 3 As shown, the memory array 100 further includes an isolation layer 5 .

[0114] In which, the isolation layer 5 can be arranged on a partial surface of each channel layer 4, and this portion of the channel layer 4 does not contact the first electrode 21 and the second electrode 22, so as to isolate multiple channel layers 4 in different electrode layers 2 and ensure that the multiple channel layers 2 are disconnected from each other.

[0115] For example, Figure 2 In the figure, along direction Y, the upper arc portion of the channel layer 4 contacts the first electrode 21, and the lower arc portion of the channel layer 4 contacts the second electrode 22. In addition to the above-mentioned upper arc portion and lower arc portion, an isolation layer 5 is provided on the surface of other parts of the channel layer 4.

[0116] Exemplarily, the isolation layer 5 can be composed of a material with insulating properties, which is used to separate multiple channel layers 2 in different electrode layers 2, thereby avoiding the interconnection of multiple channel layers and causing crosstalk, such as silicon dioxide, silicon nitride and other materials. This application does not limit this material.

[0117] In some embodiments, as Figures 1 to 3 As shown, the memory array 100 further includes an insulating structure 6 .

[0118] For example, Figure 2 As shown, the insulating structure 6 can be simultaneously arranged between the first electrode 21 and the second electrode 22, between two adjacent storage structures 2, in the gap between the bit line 23 and one end of the multiple second electrodes 22, and in the gap between the source line 24 and one end of the multiple first electrodes 21, so as to facilitate the photolithography pattern when preparing the storage array 100, thereby forming multiple first electrodes 21 and multiple second electrodes 22.

[0119] For example, in Figure 2 In the area formed by the bit line 23, the outermost first electrode 21, the source line 24 and the outermost second electrode 22 in each electrode layer 2, except for the partial area occupied by the bit line 23, the source line 24, multiple first electrodes 21, multiple second electrodes 22, multiple storage structures S2 and the isolation layer 4, the remaining area can be provided with an insulating structure 6.

[0120] Illustratively, the constituent material of the insulating structure 6 may be the same as that of the insulating layer 1 , such as silicon oxide, silicon nitride, and zirconium oxide, etc., which is not limited in the embodiment of the present application.

[0121] For example, Figure 1 and Figure 3 As shown, the insulating structure 6 in each electrode layer 2 can extend along the third direction to penetrate the stack structure S1 , thereby accommodating the storage structure S2 penetrating the stack structure S1 along the third direction.

[0122] After the insulating structure 6 penetrates the stacked structure S1 , the multi-layer insulating layer 1 also includes the insulating structure 6 .

[0123] In some embodiments, as Figure 1 As shown, the stacking structure S1 in the above embodiment is provided with a plurality of openings K1, and a plurality of storage structures S2 can be arranged in each opening K1, so that the plurality of storage structures S2 can pass through the stacking structure S1, thereby realizing stacking a plurality of storage structures S2 along the third direction. Figure 1 In the embodiment, four storage structures S2 can be set in each opening K1.

[0124] For example, Figures 1 to 3 As shown, a groove 7 is provided in each electrode layer 2. The groove 7 can be arranged on the inner wall of the opening K1 and is arranged around the gate structure 3 of the storage structure S2 of the electrode layer 2 to form an annular structure so as to subsequently fill the channel material to form the channel layer 4 of the storage structure S2.

[0125] The annular structure here can be filled with channel material to form the channel layer 4 of the storage structure S2.

[0126] For example, Figure 1 In the embodiment, a groove 7 is formed on the side of the electrode layer 2 facing the opening K1 , which is concave relative to the side of the insulating layer 1 facing the opening K1 .

[0127] For example, Figure 2 As shown, in each electrode layer 2, an isolation layer 5 can be provided on the inner wall of a portion of the groove 7 near the insulating structure 6 to ensure that the insulating structure 6 is isolated from the channel layer 4, thereby facilitating the disconnection of multiple channel layers 4. For example, Figure 2 In the figure, along the direction X, the channel layer 4 in the left and right regions of the storage structure S2 is close to the insulating structure 6, and the isolation layer 5 is provided on the inner wall of the groove 7 in the above region.

[0128] For example, Figure 1 and Figure 3As shown, along the third direction, in two adjacent electrode layers 2, two channel layers 4 formed by filling the grooves 7 in each electrode layer 2 with channel material can be spaced apart by the insulating layer 1 between the two adjacent electrode layers 2, that is, an insulating layer 1 is placed between the two channel layers 4 to achieve mutual disconnection of multiple channel layers 4 in different electrode layers 2, thereby avoiding crosstalk.

[0129] For example, ions may be injected between the channel layers 4 in two adjacent electrode layers 2 to disconnect the two channel layers 4 from each other, or other methods may be used to ensure that the channel layers 4 in two adjacent electrode layers 2 are disconnected from each other. This application does not impose any restrictions on this.

[0130] In some embodiments, as Figures 1 to 3 As shown, the groove 7 in the above embodiment includes a first sub-groove 71 and a second sub-groove 72 .

[0131] For example, Figure 1 and Figure 2 As shown, the first sub-groove 71 can be set in the first electrode 21 and the second electrode 22. The partial channel layer 4 formed after the channel material is filled in the first sub-groove 71 can connect the first electrode 21 and the second electrode 22 respectively, thereby ensuring that the storage structure S2 can contact the first electrode 21 and the second electrode 22 respectively.

[0132] For example, Figure 1 As shown, part of the inner wall of the first sub-groove 71 may be formed by the insulating layer 1, for example, Figure 1 In the embodiment, along the direction Z, the upper and lower inner walls of the first sub-groove 71 are formed by the upper and lower insulating layers 1 adjacent to the electrode 2 .

[0133] For example, Figure 2 and Figure 3 As shown, the second sub-groove 72 can be surrounded by a partial insulating structure 7 and an insulating layer 1 located in the electrode layer 2, that is, along the third direction, the partial insulating structure 6 close to the storage structure S2 in each electrode layer 2 and the two insulating layers 1 adjacent to each electrode layer 2 can constitute the second sub-groove 72.

[0134] For example, Figure 3 As shown, in each electrode layer 2, the side wall of the insulating structure 6 close to the opening K1 can be spaced apart from the storage structure S2, that is, there is a gap between the side wall of the insulating structure 6 close to the opening K1 and the storage structure S2, so as to facilitate the subsequent setting of the isolation layer 5.

[0135] For example, Figures 1 to 3As shown, an isolation layer 5 can be provided on the inner wall of the second sub-groove 72 and the inner wall of the first sub-groove 71 formed by the insulating layer 1. In this way, while ensuring that the storage structure S2 of each electrode layer is electrically connected to the bit line 23 and the source line 24, the multiple channel layers 4 in different electrode layers 2 can be disconnected from each other to avoid crosstalk between the multiple channel layers 4.

[0136] For example, Figure 1 In the middle, along the direction Z, an isolation layer 4 is provided on the upper and lower inner walls of the first sub-groove 71. Figure 3 In the embodiment, an isolation layer 4 is provided on the inner wall of the second sub-groove 72 .

[0137] The embodiment of the present application also provides a memory, Figure 6 A schematic diagram of the structure of the memory provided in an embodiment of the present application.

[0138] like Figure 6 As shown, the memory 200 includes the memory array 100 and a peripheral circuit E in the above embodiment.

[0139] The memory array 100 is disposed on a substrate P.

[0140] The peripheral circuit E can be electrically connected to the memory array 100 and can realize functions such as selecting the storage structure S2 in the memory array 100 and controlling the operation timing, thereby ensuring the accuracy and orderliness of data reading and storage.

[0141] The memory 200 includes a memory array 100 stacked in a vertical direction with channel layers disconnected from each other. This structural feature can improve the storage density and reliability of the memory 200.

[0142] The embodiment of the present application also provides an electronic device, Figure 7 This is a structural diagram of an electronic device provided in an embodiment of the present application.

[0143] like Figure 7 As shown, the electronic device 300 includes the memory 200 and a bus D in the above embodiment.

[0144] The bus D is electrically connected to the memory 100 and is used to implement the transmission of data, addresses and control signals between the CPU or other host devices and the memory 100 .

[0145] By adopting a memory 200 with high storage density, the electronic device 300 can significantly enhance the data processing speed, multi-tasking capability, and application loading efficiency of the electronic device 300, thereby providing users with a smoother and more efficient user experience.

[0146] This application also provides a storage array preparation method, Figure 8 As shown, Figure 8 A schematic diagram of a process for preparing a storage array provided in an embodiment of the present application, FIG9 to FIG20 are Figure 8 Diagram of each step of the preparation method shown.

[0147] like Figure 8 As shown, the preparation method includes the following steps S11 to S13:

[0148] Step S11: As shown in FIG9 , an initial stacking structure S0 is formed.

[0149] Figure 9b for Figure 9a A cross-sectional view of the initial stacking structure along section line AA'.

[0150] For example, Figure 9a and Figure 9b As shown, dielectric materials and sacrificial layer materials can be alternately grown in sequence along the third direction to form multiple dielectric layers a1 and multiple sacrificial layers a2. These multiple dielectric layers a1 and multiple sacrificial layers a2 are alternately stacked along the third direction to form an initial stacking structure S0.

[0151] The multi-layer dielectric layer a1 herein is the multi-layer insulating layer 1 .

[0152] Step S12: As shown in Figures 10 to 14, a plurality of storage structures S2 are formed that penetrate the initial stacking structure S0. The plurality of storage structures S2 all penetrate the initial stacking structure S0. The plurality of storage structures S2 are arranged in an array along the first direction and the second direction. The storage structure S2 includes a gate structure 3 and a channel layer 4. The gate structure 3 penetrates the initial stacking structure S0, and the channel layer 4 is arranged around the gate structure 3. The first direction and the second direction intersect and are both perpendicular to the third direction.

[0153] Exemplarily, forming a plurality of storage structures S2 that penetrate the initial stacking structure S0 includes steps S121 to S124:

[0154] Step S121: as shown in FIG. 10 and FIG. 11 , a first groove is formed by photolithography and etching processes, and the first groove includes an opening K1 .

[0155] Figure 10b for Figure 10a The cross-section of the initial stacking structure along the section line AA', Figure 10c for Figure 10a 11 to 13 are cross-sectional views of the initial stacking structure along the section line BB′, and the section lines of FIG. 11 to FIG. 13 are the same as those of FIG. 10 .

[0156] For example, Figure 10a 、 Figure 10b and Figure 10cAs shown, a hole K1 is opened on the initial stacking structure S0 through photolithography and etching processes, and the hole K1 penetrates the initial stacking structure S0 along the third direction, so that a plurality of storage structures S2 can be subsequently arranged.

[0157] For example, Figure 11a 、 Figure 11b and Figure 11c As shown, the multi-layer sacrificial layer a2 is selectively etched by an etching process to form a groove 7, which is arranged on the inner wall of the opening K1 and is located in the same layer as the sacrificial layer a2, for example, Figure 11b As shown, the side surface of each sacrificial layer a2 facing the opening K1 is recessed relative to the side surface of each dielectric layer a1 facing the opening K1 to form a groove 7 .

[0158] Step S122: Figure 12a 、 Figure 12b and Figure 12c As shown, a material with insulating properties, such as silicon oxide, silicon carbide, etc., is isotropically grown or deposited to form an isolation layer 5, and then semiconductor materials, oxide transistor materials and two-dimensional materials, such as silicon, polysilicon, indium gallium zinc oxide, molybdenum disulfide and hexagonal boron nitride, are isotropically grown or deposited to form a channel layer 4.

[0159] Step S123: Figure 13a 、 Figure 13b and Figure 13c As shown, the opening K1 can be anisotropically etched through an etching process, for example, etching is performed along the direction Z to remove the insulating material, semiconductor material, oxide transistor material and two-dimensional material on the inner wall of the opening K1 outside the groove 7, thereby disconnecting the multiple channel layers 4 of different sacrificial layers a2 from each other.

[0160] Figure 14b for Figure 14a The enlarged view of the initial stacking structure at P, Figure 14c for Figure 14a A cross-sectional view of the initial stacking structure along section line EE'.

[0161] Step S124: Figure 14a 、 14b and Figure 14c As shown, insulating material, charge trap material, insulating material and word line material can be deposited in each opening K1 in sequence to form a tunneling layer 34, a charge storage layer 33, a blocking layer 32 and a gate 31 in sequence to constitute the gate structure 3 of the storage structure S2, thereby forming multiple storage structures S2.

[0162] Exemplarily, the insulating material may include non-metallic multinary compounds and metallic multinary compounds, such as silicon oxide, silicon nitride, aluminum oxide, and yttrium oxide; the charge trap material may include nitrides and oxides, such as silicon nitride, aluminum oxide, and hafnium oxide; the word line material may include metals and their alloys, metallic compounds, such as platinum, palladium, iridium, tantalum, hafnium, and aluminum; and metallic compounds such as titanium nitride, tantalum nitride, and polysilicon; and the present application does not impose any restrictions on this.

[0163] Figure 15b for Figure 15a The cross-section of the initial stacking structure along the section line DD', Figure 15c for Figure 15a 16 to 20 are cross-sectional views of the initial stacking structure along the section line CC′, and the section lines of FIG. 16 to FIG. 20 are the same as those of FIG. 15 .

[0164] For example, as shown in FIG15 , the above-mentioned multiple storage structures S2 all penetrate the initial stacking structure S0 along the third direction, and the channel layers 4 of the multiple storage structures S2 in different sacrificial layers a2 are disconnected from each other, thereby avoiding the crosstalk problem caused by the mutual connection of multiple channel layers 4.

[0165] Illustratively, after forming multiple storage structures S2, the multiple storage structures S2 can be regularly arranged along the first direction and the second direction to form an ordered array, for example, an N*N array or an N*M array. In this way, not only can more storage structures S2 be set in a limited space to improve storage density, but also data management can be simplified and data access efficiency can be improved.

[0166] The first direction here may be a planar direction, and this direction intersects with the second direction and is perpendicular to the third direction, for example, Figure 14a The direction X in .

[0167] For example, Figure 5 As shown, in each layer, 3 rows of storage structures S2 are sequentially arranged along direction X, and m / 3 columns of storage structures S2 are sequentially arranged along direction Y, where m is a multiple of 3, forming a 3*(m / 3) array.

[0168] Step S13: As shown in Figures 16 to 20, the sacrificial layer a2 is replaced with the electrode layer 2, each electrode layer 2 includes a plurality of first electrodes 21 and a plurality of second electrodes 22, and the plurality of first electrodes 21 and the plurality of second electrodes 22 are alternately and spaced in sequence along the second direction, and each storage structure S2 is arranged between the first electrode 21 and the second electrode 22, and is in contact with the first electrode 21 and the second electrode 22, respectively, wherein the channel layers 4 contacted by the first electrode 21 and the second electrode 22 in different electrode layers are disconnected from each other in the third direction.

[0169] Exemplarily, the sacrificial layer a2 is replaced with the electrode layer 2, that is, a stacked structure S1 is formed, including steps S131 to S135:

[0170] Step S131: Figure 16a 、 Figure 16b and Figure 16c As shown, each sacrificial layer a2 is selectively etched by photolithography and etching processes to form an interdigitated structure in each sacrificial layer a2, for example, Figure 16a In the two interdigitated finger-like structures, along direction X, the interdigitated finger-like structure on the left can be composed of structure a21 and structure a23, and the interdigitated finger-like structure on the right can be composed of structure a22 and structure a24.

[0171] For example, Figure 16a As shown, after the interdigital structure is formed in the sacrificial layer a2 by etching, the remaining portion of the sacrificial layer a2 except the interdigital structure and the storage structure S2 is a trench structure a6, so that it can be subsequently filled with insulating material to form an insulating structure 6.

[0172] Step S132: Figure 17a 、 Figure 17b and Figure 17c As shown, insulating materials such as non-metallic multi-component compounds such as silicon oxide, silicon nitride, phosphorus oxide, and silicon oxynitride, as well as metallic multi-component compounds such as aluminum oxide, titanium oxide, and yttrium oxide are deposited to fill the trench structure a6, thereby forming an insulating structure 6.

[0173] Step S133: Figure 18a 、 Figure 18b and Figure 18c As shown, each sacrificial layer a2 is etched by an etching process, that is, each sacrificial layer a2 can be isotropically etched to remove the sacrificial material in each sacrificial layer a2 to form a structure a8, for example, Figure 19b In the figure, two interdigitated finger-like structures are not filled with any material so that the electrode layer 2 can be formed later.

[0174] Step S134: Figure 19a 、 Figure 19b and Figure 19c As shown, the isolation layer 5 of the storage structure S2 is patterned. For example, an etching process is used to selectively etch the isolation layer 5 to form a first sub-groove 71 and a second sub-groove 72 .

[0175] Exemplarily, the first sub-groove 71 and the second sub-groove 72 are different parts of the groove 7 , wherein the isolation layer 5 is retained on the inner wall of the first sub-groove 71 formed by the dielectric layer a1 , for example, Figure 19aAlong the direction Z, the isolation layer 5 is retained on the upper and lower inner walls of the first sub-groove 71, and the isolation layer 5 is removed from the sidewalls of the first sub-groove 71 so as to contact the first electrode 21 and the second electrode 22 to achieve electrical connection of the storage structure S2.

[0176] Here, the second sub-groove 72 is a portion of the groove 7 excluding the first sub-groove 71 .

[0177] In this way, selective etching is performed to provide an isolation layer 5 in the groove 7, thereby ensuring that the multiple storage structures S2 can contact the first electrode 21 and the second electrode 22, while also disconnecting the channel layers of the multiple storage structures S2 from each other to avoid crosstalk.

[0178] Step S135: Figure 20a 、 Figure 20b and Figure 20c As shown, metals and their alloys, metallic compounds, such as platinum, palladium, iridium, tantalum, hafnium and aluminum, and metallic compounds such as titanium nitride, tantalum nitride and polysilicon are deposited to form a first electrode 21, a second electrode 22, a bit line 23 and a source line 24, so that the sacrificial layer a2 is converted into an electrode layer 2, thereby forming a stacked structure S1, for example, Figure 19b As shown, metals such as platinum, palladium, iridium, tantalum, hafnium and aluminum, and metallic compounds such as titanium nitride, tantalum nitride and polysilicon are deposited in structure a8.

[0179] Illustratively, each electrode layer 2 may include a plurality of first electrodes 21 , a plurality of second electrodes 22 , a bit line 23 and a source line 24 .

[0180] Among them, the multiple first electrodes 21 in each electrode layer 2 are electrically connected to the same bit line 23, and the multiple second electrodes 22 are electrically connected to the same source line 24, so that the multiple storage structures S2 in each electrode layer 2 can be controlled by one bit line 23 and one source line 24 to simplify management.

[0181] Exemplarily, as shown in FIG. 20 , the plurality of first electrodes 21 and the plurality of second electrodes 22 in each electrode layer 2 may be alternately arranged in sequence along the second direction to accommodate the arrangement of the plurality of storage structures S2 in each electrode layer 2 .

[0182] For example, as shown in FIG. 20 , each storage structure S2 may be disposed between the first electrode 21 and the second electrode 22 and contact the first electrode 21 and the second electrode 22 , respectively, to ensure that each storage structure S2 can be electrically connected.

[0183] Illustratively, after forming the multi-layer electrode layer 2, along the third direction, the channel layers 4 contacted by the first electrode 21 and the second electrode 22 in different electrode layers 2 are disconnected from each other, that is, in the third direction, the channel layers 4 of the multiple storage structures S2 in different electrode layers 2 are separated from each other, thereby avoiding crosstalk caused by the mutual connection of the channel layers 4 in the third direction.

[0184] At this point, the storage array 100 is completed.

[0185] The above-mentioned preparation method is simple to operate and easy to implement. In the storage array 100 prepared by this method, multiple channel layers 4 of different electrode layers 2 are disconnected from each other in the third direction, which can avoid the crosstalk problem caused by the mutual connection of multiple channel layers 4, and is conducive to further improving the number of stacking layers and integration density of the storage array 100.

[0186] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that: include: A stacked structure comprising a plurality of electrode layers and a plurality of insulating layers alternately and stacked in sequence along a third direction; the electrode layers comprising a plurality of first electrodes and a plurality of second electrodes, the plurality of first electrodes and the plurality of second electrodes alternately and spaced apart in sequence along a second direction; the second direction being perpendicular to the third direction; a plurality of storage structures, each storage structure extending through the stacked structure; the plurality of storage structures being arranged in an array along a first direction and a second direction, and each storage structure being disposed between the first electrode and the second electrode; the storage structure comprising a gate structure and a channel layer, the gate structure extending through the stacked structure, the channel layer being disposed around the gate structure and contacting the first electrode and the second electrode, respectively; The first direction is perpendicular to the third direction and intersects with the second direction; The channel layers contacted by the first electrode and the second electrode in different electrode layers are disconnected from each other in the third direction.

2. The storage array according to claim 1, wherein: Also includes: An isolation layer is provided on a portion of the surface of the channel layer except for a portion in contact with the first electrode and the second electrode.

3. The storage array according to claim 1, wherein: Also includes: an insulating structure, disposed between the first electrode and the second electrode, and between two adjacent storage structures; The insulating structure penetrates the stack structure.

4. The storage array according to claim 1, wherein: The stack structure is provided with an opening, and the storage structure is arranged in the opening; the electrode layer is provided with a groove, and the groove is arranged on the inner wall of the opening and is arranged around the storage structure; The channel layer is filled in the groove, and the channel layers filled in the grooves of two adjacent electrode layers are spaced apart by the insulating layer.

5. The storage array according to claim 4, wherein: The memory array further includes an isolation layer and an insulating structure; The groove includes a first sub-groove and a second sub-groove, the first sub-groove is opened in the first electrode and the second electrode, the side wall of the insulating structure close to the opening is spaced apart from the storage structure, and a portion of the insulating structure located in the electrode layer and the insulating layer form the second sub-groove; The isolation layer is disposed on an inner wall of the second sub-groove, and on an inner wall of the first sub-groove formed by the insulating layer.

6. The storage array according to claim 1, wherein: Each electrode layer further includes a bit line and a source line, wherein the bit line and the source line are arranged along the first direction on both sides of the region where the plurality of first electrodes and the plurality of second electrodes are located; The bit line is electrically connected to one end of the plurality of first electrodes and spaced apart from one end of the plurality of second electrodes; the source line is electrically connected to the other end of the plurality of second electrodes and spaced apart from the other end of the plurality of first electrodes.

7. The storage array according to claim 1, wherein: The gate structure includes a gate, a blocking layer, a charge storage layer and a tunneling layer stacked in an annular manner, and the channel layer surrounds the surface of the tunneling layer; The charge storage layer is a floating gate structure or a charge trap structure.

8. A memory, characterized in that: include: The storage array according to any one of claims 1 to 7; The peripheral circuit is electrically connected to the memory array.

9. An electronic device, characterized in that: include: The memory according to claim 8; A bus is electrically connected to the memory.

10. A method for preparing a storage array, characterized in that: include: forming an initial stacking structure; The initial stacking structure includes multiple dielectric layers and multiple sacrificial layers alternately and stacked in sequence along the third direction; forming a plurality of storage structures penetrating the initial stacked structure; the plurality of storage structures penetrating the initial stacked structure; the plurality of storage structures being arranged in an array along a first direction and a second direction; the storage structure comprising a gate structure and a channel layer, the gate structure penetrating the initial stacked structure, and the channel layer being arranged around the gate structure; the first direction and the second direction intersecting and being perpendicular to the third direction; The sacrificial layer is replaced with an electrode layer; each electrode layer includes a plurality of first electrodes and a plurality of second electrodes, and the plurality of first electrodes and the plurality of second electrodes are alternately and spaced apart along the second direction; each storage structure is disposed between the first electrode and the second electrode, and is in contact with the first electrode and the second electrode respectively; The channel layers contacted by the first electrode and the second electrode in different electrode layers are disconnected from each other in the third direction.

11. The preparation method according to claim 10, characterized in that: The forming of a plurality of storage structures penetrating the initial stacking structure comprises: forming a first slot; the first slot includes an opening and a groove, the opening penetrating the initial stacking structure, the groove being arranged on an inner wall of the opening and being located on the same layer as the sacrificial layer; filling the first groove with a channel material; The portion of the channel material located in the opening is removed to form the channel layer.

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