Memory device

Abstract

A memory device according to an embodiment includes a substrate, a plurality of first conductor layers (22), a plurality of memory pillars (MP), a plurality of first pillars (HR), and a plurality of second pillars (DMP). The substrate includes a first region (MA), a second region (BA), and a third region (HA) arranged in this order in a first direction. The first conductor layers are arranged in the second direction above the substrate. A plurality of storage pillars are disposed in the first area. The plurality of memory pillars each have a portion that intersects the plurality of first conductor layers, and include a laminated film (42). A plurality of first pillars are disposed in the second region and the third region. Each of the plurality of first pillars has a portion that intersects at least a portion of the plurality of first conductor layers, and is of a different configuration from the memory pillars. A plurality of second pillars are disposed in the second region. The plurality of second pillars each have a portion intersecting at least one of the plurality of first conductor layers, and include a laminated film.

Description

Technical Field

[0001] Embodiments relate to memory devices. Background Art

[0002] NAND flash memories capable of storing data in a nonvolatile manner are known. Summary of the Invention

[0003] The memory device of the embodiment includes: a substrate, multiple first conductive layers, multiple memory pillars, multiple first pillars, and multiple second pillars. The substrate includes a first region, a second region, and a third region arranged in sequence in a first direction. The first conductive layer is arranged above the substrate in a second direction intersecting with the first direction. Multiple memory pillars MP are arranged in the first region. Each of the multiple memory pillars has a portion intersecting with the multiple first conductive layers and includes a stacked film 42. Multiple first pillars are arranged in the second region and the third region. Each of the multiple first pillars has a portion intersecting with at least a portion of the multiple first conductive layers and has a different structure from the memory pillars. Multiple second pillars are arranged in the second region. Each of the multiple second pillars has a portion intersecting with at least one of the multiple first conductive layers and includes a stacked film. As a result, the manufacturing cost of the memory device can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 This is a block diagram showing an example of the overall configuration of a storage system including the storage device according to the first embodiment. Figure 2 This is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the memory device according to the first embodiment. Figure 3 This is a perspective view showing an example of the appearance of the memory device according to the first embodiment. Figure 4 It is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment. Figure 5 It is a plan view showing an example of a planar layout in a storage region of a memory cell array included in the memory device according to the first embodiment. Figure 6 An example of a cross-sectional structure of a memory region of a memory cell array included in the memory device according to the first embodiment is shown. Figure 5 Cross-sectional view along line VI-VI. Figure 7 An example of a cross-sectional structure of a memory pillar included in the memory device according to the first embodiment is shown along the Figure 6 Cross-sectional view along line VII-VII. Figure 8This is a plan view showing an example of a planar layout near a boundary region of a memory cell array included in the memory device according to the first embodiment. Figure 9 An example of a cross-sectional structure near a boundary region of a memory cell array included in the memory device according to the first embodiment is shown. Figure 8 Cross-sectional view along line IX-IX. Figure 10 This is a cross-sectional view illustrating an example of the cross-sectional structure of the memory device according to the first embodiment. Figure 11 It is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment during the manufacturing process. Figure 12 An example of a cross-sectional structure of a memory cell array included in the memory device according to the first embodiment during the manufacturing process is shown. Figure 11 Cross-sectional view along line XII-XII. Figure 13 It is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment during the manufacturing process. Figure 14 An example of a cross-sectional structure of a memory cell array included in the memory device according to the first embodiment during the manufacturing process is shown. Figure 13 Cross-sectional view along line XIV-XIV. Figure 15 It is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment during the manufacturing process. Figure 16 An example of a cross-sectional structure of a memory cell array included in the memory device according to the first embodiment during the manufacturing process is shown. Figure 15 Cross-sectional view along line XVI-XVI. Figure 17 This is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment during the manufacturing process. Figure 18 An example of a cross-sectional structure of a memory cell array included in the memory device according to the first embodiment during the manufacturing process is shown. Figure 17 Cross-sectional view along line XVIII-XVIII. Figure 19 This is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment during the manufacturing process. Figure 20An example of a cross-sectional structure of a memory cell array included in the memory device according to the first embodiment during the manufacturing process is shown. Figure 19 Cross-sectional view of line XX-XX. Figure 21 It is a plan view showing an example of a planar layout of a memory cell array according to the first comparative example. Figure 22 is an example of a cross-sectional structure of a memory cell array according to the first comparative example, along Figure 21 Cross-sectional view along line XXII-XXII. Figure 23 It is a plan view showing an example of a planar layout of a memory cell array according to a second comparative example. Figure 24 is an example of a cross-sectional structure of a memory cell array according to the second comparative example, along Figure 23 Cross-sectional view along line XXIV-XXIV. Figure 25 This is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to the second embodiment. Figure 26 This is a cross-sectional view illustrating an example of a cross-sectional structure near a boundary region of a memory cell array included in the memory device according to the second embodiment. Figure 27 This is a cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the second embodiment during the manufacturing process. Figure 28 This is a cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the second embodiment during the manufacturing process. Figure 29 This is a cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the second embodiment during the manufacturing process. Figure 30 This is a cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the second embodiment during the manufacturing process. Figure 31 This is a cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the second embodiment during the manufacturing process. Figure 32 This is a cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the second embodiment during the manufacturing process. Figure 33 This is a cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the second embodiment during the manufacturing process. Figure 34 It is a plan view showing an example of a planar layout of a memory cell array according to the first modification. Figure 35 An example of a cross-sectional structure of a memory cell array according to the first modification is shown. Figure 34 Cross-sectional view along line XXXV-XXXV. Figure 36 It is a plan view showing an example of a planar layout of a memory cell array according to the second modification. Figure 37 An example of a cross-sectional structure of a memory cell array according to the second modification is shown along Figure 36 Cross-sectional view along line XXXVII-XXXVII. Figure 38 This is a cross-sectional view showing an example of a detailed cross-sectional structure near two bonding pads arranged facing each other. Figure 39 This is a cross-sectional view showing an example of a detailed cross-sectional structure of a boundary portion between a first level and a second level of a memory pillar included in a memory device according to the second embodiment. Figure 40 This is a cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array according to a third modification. Figure 41 is a cross-sectional view illustrating an example of a cross-sectional structure of a memory device according to a fourth modification. DETAILED DESCRIPTION

[0005] Below, the embodiments are described with reference to the accompanying drawings. Each embodiment illustrates an apparatus or method for concretizing the technical concept of the invention. The drawings are schematic or conceptual. The dimensions, ratios, etc. of each drawing are not necessarily the same as the actual ones. The illustrations of the components are appropriately omitted. The hatching added to the top view is not necessarily related to the material or characteristics of the components. In this specification, the same figure marks are attached to the components with roughly the same function and structure. The numbers and characters attached to the figure marks are used to refer to each other through the same figure marks and to distinguish similar elements from each other.

[0006] <1> First embodiment The memory device 1 according to the first embodiment has a structure obtained by a manufacturing method that three-dimensionally stacks memory cells and bonds two semiconductor substrates. Furthermore, the pattern of the openings for the memory holes at the auxiliary end and the pattern for maintaining the stacked wiring structure in the lead-out region are arranged so that they overlap at the boundary region. The memory device 1 according to the first embodiment is described in detail below.

[0007] <1-1>Composition First, the configuration of the memory device 1 according to the first embodiment will be described.

[0008] <1-1-1> Overall Configuration of Memory Device 1 Figure 1 1 is a block diagram showing an example of the overall configuration of a storage system including a storage device according to the first embodiment. Figure 1 As shown, memory device 1 is controlled by an external memory controller 2. Memory device 1 is, for example, a NAND flash memory capable of non-volatile data storage. Memory device 1 includes, for example, a memory cell array 10, input / output circuits 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17.

[0009] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn ("n" is an integer greater than or equal to 1). A block BLK is a collection of a plurality of memory cells. A block BLK corresponds to, for example, a unit for erasing data. A block BLK includes a plurality of pages. A page corresponds to a unit for performing reading and writing of data. Although not shown in the figure, a plurality of bit lines BL0 to BLm ("m" is an integer greater than or equal to 1) and a plurality of word lines WL are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line BL and one word line WL.

[0010] The input / output circuit 11 is an interface circuit responsible for transmitting and receiving input / output signals to and from the memory controller 2. These input / output signals include, for example, data DAT, status information, address information, and commands. The input / output circuit 11 can input and output data DAT between the sense amplifier module 17 and the memory controller 2. The input / output circuit 11 can output status information transmitted from the register circuit 13 to the memory controller 2. The input / output circuit 11 can also output address information and commands transmitted from the memory controller 2 to the register circuit 13.

[0011] The logic controller 12 controls the input / output circuit 11 and the sequencer 14, respectively, based on control signals input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to enable the memory device 1. The logic controller 12 notifies the input / output circuit 11 that the input / output signals received by the input / output circuit 11 are commands, address information, etc. The logic controller 12 instructs the input / output circuit 11 to input or output the input / output signals.

[0012] Register circuit 13 temporarily stores status information, address information, and commands. Status information is updated under the control of sequencer 14 and transmitted to input / output circuit 11. Address information includes, for example, block address, page address, and column address. Commands include commands related to various operations of memory device 1.

[0013] The sequencer 14 controls the operation of the entire memory device 1. The sequencer 14 executes a read operation, a write operation, an erase operation, etc. according to the command and address information stored in the register circuit 13.

[0014] The driver circuit 15 generates voltages used in a read operation, a write operation, an erase operation, etc. The driver circuit 15 supplies the generated voltages to the row decoder block 16 , the sense amplifier block 17 , and the like.

[0015] The row decoder module 16 is a circuit used to select the target block BLK and transmit voltages to wiring such as word lines WL. The row decoder module 16 includes multiple row decoders RD0 through RDn. Row decoders RD0 through RDn are associated with each of the blocks BLK0 through BLKn and are used to select the blocks BLK. Each row decoder RD transmits the voltage generated by the driver circuit 15 to various wirings within the memory cell array 10.

[0016] The sense amplifier module 17 is a circuit for transmitting voltage to each bit line BL and reading data. Sense amplifier module 17 includes multiple sense amplifier units SAU0 through SAUm. Each sense amplifier unit SAU0 through SAUm is associated with a plurality of bit lines BL0 through BLm, respectively. Each sense amplifier unit SAU includes a sense amplifier capable of determining data based on the voltage of the associated bit line BL, a latch circuit for temporarily holding the data, and other components.

[0017] Alternatively, a semiconductor device may be formed by combining the memory device 1 and the memory controller 2. As such a semiconductor device, for example, an SD card may be used. TM Memory cards like SD cards, SSD (solid state drive), etc.

[0018] <1-1-2> Circuit Configuration of Memory Cell Array 10 Figure 2 1 is a circuit diagram showing an example of a circuit configuration of a memory cell array 10 included in the memory device 1 according to the first embodiment. Figure 2 FIG. 2 shows one block BLK among the multiple blocks BLK included in the memory cell array 10. Figure 2As shown, within block BLK, select gate lines SGD0-SGD4, word lines WL0-WL(N-1) (N is an integer greater than or equal to 2), select gate line SGS, bit lines BL0-BLm, and source line SL are connected. Select gate lines SGD0-SGD4, word lines WL0-WL(N-1), and select gate line SGS are provided for each block BLK. Bit lines BL0-BLm and source line SL can be shared by multiple blocks BLK.

[0019] For example, a block BLK includes five string units SU0-SU4. Each string unit SU includes NAND strings NS0-NSm. NAND strings NS0-NSm are associated with bit lines BL0-BLm, respectively. Each NAND string NS is connected between its associated bit line BL and a source line SL. Each bit line BL is shared across multiple blocks BLK by NAND strings NS assigned the same column address.

[0020] Each NAND string NS includes, for example, a selection transistor ST1, N memory cell transistors MT0 to MT(N-1), and a selection transistor ST2. In each NAND string NS, the selection transistor ST1, the memory cell transistors MT(N-1) to MT0, and the selection transistor ST2 are connected in series in this order. Furthermore, the drain of the selection transistor ST1 is connected to the associated bit line BL, and the source of the selection transistor ST2 is connected to the source line SL. Each memory cell transistor MT has a control gate and a charge storage layer, and non-volatilely retains (stores) data. The selection transistors ST1 and ST2 are used to select the string unit SU.

[0021] Select gate lines SGD0 through SGD4 are associated with string units SU0 through SU4, respectively. Each select gate line SGD is connected to the gates of the multiple select transistors ST1 included in the associated string unit SU. Select gate line SGS is connected to the gates of the multiple select transistors ST2 included in block BLK. Word lines WL0 through WL(N-1) are connected to the control gates of the memory cell transistors MT0 through MT(N-1) included in block BLK, respectively.

[0022] The set of multiple memory cell transistors MT connected to a common word line WL within a string unit SU corresponds to a "page." Depending on the number of bits stored by the memory cell transistors MT, the set of multiple memory cell transistors MT connected to a common word line WL within a string unit SU may have a storage capacity of more than two pages.

[0023] Furthermore, the memory cell array 10 may have other circuit configurations. For example, the number of string units SU included in the block BLK, the number of memory cell transistors MT included in the NAND string NS, and the number of select transistors ST1 and ST2 may be designed to be arbitrary. The following describes the memory device 1 according to the first embodiment, taking as an example a case where each NAND string NS has eight memory cell transistors MT0 to MT7 connected to word lines WL0 to WL7, respectively.

[0024] <1-1-3> Structure of Memory Device 1 Next, the structure of the memory device 1 according to the first embodiment will be described.

[0025] In addition, in the drawings referenced below, a three-dimensional orthogonal coordinate system is used. The X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction relative to the front surface of the semiconductor substrate used as a reference. "Up and down" are defined based on the direction along the Z direction. The positive direction (upward) corresponds to the direction away from the front side of the semiconductor substrate used as a reference. The XY plane (cross section) corresponds to the plane (cross section) parallel to the X direction and the Y direction, respectively. The YZ cross section corresponds to the cross section parallel to the Y direction and the Z direction, respectively. The XZ cross section corresponds to the cross section parallel to the X direction and the Z direction, respectively. The "front surface of the semiconductor substrate" corresponds to the surface on the side where the semiconductor circuit is formed. The "back surface of the semiconductor substrate" corresponds to the surface on the side opposite to the front surface of the semiconductor substrate.

[0026] (1: Appearance of memory device 1) First, the appearance of the memory device 1 involved in the first embodiment is described. The memory device 1 involved in the first embodiment is formed by bonding two semiconductor circuit substrates each having a semiconductor circuit formed thereon, and separating the bonded semiconductor circuit substrates into individual chips. Specifically, the memory device 1 involved in the first embodiment includes a structure formed by bonding semiconductor substrates W1 and W2. The semiconductor substrates W1 and W2 are respectively silicon substrates. The following describes a case where the semiconductor substrate W2 is removed during the manufacturing process of the memory device 1. Depending on the structure of the memory cell array 10, a portion of the semiconductor substrate W2 may remain after the semiconductor substrates W1 and W2 are bonded.

[0027] Figure 3 1 is a perspective view showing an example of the appearance of the memory device 1 according to the first embodiment. Figure 3 As shown, the memory device 1 has a structure in which, for example, a semiconductor substrate W1 , a CMOS layer 100 , a bonding layer B1 , a bonding layer B2 , a memory layer 200 , and a wiring layer 300 are stacked in this order from below.

[0028] CMOS layer 100 includes a CMOS circuit (control circuit) formed using semiconductor substrate W1. Semiconductor substrate W1 has impurity diffusion regions and other components corresponding to the design of the CMOS circuit. CMOS layer 100 includes, for example, input / output circuits 11, logic controller 12, register circuits 13, sequencer 14, driver circuits 15, row decoder modules 16, and control circuits such as sense amplifier modules 17.

[0029] The bonding layer B1 is formed using a semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to the CMOS circuit provided in the CMOS layer 100 to form a portion of the semiconductor circuit. The bonding layer B2 is formed using a semiconductor substrate W2 (not shown). The bonding layer B2 includes a plurality of bonding pads that are electrically connected to the memory cell array 10 provided in the memory layer 200 to form a portion of the semiconductor circuit. The plurality of bonding pads included in the bonding layer B1 are respectively connected to the plurality of bonding pads BP included in the bonding layer B2. The boundary between the bonding layers B1 and B2 corresponds to the boundary between the layer formed using the semiconductor substrate W1 and the layer formed using the semiconductor substrate W2 (not shown).

[0030] The memory layer 200 includes a memory cell array 10 formed using a semiconductor substrate W2. The wiring layer 300 is formed after bonding the semiconductor substrates W1 and W2. The wiring layer 300 includes wiring connected to the semiconductor circuits provided in the memory layer 200 and a plurality of pads PD. The plurality of pads PD are exposed on the surface of the memory device 1. The plurality of pads PD are used to connect the memory device 1 to, for example, the memory controller 2.

[0031] (2: Planar layout of memory cell array 10) Figure 4 FIG1 is a top view showing an example of a planar layout of the memory cell array 10 included in the memory device 1 according to the first embodiment. Figure 4 As shown, the memory cell array 10 includes a plurality of slits SLT. In addition, the memory cell array 10 includes a memory area MA and a lead-out area HA arranged in the X direction.

[0032] Each slit SLT corresponds to a plate-shaped member extending in the X direction. Each slit SLT has a portion extending in the X direction, transversely intersecting the memory area MA and the lead-out area HA in the X direction. Multiple slits SLT are arranged in the Y direction. Each slit SLT divides adjacent wiring (e.g., word lines WL0-WL7 and select gate lines SGD and SGS) through the slit SLT. In the memory cell array 10, each area divided in the Y direction by a slit SLT corresponds to a block BLK.

[0033] The storage area MA is an area for storing data. The storage area MA includes a plurality of storage pillars configured to store data. The lead-out area HA is, for example, an area for connecting stacked wiring (e.g., word lines WL, select gate lines SGD, and SGS) to the row decoder module 16. The lead-out area HA includes a plurality of support pillars for maintaining the structure of the stacked wiring during its formation. Hereinafter, the area sandwiched between the storage area MA and the lead-out area HA is referred to as the boundary area BA. The boundary area BA includes a pattern for assisting in the formation of the storage pillars arranged at the end of the storage area MA.

[0034] (3: Planar Layout in the Memory Area MA of the Memory Cell Array 10) Figure 5 It is a plan view showing an example of a planar layout in a storage region of the memory cell array 10 included in the memory device 1 according to the first embodiment. Figure 5 FIG. 1 shows a region including one block BLK sandwiched between two adjacent slits SLT. Figure 5 As shown, the memory device 1 includes, for example, a plurality of slits SHE, a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL in a memory area MA.

[0035] Each slit SHE has a portion extending in the X direction and crosses the storage area MA in the X direction. Multiple slits SHE are arranged in the Y direction. In this example, four slits SHE are arranged between two adjacent slits SLT in the Y direction. Each slit SHE has a structure filled with an insulator, for example. Each slit SHE divides adjacent wiring (at least the selection gate line SGD) through the slit SHE. In the memory cell array 10, the area divided by the slits SLT and SHE each corresponds to one string unit SU. In this example, string units SU0 to SU4 are arranged between two adjacent slits SLT.

[0036] Each storage column MP is, for example, a columnar component corresponding to one NAND string NS. A plurality of storage columns MP are arranged in a staggered pattern (lattice pattern) for each block BLK. For example, a plurality of storage columns MP are arranged in a staggered pattern of 24 rows in the area between two adjacent slits SLT. In this example, one slit SHE overlaps each of the storage columns MP in the 5th row, the 10th row, the 15th row, and the 20th row, as counted from the top of the paper.

[0037] Each bit line BL has a portion extending along the Y direction. A plurality of bit lines BL are provided separately from the stacked wiring (e.g., word line WL, selection gate line SGD, and SGS) in the Z direction and are arranged in the X direction. Each bit line BL is configured to overlap with at least one storage column MP in each string unit SU. In this example, two bit lines BL are overlapped on one storage column MP. The storage column MP is electrically connected to one bit line BL of the plurality of overlapping bit lines BL via a contact CV. In addition, the contact CV between the storage column MP and the bit line BL connected to two different selection gate lines SGD can be omitted.

[0038] The planar layout of the memory area MA may also be another layout. For example, the number and arrangement of memory pillars MP and slits SHE between two adjacent slits SLT may be appropriately changed. The number of bit lines BL overlapping each memory pillar MP may be designed to be any number.

[0039] (4: Cross-sectional structure in the memory area MA of the memory cell array 10) Figure 6 FIG. 1 is a diagram showing an example of a cross-sectional structure in a memory region MA of a memory cell array 10 included in the memory device 1 according to the first embodiment, along the Figure 5 Cross-sectional view along line VI-VI. Figure 6 FIG. 1 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before being bonded to the semiconductor substrate W1, and shows the coordinate axes based on the semiconductor substrate W2. Figure 6 As shown, the memory cell array 10 includes, for example, conductive layers 21 to 26 , insulating layers 30 to 36 , an insulating member 37 , and contacts V0 and V1 in the memory region MA.

[0040] An insulating layer 30 is provided on the semiconductor substrate W2. A conductive layer 21 is provided on the insulating layer 30. On the conductive layer 21, insulating layers 31 and conductive layers 22 are alternately provided. On the top conductive layer 22, insulating layers 32, conductive layers 23, insulating layers 33, insulating layers 34, and conductive layers 24 are provided in this order. Each conductive layer 21, 22, and 23 is formed, for example, in the shape of a plate extending along the XY plane. The conductive layer 24 has, for example, a linear portion extending in the Y direction. The conductive layer 21 serves as a selection gate line SGS. The plurality of conductive layers 22 serve, in order from the bottom, as word lines WL0 to WL7. The conductive layer 23 serves as a selection gate line SGD. The conductive layer 24 serves as a bit line BL.

[0041] A conductive layer 25 is provided above the conductive layer 24. The conductive layers 24 and 25 are connected via a contact V0. A conductive layer 26 is provided above the conductive layer 25. The conductive layers 25 and 26 are connected via a contact V1. The sides of the conductive layer 25 and the contacts V0 and V1 are covered by an insulating layer 35. The insulating layer 35 can be formed of a multilayer insulating film. The sides of the conductive layer 26 are covered by the insulating layer 36. The insulating layer 36 and the conductive layer 26 are contained in the bonding layer B2. The conductive layer 26 corresponds to the bonding pad BP. The conductive layer 26 comprises, for example, copper.

[0042] The slits SLT separate the insulating layers 30-33 from the conductive layers 21-23. For example, an insulating member 37 is embedded in the slits SLT. The insulating member 37 has a plate-shaped portion extending along the XZ plane. Conductive members having insulating spacers provided on their sidewalls may be arranged in the slits SLT to insulate them from the wiring.

[0043] Each memory pillar MP extends in the Z direction, penetrating the insulator layers 30-33 and the conductor layers 21-23. Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a laminate film 42. The core member 40 is an insulator extending in the Z direction. The semiconductor layer 41 covers the core member 40. The lower portion of the semiconductor layer 41 is in contact with, for example, the semiconductor substrate W2. The laminate film 42 covers the side and bottom surfaces of the semiconductor layer 41. The semiconductor layer 41 is connected to the conductor layer 24 via a contact CV.

[0044] The portion where the memory column MP intersects the conductive layer 21 functions as a select transistor ST2. The portion where the memory column MP intersects the conductive layer 22 functions as a memory cell transistor MT. The portion where the memory column MP intersects the conductive layer 23 functions as a select transistor ST1. In each memory column MP, the semiconductor layer 41 serves as a channel (current path) for the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2 included in the NAND string NS.

[0045] (5: Cross-sectional structure of the memory column MP) Figure 7 FIG. 1 is a diagram showing an example of a cross-sectional structure of a memory pillar MP included in the memory device 1 according to the first embodiment, along the Figure 6 Cross-sectional view along line VII-VII. Figure 7 FIG. 2 shows a cross section including the memory pillar MP and the conductive layer 22 and parallel to the surface of the semiconductor substrate W2. Figure 7As shown, the stacked film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a blocking insulating film 45. The tunnel insulating film 43 surrounds the side surfaces of the semiconductor layer 41. The insulating film 44 surrounds the side surfaces of the tunnel insulating film 43. The blocking insulating film 45 surrounds the side surfaces of the insulating film 44. The conductive layer 22 surrounds the side surfaces of the blocking insulating film 45. The tunnel insulating film 43 and the blocking insulating film 45 each include, for example, silicon oxide (SiO2). The insulating film 44 serves as a charge storage layer for the memory cell transistor MT. The insulating film 44 includes, for example, silicon nitride.

[0046] (6: Planar Layout of the Memory Cell Array 10 Near the Boundary Area BA) Figure 8 1 is a plan view showing an example of a planar layout near a boundary area BA of a memory cell array 10 included in the memory device 1 according to the first embodiment. Figure 8 The boundary area BA, the storage area MA adjacent to the boundary area BA, and a portion of the lead-out area HA are extracted and shown. Figure 8 As shown, the lead-out area HA and the boundary area BA each include a plurality of support posts HR. The boundary area BA also includes a plurality of dummy posts DMP.

[0047] Each support pillar HR is a columnar member used to maintain the stacked wiring structure of the memory cell array 10. At the same height, the diameter of the support pillar HR is larger than the diameter of the memory pillar MP. Multiple support pillars HR are arranged in a staggered (lattice-like) pattern per block BLK in each of the lead-out area HA and the boundary area BA.

[0048] Each dummy pillar DMP corresponds to a pattern used to assist in forming the storage pillar MP disposed at the end of the storage area MA. At the same height, the diameter of the dummy pillar DMP is smaller than the diameter of the support pillar HR. Furthermore, the diameter of the dummy pillar DMP tends to decrease as it approaches the lead-out area HA. ​​Each dummy pillar DMP has the same layer structure as the storage pillar MP. Depending on its position, each dummy pillar DMP may have a structure in which a portion of the components included in the storage pillar MP are omitted.

[0049] The plurality of dummy pillars DMP are arranged in a staggered pattern for each block BLK in the boundary area BA. Preferably, the number of rows and columns of the staggered support pillars HR between two adjacent slits SLT within the boundary area BA is designed to be the same as the number of rows and columns of the staggered dummy pillars DMP. Furthermore, it is more preferred that the plurality of dummy pillars DMP provided in the boundary area BA completely overlap with the plurality of support pillars HR provided in the boundary area BA in the Z direction.

[0050] (7: Cross-sectional structure near the boundary area BA of the memory cell array 10) Figure 9 FIG. 1 is a diagram showing an example of a cross-sectional structure near a boundary area BA of the memory cell array 10 included in the memory device 1 according to the first embodiment, along the Figure 8 Cross-sectional view along line IX-IX. Figure 9 FIG. 1 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before being bonded to the semiconductor substrate W1, and shows the coordinate axes based on the semiconductor substrate W2. Figure 9 As shown, the memory cell array 10 includes a plurality of insulating members 50 corresponding to the plurality of support posts HR in the lead-out area HA and the boundary area BA.

[0051] Each insulating member 50 has a shape extending from the insulating layer 33 to the insulating layer 30 in the Z direction. Each support column HR penetrates the insulating layers 30 and 33, the insulating layers 31 and 32, and at least a portion of the conductive layers 21 to 23 that is sandwiched between the insulating layer 33 and the insulating layer 30. Moreover, the bottom of the insulating member 50 is in contact with the semiconductor substrate W2. The structure of each insulating member 50 is the same between the lead-out area HA and the boundary area BA. The insulating member 50 contains, for example, silicon oxide (SiO2). That is, the insulating member 50 contains, for example, oxygen and silicon. In this way, the structure of the support column HR is different from that of the storage column MP.

[0052] The upper surface of the dummy column DMP is flush with the upper surface of the storage column MP. In addition, the upper surface of the dummy column DMP may be flush with the upper surface of the support column HR or not. The side and bottom of each dummy column DMP are covered by an insulating member 50 (support column HR) overlapping in the Z direction. Therefore, the length of each dummy column DMP in the Z direction is shorter than the length of the support column HR in the Z direction. In this example, the dummy column DMP arranged on the side of the storage area MA has the same layer structure (core member 40, semiconductor layer 41 and stacked film 42) as the storage column MP. For example, the film thickness of the stacked film 42 included in the dummy column DMP is approximately the same as the film thickness of the stacked film 42 included in the storage column MP. In addition, in this example, for the dummy column DMP arranged on the side of the lead-out area HA, as its diameter is smaller than the diameter of the dummy column DMP on the side of the storage area MA, it only has the semiconductor layer 41 and stacked film 42 in the layer structure of the storage column MP. A conductive layer (eg, bit line BL) separated from the stacked wiring included in the memory cell array 10 in the Z direction is not connected to the dummy pillar DMP.

[0053] In addition, in the lead-out area HA, each stacked wiring of the memory cell array 10 may have a platform portion. The platform portion corresponds to a portion that does not overlap with the wiring (conductive layer) of the upper layer (the side opposite to the semiconductor substrate W2) when viewed from above. The structure formed by multiple platform portions is similar to a step, a terrace, a rimstone, etc. In this example, only the platform portions of two conductive layers 22 are illustrated. In addition, in this example, the steps formed by the platform portions are filled with an insulating layer 33. The contacts (not shown) provided in the lead-out area HA are connected to the platform portion of the associated wiring in the stacked wiring. And, via the contacts and the wiring omitted from the illustration, the wiring is electrically connected to the row decoder module 16.

[0054] (8: Cross-sectional structure of memory device 1) Figure 10 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the first embodiment. Figure 10 The coordinate axes based on the semiconductor substrate W1 are shown. Figure 10 As shown, CMOS layer 100 includes an insulator layer 60, multiple conductive layers 62, and multiple contacts 63. Bonding layer B1 includes an insulator layer 61 and a conductive layer 64. Memory layer 200 includes insulator layers 30-36, conductive layers 21-27, multiple memory pillars MP, slits SLT, contacts CV, V0, and V1. Wiring layer 300 includes an insulator layer 38. Transistor TR is provided on semiconductor substrate W1. Transistor TR corresponds to the element included in sense amplifier module 17.

[0055] In the CMOS layer 100, an insulator layer 60 is provided on the semiconductor substrate W1. Within the insulator layer 60, at least one contact 63 and at least one conductive layer 62 are connected in series on the transistor TR. The insulator layer 60 may also be composed of a multilayer insulating film. An insulator layer 61 is provided on the insulator layer 60. A conductive layer 64 is in contact with the upper portion of the topmost contact 63, which is indirectly connected to the transistor TR. The conductive layer 64 corresponds to the bonding pad BP formed on the semiconductor substrate W1. The conductive layer 64 is in contact with the conductive layer 26, which is arranged opposite to the transistor TR in the Z direction.

[0056] The storage layer 200 includes the use of Figure 6The structure in the storage area MA of the described memory cell array 10 is reversed upside down. In this example, the semiconductor substrate W2 is removed, and a portion of the insulator layer 30, a portion of the insulating member 37 in the slit SLT, and the stacked film 42 on the upper portion of the storage column MP are removed. The conductive layer 27 is provided on the insulating layer 30. The conductive layer 27 is formed into a plate shape extending along the XY plane. The conductive layer 27 is connected to the semiconductor layer 41 on the upper portion of the storage column MP. The conductive layer 27 serves as a source line SL. The insulating layer 38 is provided on the conductive layer 27. The insulating layer 38 includes a conductive layer 27 formed using Figure 3 The described pads PD and wirings (not shown) for connecting the pads PD to the input / output circuit 11 are also provided.

[0057] In addition, although not shown in the figure in this example, by removing the stacked film 42 on the upper portion of the semiconductor substrate W2 and the storage column MP, the height of the upper surface of the support column HR becomes flush with the upper surface of the storage column MP. In addition, although not shown in the figure, the upper portion of the support column HR can be connected to the conductive layer 27 (source line SL) in the same manner as the storage column MP, or can be connected to the insulating layer not shown. The number of wiring layers provided by the memory device 1 is not limited to Figure 10 The number of routing layers shown.

[0058] <1-2> Manufacturing method Next, use Figures 11 to 20 , a method for manufacturing the memory device 1 according to the first embodiment will be described. Figure 11 、 Figure 13 、 Figure 15 、 Figure 17 、 Figure 19 Each of them is a top view showing an example of a planar layout of the memory cell array 10 provided in the memory device 1 according to the first embodiment during the manufacturing process. The planar layout referred to in this project corresponds to Figure 8 The area near the boundary area BA of the memory cell array 10 is shown. Figure 12 、 Figure 14 、 Figure 16 、 Figure 18 、 Figure 20 Each of them is a cross-sectional view showing an example of a cross-sectional structure of the memory cell array 10 included in the memory device 1 according to the first embodiment during the manufacturing process. Figure 12 Corresponding to along Figure 11 Cross section along line XII-XII. Figure 14 Corresponding to along Figure 13 Cross section of line XIV-XIV. Figure 16 Corresponding to along Figure 15 Cross section of line XVI-XVI. Figure 18 Corresponding to along Figure 17Cross section of line XVIII-XVIII. Figure 20 Corresponding to along Figure 19 In this specification, a "stacked wiring portion" refers to a structure used to form a stacked wiring including a plurality of word lines WL arranged in the Z direction.

[0059] First, although not shown in the figure, sacrificial members 70 to 72 of the stacked wiring portion are formed. Specifically, first, the sacrificial member 70 is formed on the insulator layer 30. The insulator layer 31 and the sacrificial members 71 are alternately stacked on the sacrificial member 70. The insulator layer 32 and the sacrificial member 72 are sequentially formed on the uppermost sacrificial member 71. Then, a step structure of the sacrificial members 70 to 72 is formed in the lead-out area HA by thinning or etching. Then, the steps of the step structure are filled with the insulator layer 33, so that the upper surface of the insulator layer 33 is flattened. The sacrificial members 70 to 72 are, for example, silicon nitride (SiN). In addition, depending on the design of the memory cell array 10, the formation of the step structure of the sacrificial members 70 to 72 can also be omitted.

[0060] Then, if Figure 11 As shown, a mask REG1 is formed. Specifically, first, a mask member (e.g., carbon) used as a mask for etching the deep holes is formed on the insulating layer 33. Then, a resist material is applied to the mask member. Then, the resist material is processed into a shape having a plurality of holes H1 by photolithography. The plurality of holes H1 are respectively provided corresponding to the positions where the plurality of support pillars HR are to be formed. Thereafter, the mask member is processed by an anisotropic etching process using the resist material as a mask. As a result, the shape of the resist material is transferred to the mask member, forming a mask REG1 having a plurality of holes H1.

[0061] Next, an anisotropic etching process is performed using the mask REG1 as a mask. Thus, etching is performed through the plurality of holes H1, as shown in FIG. Figure 12 As shown in FIG, a plurality of holes HH are formed. Figure 12 The cross-sectional structure after removing the mask used in this process is shown in FIG. Each hole HH is provided through the insulator layers 30 and 33, the sacrificial members 70-72, and the portion of the insulator layers 31-32 sandwiched between the insulator layers 30 and 33. The surface of the semiconductor substrate W2 is exposed at the bottom of each hole HH. In other words, in this process, the semiconductor substrate W2 serves as an etch stop layer. Furthermore, in this process, for example, RIE (Reactive Ion Etching) is used.

[0062] Then, if Figure 13 As shown, the plurality of holes HH are respectively filled with the insulating member 50. Figure 14As shown, the bottom of each insulating member 50 is in contact with the semiconductor substrate W2. Furthermore, the side surface of each insulating member 50 is in contact with the insulator layer 33 and at least one of the insulator layers 30 to 32. Alternatively, after the plurality of holes HH are filled with the insulating member 50, an insulating film may be formed on the insulating member 50 and the laminated wiring portion to form an additional insulating layer 33.

[0063] Then, if Figure 15 As shown, a mask REG2 is formed. Specifically, first, a mask member (e.g., carbon) is formed on the insulator layer 33 to be used as a mask for etching of deep holes. Then, a resist material is applied on the mask member. Then, the resist material is processed into a shape having a plurality of holes H3 and a plurality of holes H3 by photolithography. The plurality of holes H2 are respectively provided corresponding to the positions where a plurality of storage columns MP are to be formed. The plurality of holes H3 are respectively provided corresponding to the positions where a plurality of dummy columns DMP are to be formed. In addition, at this time, the closer the plurality of holes H3 are to the end columns in the overall configuration of the plurality of holes H2 and the holes H3, the easier it is to form them with a small diameter. Thereafter, the mask member is processed by an anisotropic etching process using the resist material as a mask. As a result, the shape of the resist material is transferred to the mask member to form a mask REG2 having a plurality of holes H2 and a plurality of holes H3.

[0064] Next, an anisotropic etching process is performed using the mask REG2 as a mask. Thus, etching is performed through the plurality of holes H2 and the plurality of holes H3, as shown in FIG. Figure 16 As shown in FIG. 1 , a plurality of memory holes MH and a plurality of holes DMH are formed. Figure 16 , the cross-sectional structure after the mask used at this time is removed is shown in FIG. Each memory hole MH is provided by penetrating the insulating layers 30 to 33 and the sacrificial members 70 to 72. At the bottom of each memory hole MH, the surface of the semiconductor substrate W2 is exposed. That is, in this process, the semiconductor substrate W2 is used as an etching stop layer. Each hole DMH is provided by removing a portion of the insulating member 50 constituting the support column HR. The surface of the insulating member 50 is exposed on the side and bottom surfaces of each hole DMH. The position (height) of the bottom of each hole DMH varies depending on the diameter of the corresponding hole H3. In addition, in this process, for example, RIE is used. In RIE, when the holes H3 are formed at the same pitch on the mask REG2, the smaller the diameter of the hole H3, the more the etching in the height direction (Z direction) can be suppressed.

[0065] Then, if Figure 17As shown, a memory column MP is formed in each memory hole MH, and a dummy column DMP is formed in each hole DMH. Specifically, a stacked film 42 (i.e., a blocking insulating film 45, an insulating film 44, and a tunnel insulating film 43), a semiconductor layer 41, and a core member 40 are sequentially formed on the side and bottom of the memory hole MH. At this time, a stacked film 42, a semiconductor layer 41, and a core member 40 are also sequentially formed on the side and bottom of the hole DMH. In addition, depending on the diameter of the hole DMH, a portion of the stacked film 42, the semiconductor layer 41, and the core member 40 may not be formed in the hole DMH. Then, a portion of the core member 40 provided on the upper portion of the memory hole MH is removed, and a semiconductor layer 41 is formed on the portion after the core member 40 is removed. As a result, as shown in FIG. Figure 18 As shown, a structure corresponding to the memory pillar MP is formed in the memory hole MH. Similarly, a structure corresponding to the dummy pillar DMP is formed in the hole DMH. Then, the stacked film 42, semiconductor layer 41, and core member 40 above the insulator layer 33 are removed by CMP (Chemical Mechanical Polishing) or the like.

[0066] Then, if Figure 19 As shown, a slit SLT is formed to divide each sacrificial member 70 to 72 into each block BLK. Specifically, first, an insulating film (not shown) is formed on the insulator layer 33 in a manner that protects the storage column MP, the dummy column DMP, and the support column HR. Thereafter, the slit SLT is formed by a combination of a photolithography process and an anisotropic etching process. In addition, although not shown, the slit SLT divides the insulator layer 30 to 33 and the sacrificial members 70 to 72. Through this process, the surface of the semiconductor substrate W2 is exposed at the bottom of the slit SLT.

[0067] Next, a substitution process is performed. Specifically, a wet etching process using hot phosphoric acid or the like is performed. Figure 20 As shown in FIG. 1 , the sacrificial members 70 to 72 are selectively removed through the slit SLT. At this time, the space after the sacrificial members 70 to 72 are removed is maintained by a plurality of storage columns MP and a plurality of support columns HR. Then, the conductor fills the space after the sacrificial members 70 to 72 are removed through the slit SLT. The conductor in this process is formed using, for example, CVD. Then, the conductor formed in the slit SLT is removed by etching back, etc., and the conductor formed in the adjacent space is separated into multiple layers. Thus, a conductor layer 21 that functions as a selection gate line SGS, a plurality of conductor layers 22 that function as word lines WL respectively, and a conductor layer 23 that functions as a selection gate line SGD are formed. Thereafter, an insulating member 37 is formed in the slit SLT to complete the process. Figure 6 and Figure 9 The stacked wiring is shown.

[0068] <1-3> Effects of the First Embodiment According to the memory device 1 according to the first embodiment described above, it is possible to suppress the manufacturing cost of the memory device 1. Hereinafter, the effects of the first embodiment will be described in detail using a first comparative example and a second comparative example.

[0069] In a memory device with a three-dimensionally stacked structure of memory cells, multiple support posts HR are provided to maintain the structure of the stacked wiring portion after sacrificial members 70-72 are removed during replacement. In a manufacturing method that forms memory posts MP and support posts HR through separate processes, holes DMH are provided in the boundary area BA to assist in ensuring the openness of the end rows of memory holes MH during the processing of the multiple memory holes MH. However, controlling the depth of the holes DMH is difficult.

[0070] Figure 21 It is a plan view showing an example of a planar layout of a memory cell array 10A according to the first comparative example. Figure 22 An example of a cross-sectional structure of a memory cell array 10A according to the first comparative example is shown. Figure 21 The cross-sectional view of line XXII-XXII. Figure 21 As shown in FIG. 1 , the first comparative example corresponds to a case where a plurality of support posts HR are not formed in the boundary area BA. Figure 22 As shown, in the boundary area BA, the diameter of the dummy pillar DMP is small, and the bottom of the dummy pillar DMP does not reach the semiconductor substrate W2. In such a design, during the formation of stacked wiring, the layer structure of the insulator layer 31 below the dummy pillar DMP may collapse during the replacement process. Specifically, the insulator layer 31 may bend in the portion where the dummy pillar DMP does not reach, resulting in poor embedding of the conductor corresponding to the word line WL.

[0071] Figure 23 It is a plan view showing an example of a planar layout of a memory cell array 10B according to a second comparative example. Figure 24 An example of a cross-sectional structure of a memory cell array 10B according to the second comparative example is shown. Figure 23 The cross-sectional view of the line XXIV-XXIV. Figure 23 As shown in FIG. 1 , the second comparative example corresponds to a case where the diameter of the dummy pillar DMP in the boundary area BA is increased compared to the first comparative example. Figure 24As shown, in the boundary area BA, the bottom of the dummy pillar DMP can reach the semiconductor substrate W2. As a result, the deflection of the insulator layer 31 during the replacement process can be suppressed. On the other hand, when the diameter of the dummy pillar DMP is increased, over-etching of the semiconductor substrate W2 may occur when forming the hole HH corresponding to the dummy pillar DMP. In this case, since the height of the bottom of the storage pillar MP is different from the height of the bottom of the dummy pillar DMP, a step may be generated when the semiconductor substrate W2 is removed after the bonding process of the semiconductor substrates W1 and W2. In addition, defects caused by the generated step may occur.

[0072] In contrast, the memory device 1 according to the first embodiment has a structure in which the dummy pillars DMP and the support pillars HR overlap in the Z direction in the boundary area BA. For example, the multiple support pillars HR formed in the boundary area BA can suppress the deflection of the insulating layer 31 during the replacement process. In addition, the multiple support pillars HR formed in the boundary area BA can prevent the dummy pillars DMP from reaching the semiconductor substrate W2 when the multiple memory holes MH are formed. In other words, in the memory device 1 according to the first embodiment, the diameter of the dummy pillars DMP is designed to be small, which can suppress the occurrence of overetching of the semiconductor substrate W2 and the occurrence of defects caused by the overetching.

[0073] As described above, the memory device 1 according to the first embodiment can suppress both defects in the replacement process and defects caused by overetching of the dummy pillars DMP.

[0074] <2> Second embodiment The second embodiment applies the boundary region BA having the same planar layout as the first embodiment to a memory cell array 10C formed of multiple levels. Hereinafter, the memory device 1 according to the second embodiment will be described mainly with respect to the differences from the first embodiment.

[0075] <2-1>Composition First, the structure of the memory device 1 involved in the second embodiment is described. The structure of the memory device 1 involved in the second embodiment is the same as that of the memory device 1 involved in the first embodiment, except that the structure of the memory cell array 10 is different. In the second embodiment, the case where each NAND string NS has 16 memory cell transistors MT0 to MT15 connected to word lines WL0 to WL15, respectively, is used as an example for description. Hereinafter, the memory column MP of the memory device 1 involved in the second embodiment is referred to as "memory column MPa."

[0076] (1: Cross-sectional structure of memory cell array 10C) Figure 25 It is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array 10C included in the memory device 1 according to the second embodiment. Figure 25 FIG. 1 shows an example of the structure of a memory cell array 10C formed on a semiconductor substrate W2 before being bonded to the semiconductor substrate W1, and shows coordinate axes based on the semiconductor substrate W2. Figure 25 As shown, the memory cell array 10C includes, for example, a semiconductor substrate W2 , conductive layers 21 , 22 a , 22 b , 23 , and 24 , insulating layers 30 , 31 a , 31 b , 32 to 35 , and 80 , memory pillars MPa, slits SLT and SHE, and contacts CV.

[0077] Memory cell array 10C differs from memory cell array 10 of the first embodiment in the structure of conductive layer 21 and insulator layer 32. Specifically, insulator layer 31a and conductive layer 22a are alternately stacked on conductive layer 21. Insulator layer 80 is provided on top of conductive layer 22a. Conductor layer 22b and insulator layer 31b are alternately stacked on insulator layer 80. Insulator layer 32 is provided on top of conductive layer 22b.

[0078] Each conductive layer 22a and 22b is formed into a plate shape extending along the XY plane, for example. The eight stacked conductive layers 22a are used as word lines WL0 to WL7 in sequence from the conductive layer 21 side. The eight stacked conductive layers 22b are used as word lines WL8 to WL15 in sequence from the conductive layer 21 side. The conductive layers 22a and 22b each contain tungsten, for example. Hereinafter, the division unit of the process of forming the hole for forming the storage column MPa is referred to as a tier (Tier) TI. In this example, the memory cell array 10C includes tiers TI1 and TI2. Tier TI1 includes eight conductive layers 22a. Tier TI2 includes eight conductive layers 22b.

[0079] The storage column MPa has a structure formed by connecting a plurality of columns each extending in the Z direction. In this example, the storage column MPa includes two columns connected in the Z direction. Hereinafter, these two columns are referred to as the lower column LMP and the upper column UMP. The lower column LMP is associated with the level TI1. The lower column LMP is provided by penetrating the insulating layers 30, 31a and 80, and the conductive layers 21 and 22a, respectively. The upper column UMP is provided on the lower column LMP and is associated with the level TI2. The upper column UMP is provided by penetrating the insulating layers 31b, 32 and 33, and the conductive layers 22b and 23, respectively. The connection portion of the lower column LMP and the upper column UMP is included in the layer at the height where the insulating layer 80 is provided.

[0080] The lower column LMP and the upper column UMP share a core member 40, a semiconductor layer 41, and a stacked film 42. That is, the core member 40, the semiconductor layer 41, and the stacked film 42 included in the storage column MPa are each continuously arranged between the lower column LMP and the upper column UMP. In this example, the lower column LMP and the upper column UMP each have an inverted cone shape. In this case, the XY cross-sectional area of ​​the upper end of the lower column LMP is larger than the XY cross-sectional area of ​​the lower end of the upper column UMP. The intersection of the lower column LMP and the conductive layer 21 functions as a selection transistor ST2. The lower column LMP and the intersection with each of the 8 conductive layers 22a function as memory cell transistors MT0 to MT7 in sequence from the lower layer. The upper column UMP and the intersection with each of the 8 conductive layers 22b function as memory cell transistors MT8 to MT15 in sequence from the lower layer. The intersection portion between the upper pillar UMP and the conductive layer 23 functions as the selection transistor ST1 .

[0081] The slit SLT of the second embodiment divides the conductive layers 21, 22a, 22b, and 23 and the insulating layers 30, 31a, 80, 31b, 32, and 33. Specifically, the slit SLT divides the wiring provided in the layers TI1 and TI2. In the slit SLT of the second embodiment, conductive materials having insulating spacers provided on their sidewalls can also be arranged to be insulated from these wirings. Similar to the first embodiment, the slit SHE of the second embodiment divides at least the conductive layer 23.

[0082] (2: Cross-sectional structure near the boundary area BA of the memory cell array 10C) Figure 26 1 is a cross-sectional view showing an example of a cross-sectional structure near a boundary region of a memory cell array 10C included in the memory device 1 according to the second embodiment. Figure 26 FIG. 1 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before being bonded to the semiconductor substrate W1, and shows the coordinate axes based on the semiconductor substrate W2. Figure 26 As shown, the support column HR of the second embodiment is provided to pass through the layers TI1 and TI2. Specifically, the insulating member 50 constituting the support column HR of the second embodiment, for example, passes through the insulating layers 30, 31a, 80, 31b, 32 and 33, and the conductive layers 21, 22a, 22b and 23 respectively. That is, the insulating member 50 is provided continuously between the layers TI1 and TI2. In addition, the side surface of the insulating member 50 constituting the support column HR has a shape that is continuous across the layers TI1 and TI2. The bottom of each insulating member 50 of the second embodiment is connected to the semiconductor substrate W2. The structure of each insulating member 50 of the second embodiment is the same between the lead-out area HA and the boundary area BA.

[0083] Furthermore, the dummy columns DMP of the second embodiment are included in the level TI2, but not in the level TI1. Specifically, in the boundary area BA, the upper surface of each dummy column DMP is flush with the upper surface of the storage column MPa. In addition, the upper surface of the dummy column DMP may be flush with the upper surface of the support column HR, or may not be flush. Furthermore, the side and bottom of each dummy column DMP are covered by an insulating member 50 (support column HR) that overlaps in the Z direction. The length of each dummy column DMP in the Z direction is shorter than the height of the level TI2. In addition, without limitation to this, the boundary area BA may also include a dummy column DMP that extends from the upper part of the level TI2 to the middle of the level TI1.

[0084] Furthermore, in the lead-out area HA of the second embodiment, the stacked wiring of the level TI1 and the stacked wiring of the level TI2 included in the memory cell array 10C may each have a terrace portion. In this example, the diagram illustrates a case where the level TI1 includes terrace portions of two conductive layers 22. In this example, the steps formed by the terrace portions in the level TI1 are filled with the insulating layer 80. In the level TI2, the steps formed by the terrace portions are filled with the insulating layer 33 (not shown).

[0085] <2-2> Manufacturing method Next, use Figures 27 to 33 , a method for manufacturing the memory device 1 according to the second embodiment will be described. Figure 27 、 Figure 28 、 Figure 29 、 Figure 30 、 Figure 31 、 Figure 32 、 Figure 33 Each of them is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array 10C provided in the memory device 1 according to the second embodiment during the manufacturing process. The cross-sectional structure referred to in this project corresponds to Figure 26 The area near the boundary area BA of the memory cell array 10 is shown.

[0086] First, although not shown in the figure, sacrificial members 70 and 71a of the stacked wiring portion corresponding to the level TI1 are formed. Specifically, first, the sacrificial member 70 is formed on the insulator layer 30. The insulator layer 31a and the sacrificial member 71a are alternately stacked on the sacrificial member 70. Then, by thinning or etching, a stepped structure of the sacrificial members 70 and 71a is formed in the lead-out area HA. ​​Then, the steps of the stepped structure are filled with the insulator layer 80, so that the upper surface of the insulator layer 80 is flattened. The sacrificial members 70 and 71a are, for example, silicon nitride (SiN). In addition, depending on the design of the memory cell array 10C, the formation of the stepped structure of the sacrificial members 70 and 71a can also be omitted.

[0087] Next, a mask REG2 (not shown) similar to the first embodiment is formed, and an anisotropic etching process is performed using the mask REG2 as a mask. Then, etching is performed through the plurality of holes H2 and the plurality of holes H3. Figure 27 As shown, a plurality of memory holes LMH and a plurality of holes LDMH are formed. Each memory hole LMH is provided by penetrating the insulator layers 30, 31a, and 80 and the sacrificial members 70 and 71a. The surface of the semiconductor substrate W2 is exposed at the bottom of each memory hole LMH. That is, in this process, the semiconductor substrate W2 is used as an etching stop layer. Each hole LDMH is provided by penetrating a portion of the stacked structure of the insulator layers 30, 31a, and 80 and the sacrificial members 70 and 71a. The bottom of each hole LDMH stops midway in the stacked structure (layer TI1) of the insulator layers 30, 31a, and 80 and the sacrificial members 70 and 71a. In addition, in this process, for example, RIE is used.

[0088] Then, if Figure 28 As shown, a sacrificial member 90 is formed in each memory hole LMH, and an insulating member 91 is formed in each hole LDMH. The material used for sacrificial member 90 is different from the material used for insulating member 91. Therefore, the formation of sacrificial member 90 and insulating member 91 are performed in different steps. Sacrificial member 90 is, for example, carbon (C). Insulating member 91 is, for example, silicon oxide (SiO2).

[0089] First, if Figure 29 As shown, sacrificial members 71b and 72 of the stacked wiring portion corresponding to the level TI2 are formed. Specifically, first, sacrificial members 71b and insulating layers 31b are alternately stacked on the insulating layer 30. Then, a step structure (not shown) of the sacrificial members 71b and 72 is formed in the lead-out area HA by thinning or etching. Then, the steps of the step structure are filled with the insulating layer 33 to flatten the upper surface of the insulating layer 33. The sacrificial members 71b and 72 are, for example, silicon nitride (SiN). In addition, depending on the design of the memory cell array 10C, the formation of the step structure of the sacrificial members 71b and 72 can also be omitted.

[0090] Next, a mask REG1 (not shown) similar to that of the first embodiment is formed, and an anisotropic etching process is performed using the mask REG1 as a mask. Then, etching is performed through the plurality of holes H1. Figure 30Multiple holes HH are formed as shown. Each hole HH in the second embodiment is provided through the insulator layers 30, 33, and 80, the sacrificial members 70, 71a, 71b, and 72, and the portions of the insulator layers 31, 31a, 31b, and 32 sandwiched between the insulator layers 30 and 33. The surface of the semiconductor substrate W2 is exposed at the bottom of each hole HH. In other words, in this process, the semiconductor substrate W2 serves as an etching stop layer. Thus, each hole HH in the second embodiment is provided through the stacked wiring portions of each of the levels TI1 and TI2. Through this process, each hole HH removes part or all of the insulating member 91 provided in the level TI1.

[0091] Then, if Figure 31 As shown, the insulating member 50 is formed, and the plurality of holes HH are respectively filled with the insulating member 50. At this time, the bottom of the insulating member 50 is in contact with the semiconductor substrate W2. In addition, the side surface of each insulating member 50 is in contact with at least one of the insulating layers 33 and 80, and the insulating layers 30, 31a, 31b, 32, and 33.

[0092] Next, a mask REG2 (not shown) similar to the first embodiment is formed, and an anisotropic etching process is performed using the mask REG2 as a mask. Then, etching is performed through the plurality of holes H2 and the plurality of holes H3. Figure 32 A plurality of memory holes UMH and a plurality of holes UDMH are formed as shown. Each memory hole UMH is provided by penetrating the insulating layers 31b and 33 and the sacrificial members 71b and 72. At the bottom of each memory hole UMH, the upper surface of the sacrificial member 90 of the associated memory hole LMH is exposed. That is, in this process, the sacrificial member 90 of the memory hole LMH is used as an etching stop layer when forming the memory hole UMH. Each hole UDMH is provided by removing a portion of the insulating member 50 constituting the support column HR. On the side and bottom surfaces of each hole UDMH, the surface of the insulating member 50 is exposed. The position (height) of the bottom of each hole UDMH varies depending on the diameter of the corresponding hole H3. In addition, in this process, for example, RIE is used.

[0093] Next, for example, by wet etching, the sacrificial member 90 in the corresponding memory hole LMH is removed through each memory hole UMH. Figure 33As shown, a memory column MPa is formed in the group of connected memory holes LMH and UMH, and a dummy column DMP is formed in each hole UDMH. Specifically, a stacked film 42 (i.e., a blocking insulating film 45, an insulating film 44, and a tunnel insulating film 43), a semiconductor layer 41, and a core member 40 are sequentially formed on the side and bottom surfaces of the connected memory holes LMH and UMH. At this time, a stacked film 42, a semiconductor layer 41, and a core member 40 are also sequentially formed on the side and bottom surfaces of the hole UDMH. In addition, depending on the diameter of the hole UDMH, a portion of the stacked film 42, the semiconductor layer 41, and the core member 40 may not be formed in the hole UDMH. Then, a portion of the core member 40 provided on the upper portion of the connected memory holes LMH and UMH is removed, and a semiconductor layer 41 is formed on the portion after the core member 40 is removed. As a result, as shown in FIG. Figure 33 As shown, a structure corresponding to the memory pillar MPa is formed in the connected memory holes LMH and UMH. Similarly, a structure corresponding to the dummy pillar DMP is formed in the hole UDMH. Then, the stacked film 42, semiconductor layer 41, and core member 40 above the insulator layer 33 are removed by CMP or the like.

[0094] Next, although not shown in the figure, slits SLT are formed to divide the sacrificial members 70, 71a, 71b, and 72 into each block BLK, and a replacement process is performed. Specifically, the sacrificial members 70, 71a, 71b, and 72 are selectively removed through the slits SLT by a wet etching process using hot phosphoric acid or the like. At this time, the space after the sacrificial members 70, 71a, 71b, and 72 are removed is maintained by a plurality of storage pillars MPa and a plurality of support pillars HR. Then, a conductor is filled into the space after the sacrificial members 70, 71a, 71b, and 72 are removed through the slits SLT. The conductor is formed in this process using, for example, CVD. Thereafter, the conductor formed in the slits SLT is removed by an etch-back process or the like, and the conductor formed in the adjacent spaces is separated into multiple layers. Thus, a conductor layer 21 that functions as a selection gate line SGS, a plurality of conductor layers 22a and 22b that function as word lines WL, and a conductor layer 23 that functions as a selection gate line SGD are formed. After that, the insulating member 37 is formed in the slit SLT to complete the Figure 25 and Figure 26 The stacked wiring is shown.

[0095] <2-3> Effects of the Second Embodiment As described above, the memory device 1 according to the second embodiment includes memory pillars MPa formed in multiple layers, and has a structure in which multiple dummy pillars DMP and multiple support pillars HR overlap in the Z direction in the boundary area BA. Even in this case, the memory device 1 according to the second embodiment can, similar to the first embodiment, suppress both defects during the replacement process and defects caused by overetching of the dummy pillars DMP. Therefore, the memory device 1 according to the second embodiment can improve the yield rate and reduce the manufacturing cost of the memory device 1.

[0096] <3> Modifications, etc. The storage device 1 described above can be variously modified.

[0097] Figure 34 1 is a plan view showing an example of a planar layout of a memory cell array 10D according to the first modification. Figure 35 An example of a cross-sectional structure of a memory cell array 10D according to the first modification is shown. Figure 34 The cross-sectional view of the XXXV-XXXV line. Figure 34 As shown, the first modification corresponds to the case where the positions of the plurality of dummy pillars DMP and the plurality of support pillars HR are offset in the boundary area BA. That is, it corresponds to the state where the dummy pillars DMP and the support pillars HR partially overlap. In this case, as shown in FIG. Figure 35 As shown, a portion of the stacked film 42 of the dummy pillar DMP is in contact with at least one of the conductive layers 21 to 23. Thus, even when the dummy pillar DMP and the support pillar HR are misaligned in the boundary area BA, the same effects as those of the first embodiment can be achieved.

[0098] Figure 36 1 is a plan view showing an example of a planar layout of a memory cell array 10E according to the second modification. Figure 37 An example of a cross-sectional structure of a memory cell array 10E according to the second modification is shown. Figure 36 The cross-sectional view of the line XXXVII-XXXVII. Figure 36 As shown in FIG. 1 , the second modification corresponds to a case where the plurality of dummy pillars DMP and the plurality of supporting pillars HR are separated (do not overlap) in the boundary area BA. In this case, as shown in FIG. Figure 37 As shown, the side surface of the dummy pillar DMP is in contact with at least one of the conductive layers 21 to 23. Thus, even when the dummy pillar DMP is separated from the support pillar HR in the boundary area BA, the same effects as those of the first embodiment can be achieved.

[0099] The structures described in the first and second variants may also be caused by alignment deviation in the photolithography process. The more the support pillars HR and the dummy pillars DMP in the boundary area BA overlap, the more the increase in wiring resistance associated with the formation of the dummy pillars DMP can be suppressed. Therefore, for the support pillars HR and the dummy pillars DMP arranged in a staggered manner between two adjacent slits SLT in the boundary area BA, their number of rows and columns, and spacing may be different from each other, but are more preferably the same. In addition, in the second embodiment, if alignment deviation occurs between the formation of the memory hole LMH and the hole LDMH of the layer TI1 and the formation of the hole HH of the layers TI1 and TI2, the insulating member 91 formed in the hole LDMH may remain in the memory device 1.

[0100] Figure 38 1 is a cross-sectional view showing an example of a detailed cross-sectional structure near two bonding pads BP arranged to face each other. Figure 38 The figure shows a conductive layer 64 (bonding pad BP) formed using a semiconductor substrate W1 (not shown), a conductive layer 26 (bonding pad BP) formed using a semiconductor substrate W2 (not shown), a portion of contacts 63 and V1 connected to these bonding pads BP, and conductive layers 62 and 25. Figure 38 As shown, the two opposing bonding pads BP may have different tapered shapes depending on the etching direction during formation. Specifically, the conductive layer 64 formed using semiconductor substrate W1 may have an inverted tapered shape, for example. The conductive layer 26 formed using semiconductor substrate W2 may have a tapered shape, for example. Therefore, the sidewalls of the cross-section along the Z direction at the junction of conductive layer 64 and conductive layer 26 may not be straight lines but rather non-rectangular. The two opposing bonding pads BP in other locations may also have the same shape as conductive layers 26 and 64. Furthermore, the pair of opposing bonding pads BP may be staggered due to alignment during the bonding process. As a result, a step may be formed between the upper surface of conductive layer 64 and the lower surface of conductive layer 26. The pair of opposing bonding pads BP may have a boundary or be integrated. The bonding pad BP and the contacts 63 and V1 connected to the bonding pad BP may also be formed integrally. Alternatively, multiple corresponding contacts 63 and V1 may be connected to the bonding pad BP. For example, the conductor layer 64 may be connected to the conductor layer 62 via the plurality of contacts 63. Similarly, the conductor layer 26 may be connected to the conductor layer 25 via the plurality of contacts V1.

[0101] Figure 39 1 is a cross-sectional view showing an example of a detailed cross-sectional structure of a boundary portion between a first level TI1 and a second level TI2 of a memory pillar MPa included in the memory device 1 according to the second embodiment. Figure 39As shown, for example, in the YZ cross section, the upper end of the lower storage column LMP may not have an angular shape, but may have a rounded shape. In this case, it cannot be said that the XY cross-sectional area of ​​the upper end of the lower storage column LMP is significantly larger than the XY cross-sectional area of ​​the lower end of the upper storage column UMP. However, the shape of the side surface of the storage column MPa will be discontinuous at the boundary between the lower storage column LMP and the upper storage column UMP. Specifically, for example, in the YZ cross section, the side surface SLMP of the lower storage column LMP deviates from Figure 39 The extension line of the side surface SUMP of the upper storage column UMP is shown by the single dotted line. The deviation of the two side surfaces SLMP and SUMP may occur on any section including the Z direction, such as the XZ section. In this specification, the boundary portion of the storage column MP in two adjacent levels TI in the Z direction can be determined based on the discontinuous portion at the shape of the side surface of the storage column MP. The storage column MPa may also have a structure in which more than three columns, each extending along the Z direction, are connected. Even in such a case, the storage column MPa may have the following structure at the boundary portion of the adjacent levels TI: Figure 39 The structure shown.

[0102] Figure 40 1 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array 10F according to the third modification. Figure 40 As shown, the third variant corresponds to the case where the support pillars HR and dummy pillars DMP described in the first embodiment are formed in each level TI. Specifically, the memory cell array 10F involved in the third variant has a structure in which the support pillars HR in the second embodiment are replaced with support pillars HRa, and the insulating member 91 corresponding to the hole LDMH remains. The support pillars HRa include an insulating member 50a provided corresponding to the level TI1 and an insulating member 50b provided corresponding to the level TI2. The shape of the side surface of the insulating member 50a is discontinuous with the shape of the side surface of the insulating member 50b. The dummy pillars DMP overlap with the support pillars HRa in the Z direction and are provided by removing a portion of the insulating member 50b. The insulating member 91 corresponding to the hole LDMH overlaps with the support pillars HRa in the Z direction and is provided by removing a portion of the insulating member 50a. In this way, even when the support pillars HR are provided for each level TI, the same effects as the second embodiment can be achieved. In addition, in the memory cell array 10F involved in the third variant, a sacrificial member 90 can be formed in the hole LDMH instead of the insulating member 91.

[0103] Figure 41 1 is a cross-sectional view showing an example of a cross-sectional structure of a memory device 1A according to a fourth modification. Figure 41As shown, the fourth modification corresponds to the case where the memory device 1A is formed using a single semiconductor substrate SUB, and the CMOS circuit is arranged below the memory cell array 10. Thus, even when the memory device 1A is not formed using multiple semiconductor substrates, by forming the support pillars HR and the dummy pillars DMP in the boundary area BA as in the first embodiment, it is possible to suppress the penetration of the dummy pillars DMP into the insulator layer 60. This suppresses defects caused by interference between the bottom of the dummy pillars DMP and the CMOS circuit formed below the memory cell array 10. As a result, the memory device 1A according to the fourth modification can improve the yield and reduce the manufacturing cost of the memory device 1A.

[0104] In the above embodiment, the circuit structure, planar layout and cross-sectional structure of the memory device 1 can be appropriately changed. The memory column MP can also have a structure in which a column corresponding to the selection gate line SGD and a column corresponding to the word line WL are connected. The memory column MP and the bit line BL can also be connected by a plurality of contacts connected in the Z direction. A conductive layer can also be inserted into the connection part of the plurality of contacts. The number of wiring layers or contacts provided by the memory device 1 can be appropriately changed according to the circuit design. The memory column MP can have a conical shape, an inverted conical shape or an arch shape. The slit SLT can have a conical shape, an inverted conical shape or an arch shape. The XY cross-sectional structure of the memory column MP and the support column HR can be circular or elliptical. In this specification, the "XY cross-sectional area" corresponds to the cross-sectional area in the cross section parallel to the semiconductor substrate W1 or W2. Each wiring in the stacked wiring can also include a metal oxide film around a conductor such as tungsten. The conductive layer alternately stacked with the insulating layer in the stacked wiring can also be regarded as including such a metal oxide film.

[0105] The manufacturing process described in the above embodiment is merely an example. For example, other processes may be inserted between the manufacturing processes, and the order of the manufacturing processes may be reversed within a range that does not cause problems. In this specification, "connection" means electrical connection, and does not exclude the situation where, for example, other elements are interposed therebetween. Regarding "electrical connection", as long as it can operate in the same way as the electrically connected components, it may be through an insulator. "Tapered shape" means a shape that becomes thinner as it moves away from a reference member. "Inverted tapered shape" means a shape that becomes thicker as it moves away from a reference member. "Columnar" means a structure provided in a hole formed in the manufacturing process of the storage device 1. "Diameter" means the inner diameter of the hole or the outer diameter of the column in a cross section (XY cross section) parallel to the surface of the substrate. "Semiconductor substrate" may also be referred to as "substrate". "Semiconductor layer" may also be referred to as "conductive layer". "Region" may be considered as a structure contained in the substrate. For example, in the case where it is specified that the semiconductor substrate W1 includes a storage area MA and a lead-out area HA, the storage area MA and the lead-out area HA are respectively associated with different regions above the semiconductor substrate W1. "Height" corresponds to, for example, the distance between the structure being measured and the semiconductor substrate W1 in the Z direction. Structures other than the semiconductor substrate W1 can also be used as a reference for "height." "Top (planar) view" corresponds to, for example, the front face of the semiconductor substrate W1 as viewed from a direction perpendicular to the semiconductor substrate W1.

[0106] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention and are included in the scope equivalent to the invention described in the claims. [Explanation of Reference Numerals]

[0107] 1. 1A: Memory device, 2: Memory controller, 10. 10A. 10B. 10C. 10D. 10E. 10F: Memory cell array, 11. Input / output circuit, 12. Logic controller, 13. Register circuit, 14. Sequencer, 15. Driver circuit, 16. Row decoder module, 17. Sense amplifier module, 21-27, 22a, 22b, 62, 64: Conductor layer, 30-36, 31a, 31b, 38, 60, 61, 80: Insulator layer, 37, 50, 50a, 50b, 91: Insulating member, 40: Core member, 41: Semiconductor layer, 42: Laminated film, 43: Tunnel insulating film, 44: Insulating film, 45 5: blocking insulating film, 63, CV, V0, V1: contacts, 70~72, 71a, 71b, 90: sacrificial member, W1, W2: semiconductor substrate, 100: CMOS layer, 200: storage layer, 300: wiring layer, B1, B2: bonding layer, BLK: block, SU: string unit, NS: NAND string, BL: bit line, WL: word line, SGD, SGS: selection gate line, MT: memory cell transistor, ST1, ST2: selection transistor, H1~H3: hole, LMP: lower pillar, UMP: upper pillar, REG1, REG2: mask, SAU: sense amplifier unit, RD: row decoder, TI1, TI2: layer.

Claims

1. A storage device comprising: The substrate comprises a first region, a second region, and a third region sequentially arranged in a first direction; a plurality of first conductive layers arranged above the substrate in a second direction intersecting the first direction; a plurality of memory pillars provided in the first region, each having a portion intersecting with the plurality of first conductive layers and comprising a stacked film; a plurality of first pillars disposed in the second region and the third region, each having a portion intersecting at least a portion of the plurality of first conductive layers and having a different configuration from the memory pillars; as well as A plurality of second pillars are provided in the second region, each having a portion intersecting with at least one first conductor layer among the plurality of first conductor layers, and including the stacked film.

2. The memory device according to claim 1, wherein In the second region, at least a portion of each of the plurality of second pillars overlaps with one of the plurality of first pillars in the second direction.

3. The memory device according to claim 1, wherein Each of the plurality of second pillars is separated from the plurality of first electrical conductor layers.

4. The memory device according to claim 1, wherein The plurality of first pillars are arranged in a lattice pattern in the second region, The plurality of second pillars are arranged in a lattice pattern in the second region. The number of rows and the number of columns of the second pillars arranged in the second area are respectively the same as the number of rows and the number of columns of the first pillars arranged in the second area.

5. The memory device according to claim 1, wherein The plurality of first pillars are arranged in a lattice pattern in the second region, The plurality of second pillars are arranged in a lattice pattern in the second region. The pitches of the second pillars arranged in the second region are respectively the same as the pitches of the first pillars arranged in the second region. The memory device according to claim 1 , wherein: At least one of the plurality of second pillars is shorter than the plurality of storage pillars in the second direction.

7. The memory device according to claim 1, wherein The diameter of the second plurality of pillars is smaller than the diameter of the first plurality of pillars in the second region.

8. The memory device according to claim 7, wherein: A diameter of at least one of the plurality of second pillars is smaller than a diameter of the plurality of storage pillars.

9. The memory device according to claim 1, wherein The lengths of the plurality of storage pillars in the second direction are substantially equal to the lengths of the plurality of first pillars in the second direction.

10. The memory device according to claim 1, wherein The multiple storage pillars each include a first part and a second part, the first part is included in the first level, the second part is arranged in the second direction above the substrate and the first level, and is included in the second level, and the shape of the side surface of the first part is discontinuous with the shape of the side surface of the second part. The memory device according to claim 10 , wherein: Each of the plurality of first pillars includes a first insulating member continuously disposed between the first level and the second level.

12. The memory device according to claim 10, wherein: further comprising a plurality of third pillars arranged in the second region, each having a portion intersecting at least one other first conductive layer among the plurality of first conductive layers, and including a second insulating member; The plurality of second columns are included in the second level, The plurality of third columns are included in the first level.

13. The memory device according to claim 12, wherein: Each of the plurality of first pillars includes a third portion and a fourth portion, the third portion is included in the first level, the fourth portion is included in the second level, and a shape of a side surface of the third portion is discontinuous with a shape of a side surface of the fourth portion.

14. The memory device according to claim 1, wherein Each of the plurality of memory pillars further comprises a semiconductor layer, The stacked film includes a tunnel insulating film surrounding a side surface of the semiconductor layer, a charge storage layer surrounding a side surface of the tunnel insulating film, and a blocking insulating film surrounding a side surface of the charge storage layer.

15. The memory device according to claim 14, wherein A film thickness of the stacked films included in the plurality of second pillars is substantially the same as a film thickness of the stacked films included in the plurality of storage pillars.

16. The memory device according to claim 1, wherein The plurality of first pillars include a first insulating member including oxygen and silicon.

17. The memory device according to claim 1, wherein Upper surfaces of the plurality of storage pillars are flush with upper surfaces of the plurality of second pillars.

18. The memory device according to claim 1, wherein There are also a plurality of second conductive layers, each of which has a portion extending in a third direction intersecting the first direction and the second direction, and is separated from the plurality of first conductive layers in the second direction and arranged in the first direction. Each of the plurality of storage pillars is connected to one of the plurality of second conductive layers, and no conductive layer separated from the plurality of first conductive layers in the second direction is connected to the plurality of second pillars.

19. The memory device according to claim 1, wherein further comprising a third conductive layer and a fourth conductive layer, which are provided between the substrate and the plurality of first conductive layers and are arranged to face each other in the second direction, The substrate includes a control circuit, and the control circuit is connected to the plurality of storage pillars via the third conductive layer and the fourth conductive layer. The third conductive layer and the fourth conductive layer have mutually different tapered shapes.

20. The memory device according to claim 1, wherein A fifth conductive layer is further provided, which is provided between the substrate and the plurality of first conductive layers and is connected to one end of each of the plurality of storage pillars. The fifth conductive layer functions as a source line.

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